1*5ca02815Sjsg /* SPDX-License-Identifier: MIT */
2c349dbc7Sjsg /*
3c349dbc7Sjsg * Copyright © 2019 Intel Corporation
4c349dbc7Sjsg */
5c349dbc7Sjsg
6c349dbc7Sjsg #ifndef INTEL_GT_IRQ_H
7c349dbc7Sjsg #define INTEL_GT_IRQ_H
8c349dbc7Sjsg
9c349dbc7Sjsg #include <linux/types.h>
10c349dbc7Sjsg
11*5ca02815Sjsg #include "intel_engine_types.h"
12*5ca02815Sjsg
13c349dbc7Sjsg struct intel_gt;
14c349dbc7Sjsg
15c349dbc7Sjsg #define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \
16c349dbc7Sjsg GEN8_GT_BCS_IRQ | \
17c349dbc7Sjsg GEN8_GT_VCS0_IRQ | \
18c349dbc7Sjsg GEN8_GT_VCS1_IRQ | \
19c349dbc7Sjsg GEN8_GT_VECS_IRQ | \
20c349dbc7Sjsg GEN8_GT_PM_IRQ | \
21c349dbc7Sjsg GEN8_GT_GUC_IRQ)
22c349dbc7Sjsg
23c349dbc7Sjsg void gen11_gt_irq_reset(struct intel_gt *gt);
24c349dbc7Sjsg void gen11_gt_irq_postinstall(struct intel_gt *gt);
25c349dbc7Sjsg void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl);
26c349dbc7Sjsg
27c349dbc7Sjsg bool gen11_gt_reset_one_iir(struct intel_gt *gt,
28c349dbc7Sjsg const unsigned int bank,
29c349dbc7Sjsg const unsigned int bit);
30c349dbc7Sjsg
31c349dbc7Sjsg void gen5_gt_irq_handler(struct intel_gt *gt, u32 gt_iir);
32c349dbc7Sjsg
33c349dbc7Sjsg void gen5_gt_irq_postinstall(struct intel_gt *gt);
34c349dbc7Sjsg void gen5_gt_irq_reset(struct intel_gt *gt);
35c349dbc7Sjsg void gen5_gt_disable_irq(struct intel_gt *gt, u32 mask);
36c349dbc7Sjsg void gen5_gt_enable_irq(struct intel_gt *gt, u32 mask);
37c349dbc7Sjsg
38c349dbc7Sjsg void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir);
39c349dbc7Sjsg
40c349dbc7Sjsg void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl);
41c349dbc7Sjsg void gen8_gt_irq_reset(struct intel_gt *gt);
42c349dbc7Sjsg void gen8_gt_irq_postinstall(struct intel_gt *gt);
43c349dbc7Sjsg
intel_engine_cs_irq(struct intel_engine_cs * engine,u16 iir)44*5ca02815Sjsg static inline void intel_engine_cs_irq(struct intel_engine_cs *engine, u16 iir)
45*5ca02815Sjsg {
46*5ca02815Sjsg if (iir)
47*5ca02815Sjsg engine->irq_handler(engine, iir);
48*5ca02815Sjsg }
49*5ca02815Sjsg
50*5ca02815Sjsg static inline void
intel_engine_set_irq_handler(struct intel_engine_cs * engine,void (* fn)(struct intel_engine_cs * engine,u16 iir))51*5ca02815Sjsg intel_engine_set_irq_handler(struct intel_engine_cs *engine,
52*5ca02815Sjsg void (*fn)(struct intel_engine_cs *engine,
53*5ca02815Sjsg u16 iir))
54*5ca02815Sjsg {
55*5ca02815Sjsg /*
56*5ca02815Sjsg * As the interrupt is live as allocate and setup the engines,
57*5ca02815Sjsg * err on the side of caution and apply barriers to updating
58*5ca02815Sjsg * the irq handler callback. This assures that when we do use
59*5ca02815Sjsg * the engine, we will receive interrupts only to ourselves,
60*5ca02815Sjsg * and not lose any.
61*5ca02815Sjsg */
62*5ca02815Sjsg smp_store_mb(engine->irq_handler, fn);
63*5ca02815Sjsg }
64*5ca02815Sjsg
65c349dbc7Sjsg #endif /* INTEL_GT_IRQ_H */
66