xref: /openbsd-src/sys/dev/pci/drm/i915/gt/intel_gt_debugfs.c (revision f005ef32267c16bdb134f0e9fa4477dbe07c263a)
11bb76ff1Sjsg // SPDX-License-Identifier: MIT
21bb76ff1Sjsg /*
31bb76ff1Sjsg  * Copyright © 2019 Intel Corporation
41bb76ff1Sjsg  */
51bb76ff1Sjsg 
61bb76ff1Sjsg #include <linux/debugfs.h>
71bb76ff1Sjsg 
81bb76ff1Sjsg #include "i915_drv.h"
91bb76ff1Sjsg #include "intel_gt.h"
101bb76ff1Sjsg #include "intel_gt_debugfs.h"
111bb76ff1Sjsg #include "intel_gt_engines_debugfs.h"
121bb76ff1Sjsg #include "intel_gt_mcr.h"
131bb76ff1Sjsg #include "intel_gt_pm_debugfs.h"
141bb76ff1Sjsg #include "intel_sseu_debugfs.h"
151bb76ff1Sjsg #include "uc/intel_uc_debugfs.h"
161bb76ff1Sjsg 
intel_gt_debugfs_reset_show(struct intel_gt * gt,u64 * val)171bb76ff1Sjsg int intel_gt_debugfs_reset_show(struct intel_gt *gt, u64 *val)
181bb76ff1Sjsg {
191bb76ff1Sjsg 	int ret = intel_gt_terminally_wedged(gt);
201bb76ff1Sjsg 
211bb76ff1Sjsg 	switch (ret) {
221bb76ff1Sjsg 	case -EIO:
231bb76ff1Sjsg 		*val = 1;
241bb76ff1Sjsg 		return 0;
251bb76ff1Sjsg 	case 0:
261bb76ff1Sjsg 		*val = 0;
271bb76ff1Sjsg 		return 0;
281bb76ff1Sjsg 	default:
291bb76ff1Sjsg 		return ret;
301bb76ff1Sjsg 	}
311bb76ff1Sjsg }
321bb76ff1Sjsg 
intel_gt_debugfs_reset_store(struct intel_gt * gt,u64 val)331bb76ff1Sjsg void intel_gt_debugfs_reset_store(struct intel_gt *gt, u64 val)
341bb76ff1Sjsg {
351bb76ff1Sjsg 	/* Flush any previous reset before applying for a new one */
361bb76ff1Sjsg 	wait_event(gt->reset.queue,
371bb76ff1Sjsg 		   !test_bit(I915_RESET_BACKOFF, &gt->reset.flags));
381bb76ff1Sjsg 
391bb76ff1Sjsg 	intel_gt_handle_error(gt, val, I915_ERROR_CAPTURE,
401bb76ff1Sjsg 			      "Manually reset engine mask to %llx", val);
411bb76ff1Sjsg }
421bb76ff1Sjsg 
431bb76ff1Sjsg /*
441bb76ff1Sjsg  * keep the interface clean where the first parameter
451bb76ff1Sjsg  * is a 'struct intel_gt *' instead of 'void *'
461bb76ff1Sjsg  */
__intel_gt_debugfs_reset_show(void * data,u64 * val)471bb76ff1Sjsg static int __intel_gt_debugfs_reset_show(void *data, u64 *val)
481bb76ff1Sjsg {
491bb76ff1Sjsg 	return intel_gt_debugfs_reset_show(data, val);
501bb76ff1Sjsg }
511bb76ff1Sjsg 
521bb76ff1Sjsg #ifdef notyet
531bb76ff1Sjsg 
__intel_gt_debugfs_reset_store(void * data,u64 val)541bb76ff1Sjsg static int __intel_gt_debugfs_reset_store(void *data, u64 val)
551bb76ff1Sjsg {
561bb76ff1Sjsg 	intel_gt_debugfs_reset_store(data, val);
571bb76ff1Sjsg 
581bb76ff1Sjsg 	return 0;
591bb76ff1Sjsg }
601bb76ff1Sjsg 
611bb76ff1Sjsg DEFINE_SIMPLE_ATTRIBUTE(reset_fops, __intel_gt_debugfs_reset_show,
621bb76ff1Sjsg 			__intel_gt_debugfs_reset_store, "%llu\n");
631bb76ff1Sjsg 
steering_show(struct seq_file * m,void * data)641bb76ff1Sjsg static int steering_show(struct seq_file *m, void *data)
651bb76ff1Sjsg {
661bb76ff1Sjsg 	struct drm_printer p = drm_seq_file_printer(m);
671bb76ff1Sjsg 	struct intel_gt *gt = m->private;
681bb76ff1Sjsg 
691bb76ff1Sjsg 	intel_gt_mcr_report_steering(&p, gt, true);
701bb76ff1Sjsg 
711bb76ff1Sjsg 	return 0;
721bb76ff1Sjsg }
731bb76ff1Sjsg DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(steering);
741bb76ff1Sjsg 
gt_debugfs_register(struct intel_gt * gt,struct dentry * root)751bb76ff1Sjsg static void gt_debugfs_register(struct intel_gt *gt, struct dentry *root)
761bb76ff1Sjsg {
771bb76ff1Sjsg 	static const struct intel_gt_debugfs_file files[] = {
781bb76ff1Sjsg 		{ "reset", &reset_fops, NULL },
791bb76ff1Sjsg 		{ "steering", &steering_fops },
801bb76ff1Sjsg 	};
811bb76ff1Sjsg 
821bb76ff1Sjsg 	intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
831bb76ff1Sjsg }
841bb76ff1Sjsg 
851bb76ff1Sjsg #endif /* notyet */
861bb76ff1Sjsg 
intel_gt_debugfs_register(struct intel_gt * gt)871bb76ff1Sjsg void intel_gt_debugfs_register(struct intel_gt *gt)
881bb76ff1Sjsg {
891bb76ff1Sjsg #ifdef notyet
901bb76ff1Sjsg 	struct dentry *root;
91*f005ef32Sjsg 	char gtname[4];
921bb76ff1Sjsg 
931bb76ff1Sjsg 	if (!gt->i915->drm.primary->debugfs_root)
941bb76ff1Sjsg 		return;
951bb76ff1Sjsg 
96*f005ef32Sjsg 	snprintf(gtname, sizeof(gtname), "gt%u", gt->info.id);
97*f005ef32Sjsg 	root = debugfs_create_dir(gtname, gt->i915->drm.primary->debugfs_root);
981bb76ff1Sjsg 	if (IS_ERR(root))
991bb76ff1Sjsg 		return;
1001bb76ff1Sjsg 
1011bb76ff1Sjsg 	gt_debugfs_register(gt, root);
1021bb76ff1Sjsg 
1031bb76ff1Sjsg 	intel_gt_engines_debugfs_register(gt, root);
1041bb76ff1Sjsg 	intel_gt_pm_debugfs_register(gt, root);
1051bb76ff1Sjsg 	intel_sseu_debugfs_register(gt, root);
1061bb76ff1Sjsg 
1071bb76ff1Sjsg 	intel_uc_debugfs_register(&gt->uc, root);
1081bb76ff1Sjsg #endif
1091bb76ff1Sjsg }
1101bb76ff1Sjsg 
intel_gt_debugfs_register_files(struct dentry * root,const struct intel_gt_debugfs_file * files,unsigned long count,void * data)1111bb76ff1Sjsg void intel_gt_debugfs_register_files(struct dentry *root,
1121bb76ff1Sjsg 				     const struct intel_gt_debugfs_file *files,
1131bb76ff1Sjsg 				     unsigned long count, void *data)
1141bb76ff1Sjsg {
1151bb76ff1Sjsg #ifdef notyet
1161bb76ff1Sjsg 	while (count--) {
1171bb76ff1Sjsg 		umode_t mode = files->fops->write ? 0644 : 0444;
1181bb76ff1Sjsg 
1191bb76ff1Sjsg 		if (!files->eval || files->eval(data))
1201bb76ff1Sjsg 			debugfs_create_file(files->name,
1211bb76ff1Sjsg 					    mode, root, data,
1221bb76ff1Sjsg 					    files->fops);
1231bb76ff1Sjsg 
1241bb76ff1Sjsg 		files++;
1251bb76ff1Sjsg 	}
1261bb76ff1Sjsg #endif
1271bb76ff1Sjsg }
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