10fe191bfSjsg // SPDX-License-Identifier: MIT 20fe191bfSjsg /* 30fe191bfSjsg * Copyright © 2024 Intel Corporation 40fe191bfSjsg */ 50fe191bfSjsg 60fe191bfSjsg #include "i915_drv.h" 70fe191bfSjsg #include "intel_gt.h" 80fe191bfSjsg #include "intel_gt_ccs_mode.h" 90fe191bfSjsg #include "intel_gt_regs.h" 100fe191bfSjsg intel_gt_apply_ccs_mode(struct intel_gt * gt)116081a0efSjsgunsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt) 120fe191bfSjsg { 130fe191bfSjsg int cslice; 140fe191bfSjsg u32 mode = 0; 150fe191bfSjsg int first_ccs = __ffs(CCS_MASK(gt)); 160fe191bfSjsg 170fe191bfSjsg if (!IS_DG2(gt->i915)) 186081a0efSjsg return 0; 190fe191bfSjsg 200fe191bfSjsg /* Build the value for the fixed CCS load balancing */ 210fe191bfSjsg for (cslice = 0; cslice < I915_MAX_CCS; cslice++) { 22*e90eceb0Sjsg if (gt->ccs.cslices & BIT(cslice)) 230fe191bfSjsg /* 240fe191bfSjsg * If available, assign the cslice 250fe191bfSjsg * to the first available engine... 260fe191bfSjsg */ 270fe191bfSjsg mode |= XEHP_CCS_MODE_CSLICE(cslice, first_ccs); 280fe191bfSjsg 290fe191bfSjsg else 300fe191bfSjsg /* 310fe191bfSjsg * ... otherwise, mark the cslice as 320fe191bfSjsg * unavailable if no CCS dispatches here 330fe191bfSjsg */ 340fe191bfSjsg mode |= XEHP_CCS_MODE_CSLICE(cslice, 350fe191bfSjsg XEHP_CCS_MODE_CSLICE_MASK); 360fe191bfSjsg } 370fe191bfSjsg 386081a0efSjsg return mode; 390fe191bfSjsg } 40