1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2016 Intel Corporation 4 */ 5 6 #include <drm/drm_print.h> 7 8 #include "gem/i915_gem_context.h" 9 10 #include "i915_drv.h" 11 12 #include "intel_breadcrumbs.h" 13 #include "intel_context.h" 14 #include "intel_engine.h" 15 #include "intel_engine_pm.h" 16 #include "intel_engine_user.h" 17 #include "intel_execlists_submission.h" 18 #include "intel_gt.h" 19 #include "intel_gt_requests.h" 20 #include "intel_gt_pm.h" 21 #include "intel_lrc_reg.h" 22 #include "intel_reset.h" 23 #include "intel_ring.h" 24 #include "uc/intel_guc_submission.h" 25 26 /* Haswell does have the CXT_SIZE register however it does not appear to be 27 * valid. Now, docs explain in dwords what is in the context object. The full 28 * size is 70720 bytes, however, the power context and execlist context will 29 * never be saved (power context is stored elsewhere, and execlists don't work 30 * on HSW) - so the final size, including the extra state required for the 31 * Resource Streamer, is 66944 bytes, which rounds to 17 pages. 32 */ 33 #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) 34 35 #define DEFAULT_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) 36 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) 37 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) 38 #define GEN11_LR_CONTEXT_RENDER_SIZE (14 * PAGE_SIZE) 39 40 #define GEN8_LR_CONTEXT_OTHER_SIZE ( 2 * PAGE_SIZE) 41 42 #define MAX_MMIO_BASES 3 43 struct engine_info { 44 u8 class; 45 u8 instance; 46 /* mmio bases table *must* be sorted in reverse graphics_ver order */ 47 struct engine_mmio_base { 48 u32 graphics_ver : 8; 49 u32 base : 24; 50 } mmio_bases[MAX_MMIO_BASES]; 51 }; 52 53 static const struct engine_info intel_engines[] = { 54 [RCS0] = { 55 .class = RENDER_CLASS, 56 .instance = 0, 57 .mmio_bases = { 58 { .graphics_ver = 1, .base = RENDER_RING_BASE } 59 }, 60 }, 61 [BCS0] = { 62 .class = COPY_ENGINE_CLASS, 63 .instance = 0, 64 .mmio_bases = { 65 { .graphics_ver = 6, .base = BLT_RING_BASE } 66 }, 67 }, 68 [VCS0] = { 69 .class = VIDEO_DECODE_CLASS, 70 .instance = 0, 71 .mmio_bases = { 72 { .graphics_ver = 11, .base = GEN11_BSD_RING_BASE }, 73 { .graphics_ver = 6, .base = GEN6_BSD_RING_BASE }, 74 { .graphics_ver = 4, .base = BSD_RING_BASE } 75 }, 76 }, 77 [VCS1] = { 78 .class = VIDEO_DECODE_CLASS, 79 .instance = 1, 80 .mmio_bases = { 81 { .graphics_ver = 11, .base = GEN11_BSD2_RING_BASE }, 82 { .graphics_ver = 8, .base = GEN8_BSD2_RING_BASE } 83 }, 84 }, 85 [VCS2] = { 86 .class = VIDEO_DECODE_CLASS, 87 .instance = 2, 88 .mmio_bases = { 89 { .graphics_ver = 11, .base = GEN11_BSD3_RING_BASE } 90 }, 91 }, 92 [VCS3] = { 93 .class = VIDEO_DECODE_CLASS, 94 .instance = 3, 95 .mmio_bases = { 96 { .graphics_ver = 11, .base = GEN11_BSD4_RING_BASE } 97 }, 98 }, 99 [VCS4] = { 100 .class = VIDEO_DECODE_CLASS, 101 .instance = 4, 102 .mmio_bases = { 103 { .graphics_ver = 12, .base = XEHP_BSD5_RING_BASE } 104 }, 105 }, 106 [VCS5] = { 107 .class = VIDEO_DECODE_CLASS, 108 .instance = 5, 109 .mmio_bases = { 110 { .graphics_ver = 12, .base = XEHP_BSD6_RING_BASE } 111 }, 112 }, 113 [VCS6] = { 114 .class = VIDEO_DECODE_CLASS, 115 .instance = 6, 116 .mmio_bases = { 117 { .graphics_ver = 12, .base = XEHP_BSD7_RING_BASE } 118 }, 119 }, 120 [VCS7] = { 121 .class = VIDEO_DECODE_CLASS, 122 .instance = 7, 123 .mmio_bases = { 124 { .graphics_ver = 12, .base = XEHP_BSD8_RING_BASE } 125 }, 126 }, 127 [VECS0] = { 128 .class = VIDEO_ENHANCEMENT_CLASS, 129 .instance = 0, 130 .mmio_bases = { 131 { .graphics_ver = 11, .base = GEN11_VEBOX_RING_BASE }, 132 { .graphics_ver = 7, .base = VEBOX_RING_BASE } 133 }, 134 }, 135 [VECS1] = { 136 .class = VIDEO_ENHANCEMENT_CLASS, 137 .instance = 1, 138 .mmio_bases = { 139 { .graphics_ver = 11, .base = GEN11_VEBOX2_RING_BASE } 140 }, 141 }, 142 [VECS2] = { 143 .class = VIDEO_ENHANCEMENT_CLASS, 144 .instance = 2, 145 .mmio_bases = { 146 { .graphics_ver = 12, .base = XEHP_VEBOX3_RING_BASE } 147 }, 148 }, 149 [VECS3] = { 150 .class = VIDEO_ENHANCEMENT_CLASS, 151 .instance = 3, 152 .mmio_bases = { 153 { .graphics_ver = 12, .base = XEHP_VEBOX4_RING_BASE } 154 }, 155 }, 156 }; 157 158 /** 159 * intel_engine_context_size() - return the size of the context for an engine 160 * @gt: the gt 161 * @class: engine class 162 * 163 * Each engine class may require a different amount of space for a context 164 * image. 165 * 166 * Return: size (in bytes) of an engine class specific context image 167 * 168 * Note: this size includes the HWSP, which is part of the context image 169 * in LRC mode, but does not include the "shared data page" used with 170 * GuC submission. The caller should account for this if using the GuC. 171 */ 172 u32 intel_engine_context_size(struct intel_gt *gt, u8 class) 173 { 174 struct intel_uncore *uncore = gt->uncore; 175 u32 cxt_size; 176 177 BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE); 178 179 switch (class) { 180 case RENDER_CLASS: 181 switch (GRAPHICS_VER(gt->i915)) { 182 default: 183 MISSING_CASE(GRAPHICS_VER(gt->i915)); 184 return DEFAULT_LR_CONTEXT_RENDER_SIZE; 185 case 12: 186 case 11: 187 return GEN11_LR_CONTEXT_RENDER_SIZE; 188 case 9: 189 return GEN9_LR_CONTEXT_RENDER_SIZE; 190 case 8: 191 return GEN8_LR_CONTEXT_RENDER_SIZE; 192 case 7: 193 if (IS_HASWELL(gt->i915)) 194 return HSW_CXT_TOTAL_SIZE; 195 196 cxt_size = intel_uncore_read(uncore, GEN7_CXT_SIZE); 197 return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64, 198 PAGE_SIZE); 199 case 6: 200 cxt_size = intel_uncore_read(uncore, CXT_SIZE); 201 return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64, 202 PAGE_SIZE); 203 case 5: 204 case 4: 205 /* 206 * There is a discrepancy here between the size reported 207 * by the register and the size of the context layout 208 * in the docs. Both are described as authorative! 209 * 210 * The discrepancy is on the order of a few cachelines, 211 * but the total is under one page (4k), which is our 212 * minimum allocation anyway so it should all come 213 * out in the wash. 214 */ 215 cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1; 216 drm_dbg(>->i915->drm, 217 "graphics_ver = %d CXT_SIZE = %d bytes [0x%08x]\n", 218 GRAPHICS_VER(gt->i915), cxt_size * 64, 219 cxt_size - 1); 220 return round_up(cxt_size * 64, PAGE_SIZE); 221 case 3: 222 case 2: 223 /* For the special day when i810 gets merged. */ 224 case 1: 225 return 0; 226 } 227 break; 228 default: 229 MISSING_CASE(class); 230 fallthrough; 231 case VIDEO_DECODE_CLASS: 232 case VIDEO_ENHANCEMENT_CLASS: 233 case COPY_ENGINE_CLASS: 234 if (GRAPHICS_VER(gt->i915) < 8) 235 return 0; 236 return GEN8_LR_CONTEXT_OTHER_SIZE; 237 } 238 } 239 240 static u32 __engine_mmio_base(struct drm_i915_private *i915, 241 const struct engine_mmio_base *bases) 242 { 243 int i; 244 245 for (i = 0; i < MAX_MMIO_BASES; i++) 246 if (GRAPHICS_VER(i915) >= bases[i].graphics_ver) 247 break; 248 249 GEM_BUG_ON(i == MAX_MMIO_BASES); 250 GEM_BUG_ON(!bases[i].base); 251 252 return bases[i].base; 253 } 254 255 static void __sprint_engine_name(struct intel_engine_cs *engine) 256 { 257 /* 258 * Before we know what the uABI name for this engine will be, 259 * we still would like to keep track of this engine in the debug logs. 260 * We throw in a ' here as a reminder that this isn't its final name. 261 */ 262 GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u", 263 intel_engine_class_repr(engine->class), 264 engine->instance) >= sizeof(engine->name)); 265 } 266 267 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask) 268 { 269 /* 270 * Though they added more rings on g4x/ilk, they did not add 271 * per-engine HWSTAM until gen6. 272 */ 273 if (GRAPHICS_VER(engine->i915) < 6 && engine->class != RENDER_CLASS) 274 return; 275 276 if (GRAPHICS_VER(engine->i915) >= 3) 277 ENGINE_WRITE(engine, RING_HWSTAM, mask); 278 else 279 ENGINE_WRITE16(engine, RING_HWSTAM, mask); 280 } 281 282 static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine) 283 { 284 /* Mask off all writes into the unknown HWSP */ 285 intel_engine_set_hwsp_writemask(engine, ~0u); 286 } 287 288 static void nop_irq_handler(struct intel_engine_cs *engine, u16 iir) 289 { 290 GEM_DEBUG_WARN_ON(iir); 291 } 292 293 static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id) 294 { 295 const struct engine_info *info = &intel_engines[id]; 296 struct drm_i915_private *i915 = gt->i915; 297 struct intel_engine_cs *engine; 298 u8 guc_class; 299 300 BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH)); 301 BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH)); 302 BUILD_BUG_ON(I915_MAX_VCS > (MAX_ENGINE_INSTANCE + 1)); 303 BUILD_BUG_ON(I915_MAX_VECS > (MAX_ENGINE_INSTANCE + 1)); 304 305 if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine))) 306 return -EINVAL; 307 308 if (GEM_DEBUG_WARN_ON(info->class > MAX_ENGINE_CLASS)) 309 return -EINVAL; 310 311 if (GEM_DEBUG_WARN_ON(info->instance > MAX_ENGINE_INSTANCE)) 312 return -EINVAL; 313 314 if (GEM_DEBUG_WARN_ON(gt->engine_class[info->class][info->instance])) 315 return -EINVAL; 316 317 engine = kzalloc(sizeof(*engine), GFP_KERNEL); 318 if (!engine) 319 return -ENOMEM; 320 321 BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES); 322 323 INIT_LIST_HEAD(&engine->pinned_contexts_list); 324 engine->id = id; 325 engine->legacy_idx = INVALID_ENGINE; 326 engine->mask = BIT(id); 327 engine->i915 = i915; 328 engine->gt = gt; 329 engine->uncore = gt->uncore; 330 guc_class = engine_class_to_guc_class(info->class); 331 engine->guc_id = MAKE_GUC_ID(guc_class, info->instance); 332 engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases); 333 334 engine->irq_handler = nop_irq_handler; 335 336 engine->class = info->class; 337 engine->instance = info->instance; 338 __sprint_engine_name(engine); 339 340 engine->props.heartbeat_interval_ms = 341 CONFIG_DRM_I915_HEARTBEAT_INTERVAL; 342 engine->props.max_busywait_duration_ns = 343 CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT; 344 engine->props.preempt_timeout_ms = 345 CONFIG_DRM_I915_PREEMPT_TIMEOUT; 346 engine->props.stop_timeout_ms = 347 CONFIG_DRM_I915_STOP_TIMEOUT; 348 engine->props.timeslice_duration_ms = 349 CONFIG_DRM_I915_TIMESLICE_DURATION; 350 351 /* Override to uninterruptible for OpenCL workloads. */ 352 if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS) 353 engine->props.preempt_timeout_ms = 0; 354 355 engine->defaults = engine->props; /* never to change again */ 356 357 engine->context_size = intel_engine_context_size(gt, engine->class); 358 if (WARN_ON(engine->context_size > BIT(20))) 359 engine->context_size = 0; 360 if (engine->context_size) 361 DRIVER_CAPS(i915)->has_logical_contexts = true; 362 363 ewma__engine_latency_init(&engine->latency); 364 seqcount_init(&engine->stats.lock); 365 366 ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier); 367 368 /* Scrub mmio state on takeover */ 369 intel_engine_sanitize_mmio(engine); 370 371 gt->engine_class[info->class][info->instance] = engine; 372 gt->engine[id] = engine; 373 374 return 0; 375 } 376 377 static void __setup_engine_capabilities(struct intel_engine_cs *engine) 378 { 379 struct drm_i915_private *i915 = engine->i915; 380 381 if (engine->class == VIDEO_DECODE_CLASS) { 382 /* 383 * HEVC support is present on first engine instance 384 * before Gen11 and on all instances afterwards. 385 */ 386 if (GRAPHICS_VER(i915) >= 11 || 387 (GRAPHICS_VER(i915) >= 9 && engine->instance == 0)) 388 engine->uabi_capabilities |= 389 I915_VIDEO_CLASS_CAPABILITY_HEVC; 390 391 /* 392 * SFC block is present only on even logical engine 393 * instances. 394 */ 395 if ((GRAPHICS_VER(i915) >= 11 && 396 (engine->gt->info.vdbox_sfc_access & 397 BIT(engine->instance))) || 398 (GRAPHICS_VER(i915) >= 9 && engine->instance == 0)) 399 engine->uabi_capabilities |= 400 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC; 401 } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) { 402 if (GRAPHICS_VER(i915) >= 9) 403 engine->uabi_capabilities |= 404 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC; 405 } 406 } 407 408 static void intel_setup_engine_capabilities(struct intel_gt *gt) 409 { 410 struct intel_engine_cs *engine; 411 enum intel_engine_id id; 412 413 for_each_engine(engine, gt, id) 414 __setup_engine_capabilities(engine); 415 } 416 417 /** 418 * intel_engines_release() - free the resources allocated for Command Streamers 419 * @gt: pointer to struct intel_gt 420 */ 421 void intel_engines_release(struct intel_gt *gt) 422 { 423 struct intel_engine_cs *engine; 424 enum intel_engine_id id; 425 426 /* 427 * Before we release the resources held by engine, we must be certain 428 * that the HW is no longer accessing them -- having the GPU scribble 429 * to or read from a page being used for something else causes no end 430 * of fun. 431 * 432 * The GPU should be reset by this point, but assume the worst just 433 * in case we aborted before completely initialising the engines. 434 */ 435 GEM_BUG_ON(intel_gt_pm_is_awake(gt)); 436 if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) 437 __intel_gt_reset(gt, ALL_ENGINES); 438 439 /* Decouple the backend; but keep the layout for late GPU resets */ 440 for_each_engine(engine, gt, id) { 441 if (!engine->release) 442 continue; 443 444 intel_wakeref_wait_for_idle(&engine->wakeref); 445 GEM_BUG_ON(intel_engine_pm_is_awake(engine)); 446 447 engine->release(engine); 448 engine->release = NULL; 449 450 memset(&engine->reset, 0, sizeof(engine->reset)); 451 } 452 } 453 454 void intel_engine_free_request_pool(struct intel_engine_cs *engine) 455 { 456 if (!engine->request_pool) 457 return; 458 459 #ifdef __linux__ 460 kmem_cache_free(i915_request_slab_cache(), engine->request_pool); 461 #else 462 pool_put(i915_request_slab_cache(), engine->request_pool); 463 #endif 464 } 465 466 void intel_engines_free(struct intel_gt *gt) 467 { 468 struct intel_engine_cs *engine; 469 enum intel_engine_id id; 470 471 /* Free the requests! dma-resv keeps fences around for an eternity */ 472 rcu_barrier(); 473 474 for_each_engine(engine, gt, id) { 475 intel_engine_free_request_pool(engine); 476 kfree(engine); 477 gt->engine[id] = NULL; 478 } 479 } 480 481 static 482 bool gen11_vdbox_has_sfc(struct drm_i915_private *i915, 483 unsigned int physical_vdbox, 484 unsigned int logical_vdbox, u16 vdbox_mask) 485 { 486 /* 487 * In Gen11, only even numbered logical VDBOXes are hooked 488 * up to an SFC (Scaler & Format Converter) unit. 489 * In Gen12, Even numbered physical instance always are connected 490 * to an SFC. Odd numbered physical instances have SFC only if 491 * previous even instance is fused off. 492 */ 493 if (GRAPHICS_VER(i915) == 12) 494 return (physical_vdbox % 2 == 0) || 495 !(BIT(physical_vdbox - 1) & vdbox_mask); 496 else if (GRAPHICS_VER(i915) == 11) 497 return logical_vdbox % 2 == 0; 498 499 MISSING_CASE(GRAPHICS_VER(i915)); 500 return false; 501 } 502 503 /* 504 * Determine which engines are fused off in our particular hardware. 505 * Note that we have a catch-22 situation where we need to be able to access 506 * the blitter forcewake domain to read the engine fuses, but at the same time 507 * we need to know which engines are available on the system to know which 508 * forcewake domains are present. We solve this by intializing the forcewake 509 * domains based on the full engine mask in the platform capabilities before 510 * calling this function and pruning the domains for fused-off engines 511 * afterwards. 512 */ 513 static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) 514 { 515 struct drm_i915_private *i915 = gt->i915; 516 struct intel_gt_info *info = >->info; 517 struct intel_uncore *uncore = gt->uncore; 518 unsigned int logical_vdbox = 0; 519 unsigned int i; 520 u32 media_fuse; 521 u16 vdbox_mask; 522 u16 vebox_mask; 523 524 info->engine_mask = INTEL_INFO(i915)->platform_engine_mask; 525 526 if (GRAPHICS_VER(i915) < 11) 527 return info->engine_mask; 528 529 /* 530 * On newer platforms the fusing register is called 'enable' and has 531 * enable semantics, while on older platforms it is called 'disable' 532 * and bits have disable semantices. 533 */ 534 media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE); 535 if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) 536 media_fuse = ~media_fuse; 537 538 vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; 539 vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> 540 GEN11_GT_VEBOX_DISABLE_SHIFT; 541 542 for (i = 0; i < I915_MAX_VCS; i++) { 543 if (!HAS_ENGINE(gt, _VCS(i))) { 544 vdbox_mask &= ~BIT(i); 545 continue; 546 } 547 548 if (!(BIT(i) & vdbox_mask)) { 549 info->engine_mask &= ~BIT(_VCS(i)); 550 drm_dbg(&i915->drm, "vcs%u fused off\n", i); 551 continue; 552 } 553 554 if (gen11_vdbox_has_sfc(i915, i, logical_vdbox, vdbox_mask)) 555 gt->info.vdbox_sfc_access |= BIT(i); 556 logical_vdbox++; 557 } 558 drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n", 559 vdbox_mask, VDBOX_MASK(gt)); 560 GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt)); 561 562 for (i = 0; i < I915_MAX_VECS; i++) { 563 if (!HAS_ENGINE(gt, _VECS(i))) { 564 vebox_mask &= ~BIT(i); 565 continue; 566 } 567 568 if (!(BIT(i) & vebox_mask)) { 569 info->engine_mask &= ~BIT(_VECS(i)); 570 drm_dbg(&i915->drm, "vecs%u fused off\n", i); 571 } 572 } 573 drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n", 574 vebox_mask, VEBOX_MASK(gt)); 575 GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt)); 576 577 return info->engine_mask; 578 } 579 580 /** 581 * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers 582 * @gt: pointer to struct intel_gt 583 * 584 * Return: non-zero if the initialization failed. 585 */ 586 int intel_engines_init_mmio(struct intel_gt *gt) 587 { 588 struct drm_i915_private *i915 = gt->i915; 589 const unsigned int engine_mask = init_engine_mask(gt); 590 unsigned int mask = 0; 591 unsigned int i; 592 int err; 593 594 drm_WARN_ON(&i915->drm, engine_mask == 0); 595 drm_WARN_ON(&i915->drm, engine_mask & 596 GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES)); 597 598 if (i915_inject_probe_failure(i915)) 599 return -ENODEV; 600 601 for (i = 0; i < ARRAY_SIZE(intel_engines); i++) { 602 if (!HAS_ENGINE(gt, i)) 603 continue; 604 605 err = intel_engine_setup(gt, i); 606 if (err) 607 goto cleanup; 608 609 mask |= BIT(i); 610 } 611 612 /* 613 * Catch failures to update intel_engines table when the new engines 614 * are added to the driver by a warning and disabling the forgotten 615 * engines. 616 */ 617 if (drm_WARN_ON(&i915->drm, mask != engine_mask)) 618 gt->info.engine_mask = mask; 619 620 gt->info.num_engines = hweight32(mask); 621 622 intel_gt_check_and_clear_faults(gt); 623 624 intel_setup_engine_capabilities(gt); 625 626 intel_uncore_prune_engine_fw_domains(gt->uncore, gt); 627 628 return 0; 629 630 cleanup: 631 intel_engines_free(gt); 632 return err; 633 } 634 635 void intel_engine_init_execlists(struct intel_engine_cs *engine) 636 { 637 struct intel_engine_execlists * const execlists = &engine->execlists; 638 639 execlists->port_mask = 1; 640 GEM_BUG_ON(!is_power_of_2(execlists_num_ports(execlists))); 641 GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS); 642 643 memset(execlists->pending, 0, sizeof(execlists->pending)); 644 execlists->active = 645 memset(execlists->inflight, 0, sizeof(execlists->inflight)); 646 } 647 648 static void cleanup_status_page(struct intel_engine_cs *engine) 649 { 650 struct i915_vma *vma; 651 652 /* Prevent writes into HWSP after returning the page to the system */ 653 intel_engine_set_hwsp_writemask(engine, ~0u); 654 655 vma = fetch_and_zero(&engine->status_page.vma); 656 if (!vma) 657 return; 658 659 if (!HWS_NEEDS_PHYSICAL(engine->i915)) 660 i915_vma_unpin(vma); 661 662 i915_gem_object_unpin_map(vma->obj); 663 i915_gem_object_put(vma->obj); 664 } 665 666 static int pin_ggtt_status_page(struct intel_engine_cs *engine, 667 struct i915_gem_ww_ctx *ww, 668 struct i915_vma *vma) 669 { 670 unsigned int flags; 671 672 if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt)) 673 /* 674 * On g33, we cannot place HWS above 256MiB, so 675 * restrict its pinning to the low mappable arena. 676 * Though this restriction is not documented for 677 * gen4, gen5, or byt, they also behave similarly 678 * and hang if the HWS is placed at the top of the 679 * GTT. To generalise, it appears that all !llc 680 * platforms have issues with us placing the HWS 681 * above the mappable region (even though we never 682 * actually map it). 683 */ 684 flags = PIN_MAPPABLE; 685 else 686 flags = PIN_HIGH; 687 688 return i915_ggtt_pin(vma, ww, 0, flags); 689 } 690 691 static int init_status_page(struct intel_engine_cs *engine) 692 { 693 struct drm_i915_gem_object *obj; 694 struct i915_gem_ww_ctx ww; 695 struct i915_vma *vma; 696 void *vaddr; 697 int ret; 698 699 INIT_LIST_HEAD(&engine->status_page.timelines); 700 701 /* 702 * Though the HWS register does support 36bit addresses, historically 703 * we have had hangs and corruption reported due to wild writes if 704 * the HWS is placed above 4G. We only allow objects to be allocated 705 * in GFP_DMA32 for i965, and no earlier physical address users had 706 * access to more than 4G. 707 */ 708 obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE); 709 if (IS_ERR(obj)) { 710 drm_err(&engine->i915->drm, 711 "Failed to allocate status page\n"); 712 return PTR_ERR(obj); 713 } 714 715 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC); 716 717 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); 718 if (IS_ERR(vma)) { 719 ret = PTR_ERR(vma); 720 goto err_put; 721 } 722 723 i915_gem_ww_ctx_init(&ww, true); 724 retry: 725 ret = i915_gem_object_lock(obj, &ww); 726 if (!ret && !HWS_NEEDS_PHYSICAL(engine->i915)) 727 ret = pin_ggtt_status_page(engine, &ww, vma); 728 if (ret) 729 goto err; 730 731 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); 732 if (IS_ERR(vaddr)) { 733 ret = PTR_ERR(vaddr); 734 goto err_unpin; 735 } 736 737 engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE); 738 engine->status_page.vma = vma; 739 740 err_unpin: 741 if (ret) 742 i915_vma_unpin(vma); 743 err: 744 if (ret == -EDEADLK) { 745 ret = i915_gem_ww_ctx_backoff(&ww); 746 if (!ret) 747 goto retry; 748 } 749 i915_gem_ww_ctx_fini(&ww); 750 err_put: 751 if (ret) 752 i915_gem_object_put(obj); 753 return ret; 754 } 755 756 static int engine_setup_common(struct intel_engine_cs *engine) 757 { 758 int err; 759 760 init_llist_head(&engine->barrier_tasks); 761 762 err = init_status_page(engine); 763 if (err) 764 return err; 765 766 engine->breadcrumbs = intel_breadcrumbs_create(engine); 767 if (!engine->breadcrumbs) { 768 err = -ENOMEM; 769 goto err_status; 770 } 771 772 engine->sched_engine = i915_sched_engine_create(ENGINE_PHYSICAL); 773 if (!engine->sched_engine) { 774 err = -ENOMEM; 775 goto err_sched_engine; 776 } 777 engine->sched_engine->private_data = engine; 778 779 err = intel_engine_init_cmd_parser(engine); 780 if (err) 781 goto err_cmd_parser; 782 783 intel_engine_init_execlists(engine); 784 intel_engine_init__pm(engine); 785 intel_engine_init_retire(engine); 786 787 /* Use the whole device by default */ 788 engine->sseu = 789 intel_sseu_from_device_info(&engine->gt->info.sseu); 790 791 intel_engine_init_workarounds(engine); 792 intel_engine_init_whitelist(engine); 793 intel_engine_init_ctx_wa(engine); 794 795 if (GRAPHICS_VER(engine->i915) >= 12) 796 engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO; 797 798 return 0; 799 800 err_cmd_parser: 801 i915_sched_engine_put(engine->sched_engine); 802 err_sched_engine: 803 intel_breadcrumbs_put(engine->breadcrumbs); 804 err_status: 805 cleanup_status_page(engine); 806 return err; 807 } 808 809 struct measure_breadcrumb { 810 struct i915_request rq; 811 struct intel_ring ring; 812 u32 cs[2048]; 813 }; 814 815 static int measure_breadcrumb_dw(struct intel_context *ce) 816 { 817 struct intel_engine_cs *engine = ce->engine; 818 struct measure_breadcrumb *frame; 819 int dw; 820 821 GEM_BUG_ON(!engine->gt->scratch); 822 823 frame = kzalloc(sizeof(*frame), GFP_KERNEL); 824 if (!frame) 825 return -ENOMEM; 826 827 frame->rq.engine = engine; 828 frame->rq.context = ce; 829 rcu_assign_pointer(frame->rq.timeline, ce->timeline); 830 frame->rq.hwsp_seqno = ce->timeline->hwsp_seqno; 831 832 frame->ring.vaddr = frame->cs; 833 frame->ring.size = sizeof(frame->cs); 834 frame->ring.wrap = 835 BITS_PER_TYPE(frame->ring.size) - ilog2(frame->ring.size); 836 frame->ring.effective_size = frame->ring.size; 837 intel_ring_update_space(&frame->ring); 838 frame->rq.ring = &frame->ring; 839 840 mutex_lock(&ce->timeline->mutex); 841 spin_lock_irq(&engine->sched_engine->lock); 842 843 dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs; 844 845 spin_unlock_irq(&engine->sched_engine->lock); 846 mutex_unlock(&ce->timeline->mutex); 847 848 GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */ 849 850 kfree(frame); 851 return dw; 852 } 853 854 struct intel_context * 855 intel_engine_create_pinned_context(struct intel_engine_cs *engine, 856 struct i915_address_space *vm, 857 unsigned int ring_size, 858 unsigned int hwsp, 859 struct lock_class_key *key, 860 const char *name) 861 { 862 struct intel_context *ce; 863 int err; 864 865 ce = intel_context_create(engine); 866 if (IS_ERR(ce)) 867 return ce; 868 869 __set_bit(CONTEXT_BARRIER_BIT, &ce->flags); 870 ce->timeline = page_pack_bits(NULL, hwsp); 871 ce->ring = NULL; 872 ce->ring_size = ring_size; 873 874 i915_vm_put(ce->vm); 875 ce->vm = i915_vm_get(vm); 876 877 err = intel_context_pin(ce); /* perma-pin so it is always available */ 878 if (err) { 879 intel_context_put(ce); 880 return ERR_PTR(err); 881 } 882 883 list_add_tail(&ce->pinned_contexts_link, &engine->pinned_contexts_list); 884 885 /* 886 * Give our perma-pinned kernel timelines a separate lockdep class, 887 * so that we can use them from within the normal user timelines 888 * should we need to inject GPU operations during their request 889 * construction. 890 */ 891 lockdep_set_class_and_name(&ce->timeline->mutex, key, name); 892 893 return ce; 894 } 895 896 void intel_engine_destroy_pinned_context(struct intel_context *ce) 897 { 898 struct intel_engine_cs *engine = ce->engine; 899 struct i915_vma *hwsp = engine->status_page.vma; 900 901 GEM_BUG_ON(ce->timeline->hwsp_ggtt != hwsp); 902 903 mutex_lock(&hwsp->vm->mutex); 904 list_del(&ce->timeline->engine_link); 905 mutex_unlock(&hwsp->vm->mutex); 906 907 list_del(&ce->pinned_contexts_link); 908 intel_context_unpin(ce); 909 intel_context_put(ce); 910 } 911 912 static struct intel_context * 913 create_kernel_context(struct intel_engine_cs *engine) 914 { 915 static struct lock_class_key kernel; 916 917 return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K, 918 I915_GEM_HWS_SEQNO_ADDR, 919 &kernel, "kernel_context"); 920 } 921 922 /** 923 * intel_engines_init_common - initialize cengine state which might require hw access 924 * @engine: Engine to initialize. 925 * 926 * Initializes @engine@ structure members shared between legacy and execlists 927 * submission modes which do require hardware access. 928 * 929 * Typcally done at later stages of submission mode specific engine setup. 930 * 931 * Returns zero on success or an error code on failure. 932 */ 933 static int engine_init_common(struct intel_engine_cs *engine) 934 { 935 struct intel_context *ce; 936 int ret; 937 938 engine->set_default_submission(engine); 939 940 /* 941 * We may need to do things with the shrinker which 942 * require us to immediately switch back to the default 943 * context. This can cause a problem as pinning the 944 * default context also requires GTT space which may not 945 * be available. To avoid this we always pin the default 946 * context. 947 */ 948 ce = create_kernel_context(engine); 949 if (IS_ERR(ce)) 950 return PTR_ERR(ce); 951 952 ret = measure_breadcrumb_dw(ce); 953 if (ret < 0) 954 goto err_context; 955 956 engine->emit_fini_breadcrumb_dw = ret; 957 engine->kernel_context = ce; 958 959 return 0; 960 961 err_context: 962 intel_engine_destroy_pinned_context(ce); 963 return ret; 964 } 965 966 int intel_engines_init(struct intel_gt *gt) 967 { 968 int (*setup)(struct intel_engine_cs *engine); 969 struct intel_engine_cs *engine; 970 enum intel_engine_id id; 971 int err; 972 973 if (intel_uc_uses_guc_submission(>->uc)) { 974 gt->submission_method = INTEL_SUBMISSION_GUC; 975 setup = intel_guc_submission_setup; 976 } else if (HAS_EXECLISTS(gt->i915)) { 977 gt->submission_method = INTEL_SUBMISSION_ELSP; 978 setup = intel_execlists_submission_setup; 979 } else { 980 gt->submission_method = INTEL_SUBMISSION_RING; 981 setup = intel_ring_submission_setup; 982 } 983 984 for_each_engine(engine, gt, id) { 985 err = engine_setup_common(engine); 986 if (err) 987 return err; 988 989 err = setup(engine); 990 if (err) 991 return err; 992 993 err = engine_init_common(engine); 994 if (err) 995 return err; 996 997 intel_engine_add_user(engine); 998 } 999 1000 return 0; 1001 } 1002 1003 /** 1004 * intel_engines_cleanup_common - cleans up the engine state created by 1005 * the common initiailizers. 1006 * @engine: Engine to cleanup. 1007 * 1008 * This cleans up everything created by the common helpers. 1009 */ 1010 void intel_engine_cleanup_common(struct intel_engine_cs *engine) 1011 { 1012 GEM_BUG_ON(!list_empty(&engine->sched_engine->requests)); 1013 1014 i915_sched_engine_put(engine->sched_engine); 1015 intel_breadcrumbs_put(engine->breadcrumbs); 1016 1017 intel_engine_fini_retire(engine); 1018 intel_engine_cleanup_cmd_parser(engine); 1019 1020 if (engine->default_state) 1021 uao_detach(engine->default_state); 1022 1023 if (engine->kernel_context) 1024 intel_engine_destroy_pinned_context(engine->kernel_context); 1025 1026 GEM_BUG_ON(!llist_empty(&engine->barrier_tasks)); 1027 cleanup_status_page(engine); 1028 1029 intel_wa_list_free(&engine->ctx_wa_list); 1030 intel_wa_list_free(&engine->wa_list); 1031 intel_wa_list_free(&engine->whitelist); 1032 } 1033 1034 /** 1035 * intel_engine_resume - re-initializes the HW state of the engine 1036 * @engine: Engine to resume. 1037 * 1038 * Returns zero on success or an error code on failure. 1039 */ 1040 int intel_engine_resume(struct intel_engine_cs *engine) 1041 { 1042 intel_engine_apply_workarounds(engine); 1043 intel_engine_apply_whitelist(engine); 1044 1045 return engine->resume(engine); 1046 } 1047 1048 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine) 1049 { 1050 struct drm_i915_private *i915 = engine->i915; 1051 1052 u64 acthd; 1053 1054 if (GRAPHICS_VER(i915) >= 8) 1055 acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW); 1056 else if (GRAPHICS_VER(i915) >= 4) 1057 acthd = ENGINE_READ(engine, RING_ACTHD); 1058 else 1059 acthd = ENGINE_READ(engine, ACTHD); 1060 1061 return acthd; 1062 } 1063 1064 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine) 1065 { 1066 u64 bbaddr; 1067 1068 if (GRAPHICS_VER(engine->i915) >= 8) 1069 bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW); 1070 else 1071 bbaddr = ENGINE_READ(engine, RING_BBADDR); 1072 1073 return bbaddr; 1074 } 1075 1076 static unsigned long stop_timeout(const struct intel_engine_cs *engine) 1077 { 1078 if (in_atomic() || irqs_disabled()) /* inside atomic preempt-reset? */ 1079 return 0; 1080 1081 /* 1082 * If we are doing a normal GPU reset, we can take our time and allow 1083 * the engine to quiesce. We've stopped submission to the engine, and 1084 * if we wait long enough an innocent context should complete and 1085 * leave the engine idle. So they should not be caught unaware by 1086 * the forthcoming GPU reset (which usually follows the stop_cs)! 1087 */ 1088 return READ_ONCE(engine->props.stop_timeout_ms); 1089 } 1090 1091 static int __intel_engine_stop_cs(struct intel_engine_cs *engine, 1092 int fast_timeout_us, 1093 int slow_timeout_ms) 1094 { 1095 struct intel_uncore *uncore = engine->uncore; 1096 const i915_reg_t mode = RING_MI_MODE(engine->mmio_base); 1097 int err; 1098 1099 intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); 1100 err = __intel_wait_for_register_fw(engine->uncore, mode, 1101 MODE_IDLE, MODE_IDLE, 1102 fast_timeout_us, 1103 slow_timeout_ms, 1104 NULL); 1105 1106 /* A final mmio read to let GPU writes be hopefully flushed to memory */ 1107 intel_uncore_posting_read_fw(uncore, mode); 1108 return err; 1109 } 1110 1111 int intel_engine_stop_cs(struct intel_engine_cs *engine) 1112 { 1113 int err = 0; 1114 1115 if (GRAPHICS_VER(engine->i915) < 3) 1116 return -ENODEV; 1117 1118 ENGINE_TRACE(engine, "\n"); 1119 if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) { 1120 ENGINE_TRACE(engine, 1121 "timed out on STOP_RING -> IDLE; HEAD:%04x, TAIL:%04x\n", 1122 ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR, 1123 ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR); 1124 1125 /* 1126 * Sometimes we observe that the idle flag is not 1127 * set even though the ring is empty. So double 1128 * check before giving up. 1129 */ 1130 if ((ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) != 1131 (ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR)) 1132 err = -ETIMEDOUT; 1133 } 1134 1135 return err; 1136 } 1137 1138 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine) 1139 { 1140 ENGINE_TRACE(engine, "\n"); 1141 1142 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); 1143 } 1144 1145 const char *i915_cache_level_str(struct drm_i915_private *i915, int type) 1146 { 1147 switch (type) { 1148 case I915_CACHE_NONE: return " uncached"; 1149 case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped"; 1150 case I915_CACHE_L3_LLC: return " L3+LLC"; 1151 case I915_CACHE_WT: return " WT"; 1152 default: return ""; 1153 } 1154 } 1155 1156 static u32 1157 read_subslice_reg(const struct intel_engine_cs *engine, 1158 int slice, int subslice, i915_reg_t reg) 1159 { 1160 return intel_uncore_read_with_mcr_steering(engine->uncore, reg, 1161 slice, subslice); 1162 } 1163 1164 /* NB: please notice the memset */ 1165 void intel_engine_get_instdone(const struct intel_engine_cs *engine, 1166 struct intel_instdone *instdone) 1167 { 1168 struct drm_i915_private *i915 = engine->i915; 1169 const struct sseu_dev_info *sseu = &engine->gt->info.sseu; 1170 struct intel_uncore *uncore = engine->uncore; 1171 u32 mmio_base = engine->mmio_base; 1172 int slice; 1173 int subslice; 1174 1175 memset(instdone, 0, sizeof(*instdone)); 1176 1177 switch (GRAPHICS_VER(i915)) { 1178 default: 1179 instdone->instdone = 1180 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); 1181 1182 if (engine->id != RCS0) 1183 break; 1184 1185 instdone->slice_common = 1186 intel_uncore_read(uncore, GEN7_SC_INSTDONE); 1187 if (GRAPHICS_VER(i915) >= 12) { 1188 instdone->slice_common_extra[0] = 1189 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA); 1190 instdone->slice_common_extra[1] = 1191 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA2); 1192 } 1193 for_each_instdone_slice_subslice(i915, sseu, slice, subslice) { 1194 instdone->sampler[slice][subslice] = 1195 read_subslice_reg(engine, slice, subslice, 1196 GEN7_SAMPLER_INSTDONE); 1197 instdone->row[slice][subslice] = 1198 read_subslice_reg(engine, slice, subslice, 1199 GEN7_ROW_INSTDONE); 1200 } 1201 break; 1202 case 7: 1203 instdone->instdone = 1204 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); 1205 1206 if (engine->id != RCS0) 1207 break; 1208 1209 instdone->slice_common = 1210 intel_uncore_read(uncore, GEN7_SC_INSTDONE); 1211 instdone->sampler[0][0] = 1212 intel_uncore_read(uncore, GEN7_SAMPLER_INSTDONE); 1213 instdone->row[0][0] = 1214 intel_uncore_read(uncore, GEN7_ROW_INSTDONE); 1215 1216 break; 1217 case 6: 1218 case 5: 1219 case 4: 1220 instdone->instdone = 1221 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); 1222 if (engine->id == RCS0) 1223 /* HACK: Using the wrong struct member */ 1224 instdone->slice_common = 1225 intel_uncore_read(uncore, GEN4_INSTDONE1); 1226 break; 1227 case 3: 1228 case 2: 1229 instdone->instdone = intel_uncore_read(uncore, GEN2_INSTDONE); 1230 break; 1231 } 1232 } 1233 1234 static bool ring_is_idle(struct intel_engine_cs *engine) 1235 { 1236 bool idle = true; 1237 1238 if (I915_SELFTEST_ONLY(!engine->mmio_base)) 1239 return true; 1240 1241 if (!intel_engine_pm_get_if_awake(engine)) 1242 return true; 1243 1244 /* First check that no commands are left in the ring */ 1245 if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) != 1246 (ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR)) 1247 idle = false; 1248 1249 /* No bit for gen2, so assume the CS parser is idle */ 1250 if (GRAPHICS_VER(engine->i915) > 2 && 1251 !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE)) 1252 idle = false; 1253 1254 intel_engine_pm_put(engine); 1255 1256 return idle; 1257 } 1258 1259 void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync) 1260 { 1261 struct tasklet_struct *t = &engine->sched_engine->tasklet; 1262 1263 if (!t->callback) 1264 return; 1265 1266 local_bh_disable(); 1267 if (tasklet_trylock(t)) { 1268 /* Must wait for any GPU reset in progress. */ 1269 if (__tasklet_is_enabled(t)) 1270 t->callback(t); 1271 tasklet_unlock(t); 1272 } 1273 local_bh_enable(); 1274 1275 /* Synchronise and wait for the tasklet on another CPU */ 1276 if (sync) 1277 tasklet_unlock_wait(t); 1278 } 1279 1280 /** 1281 * intel_engine_is_idle() - Report if the engine has finished process all work 1282 * @engine: the intel_engine_cs 1283 * 1284 * Return true if there are no requests pending, nothing left to be submitted 1285 * to hardware, and that the engine is idle. 1286 */ 1287 bool intel_engine_is_idle(struct intel_engine_cs *engine) 1288 { 1289 /* More white lies, if wedged, hw state is inconsistent */ 1290 if (intel_gt_is_wedged(engine->gt)) 1291 return true; 1292 1293 if (!intel_engine_pm_is_awake(engine)) 1294 return true; 1295 1296 /* Waiting to drain ELSP? */ 1297 intel_synchronize_hardirq(engine->i915); 1298 intel_engine_flush_submission(engine); 1299 1300 /* ELSP is empty, but there are ready requests? E.g. after reset */ 1301 if (!i915_sched_engine_is_empty(engine->sched_engine)) 1302 return false; 1303 1304 /* Ring stopped? */ 1305 return ring_is_idle(engine); 1306 } 1307 1308 bool intel_engines_are_idle(struct intel_gt *gt) 1309 { 1310 struct intel_engine_cs *engine; 1311 enum intel_engine_id id; 1312 1313 /* 1314 * If the driver is wedged, HW state may be very inconsistent and 1315 * report that it is still busy, even though we have stopped using it. 1316 */ 1317 if (intel_gt_is_wedged(gt)) 1318 return true; 1319 1320 /* Already parked (and passed an idleness test); must still be idle */ 1321 if (!READ_ONCE(gt->awake)) 1322 return true; 1323 1324 for_each_engine(engine, gt, id) { 1325 if (!intel_engine_is_idle(engine)) 1326 return false; 1327 } 1328 1329 return true; 1330 } 1331 1332 bool intel_engine_irq_enable(struct intel_engine_cs *engine) 1333 { 1334 if (!engine->irq_enable) 1335 return false; 1336 1337 /* Caller disables interrupts */ 1338 spin_lock(&engine->gt->irq_lock); 1339 engine->irq_enable(engine); 1340 spin_unlock(&engine->gt->irq_lock); 1341 1342 return true; 1343 } 1344 1345 void intel_engine_irq_disable(struct intel_engine_cs *engine) 1346 { 1347 if (!engine->irq_disable) 1348 return; 1349 1350 /* Caller disables interrupts */ 1351 spin_lock(&engine->gt->irq_lock); 1352 engine->irq_disable(engine); 1353 spin_unlock(&engine->gt->irq_lock); 1354 } 1355 1356 void intel_engines_reset_default_submission(struct intel_gt *gt) 1357 { 1358 struct intel_engine_cs *engine; 1359 enum intel_engine_id id; 1360 1361 for_each_engine(engine, gt, id) { 1362 if (engine->sanitize) 1363 engine->sanitize(engine); 1364 1365 engine->set_default_submission(engine); 1366 } 1367 } 1368 1369 bool intel_engine_can_store_dword(struct intel_engine_cs *engine) 1370 { 1371 switch (GRAPHICS_VER(engine->i915)) { 1372 case 2: 1373 return false; /* uses physical not virtual addresses */ 1374 case 3: 1375 /* maybe only uses physical not virtual addresses */ 1376 return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915)); 1377 case 4: 1378 return !IS_I965G(engine->i915); /* who knows! */ 1379 case 6: 1380 return engine->class != VIDEO_DECODE_CLASS; /* b0rked */ 1381 default: 1382 return true; 1383 } 1384 } 1385 1386 static struct intel_timeline *get_timeline(struct i915_request *rq) 1387 { 1388 struct intel_timeline *tl; 1389 1390 /* 1391 * Even though we are holding the engine->sched_engine->lock here, there 1392 * is no control over the submission queue per-se and we are 1393 * inspecting the active state at a random point in time, with an 1394 * unknown queue. Play safe and make sure the timeline remains valid. 1395 * (Only being used for pretty printing, one extra kref shouldn't 1396 * cause a camel stampede!) 1397 */ 1398 rcu_read_lock(); 1399 tl = rcu_dereference(rq->timeline); 1400 if (!kref_get_unless_zero(&tl->kref)) 1401 tl = NULL; 1402 rcu_read_unlock(); 1403 1404 return tl; 1405 } 1406 1407 static int print_ring(char *buf, int sz, struct i915_request *rq) 1408 { 1409 int len = 0; 1410 1411 if (!i915_request_signaled(rq)) { 1412 struct intel_timeline *tl = get_timeline(rq); 1413 1414 len = scnprintf(buf, sz, 1415 "ring:{start:%08x, hwsp:%08x, seqno:%08x, runtime:%llums}, ", 1416 i915_ggtt_offset(rq->ring->vma), 1417 tl ? tl->hwsp_offset : 0, 1418 hwsp_seqno(rq), 1419 DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context), 1420 1000 * 1000)); 1421 1422 if (tl) 1423 intel_timeline_put(tl); 1424 } 1425 1426 return len; 1427 } 1428 1429 static void hexdump(struct drm_printer *m, const void *buf, size_t len) 1430 { 1431 STUB(); 1432 #ifdef notyet 1433 const size_t rowsize = 8 * sizeof(u32); 1434 const void *prev = NULL; 1435 bool skip = false; 1436 size_t pos; 1437 1438 for (pos = 0; pos < len; pos += rowsize) { 1439 char line[128]; 1440 1441 if (prev && !memcmp(prev, buf + pos, rowsize)) { 1442 if (!skip) { 1443 drm_printf(m, "*\n"); 1444 skip = true; 1445 } 1446 continue; 1447 } 1448 1449 WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos, 1450 rowsize, sizeof(u32), 1451 line, sizeof(line), 1452 false) >= sizeof(line)); 1453 drm_printf(m, "[%04zx] %s\n", pos, line); 1454 1455 prev = buf + pos; 1456 skip = false; 1457 } 1458 #endif 1459 } 1460 1461 static const char *repr_timer(const struct timeout *t) 1462 { 1463 if (!READ_ONCE(t->to_time)) 1464 return "inactive"; 1465 1466 if (timer_pending(t)) 1467 return "active"; 1468 1469 return "expired"; 1470 } 1471 1472 static void intel_engine_print_registers(struct intel_engine_cs *engine, 1473 struct drm_printer *m) 1474 { 1475 struct drm_i915_private *dev_priv = engine->i915; 1476 struct intel_engine_execlists * const execlists = &engine->execlists; 1477 u64 addr; 1478 1479 if (engine->id == RENDER_CLASS && IS_GRAPHICS_VER(dev_priv, 4, 7)) 1480 drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID)); 1481 if (HAS_EXECLISTS(dev_priv)) { 1482 drm_printf(m, "\tEL_STAT_HI: 0x%08x\n", 1483 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI)); 1484 drm_printf(m, "\tEL_STAT_LO: 0x%08x\n", 1485 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO)); 1486 } 1487 drm_printf(m, "\tRING_START: 0x%08x\n", 1488 ENGINE_READ(engine, RING_START)); 1489 drm_printf(m, "\tRING_HEAD: 0x%08x\n", 1490 ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR); 1491 drm_printf(m, "\tRING_TAIL: 0x%08x\n", 1492 ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR); 1493 drm_printf(m, "\tRING_CTL: 0x%08x%s\n", 1494 ENGINE_READ(engine, RING_CTL), 1495 ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : ""); 1496 if (GRAPHICS_VER(engine->i915) > 2) { 1497 drm_printf(m, "\tRING_MODE: 0x%08x%s\n", 1498 ENGINE_READ(engine, RING_MI_MODE), 1499 ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : ""); 1500 } 1501 1502 if (GRAPHICS_VER(dev_priv) >= 6) { 1503 drm_printf(m, "\tRING_IMR: 0x%08x\n", 1504 ENGINE_READ(engine, RING_IMR)); 1505 drm_printf(m, "\tRING_ESR: 0x%08x\n", 1506 ENGINE_READ(engine, RING_ESR)); 1507 drm_printf(m, "\tRING_EMR: 0x%08x\n", 1508 ENGINE_READ(engine, RING_EMR)); 1509 drm_printf(m, "\tRING_EIR: 0x%08x\n", 1510 ENGINE_READ(engine, RING_EIR)); 1511 } 1512 1513 addr = intel_engine_get_active_head(engine); 1514 drm_printf(m, "\tACTHD: 0x%08x_%08x\n", 1515 upper_32_bits(addr), lower_32_bits(addr)); 1516 addr = intel_engine_get_last_batch_head(engine); 1517 drm_printf(m, "\tBBADDR: 0x%08x_%08x\n", 1518 upper_32_bits(addr), lower_32_bits(addr)); 1519 if (GRAPHICS_VER(dev_priv) >= 8) 1520 addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW); 1521 else if (GRAPHICS_VER(dev_priv) >= 4) 1522 addr = ENGINE_READ(engine, RING_DMA_FADD); 1523 else 1524 addr = ENGINE_READ(engine, DMA_FADD_I8XX); 1525 drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n", 1526 upper_32_bits(addr), lower_32_bits(addr)); 1527 if (GRAPHICS_VER(dev_priv) >= 4) { 1528 drm_printf(m, "\tIPEIR: 0x%08x\n", 1529 ENGINE_READ(engine, RING_IPEIR)); 1530 drm_printf(m, "\tIPEHR: 0x%08x\n", 1531 ENGINE_READ(engine, RING_IPEHR)); 1532 } else { 1533 drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR)); 1534 drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR)); 1535 } 1536 1537 if (intel_engine_uses_guc(engine)) { 1538 /* nothing to print yet */ 1539 } else if (HAS_EXECLISTS(dev_priv)) { 1540 struct i915_request * const *port, *rq; 1541 const u32 *hws = 1542 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX]; 1543 const u8 num_entries = execlists->csb_size; 1544 unsigned int idx; 1545 u8 read, write; 1546 1547 drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? %s, timeslice? %s\n", 1548 yesno(test_bit(TASKLET_STATE_SCHED, 1549 &engine->sched_engine->tasklet.state)), 1550 enableddisabled(!atomic_read(&engine->sched_engine->tasklet.count)), 1551 repr_timer(&engine->execlists.preempt), 1552 repr_timer(&engine->execlists.timer)); 1553 1554 read = execlists->csb_head; 1555 write = READ_ONCE(*execlists->csb_write); 1556 1557 drm_printf(m, "\tExeclist status: 0x%08x %08x; CSB read:%d, write:%d, entries:%d\n", 1558 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO), 1559 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI), 1560 read, write, num_entries); 1561 1562 if (read >= num_entries) 1563 read = 0; 1564 if (write >= num_entries) 1565 write = 0; 1566 if (read > write) 1567 write += num_entries; 1568 while (read < write) { 1569 idx = ++read % num_entries; 1570 drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n", 1571 idx, hws[idx * 2], hws[idx * 2 + 1]); 1572 } 1573 1574 i915_sched_engine_active_lock_bh(engine->sched_engine); 1575 rcu_read_lock(); 1576 for (port = execlists->active; (rq = *port); port++) { 1577 char hdr[160]; 1578 int len; 1579 1580 len = scnprintf(hdr, sizeof(hdr), 1581 "\t\tActive[%d]: ccid:%08x%s%s, ", 1582 (int)(port - execlists->active), 1583 rq->context->lrc.ccid, 1584 intel_context_is_closed(rq->context) ? "!" : "", 1585 intel_context_is_banned(rq->context) ? "*" : ""); 1586 len += print_ring(hdr + len, sizeof(hdr) - len, rq); 1587 scnprintf(hdr + len, sizeof(hdr) - len, "rq: "); 1588 i915_request_show(m, rq, hdr, 0); 1589 } 1590 for (port = execlists->pending; (rq = *port); port++) { 1591 char hdr[160]; 1592 int len; 1593 1594 len = scnprintf(hdr, sizeof(hdr), 1595 "\t\tPending[%d]: ccid:%08x%s%s, ", 1596 (int)(port - execlists->pending), 1597 rq->context->lrc.ccid, 1598 intel_context_is_closed(rq->context) ? "!" : "", 1599 intel_context_is_banned(rq->context) ? "*" : ""); 1600 len += print_ring(hdr + len, sizeof(hdr) - len, rq); 1601 scnprintf(hdr + len, sizeof(hdr) - len, "rq: "); 1602 i915_request_show(m, rq, hdr, 0); 1603 } 1604 rcu_read_unlock(); 1605 i915_sched_engine_active_unlock_bh(engine->sched_engine); 1606 } else if (GRAPHICS_VER(dev_priv) > 6) { 1607 drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n", 1608 ENGINE_READ(engine, RING_PP_DIR_BASE)); 1609 drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n", 1610 ENGINE_READ(engine, RING_PP_DIR_BASE_READ)); 1611 drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n", 1612 ENGINE_READ(engine, RING_PP_DIR_DCLV)); 1613 } 1614 } 1615 1616 static void print_request_ring(struct drm_printer *m, struct i915_request *rq) 1617 { 1618 void *ring; 1619 int size; 1620 1621 drm_printf(m, 1622 "[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n", 1623 rq->head, rq->postfix, rq->tail, 1624 rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u, 1625 rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u); 1626 1627 size = rq->tail - rq->head; 1628 if (rq->tail < rq->head) 1629 size += rq->ring->size; 1630 1631 ring = kmalloc(size, GFP_ATOMIC); 1632 if (ring) { 1633 const void *vaddr = rq->ring->vaddr; 1634 unsigned int head = rq->head; 1635 unsigned int len = 0; 1636 1637 if (rq->tail < head) { 1638 len = rq->ring->size - head; 1639 memcpy(ring, vaddr + head, len); 1640 head = 0; 1641 } 1642 memcpy(ring + len, vaddr + head, size - len); 1643 1644 hexdump(m, ring, size); 1645 kfree(ring); 1646 } 1647 } 1648 1649 static unsigned long list_count(struct list_head *list) 1650 { 1651 struct list_head *pos; 1652 unsigned long count = 0; 1653 1654 list_for_each(pos, list) 1655 count++; 1656 1657 return count; 1658 } 1659 1660 static unsigned long read_ul(void *p, size_t x) 1661 { 1662 return *(unsigned long *)(p + x); 1663 } 1664 1665 static void print_properties(struct intel_engine_cs *engine, 1666 struct drm_printer *m) 1667 { 1668 static const struct pmap { 1669 size_t offset; 1670 const char *name; 1671 } props[] = { 1672 #define P(x) { \ 1673 .offset = offsetof(typeof(engine->props), x), \ 1674 .name = #x \ 1675 } 1676 P(heartbeat_interval_ms), 1677 P(max_busywait_duration_ns), 1678 P(preempt_timeout_ms), 1679 P(stop_timeout_ms), 1680 P(timeslice_duration_ms), 1681 1682 {}, 1683 #undef P 1684 }; 1685 const struct pmap *p; 1686 1687 drm_printf(m, "\tProperties:\n"); 1688 for (p = props; p->name; p++) 1689 drm_printf(m, "\t\t%s: %lu [default %lu]\n", 1690 p->name, 1691 read_ul(&engine->props, p->offset), 1692 read_ul(&engine->defaults, p->offset)); 1693 } 1694 1695 static void engine_dump_request(struct i915_request *rq, struct drm_printer *m, const char *msg) 1696 { 1697 struct intel_timeline *tl = get_timeline(rq); 1698 1699 i915_request_show(m, rq, msg, 0); 1700 1701 drm_printf(m, "\t\tring->start: 0x%08x\n", 1702 i915_ggtt_offset(rq->ring->vma)); 1703 drm_printf(m, "\t\tring->head: 0x%08x\n", 1704 rq->ring->head); 1705 drm_printf(m, "\t\tring->tail: 0x%08x\n", 1706 rq->ring->tail); 1707 drm_printf(m, "\t\tring->emit: 0x%08x\n", 1708 rq->ring->emit); 1709 drm_printf(m, "\t\tring->space: 0x%08x\n", 1710 rq->ring->space); 1711 1712 if (tl) { 1713 drm_printf(m, "\t\tring->hwsp: 0x%08x\n", 1714 tl->hwsp_offset); 1715 intel_timeline_put(tl); 1716 } 1717 1718 print_request_ring(m, rq); 1719 1720 if (rq->context->lrc_reg_state) { 1721 drm_printf(m, "Logical Ring Context:\n"); 1722 hexdump(m, rq->context->lrc_reg_state, PAGE_SIZE); 1723 } 1724 } 1725 1726 void intel_engine_dump_active_requests(struct list_head *requests, 1727 struct i915_request *hung_rq, 1728 struct drm_printer *m) 1729 { 1730 struct i915_request *rq; 1731 const char *msg; 1732 enum i915_request_state state; 1733 1734 list_for_each_entry(rq, requests, sched.link) { 1735 if (rq == hung_rq) 1736 continue; 1737 1738 state = i915_test_request_state(rq); 1739 if (state < I915_REQUEST_QUEUED) 1740 continue; 1741 1742 if (state == I915_REQUEST_ACTIVE) 1743 msg = "\t\tactive on engine"; 1744 else 1745 msg = "\t\tactive in queue"; 1746 1747 engine_dump_request(rq, m, msg); 1748 } 1749 } 1750 1751 static void engine_dump_active_requests(struct intel_engine_cs *engine, struct drm_printer *m) 1752 { 1753 struct i915_request *hung_rq = NULL; 1754 struct intel_context *ce; 1755 bool guc; 1756 1757 /* 1758 * No need for an engine->irq_seqno_barrier() before the seqno reads. 1759 * The GPU is still running so requests are still executing and any 1760 * hardware reads will be out of date by the time they are reported. 1761 * But the intention here is just to report an instantaneous snapshot 1762 * so that's fine. 1763 */ 1764 lockdep_assert_held(&engine->sched_engine->lock); 1765 1766 drm_printf(m, "\tRequests:\n"); 1767 1768 guc = intel_uc_uses_guc_submission(&engine->gt->uc); 1769 if (guc) { 1770 ce = intel_engine_get_hung_context(engine); 1771 if (ce) 1772 hung_rq = intel_context_find_active_request(ce); 1773 } else { 1774 hung_rq = intel_engine_execlist_find_hung_request(engine); 1775 } 1776 1777 if (hung_rq) 1778 engine_dump_request(hung_rq, m, "\t\thung"); 1779 1780 if (guc) 1781 intel_guc_dump_active_requests(engine, hung_rq, m); 1782 else 1783 intel_engine_dump_active_requests(&engine->sched_engine->requests, 1784 hung_rq, m); 1785 } 1786 1787 void intel_engine_dump(struct intel_engine_cs *engine, 1788 struct drm_printer *m, 1789 const char *header, ...) 1790 { 1791 struct i915_gpu_error * const error = &engine->i915->gpu_error; 1792 struct i915_request *rq; 1793 intel_wakeref_t wakeref; 1794 unsigned long flags; 1795 ktime_t dummy; 1796 1797 if (header) { 1798 va_list ap; 1799 1800 va_start(ap, header); 1801 drm_vprintf(m, header, &ap); 1802 va_end(ap); 1803 } 1804 1805 if (intel_gt_is_wedged(engine->gt)) 1806 drm_printf(m, "*** WEDGED ***\n"); 1807 1808 drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count)); 1809 drm_printf(m, "\tBarriers?: %s\n", 1810 yesno(!llist_empty(&engine->barrier_tasks))); 1811 drm_printf(m, "\tLatency: %luus\n", 1812 ewma__engine_latency_read(&engine->latency)); 1813 if (intel_engine_supports_stats(engine)) 1814 drm_printf(m, "\tRuntime: %llums\n", 1815 ktime_to_ms(intel_engine_get_busy_time(engine, 1816 &dummy))); 1817 drm_printf(m, "\tForcewake: %x domains, %d active\n", 1818 engine->fw_domain, READ_ONCE(engine->fw_active)); 1819 1820 rcu_read_lock(); 1821 rq = READ_ONCE(engine->heartbeat.systole); 1822 if (rq) 1823 drm_printf(m, "\tHeartbeat: %d ms ago\n", 1824 jiffies_to_msecs(jiffies - rq->emitted_jiffies)); 1825 rcu_read_unlock(); 1826 drm_printf(m, "\tReset count: %d (global %d)\n", 1827 i915_reset_engine_count(error, engine), 1828 i915_reset_count(error)); 1829 print_properties(engine, m); 1830 1831 spin_lock_irqsave(&engine->sched_engine->lock, flags); 1832 engine_dump_active_requests(engine, m); 1833 1834 drm_printf(m, "\tOn hold?: %lu\n", 1835 list_count(&engine->sched_engine->hold)); 1836 spin_unlock_irqrestore(&engine->sched_engine->lock, flags); 1837 1838 drm_printf(m, "\tMMIO base: 0x%08x\n", engine->mmio_base); 1839 wakeref = intel_runtime_pm_get_if_in_use(engine->uncore->rpm); 1840 if (wakeref) { 1841 intel_engine_print_registers(engine, m); 1842 intel_runtime_pm_put(engine->uncore->rpm, wakeref); 1843 } else { 1844 drm_printf(m, "\tDevice is asleep; skipping register dump\n"); 1845 } 1846 1847 intel_execlists_show_requests(engine, m, i915_request_show, 8); 1848 1849 drm_printf(m, "HWSP:\n"); 1850 hexdump(m, engine->status_page.addr, PAGE_SIZE); 1851 1852 drm_printf(m, "Idle? %s\n", yesno(intel_engine_is_idle(engine))); 1853 1854 intel_engine_print_breadcrumbs(engine, m); 1855 } 1856 1857 static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine, 1858 ktime_t *now) 1859 { 1860 ktime_t total = engine->stats.total; 1861 1862 /* 1863 * If the engine is executing something at the moment 1864 * add it to the total. 1865 */ 1866 *now = ktime_get(); 1867 if (READ_ONCE(engine->stats.active)) 1868 total = ktime_add(total, ktime_sub(*now, engine->stats.start)); 1869 1870 return total; 1871 } 1872 1873 /** 1874 * intel_engine_get_busy_time() - Return current accumulated engine busyness 1875 * @engine: engine to report on 1876 * @now: monotonic timestamp of sampling 1877 * 1878 * Returns accumulated time @engine was busy since engine stats were enabled. 1879 */ 1880 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now) 1881 { 1882 unsigned int seq; 1883 ktime_t total; 1884 1885 do { 1886 seq = read_seqcount_begin(&engine->stats.lock); 1887 total = __intel_engine_get_busy_time(engine, now); 1888 } while (read_seqcount_retry(&engine->stats.lock, seq)); 1889 1890 return total; 1891 } 1892 1893 struct intel_context * 1894 intel_engine_create_virtual(struct intel_engine_cs **siblings, 1895 unsigned int count) 1896 { 1897 if (count == 0) 1898 return ERR_PTR(-EINVAL); 1899 1900 if (count == 1) 1901 return intel_context_create(siblings[0]); 1902 1903 GEM_BUG_ON(!siblings[0]->cops->create_virtual); 1904 return siblings[0]->cops->create_virtual(siblings, count); 1905 } 1906 1907 struct i915_request * 1908 intel_engine_execlist_find_hung_request(struct intel_engine_cs *engine) 1909 { 1910 struct i915_request *request, *active = NULL; 1911 1912 /* 1913 * This search does not work in GuC submission mode. However, the GuC 1914 * will report the hanging context directly to the driver itself. So 1915 * the driver should never get here when in GuC mode. 1916 */ 1917 GEM_BUG_ON(intel_uc_uses_guc_submission(&engine->gt->uc)); 1918 1919 /* 1920 * We are called by the error capture, reset and to dump engine 1921 * state at random points in time. In particular, note that neither is 1922 * crucially ordered with an interrupt. After a hang, the GPU is dead 1923 * and we assume that no more writes can happen (we waited long enough 1924 * for all writes that were in transaction to be flushed) - adding an 1925 * extra delay for a recent interrupt is pointless. Hence, we do 1926 * not need an engine->irq_seqno_barrier() before the seqno reads. 1927 * At all other times, we must assume the GPU is still running, but 1928 * we only care about the snapshot of this moment. 1929 */ 1930 lockdep_assert_held(&engine->sched_engine->lock); 1931 1932 rcu_read_lock(); 1933 request = execlists_active(&engine->execlists); 1934 if (request) { 1935 struct intel_timeline *tl = request->context->timeline; 1936 1937 list_for_each_entry_from_reverse(request, &tl->requests, link) { 1938 if (__i915_request_is_complete(request)) 1939 break; 1940 1941 active = request; 1942 } 1943 } 1944 rcu_read_unlock(); 1945 if (active) 1946 return active; 1947 1948 list_for_each_entry(request, &engine->sched_engine->requests, 1949 sched.link) { 1950 if (i915_test_request_state(request) != I915_REQUEST_ACTIVE) 1951 continue; 1952 1953 active = request; 1954 break; 1955 } 1956 1957 return active; 1958 } 1959 1960 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 1961 #include "mock_engine.c" 1962 #include "selftest_engine.c" 1963 #include "selftest_engine_cs.c" 1964 #endif 1965