1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2016 Intel Corporation 4 */ 5 6 #include <linux/string_helpers.h> 7 8 #include <drm/drm_print.h> 9 10 #include "gem/i915_gem_context.h" 11 #include "gem/i915_gem_internal.h" 12 #include "gt/intel_gt_regs.h" 13 14 #include "i915_cmd_parser.h" 15 #include "i915_drv.h" 16 #include "intel_breadcrumbs.h" 17 #include "intel_context.h" 18 #include "intel_engine.h" 19 #include "intel_engine_pm.h" 20 #include "intel_engine_regs.h" 21 #include "intel_engine_user.h" 22 #include "intel_execlists_submission.h" 23 #include "intel_gt.h" 24 #include "intel_gt_mcr.h" 25 #include "intel_gt_pm.h" 26 #include "intel_gt_requests.h" 27 #include "intel_lrc.h" 28 #include "intel_lrc_reg.h" 29 #include "intel_reset.h" 30 #include "intel_ring.h" 31 #include "uc/intel_guc_submission.h" 32 33 /* Haswell does have the CXT_SIZE register however it does not appear to be 34 * valid. Now, docs explain in dwords what is in the context object. The full 35 * size is 70720 bytes, however, the power context and execlist context will 36 * never be saved (power context is stored elsewhere, and execlists don't work 37 * on HSW) - so the final size, including the extra state required for the 38 * Resource Streamer, is 66944 bytes, which rounds to 17 pages. 39 */ 40 #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) 41 42 #define DEFAULT_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) 43 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) 44 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) 45 #define GEN11_LR_CONTEXT_RENDER_SIZE (14 * PAGE_SIZE) 46 47 #define GEN8_LR_CONTEXT_OTHER_SIZE ( 2 * PAGE_SIZE) 48 49 #define MAX_MMIO_BASES 3 50 struct engine_info { 51 u8 class; 52 u8 instance; 53 /* mmio bases table *must* be sorted in reverse graphics_ver order */ 54 struct engine_mmio_base { 55 u32 graphics_ver : 8; 56 u32 base : 24; 57 } mmio_bases[MAX_MMIO_BASES]; 58 }; 59 60 static const struct engine_info intel_engines[] = { 61 [RCS0] = { 62 .class = RENDER_CLASS, 63 .instance = 0, 64 .mmio_bases = { 65 { .graphics_ver = 1, .base = RENDER_RING_BASE } 66 }, 67 }, 68 [BCS0] = { 69 .class = COPY_ENGINE_CLASS, 70 .instance = 0, 71 .mmio_bases = { 72 { .graphics_ver = 6, .base = BLT_RING_BASE } 73 }, 74 }, 75 [BCS1] = { 76 .class = COPY_ENGINE_CLASS, 77 .instance = 1, 78 .mmio_bases = { 79 { .graphics_ver = 12, .base = XEHPC_BCS1_RING_BASE } 80 }, 81 }, 82 [BCS2] = { 83 .class = COPY_ENGINE_CLASS, 84 .instance = 2, 85 .mmio_bases = { 86 { .graphics_ver = 12, .base = XEHPC_BCS2_RING_BASE } 87 }, 88 }, 89 [BCS3] = { 90 .class = COPY_ENGINE_CLASS, 91 .instance = 3, 92 .mmio_bases = { 93 { .graphics_ver = 12, .base = XEHPC_BCS3_RING_BASE } 94 }, 95 }, 96 [BCS4] = { 97 .class = COPY_ENGINE_CLASS, 98 .instance = 4, 99 .mmio_bases = { 100 { .graphics_ver = 12, .base = XEHPC_BCS4_RING_BASE } 101 }, 102 }, 103 [BCS5] = { 104 .class = COPY_ENGINE_CLASS, 105 .instance = 5, 106 .mmio_bases = { 107 { .graphics_ver = 12, .base = XEHPC_BCS5_RING_BASE } 108 }, 109 }, 110 [BCS6] = { 111 .class = COPY_ENGINE_CLASS, 112 .instance = 6, 113 .mmio_bases = { 114 { .graphics_ver = 12, .base = XEHPC_BCS6_RING_BASE } 115 }, 116 }, 117 [BCS7] = { 118 .class = COPY_ENGINE_CLASS, 119 .instance = 7, 120 .mmio_bases = { 121 { .graphics_ver = 12, .base = XEHPC_BCS7_RING_BASE } 122 }, 123 }, 124 [BCS8] = { 125 .class = COPY_ENGINE_CLASS, 126 .instance = 8, 127 .mmio_bases = { 128 { .graphics_ver = 12, .base = XEHPC_BCS8_RING_BASE } 129 }, 130 }, 131 [VCS0] = { 132 .class = VIDEO_DECODE_CLASS, 133 .instance = 0, 134 .mmio_bases = { 135 { .graphics_ver = 11, .base = GEN11_BSD_RING_BASE }, 136 { .graphics_ver = 6, .base = GEN6_BSD_RING_BASE }, 137 { .graphics_ver = 4, .base = BSD_RING_BASE } 138 }, 139 }, 140 [VCS1] = { 141 .class = VIDEO_DECODE_CLASS, 142 .instance = 1, 143 .mmio_bases = { 144 { .graphics_ver = 11, .base = GEN11_BSD2_RING_BASE }, 145 { .graphics_ver = 8, .base = GEN8_BSD2_RING_BASE } 146 }, 147 }, 148 [VCS2] = { 149 .class = VIDEO_DECODE_CLASS, 150 .instance = 2, 151 .mmio_bases = { 152 { .graphics_ver = 11, .base = GEN11_BSD3_RING_BASE } 153 }, 154 }, 155 [VCS3] = { 156 .class = VIDEO_DECODE_CLASS, 157 .instance = 3, 158 .mmio_bases = { 159 { .graphics_ver = 11, .base = GEN11_BSD4_RING_BASE } 160 }, 161 }, 162 [VCS4] = { 163 .class = VIDEO_DECODE_CLASS, 164 .instance = 4, 165 .mmio_bases = { 166 { .graphics_ver = 12, .base = XEHP_BSD5_RING_BASE } 167 }, 168 }, 169 [VCS5] = { 170 .class = VIDEO_DECODE_CLASS, 171 .instance = 5, 172 .mmio_bases = { 173 { .graphics_ver = 12, .base = XEHP_BSD6_RING_BASE } 174 }, 175 }, 176 [VCS6] = { 177 .class = VIDEO_DECODE_CLASS, 178 .instance = 6, 179 .mmio_bases = { 180 { .graphics_ver = 12, .base = XEHP_BSD7_RING_BASE } 181 }, 182 }, 183 [VCS7] = { 184 .class = VIDEO_DECODE_CLASS, 185 .instance = 7, 186 .mmio_bases = { 187 { .graphics_ver = 12, .base = XEHP_BSD8_RING_BASE } 188 }, 189 }, 190 [VECS0] = { 191 .class = VIDEO_ENHANCEMENT_CLASS, 192 .instance = 0, 193 .mmio_bases = { 194 { .graphics_ver = 11, .base = GEN11_VEBOX_RING_BASE }, 195 { .graphics_ver = 7, .base = VEBOX_RING_BASE } 196 }, 197 }, 198 [VECS1] = { 199 .class = VIDEO_ENHANCEMENT_CLASS, 200 .instance = 1, 201 .mmio_bases = { 202 { .graphics_ver = 11, .base = GEN11_VEBOX2_RING_BASE } 203 }, 204 }, 205 [VECS2] = { 206 .class = VIDEO_ENHANCEMENT_CLASS, 207 .instance = 2, 208 .mmio_bases = { 209 { .graphics_ver = 12, .base = XEHP_VEBOX3_RING_BASE } 210 }, 211 }, 212 [VECS3] = { 213 .class = VIDEO_ENHANCEMENT_CLASS, 214 .instance = 3, 215 .mmio_bases = { 216 { .graphics_ver = 12, .base = XEHP_VEBOX4_RING_BASE } 217 }, 218 }, 219 [CCS0] = { 220 .class = COMPUTE_CLASS, 221 .instance = 0, 222 .mmio_bases = { 223 { .graphics_ver = 12, .base = GEN12_COMPUTE0_RING_BASE } 224 } 225 }, 226 [CCS1] = { 227 .class = COMPUTE_CLASS, 228 .instance = 1, 229 .mmio_bases = { 230 { .graphics_ver = 12, .base = GEN12_COMPUTE1_RING_BASE } 231 } 232 }, 233 [CCS2] = { 234 .class = COMPUTE_CLASS, 235 .instance = 2, 236 .mmio_bases = { 237 { .graphics_ver = 12, .base = GEN12_COMPUTE2_RING_BASE } 238 } 239 }, 240 [CCS3] = { 241 .class = COMPUTE_CLASS, 242 .instance = 3, 243 .mmio_bases = { 244 { .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE } 245 } 246 }, 247 }; 248 249 /** 250 * intel_engine_context_size() - return the size of the context for an engine 251 * @gt: the gt 252 * @class: engine class 253 * 254 * Each engine class may require a different amount of space for a context 255 * image. 256 * 257 * Return: size (in bytes) of an engine class specific context image 258 * 259 * Note: this size includes the HWSP, which is part of the context image 260 * in LRC mode, but does not include the "shared data page" used with 261 * GuC submission. The caller should account for this if using the GuC. 262 */ 263 u32 intel_engine_context_size(struct intel_gt *gt, u8 class) 264 { 265 struct intel_uncore *uncore = gt->uncore; 266 u32 cxt_size; 267 268 BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE); 269 270 switch (class) { 271 case COMPUTE_CLASS: 272 fallthrough; 273 case RENDER_CLASS: 274 switch (GRAPHICS_VER(gt->i915)) { 275 default: 276 MISSING_CASE(GRAPHICS_VER(gt->i915)); 277 return DEFAULT_LR_CONTEXT_RENDER_SIZE; 278 case 12: 279 case 11: 280 return GEN11_LR_CONTEXT_RENDER_SIZE; 281 case 9: 282 return GEN9_LR_CONTEXT_RENDER_SIZE; 283 case 8: 284 return GEN8_LR_CONTEXT_RENDER_SIZE; 285 case 7: 286 if (IS_HASWELL(gt->i915)) 287 return HSW_CXT_TOTAL_SIZE; 288 289 cxt_size = intel_uncore_read(uncore, GEN7_CXT_SIZE); 290 return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64, 291 PAGE_SIZE); 292 case 6: 293 cxt_size = intel_uncore_read(uncore, CXT_SIZE); 294 return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64, 295 PAGE_SIZE); 296 case 5: 297 case 4: 298 /* 299 * There is a discrepancy here between the size reported 300 * by the register and the size of the context layout 301 * in the docs. Both are described as authorative! 302 * 303 * The discrepancy is on the order of a few cachelines, 304 * but the total is under one page (4k), which is our 305 * minimum allocation anyway so it should all come 306 * out in the wash. 307 */ 308 cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1; 309 drm_dbg(>->i915->drm, 310 "graphics_ver = %d CXT_SIZE = %d bytes [0x%08x]\n", 311 GRAPHICS_VER(gt->i915), cxt_size * 64, 312 cxt_size - 1); 313 return round_up(cxt_size * 64, PAGE_SIZE); 314 case 3: 315 case 2: 316 /* For the special day when i810 gets merged. */ 317 case 1: 318 return 0; 319 } 320 break; 321 default: 322 MISSING_CASE(class); 323 fallthrough; 324 case VIDEO_DECODE_CLASS: 325 case VIDEO_ENHANCEMENT_CLASS: 326 case COPY_ENGINE_CLASS: 327 if (GRAPHICS_VER(gt->i915) < 8) 328 return 0; 329 return GEN8_LR_CONTEXT_OTHER_SIZE; 330 } 331 } 332 333 static u32 __engine_mmio_base(struct drm_i915_private *i915, 334 const struct engine_mmio_base *bases) 335 { 336 int i; 337 338 for (i = 0; i < MAX_MMIO_BASES; i++) 339 if (GRAPHICS_VER(i915) >= bases[i].graphics_ver) 340 break; 341 342 GEM_BUG_ON(i == MAX_MMIO_BASES); 343 GEM_BUG_ON(!bases[i].base); 344 345 return bases[i].base; 346 } 347 348 static void __sprint_engine_name(struct intel_engine_cs *engine) 349 { 350 /* 351 * Before we know what the uABI name for this engine will be, 352 * we still would like to keep track of this engine in the debug logs. 353 * We throw in a ' here as a reminder that this isn't its final name. 354 */ 355 GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u", 356 intel_engine_class_repr(engine->class), 357 engine->instance) >= sizeof(engine->name)); 358 } 359 360 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask) 361 { 362 /* 363 * Though they added more rings on g4x/ilk, they did not add 364 * per-engine HWSTAM until gen6. 365 */ 366 if (GRAPHICS_VER(engine->i915) < 6 && engine->class != RENDER_CLASS) 367 return; 368 369 if (GRAPHICS_VER(engine->i915) >= 3) 370 ENGINE_WRITE(engine, RING_HWSTAM, mask); 371 else 372 ENGINE_WRITE16(engine, RING_HWSTAM, mask); 373 } 374 375 static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine) 376 { 377 /* Mask off all writes into the unknown HWSP */ 378 intel_engine_set_hwsp_writemask(engine, ~0u); 379 } 380 381 static void nop_irq_handler(struct intel_engine_cs *engine, u16 iir) 382 { 383 GEM_DEBUG_WARN_ON(iir); 384 } 385 386 static u32 get_reset_domain(u8 ver, enum intel_engine_id id) 387 { 388 u32 reset_domain; 389 390 if (ver >= 11) { 391 static const u32 engine_reset_domains[] = { 392 [RCS0] = GEN11_GRDOM_RENDER, 393 [BCS0] = GEN11_GRDOM_BLT, 394 [BCS1] = XEHPC_GRDOM_BLT1, 395 [BCS2] = XEHPC_GRDOM_BLT2, 396 [BCS3] = XEHPC_GRDOM_BLT3, 397 [BCS4] = XEHPC_GRDOM_BLT4, 398 [BCS5] = XEHPC_GRDOM_BLT5, 399 [BCS6] = XEHPC_GRDOM_BLT6, 400 [BCS7] = XEHPC_GRDOM_BLT7, 401 [BCS8] = XEHPC_GRDOM_BLT8, 402 [VCS0] = GEN11_GRDOM_MEDIA, 403 [VCS1] = GEN11_GRDOM_MEDIA2, 404 [VCS2] = GEN11_GRDOM_MEDIA3, 405 [VCS3] = GEN11_GRDOM_MEDIA4, 406 [VCS4] = GEN11_GRDOM_MEDIA5, 407 [VCS5] = GEN11_GRDOM_MEDIA6, 408 [VCS6] = GEN11_GRDOM_MEDIA7, 409 [VCS7] = GEN11_GRDOM_MEDIA8, 410 [VECS0] = GEN11_GRDOM_VECS, 411 [VECS1] = GEN11_GRDOM_VECS2, 412 [VECS2] = GEN11_GRDOM_VECS3, 413 [VECS3] = GEN11_GRDOM_VECS4, 414 [CCS0] = GEN11_GRDOM_RENDER, 415 [CCS1] = GEN11_GRDOM_RENDER, 416 [CCS2] = GEN11_GRDOM_RENDER, 417 [CCS3] = GEN11_GRDOM_RENDER, 418 }; 419 GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) || 420 !engine_reset_domains[id]); 421 reset_domain = engine_reset_domains[id]; 422 } else { 423 static const u32 engine_reset_domains[] = { 424 [RCS0] = GEN6_GRDOM_RENDER, 425 [BCS0] = GEN6_GRDOM_BLT, 426 [VCS0] = GEN6_GRDOM_MEDIA, 427 [VCS1] = GEN8_GRDOM_MEDIA2, 428 [VECS0] = GEN6_GRDOM_VECS, 429 }; 430 GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) || 431 !engine_reset_domains[id]); 432 reset_domain = engine_reset_domains[id]; 433 } 434 435 return reset_domain; 436 } 437 438 static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id, 439 u8 logical_instance) 440 { 441 const struct engine_info *info = &intel_engines[id]; 442 struct drm_i915_private *i915 = gt->i915; 443 struct intel_engine_cs *engine; 444 u8 guc_class; 445 446 BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH)); 447 BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH)); 448 BUILD_BUG_ON(I915_MAX_VCS > (MAX_ENGINE_INSTANCE + 1)); 449 BUILD_BUG_ON(I915_MAX_VECS > (MAX_ENGINE_INSTANCE + 1)); 450 451 if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine))) 452 return -EINVAL; 453 454 if (GEM_DEBUG_WARN_ON(info->class > MAX_ENGINE_CLASS)) 455 return -EINVAL; 456 457 if (GEM_DEBUG_WARN_ON(info->instance > MAX_ENGINE_INSTANCE)) 458 return -EINVAL; 459 460 if (GEM_DEBUG_WARN_ON(gt->engine_class[info->class][info->instance])) 461 return -EINVAL; 462 463 engine = kzalloc(sizeof(*engine), GFP_KERNEL); 464 if (!engine) 465 return -ENOMEM; 466 467 BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES); 468 469 INIT_LIST_HEAD(&engine->pinned_contexts_list); 470 engine->id = id; 471 engine->legacy_idx = INVALID_ENGINE; 472 engine->mask = BIT(id); 473 engine->reset_domain = get_reset_domain(GRAPHICS_VER(gt->i915), 474 id); 475 engine->i915 = i915; 476 engine->gt = gt; 477 engine->uncore = gt->uncore; 478 guc_class = engine_class_to_guc_class(info->class); 479 engine->guc_id = MAKE_GUC_ID(guc_class, info->instance); 480 engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases); 481 482 engine->irq_handler = nop_irq_handler; 483 484 engine->class = info->class; 485 engine->instance = info->instance; 486 engine->logical_mask = BIT(logical_instance); 487 __sprint_engine_name(engine); 488 489 if ((engine->class == COMPUTE_CLASS && !RCS_MASK(engine->gt) && 490 __ffs(CCS_MASK(engine->gt)) == engine->instance) || 491 engine->class == RENDER_CLASS) 492 engine->flags |= I915_ENGINE_FIRST_RENDER_COMPUTE; 493 494 /* features common between engines sharing EUs */ 495 if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) { 496 engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE; 497 engine->flags |= I915_ENGINE_HAS_EU_PRIORITY; 498 } 499 500 engine->props.heartbeat_interval_ms = 501 CONFIG_DRM_I915_HEARTBEAT_INTERVAL; 502 engine->props.max_busywait_duration_ns = 503 CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT; 504 engine->props.preempt_timeout_ms = 505 CONFIG_DRM_I915_PREEMPT_TIMEOUT; 506 engine->props.stop_timeout_ms = 507 CONFIG_DRM_I915_STOP_TIMEOUT; 508 engine->props.timeslice_duration_ms = 509 CONFIG_DRM_I915_TIMESLICE_DURATION; 510 511 /* Override to uninterruptible for OpenCL workloads. */ 512 if (GRAPHICS_VER(i915) == 12 && (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)) 513 engine->props.preempt_timeout_ms = 0; 514 515 /* Cap properties according to any system limits */ 516 #define CLAMP_PROP(field) \ 517 do { \ 518 u64 clamp = intel_clamp_##field(engine, engine->props.field); \ 519 if (clamp != engine->props.field) { \ 520 drm_notice(&engine->i915->drm, \ 521 "Warning, clamping %s to %lld to prevent overflow\n", \ 522 #field, clamp); \ 523 engine->props.field = clamp; \ 524 } \ 525 } while (0) 526 527 CLAMP_PROP(heartbeat_interval_ms); 528 CLAMP_PROP(max_busywait_duration_ns); 529 CLAMP_PROP(preempt_timeout_ms); 530 CLAMP_PROP(stop_timeout_ms); 531 CLAMP_PROP(timeslice_duration_ms); 532 533 #undef CLAMP_PROP 534 535 engine->defaults = engine->props; /* never to change again */ 536 537 engine->context_size = intel_engine_context_size(gt, engine->class); 538 if (WARN_ON(engine->context_size > BIT(20))) 539 engine->context_size = 0; 540 if (engine->context_size) 541 DRIVER_CAPS(i915)->has_logical_contexts = true; 542 543 ewma__engine_latency_init(&engine->latency); 544 545 ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier); 546 547 /* Scrub mmio state on takeover */ 548 intel_engine_sanitize_mmio(engine); 549 550 gt->engine_class[info->class][info->instance] = engine; 551 gt->engine[id] = engine; 552 553 return 0; 554 } 555 556 u64 intel_clamp_heartbeat_interval_ms(struct intel_engine_cs *engine, u64 value) 557 { 558 value = min_t(u64, value, jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT)); 559 560 return value; 561 } 562 563 u64 intel_clamp_max_busywait_duration_ns(struct intel_engine_cs *engine, u64 value) 564 { 565 value = min(value, jiffies_to_nsecs(2)); 566 567 return value; 568 } 569 570 u64 intel_clamp_preempt_timeout_ms(struct intel_engine_cs *engine, u64 value) 571 { 572 /* 573 * NB: The GuC API only supports 32bit values. However, the limit is further 574 * reduced due to internal calculations which would otherwise overflow. 575 */ 576 if (intel_guc_submission_is_wanted(&engine->gt->uc.guc)) 577 value = min_t(u64, value, guc_policy_max_preempt_timeout_ms()); 578 579 value = min_t(u64, value, jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT)); 580 581 return value; 582 } 583 584 u64 intel_clamp_stop_timeout_ms(struct intel_engine_cs *engine, u64 value) 585 { 586 value = min_t(u64, value, jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT)); 587 588 return value; 589 } 590 591 u64 intel_clamp_timeslice_duration_ms(struct intel_engine_cs *engine, u64 value) 592 { 593 /* 594 * NB: The GuC API only supports 32bit values. However, the limit is further 595 * reduced due to internal calculations which would otherwise overflow. 596 */ 597 if (intel_guc_submission_is_wanted(&engine->gt->uc.guc)) 598 value = min_t(u64, value, guc_policy_max_exec_quantum_ms()); 599 600 value = min_t(u64, value, jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT)); 601 602 return value; 603 } 604 605 static void __setup_engine_capabilities(struct intel_engine_cs *engine) 606 { 607 struct drm_i915_private *i915 = engine->i915; 608 609 if (engine->class == VIDEO_DECODE_CLASS) { 610 /* 611 * HEVC support is present on first engine instance 612 * before Gen11 and on all instances afterwards. 613 */ 614 if (GRAPHICS_VER(i915) >= 11 || 615 (GRAPHICS_VER(i915) >= 9 && engine->instance == 0)) 616 engine->uabi_capabilities |= 617 I915_VIDEO_CLASS_CAPABILITY_HEVC; 618 619 /* 620 * SFC block is present only on even logical engine 621 * instances. 622 */ 623 if ((GRAPHICS_VER(i915) >= 11 && 624 (engine->gt->info.vdbox_sfc_access & 625 BIT(engine->instance))) || 626 (GRAPHICS_VER(i915) >= 9 && engine->instance == 0)) 627 engine->uabi_capabilities |= 628 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC; 629 } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) { 630 if (GRAPHICS_VER(i915) >= 9 && 631 engine->gt->info.sfc_mask & BIT(engine->instance)) 632 engine->uabi_capabilities |= 633 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC; 634 } 635 } 636 637 static void intel_setup_engine_capabilities(struct intel_gt *gt) 638 { 639 struct intel_engine_cs *engine; 640 enum intel_engine_id id; 641 642 for_each_engine(engine, gt, id) 643 __setup_engine_capabilities(engine); 644 } 645 646 /** 647 * intel_engines_release() - free the resources allocated for Command Streamers 648 * @gt: pointer to struct intel_gt 649 */ 650 void intel_engines_release(struct intel_gt *gt) 651 { 652 struct intel_engine_cs *engine; 653 enum intel_engine_id id; 654 655 /* 656 * Before we release the resources held by engine, we must be certain 657 * that the HW is no longer accessing them -- having the GPU scribble 658 * to or read from a page being used for something else causes no end 659 * of fun. 660 * 661 * The GPU should be reset by this point, but assume the worst just 662 * in case we aborted before completely initialising the engines. 663 */ 664 GEM_BUG_ON(intel_gt_pm_is_awake(gt)); 665 if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) 666 __intel_gt_reset(gt, ALL_ENGINES); 667 668 /* Decouple the backend; but keep the layout for late GPU resets */ 669 for_each_engine(engine, gt, id) { 670 if (!engine->release) 671 continue; 672 673 intel_wakeref_wait_for_idle(&engine->wakeref); 674 GEM_BUG_ON(intel_engine_pm_is_awake(engine)); 675 676 engine->release(engine); 677 engine->release = NULL; 678 679 memset(&engine->reset, 0, sizeof(engine->reset)); 680 } 681 } 682 683 void intel_engine_free_request_pool(struct intel_engine_cs *engine) 684 { 685 if (!engine->request_pool) 686 return; 687 688 #ifdef __linux__ 689 kmem_cache_free(i915_request_slab_cache(), engine->request_pool); 690 #else 691 pool_put(i915_request_slab_cache(), engine->request_pool); 692 #endif 693 } 694 695 void intel_engines_free(struct intel_gt *gt) 696 { 697 struct intel_engine_cs *engine; 698 enum intel_engine_id id; 699 700 /* Free the requests! dma-resv keeps fences around for an eternity */ 701 rcu_barrier(); 702 703 for_each_engine(engine, gt, id) { 704 intel_engine_free_request_pool(engine); 705 kfree(engine); 706 gt->engine[id] = NULL; 707 } 708 } 709 710 static 711 bool gen11_vdbox_has_sfc(struct intel_gt *gt, 712 unsigned int physical_vdbox, 713 unsigned int logical_vdbox, u16 vdbox_mask) 714 { 715 struct drm_i915_private *i915 = gt->i915; 716 717 /* 718 * In Gen11, only even numbered logical VDBOXes are hooked 719 * up to an SFC (Scaler & Format Converter) unit. 720 * In Gen12, Even numbered physical instance always are connected 721 * to an SFC. Odd numbered physical instances have SFC only if 722 * previous even instance is fused off. 723 * 724 * Starting with Xe_HP, there's also a dedicated SFC_ENABLE field 725 * in the fuse register that tells us whether a specific SFC is present. 726 */ 727 if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0) 728 return false; 729 else if (MEDIA_VER(i915) >= 12) 730 return (physical_vdbox % 2 == 0) || 731 !(BIT(physical_vdbox - 1) & vdbox_mask); 732 else if (MEDIA_VER(i915) == 11) 733 return logical_vdbox % 2 == 0; 734 735 return false; 736 } 737 738 static void engine_mask_apply_media_fuses(struct intel_gt *gt) 739 { 740 struct drm_i915_private *i915 = gt->i915; 741 unsigned int logical_vdbox = 0; 742 unsigned int i; 743 u32 media_fuse, fuse1; 744 u16 vdbox_mask; 745 u16 vebox_mask; 746 747 if (MEDIA_VER(gt->i915) < 11) 748 return; 749 750 /* 751 * On newer platforms the fusing register is called 'enable' and has 752 * enable semantics, while on older platforms it is called 'disable' 753 * and bits have disable semantices. 754 */ 755 media_fuse = intel_uncore_read(gt->uncore, GEN11_GT_VEBOX_VDBOX_DISABLE); 756 if (MEDIA_VER_FULL(i915) < IP_VER(12, 50)) 757 media_fuse = ~media_fuse; 758 759 vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; 760 vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> 761 GEN11_GT_VEBOX_DISABLE_SHIFT; 762 763 if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) { 764 fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1); 765 gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1); 766 } else { 767 gt->info.sfc_mask = ~0; 768 } 769 770 for (i = 0; i < I915_MAX_VCS; i++) { 771 if (!HAS_ENGINE(gt, _VCS(i))) { 772 vdbox_mask &= ~BIT(i); 773 continue; 774 } 775 776 if (!(BIT(i) & vdbox_mask)) { 777 gt->info.engine_mask &= ~BIT(_VCS(i)); 778 drm_dbg(&i915->drm, "vcs%u fused off\n", i); 779 continue; 780 } 781 782 if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask)) 783 gt->info.vdbox_sfc_access |= BIT(i); 784 logical_vdbox++; 785 } 786 drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n", 787 vdbox_mask, VDBOX_MASK(gt)); 788 GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt)); 789 790 for (i = 0; i < I915_MAX_VECS; i++) { 791 if (!HAS_ENGINE(gt, _VECS(i))) { 792 vebox_mask &= ~BIT(i); 793 continue; 794 } 795 796 if (!(BIT(i) & vebox_mask)) { 797 gt->info.engine_mask &= ~BIT(_VECS(i)); 798 drm_dbg(&i915->drm, "vecs%u fused off\n", i); 799 } 800 } 801 drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n", 802 vebox_mask, VEBOX_MASK(gt)); 803 GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt)); 804 } 805 806 static void engine_mask_apply_compute_fuses(struct intel_gt *gt) 807 { 808 struct drm_i915_private *i915 = gt->i915; 809 struct intel_gt_info *info = >->info; 810 int ss_per_ccs = info->sseu.max_subslices / I915_MAX_CCS; 811 unsigned long ccs_mask; 812 unsigned int i; 813 814 if (GRAPHICS_VER(i915) < 11) 815 return; 816 817 if (hweight32(CCS_MASK(gt)) <= 1) 818 return; 819 820 ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask, 821 ss_per_ccs); 822 /* 823 * If all DSS in a quadrant are fused off, the corresponding CCS 824 * engine is not available for use. 825 */ 826 for_each_clear_bit(i, &ccs_mask, I915_MAX_CCS) { 827 info->engine_mask &= ~BIT(_CCS(i)); 828 drm_dbg(&i915->drm, "ccs%u fused off\n", i); 829 } 830 } 831 832 static void engine_mask_apply_copy_fuses(struct intel_gt *gt) 833 { 834 struct drm_i915_private *i915 = gt->i915; 835 struct intel_gt_info *info = >->info; 836 unsigned long meml3_mask; 837 unsigned long quad; 838 839 if (!(GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60) && 840 GRAPHICS_VER_FULL(i915) < IP_VER(12, 70))) 841 return; 842 843 meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3); 844 meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask); 845 846 /* 847 * Link Copy engines may be fused off according to meml3_mask. Each 848 * bit is a quad that houses 2 Link Copy and two Sub Copy engines. 849 */ 850 for_each_clear_bit(quad, &meml3_mask, GEN12_MAX_MSLICES) { 851 unsigned int instance = quad * 2 + 1; 852 intel_engine_mask_t mask = GENMASK(_BCS(instance + 1), 853 _BCS(instance)); 854 855 if (mask & info->engine_mask) { 856 drm_dbg(&i915->drm, "bcs%u fused off\n", instance); 857 drm_dbg(&i915->drm, "bcs%u fused off\n", instance + 1); 858 859 info->engine_mask &= ~mask; 860 } 861 } 862 } 863 864 /* 865 * Determine which engines are fused off in our particular hardware. 866 * Note that we have a catch-22 situation where we need to be able to access 867 * the blitter forcewake domain to read the engine fuses, but at the same time 868 * we need to know which engines are available on the system to know which 869 * forcewake domains are present. We solve this by intializing the forcewake 870 * domains based on the full engine mask in the platform capabilities before 871 * calling this function and pruning the domains for fused-off engines 872 * afterwards. 873 */ 874 static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) 875 { 876 struct intel_gt_info *info = >->info; 877 878 GEM_BUG_ON(!info->engine_mask); 879 880 engine_mask_apply_media_fuses(gt); 881 engine_mask_apply_compute_fuses(gt); 882 engine_mask_apply_copy_fuses(gt); 883 884 return info->engine_mask; 885 } 886 887 static void populate_logical_ids(struct intel_gt *gt, u8 *logical_ids, 888 u8 class, const u8 *map, u8 num_instances) 889 { 890 int i, j; 891 u8 current_logical_id = 0; 892 893 for (j = 0; j < num_instances; ++j) { 894 for (i = 0; i < ARRAY_SIZE(intel_engines); ++i) { 895 if (!HAS_ENGINE(gt, i) || 896 intel_engines[i].class != class) 897 continue; 898 899 if (intel_engines[i].instance == map[j]) { 900 logical_ids[intel_engines[i].instance] = 901 current_logical_id++; 902 break; 903 } 904 } 905 } 906 } 907 908 static void setup_logical_ids(struct intel_gt *gt, u8 *logical_ids, u8 class) 909 { 910 /* 911 * Logical to physical mapping is needed for proper support 912 * to split-frame feature. 913 */ 914 if (MEDIA_VER(gt->i915) >= 11 && class == VIDEO_DECODE_CLASS) { 915 const u8 map[] = { 0, 2, 4, 6, 1, 3, 5, 7 }; 916 917 populate_logical_ids(gt, logical_ids, class, 918 map, ARRAY_SIZE(map)); 919 } else { 920 int i; 921 u8 map[MAX_ENGINE_INSTANCE + 1]; 922 923 for (i = 0; i < MAX_ENGINE_INSTANCE + 1; ++i) 924 map[i] = i; 925 populate_logical_ids(gt, logical_ids, class, 926 map, ARRAY_SIZE(map)); 927 } 928 } 929 930 /** 931 * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers 932 * @gt: pointer to struct intel_gt 933 * 934 * Return: non-zero if the initialization failed. 935 */ 936 int intel_engines_init_mmio(struct intel_gt *gt) 937 { 938 struct drm_i915_private *i915 = gt->i915; 939 const unsigned int engine_mask = init_engine_mask(gt); 940 unsigned int mask = 0; 941 unsigned int i, class; 942 u8 logical_ids[MAX_ENGINE_INSTANCE + 1]; 943 int err; 944 945 drm_WARN_ON(&i915->drm, engine_mask == 0); 946 drm_WARN_ON(&i915->drm, engine_mask & 947 GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES)); 948 949 if (i915_inject_probe_failure(i915)) 950 return -ENODEV; 951 952 for (class = 0; class < MAX_ENGINE_CLASS + 1; ++class) { 953 setup_logical_ids(gt, logical_ids, class); 954 955 for (i = 0; i < ARRAY_SIZE(intel_engines); ++i) { 956 u8 instance = intel_engines[i].instance; 957 958 if (intel_engines[i].class != class || 959 !HAS_ENGINE(gt, i)) 960 continue; 961 962 err = intel_engine_setup(gt, i, 963 logical_ids[instance]); 964 if (err) 965 goto cleanup; 966 967 mask |= BIT(i); 968 } 969 } 970 971 /* 972 * Catch failures to update intel_engines table when the new engines 973 * are added to the driver by a warning and disabling the forgotten 974 * engines. 975 */ 976 if (drm_WARN_ON(&i915->drm, mask != engine_mask)) 977 gt->info.engine_mask = mask; 978 979 gt->info.num_engines = hweight32(mask); 980 981 intel_gt_check_and_clear_faults(gt); 982 983 intel_setup_engine_capabilities(gt); 984 985 intel_uncore_prune_engine_fw_domains(gt->uncore, gt); 986 987 return 0; 988 989 cleanup: 990 intel_engines_free(gt); 991 return err; 992 } 993 994 void intel_engine_init_execlists(struct intel_engine_cs *engine) 995 { 996 struct intel_engine_execlists * const execlists = &engine->execlists; 997 998 execlists->port_mask = 1; 999 GEM_BUG_ON(!is_power_of_2(execlists_num_ports(execlists))); 1000 GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS); 1001 1002 memset(execlists->pending, 0, sizeof(execlists->pending)); 1003 execlists->active = 1004 memset(execlists->inflight, 0, sizeof(execlists->inflight)); 1005 } 1006 1007 static void cleanup_status_page(struct intel_engine_cs *engine) 1008 { 1009 struct i915_vma *vma; 1010 1011 /* Prevent writes into HWSP after returning the page to the system */ 1012 intel_engine_set_hwsp_writemask(engine, ~0u); 1013 1014 vma = fetch_and_zero(&engine->status_page.vma); 1015 if (!vma) 1016 return; 1017 1018 if (!HWS_NEEDS_PHYSICAL(engine->i915)) 1019 i915_vma_unpin(vma); 1020 1021 i915_gem_object_unpin_map(vma->obj); 1022 i915_gem_object_put(vma->obj); 1023 } 1024 1025 static int pin_ggtt_status_page(struct intel_engine_cs *engine, 1026 struct i915_gem_ww_ctx *ww, 1027 struct i915_vma *vma) 1028 { 1029 unsigned int flags; 1030 1031 if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt)) 1032 /* 1033 * On g33, we cannot place HWS above 256MiB, so 1034 * restrict its pinning to the low mappable arena. 1035 * Though this restriction is not documented for 1036 * gen4, gen5, or byt, they also behave similarly 1037 * and hang if the HWS is placed at the top of the 1038 * GTT. To generalise, it appears that all !llc 1039 * platforms have issues with us placing the HWS 1040 * above the mappable region (even though we never 1041 * actually map it). 1042 */ 1043 flags = PIN_MAPPABLE; 1044 else 1045 flags = PIN_HIGH; 1046 1047 return i915_ggtt_pin(vma, ww, 0, flags); 1048 } 1049 1050 static int init_status_page(struct intel_engine_cs *engine) 1051 { 1052 struct drm_i915_gem_object *obj; 1053 struct i915_gem_ww_ctx ww; 1054 struct i915_vma *vma; 1055 void *vaddr; 1056 int ret; 1057 1058 INIT_LIST_HEAD(&engine->status_page.timelines); 1059 1060 /* 1061 * Though the HWS register does support 36bit addresses, historically 1062 * we have had hangs and corruption reported due to wild writes if 1063 * the HWS is placed above 4G. We only allow objects to be allocated 1064 * in GFP_DMA32 for i965, and no earlier physical address users had 1065 * access to more than 4G. 1066 */ 1067 obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE); 1068 if (IS_ERR(obj)) { 1069 drm_err(&engine->i915->drm, 1070 "Failed to allocate status page\n"); 1071 return PTR_ERR(obj); 1072 } 1073 1074 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC); 1075 1076 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); 1077 if (IS_ERR(vma)) { 1078 ret = PTR_ERR(vma); 1079 goto err_put; 1080 } 1081 1082 i915_gem_ww_ctx_init(&ww, true); 1083 retry: 1084 ret = i915_gem_object_lock(obj, &ww); 1085 if (!ret && !HWS_NEEDS_PHYSICAL(engine->i915)) 1086 ret = pin_ggtt_status_page(engine, &ww, vma); 1087 if (ret) 1088 goto err; 1089 1090 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); 1091 if (IS_ERR(vaddr)) { 1092 ret = PTR_ERR(vaddr); 1093 goto err_unpin; 1094 } 1095 1096 engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE); 1097 engine->status_page.vma = vma; 1098 1099 err_unpin: 1100 if (ret) 1101 i915_vma_unpin(vma); 1102 err: 1103 if (ret == -EDEADLK) { 1104 ret = i915_gem_ww_ctx_backoff(&ww); 1105 if (!ret) 1106 goto retry; 1107 } 1108 i915_gem_ww_ctx_fini(&ww); 1109 err_put: 1110 if (ret) 1111 i915_gem_object_put(obj); 1112 return ret; 1113 } 1114 1115 static int engine_setup_common(struct intel_engine_cs *engine) 1116 { 1117 int err; 1118 1119 init_llist_head(&engine->barrier_tasks); 1120 1121 err = init_status_page(engine); 1122 if (err) 1123 return err; 1124 1125 engine->breadcrumbs = intel_breadcrumbs_create(engine); 1126 if (!engine->breadcrumbs) { 1127 err = -ENOMEM; 1128 goto err_status; 1129 } 1130 1131 engine->sched_engine = i915_sched_engine_create(ENGINE_PHYSICAL); 1132 if (!engine->sched_engine) { 1133 err = -ENOMEM; 1134 goto err_sched_engine; 1135 } 1136 engine->sched_engine->private_data = engine; 1137 1138 err = intel_engine_init_cmd_parser(engine); 1139 if (err) 1140 goto err_cmd_parser; 1141 1142 intel_engine_init_execlists(engine); 1143 intel_engine_init__pm(engine); 1144 intel_engine_init_retire(engine); 1145 1146 /* Use the whole device by default */ 1147 engine->sseu = 1148 intel_sseu_from_device_info(&engine->gt->info.sseu); 1149 1150 intel_engine_init_workarounds(engine); 1151 intel_engine_init_whitelist(engine); 1152 intel_engine_init_ctx_wa(engine); 1153 1154 if (GRAPHICS_VER(engine->i915) >= 12) 1155 engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO; 1156 1157 return 0; 1158 1159 err_cmd_parser: 1160 i915_sched_engine_put(engine->sched_engine); 1161 err_sched_engine: 1162 intel_breadcrumbs_put(engine->breadcrumbs); 1163 err_status: 1164 cleanup_status_page(engine); 1165 return err; 1166 } 1167 1168 struct measure_breadcrumb { 1169 struct i915_request rq; 1170 struct intel_ring ring; 1171 u32 cs[2048]; 1172 }; 1173 1174 static int measure_breadcrumb_dw(struct intel_context *ce) 1175 { 1176 struct intel_engine_cs *engine = ce->engine; 1177 struct measure_breadcrumb *frame; 1178 int dw; 1179 1180 GEM_BUG_ON(!engine->gt->scratch); 1181 1182 frame = kzalloc(sizeof(*frame), GFP_KERNEL); 1183 if (!frame) 1184 return -ENOMEM; 1185 1186 frame->rq.engine = engine; 1187 frame->rq.context = ce; 1188 rcu_assign_pointer(frame->rq.timeline, ce->timeline); 1189 frame->rq.hwsp_seqno = ce->timeline->hwsp_seqno; 1190 1191 frame->ring.vaddr = frame->cs; 1192 frame->ring.size = sizeof(frame->cs); 1193 frame->ring.wrap = 1194 BITS_PER_TYPE(frame->ring.size) - ilog2(frame->ring.size); 1195 frame->ring.effective_size = frame->ring.size; 1196 intel_ring_update_space(&frame->ring); 1197 frame->rq.ring = &frame->ring; 1198 1199 mutex_lock(&ce->timeline->mutex); 1200 spin_lock_irq(&engine->sched_engine->lock); 1201 1202 dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs; 1203 1204 spin_unlock_irq(&engine->sched_engine->lock); 1205 mutex_unlock(&ce->timeline->mutex); 1206 1207 GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */ 1208 1209 kfree(frame); 1210 return dw; 1211 } 1212 1213 struct intel_context * 1214 intel_engine_create_pinned_context(struct intel_engine_cs *engine, 1215 struct i915_address_space *vm, 1216 unsigned int ring_size, 1217 unsigned int hwsp, 1218 struct lock_class_key *key, 1219 const char *name) 1220 { 1221 struct intel_context *ce; 1222 int err; 1223 1224 ce = intel_context_create(engine); 1225 if (IS_ERR(ce)) 1226 return ce; 1227 1228 __set_bit(CONTEXT_BARRIER_BIT, &ce->flags); 1229 ce->timeline = page_pack_bits(NULL, hwsp); 1230 ce->ring = NULL; 1231 ce->ring_size = ring_size; 1232 1233 i915_vm_put(ce->vm); 1234 ce->vm = i915_vm_get(vm); 1235 1236 err = intel_context_pin(ce); /* perma-pin so it is always available */ 1237 if (err) { 1238 intel_context_put(ce); 1239 return ERR_PTR(err); 1240 } 1241 1242 list_add_tail(&ce->pinned_contexts_link, &engine->pinned_contexts_list); 1243 1244 /* 1245 * Give our perma-pinned kernel timelines a separate lockdep class, 1246 * so that we can use them from within the normal user timelines 1247 * should we need to inject GPU operations during their request 1248 * construction. 1249 */ 1250 lockdep_set_class_and_name(&ce->timeline->mutex, key, name); 1251 1252 return ce; 1253 } 1254 1255 void intel_engine_destroy_pinned_context(struct intel_context *ce) 1256 { 1257 struct intel_engine_cs *engine = ce->engine; 1258 struct i915_vma *hwsp = engine->status_page.vma; 1259 1260 GEM_BUG_ON(ce->timeline->hwsp_ggtt != hwsp); 1261 1262 mutex_lock(&hwsp->vm->mutex); 1263 list_del(&ce->timeline->engine_link); 1264 mutex_unlock(&hwsp->vm->mutex); 1265 1266 list_del(&ce->pinned_contexts_link); 1267 intel_context_unpin(ce); 1268 intel_context_put(ce); 1269 } 1270 1271 static struct intel_context * 1272 create_kernel_context(struct intel_engine_cs *engine) 1273 { 1274 static struct lock_class_key kernel; 1275 1276 return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K, 1277 I915_GEM_HWS_SEQNO_ADDR, 1278 &kernel, "kernel_context"); 1279 } 1280 1281 /** 1282 * intel_engines_init_common - initialize cengine state which might require hw access 1283 * @engine: Engine to initialize. 1284 * 1285 * Initializes @engine@ structure members shared between legacy and execlists 1286 * submission modes which do require hardware access. 1287 * 1288 * Typcally done at later stages of submission mode specific engine setup. 1289 * 1290 * Returns zero on success or an error code on failure. 1291 */ 1292 static int engine_init_common(struct intel_engine_cs *engine) 1293 { 1294 struct intel_context *ce; 1295 int ret; 1296 1297 engine->set_default_submission(engine); 1298 1299 /* 1300 * We may need to do things with the shrinker which 1301 * require us to immediately switch back to the default 1302 * context. This can cause a problem as pinning the 1303 * default context also requires GTT space which may not 1304 * be available. To avoid this we always pin the default 1305 * context. 1306 */ 1307 ce = create_kernel_context(engine); 1308 if (IS_ERR(ce)) 1309 return PTR_ERR(ce); 1310 1311 ret = measure_breadcrumb_dw(ce); 1312 if (ret < 0) 1313 goto err_context; 1314 1315 engine->emit_fini_breadcrumb_dw = ret; 1316 engine->kernel_context = ce; 1317 1318 return 0; 1319 1320 err_context: 1321 intel_engine_destroy_pinned_context(ce); 1322 return ret; 1323 } 1324 1325 int intel_engines_init(struct intel_gt *gt) 1326 { 1327 int (*setup)(struct intel_engine_cs *engine); 1328 struct intel_engine_cs *engine; 1329 enum intel_engine_id id; 1330 int err; 1331 1332 if (intel_uc_uses_guc_submission(>->uc)) { 1333 gt->submission_method = INTEL_SUBMISSION_GUC; 1334 setup = intel_guc_submission_setup; 1335 } else if (HAS_EXECLISTS(gt->i915)) { 1336 gt->submission_method = INTEL_SUBMISSION_ELSP; 1337 setup = intel_execlists_submission_setup; 1338 } else { 1339 gt->submission_method = INTEL_SUBMISSION_RING; 1340 setup = intel_ring_submission_setup; 1341 } 1342 1343 for_each_engine(engine, gt, id) { 1344 err = engine_setup_common(engine); 1345 if (err) 1346 return err; 1347 1348 err = setup(engine); 1349 if (err) { 1350 intel_engine_cleanup_common(engine); 1351 return err; 1352 } 1353 1354 /* The backend should now be responsible for cleanup */ 1355 GEM_BUG_ON(engine->release == NULL); 1356 1357 err = engine_init_common(engine); 1358 if (err) 1359 return err; 1360 1361 intel_engine_add_user(engine); 1362 } 1363 1364 return 0; 1365 } 1366 1367 /** 1368 * intel_engines_cleanup_common - cleans up the engine state created by 1369 * the common initiailizers. 1370 * @engine: Engine to cleanup. 1371 * 1372 * This cleans up everything created by the common helpers. 1373 */ 1374 void intel_engine_cleanup_common(struct intel_engine_cs *engine) 1375 { 1376 GEM_BUG_ON(!list_empty(&engine->sched_engine->requests)); 1377 1378 i915_sched_engine_put(engine->sched_engine); 1379 intel_breadcrumbs_put(engine->breadcrumbs); 1380 1381 intel_engine_fini_retire(engine); 1382 intel_engine_cleanup_cmd_parser(engine); 1383 1384 if (engine->default_state) 1385 uao_detach(engine->default_state); 1386 1387 if (engine->kernel_context) 1388 intel_engine_destroy_pinned_context(engine->kernel_context); 1389 1390 GEM_BUG_ON(!llist_empty(&engine->barrier_tasks)); 1391 cleanup_status_page(engine); 1392 1393 intel_wa_list_free(&engine->ctx_wa_list); 1394 intel_wa_list_free(&engine->wa_list); 1395 intel_wa_list_free(&engine->whitelist); 1396 } 1397 1398 /** 1399 * intel_engine_resume - re-initializes the HW state of the engine 1400 * @engine: Engine to resume. 1401 * 1402 * Returns zero on success or an error code on failure. 1403 */ 1404 int intel_engine_resume(struct intel_engine_cs *engine) 1405 { 1406 intel_engine_apply_workarounds(engine); 1407 intel_engine_apply_whitelist(engine); 1408 1409 return engine->resume(engine); 1410 } 1411 1412 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine) 1413 { 1414 struct drm_i915_private *i915 = engine->i915; 1415 1416 u64 acthd; 1417 1418 if (GRAPHICS_VER(i915) >= 8) 1419 acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW); 1420 else if (GRAPHICS_VER(i915) >= 4) 1421 acthd = ENGINE_READ(engine, RING_ACTHD); 1422 else 1423 acthd = ENGINE_READ(engine, ACTHD); 1424 1425 return acthd; 1426 } 1427 1428 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine) 1429 { 1430 u64 bbaddr; 1431 1432 if (GRAPHICS_VER(engine->i915) >= 8) 1433 bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW); 1434 else 1435 bbaddr = ENGINE_READ(engine, RING_BBADDR); 1436 1437 return bbaddr; 1438 } 1439 1440 static unsigned long stop_timeout(const struct intel_engine_cs *engine) 1441 { 1442 if (in_atomic() || irqs_disabled()) /* inside atomic preempt-reset? */ 1443 return 0; 1444 1445 /* 1446 * If we are doing a normal GPU reset, we can take our time and allow 1447 * the engine to quiesce. We've stopped submission to the engine, and 1448 * if we wait long enough an innocent context should complete and 1449 * leave the engine idle. So they should not be caught unaware by 1450 * the forthcoming GPU reset (which usually follows the stop_cs)! 1451 */ 1452 return READ_ONCE(engine->props.stop_timeout_ms); 1453 } 1454 1455 static int __intel_engine_stop_cs(struct intel_engine_cs *engine, 1456 int fast_timeout_us, 1457 int slow_timeout_ms) 1458 { 1459 struct intel_uncore *uncore = engine->uncore; 1460 const i915_reg_t mode = RING_MI_MODE(engine->mmio_base); 1461 int err; 1462 1463 intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); 1464 1465 /* 1466 * Wa_22011802037 : gen11, gen12, Prior to doing a reset, ensure CS is 1467 * stopped, set ring stop bit and prefetch disable bit to halt CS 1468 */ 1469 if (IS_GRAPHICS_VER(engine->i915, 11, 12)) 1470 intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base), 1471 _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE)); 1472 1473 err = __intel_wait_for_register_fw(engine->uncore, mode, 1474 MODE_IDLE, MODE_IDLE, 1475 fast_timeout_us, 1476 slow_timeout_ms, 1477 NULL); 1478 1479 /* A final mmio read to let GPU writes be hopefully flushed to memory */ 1480 intel_uncore_posting_read_fw(uncore, mode); 1481 return err; 1482 } 1483 1484 int intel_engine_stop_cs(struct intel_engine_cs *engine) 1485 { 1486 int err = 0; 1487 1488 if (GRAPHICS_VER(engine->i915) < 3) 1489 return -ENODEV; 1490 1491 ENGINE_TRACE(engine, "\n"); 1492 /* 1493 * TODO: Find out why occasionally stopping the CS times out. Seen 1494 * especially with gem_eio tests. 1495 * 1496 * Occasionally trying to stop the cs times out, but does not adversely 1497 * affect functionality. The timeout is set as a config parameter that 1498 * defaults to 100ms. In most cases the follow up operation is to wait 1499 * for pending MI_FORCE_WAKES. The assumption is that this timeout is 1500 * sufficient for any pending MI_FORCEWAKEs to complete. Once root 1501 * caused, the caller must check and handle the return from this 1502 * function. 1503 */ 1504 if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) { 1505 ENGINE_TRACE(engine, 1506 "timed out on STOP_RING -> IDLE; HEAD:%04x, TAIL:%04x\n", 1507 ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR, 1508 ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR); 1509 1510 /* 1511 * Sometimes we observe that the idle flag is not 1512 * set even though the ring is empty. So double 1513 * check before giving up. 1514 */ 1515 if ((ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) != 1516 (ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR)) 1517 err = -ETIMEDOUT; 1518 } 1519 1520 return err; 1521 } 1522 1523 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine) 1524 { 1525 ENGINE_TRACE(engine, "\n"); 1526 1527 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); 1528 } 1529 1530 static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine) 1531 { 1532 static const i915_reg_t _reg[I915_NUM_ENGINES] = { 1533 [RCS0] = MSG_IDLE_CS, 1534 [BCS0] = MSG_IDLE_BCS, 1535 [VCS0] = MSG_IDLE_VCS0, 1536 [VCS1] = MSG_IDLE_VCS1, 1537 [VCS2] = MSG_IDLE_VCS2, 1538 [VCS3] = MSG_IDLE_VCS3, 1539 [VCS4] = MSG_IDLE_VCS4, 1540 [VCS5] = MSG_IDLE_VCS5, 1541 [VCS6] = MSG_IDLE_VCS6, 1542 [VCS7] = MSG_IDLE_VCS7, 1543 [VECS0] = MSG_IDLE_VECS0, 1544 [VECS1] = MSG_IDLE_VECS1, 1545 [VECS2] = MSG_IDLE_VECS2, 1546 [VECS3] = MSG_IDLE_VECS3, 1547 [CCS0] = MSG_IDLE_CS, 1548 [CCS1] = MSG_IDLE_CS, 1549 [CCS2] = MSG_IDLE_CS, 1550 [CCS3] = MSG_IDLE_CS, 1551 }; 1552 u32 val; 1553 1554 if (!_reg[engine->id].reg) { 1555 drm_err(&engine->i915->drm, 1556 "MSG IDLE undefined for engine id %u\n", engine->id); 1557 return 0; 1558 } 1559 1560 val = intel_uncore_read(engine->uncore, _reg[engine->id]); 1561 1562 /* bits[29:25] & bits[13:9] >> shift */ 1563 return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT; 1564 } 1565 1566 static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask) 1567 { 1568 int ret; 1569 1570 /* Ensure GPM receives fw up/down after CS is stopped */ 1571 udelay(1); 1572 1573 /* Wait for forcewake request to complete in GPM */ 1574 ret = __intel_wait_for_register_fw(gt->uncore, 1575 GEN9_PWRGT_DOMAIN_STATUS, 1576 fw_mask, fw_mask, 5000, 0, NULL); 1577 1578 /* Ensure CS receives fw ack from GPM */ 1579 udelay(1); 1580 1581 if (ret) 1582 GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret); 1583 } 1584 1585 /* 1586 * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any 1587 * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The 1588 * pending status is indicated by bits[13:9] (masked by bits[29:25]) in the 1589 * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we 1590 * are concerned only with the gt reset here, we use a logical OR of pending 1591 * forcewakeups from all reset domains and then wait for them to complete by 1592 * querying PWRGT_DOMAIN_STATUS. 1593 */ 1594 void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine) 1595 { 1596 u32 fw_pending = __cs_pending_mi_force_wakes(engine); 1597 1598 if (fw_pending) 1599 __gpm_wait_for_fw_complete(engine->gt, fw_pending); 1600 } 1601 1602 /* NB: please notice the memset */ 1603 void intel_engine_get_instdone(const struct intel_engine_cs *engine, 1604 struct intel_instdone *instdone) 1605 { 1606 struct drm_i915_private *i915 = engine->i915; 1607 struct intel_uncore *uncore = engine->uncore; 1608 u32 mmio_base = engine->mmio_base; 1609 int slice; 1610 int subslice; 1611 int iter; 1612 1613 memset(instdone, 0, sizeof(*instdone)); 1614 1615 if (GRAPHICS_VER(i915) >= 8) { 1616 instdone->instdone = 1617 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); 1618 1619 if (engine->id != RCS0) 1620 return; 1621 1622 instdone->slice_common = 1623 intel_uncore_read(uncore, GEN7_SC_INSTDONE); 1624 if (GRAPHICS_VER(i915) >= 12) { 1625 instdone->slice_common_extra[0] = 1626 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA); 1627 instdone->slice_common_extra[1] = 1628 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA2); 1629 } 1630 1631 for_each_ss_steering(iter, engine->gt, slice, subslice) { 1632 instdone->sampler[slice][subslice] = 1633 intel_gt_mcr_read(engine->gt, 1634 GEN7_SAMPLER_INSTDONE, 1635 slice, subslice); 1636 instdone->row[slice][subslice] = 1637 intel_gt_mcr_read(engine->gt, 1638 GEN7_ROW_INSTDONE, 1639 slice, subslice); 1640 } 1641 1642 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) { 1643 for_each_ss_steering(iter, engine->gt, slice, subslice) 1644 instdone->geom_svg[slice][subslice] = 1645 intel_gt_mcr_read(engine->gt, 1646 XEHPG_INSTDONE_GEOM_SVG, 1647 slice, subslice); 1648 } 1649 } else if (GRAPHICS_VER(i915) >= 7) { 1650 instdone->instdone = 1651 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); 1652 1653 if (engine->id != RCS0) 1654 return; 1655 1656 instdone->slice_common = 1657 intel_uncore_read(uncore, GEN7_SC_INSTDONE); 1658 instdone->sampler[0][0] = 1659 intel_uncore_read(uncore, GEN7_SAMPLER_INSTDONE); 1660 instdone->row[0][0] = 1661 intel_uncore_read(uncore, GEN7_ROW_INSTDONE); 1662 } else if (GRAPHICS_VER(i915) >= 4) { 1663 instdone->instdone = 1664 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); 1665 if (engine->id == RCS0) 1666 /* HACK: Using the wrong struct member */ 1667 instdone->slice_common = 1668 intel_uncore_read(uncore, GEN4_INSTDONE1); 1669 } else { 1670 instdone->instdone = intel_uncore_read(uncore, GEN2_INSTDONE); 1671 } 1672 } 1673 1674 static bool ring_is_idle(struct intel_engine_cs *engine) 1675 { 1676 bool idle = true; 1677 1678 if (I915_SELFTEST_ONLY(!engine->mmio_base)) 1679 return true; 1680 1681 if (!intel_engine_pm_get_if_awake(engine)) 1682 return true; 1683 1684 /* First check that no commands are left in the ring */ 1685 if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) != 1686 (ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR)) 1687 idle = false; 1688 1689 /* No bit for gen2, so assume the CS parser is idle */ 1690 if (GRAPHICS_VER(engine->i915) > 2 && 1691 !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE)) 1692 idle = false; 1693 1694 intel_engine_pm_put(engine); 1695 1696 return idle; 1697 } 1698 1699 void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync) 1700 { 1701 struct tasklet_struct *t = &engine->sched_engine->tasklet; 1702 1703 if (!t->callback) 1704 return; 1705 1706 local_bh_disable(); 1707 if (tasklet_trylock(t)) { 1708 /* Must wait for any GPU reset in progress. */ 1709 if (__tasklet_is_enabled(t)) 1710 t->callback(t); 1711 tasklet_unlock(t); 1712 } 1713 local_bh_enable(); 1714 1715 /* Synchronise and wait for the tasklet on another CPU */ 1716 if (sync) 1717 tasklet_unlock_wait(t); 1718 } 1719 1720 /** 1721 * intel_engine_is_idle() - Report if the engine has finished process all work 1722 * @engine: the intel_engine_cs 1723 * 1724 * Return true if there are no requests pending, nothing left to be submitted 1725 * to hardware, and that the engine is idle. 1726 */ 1727 bool intel_engine_is_idle(struct intel_engine_cs *engine) 1728 { 1729 /* More white lies, if wedged, hw state is inconsistent */ 1730 if (intel_gt_is_wedged(engine->gt)) 1731 return true; 1732 1733 if (!intel_engine_pm_is_awake(engine)) 1734 return true; 1735 1736 /* Waiting to drain ELSP? */ 1737 intel_synchronize_hardirq(engine->i915); 1738 intel_engine_flush_submission(engine); 1739 1740 /* ELSP is empty, but there are ready requests? E.g. after reset */ 1741 if (!i915_sched_engine_is_empty(engine->sched_engine)) 1742 return false; 1743 1744 /* Ring stopped? */ 1745 return ring_is_idle(engine); 1746 } 1747 1748 bool intel_engines_are_idle(struct intel_gt *gt) 1749 { 1750 struct intel_engine_cs *engine; 1751 enum intel_engine_id id; 1752 1753 /* 1754 * If the driver is wedged, HW state may be very inconsistent and 1755 * report that it is still busy, even though we have stopped using it. 1756 */ 1757 if (intel_gt_is_wedged(gt)) 1758 return true; 1759 1760 /* Already parked (and passed an idleness test); must still be idle */ 1761 if (!READ_ONCE(gt->awake)) 1762 return true; 1763 1764 for_each_engine(engine, gt, id) { 1765 if (!intel_engine_is_idle(engine)) 1766 return false; 1767 } 1768 1769 return true; 1770 } 1771 1772 bool intel_engine_irq_enable(struct intel_engine_cs *engine) 1773 { 1774 if (!engine->irq_enable) 1775 return false; 1776 1777 /* Caller disables interrupts */ 1778 spin_lock(engine->gt->irq_lock); 1779 engine->irq_enable(engine); 1780 spin_unlock(engine->gt->irq_lock); 1781 1782 return true; 1783 } 1784 1785 void intel_engine_irq_disable(struct intel_engine_cs *engine) 1786 { 1787 if (!engine->irq_disable) 1788 return; 1789 1790 /* Caller disables interrupts */ 1791 spin_lock(engine->gt->irq_lock); 1792 engine->irq_disable(engine); 1793 spin_unlock(engine->gt->irq_lock); 1794 } 1795 1796 void intel_engines_reset_default_submission(struct intel_gt *gt) 1797 { 1798 struct intel_engine_cs *engine; 1799 enum intel_engine_id id; 1800 1801 for_each_engine(engine, gt, id) { 1802 if (engine->sanitize) 1803 engine->sanitize(engine); 1804 1805 engine->set_default_submission(engine); 1806 } 1807 } 1808 1809 bool intel_engine_can_store_dword(struct intel_engine_cs *engine) 1810 { 1811 switch (GRAPHICS_VER(engine->i915)) { 1812 case 2: 1813 return false; /* uses physical not virtual addresses */ 1814 case 3: 1815 /* maybe only uses physical not virtual addresses */ 1816 return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915)); 1817 case 4: 1818 return !IS_I965G(engine->i915); /* who knows! */ 1819 case 6: 1820 return engine->class != VIDEO_DECODE_CLASS; /* b0rked */ 1821 default: 1822 return true; 1823 } 1824 } 1825 1826 static struct intel_timeline *get_timeline(struct i915_request *rq) 1827 { 1828 struct intel_timeline *tl; 1829 1830 /* 1831 * Even though we are holding the engine->sched_engine->lock here, there 1832 * is no control over the submission queue per-se and we are 1833 * inspecting the active state at a random point in time, with an 1834 * unknown queue. Play safe and make sure the timeline remains valid. 1835 * (Only being used for pretty printing, one extra kref shouldn't 1836 * cause a camel stampede!) 1837 */ 1838 rcu_read_lock(); 1839 tl = rcu_dereference(rq->timeline); 1840 if (!kref_get_unless_zero(&tl->kref)) 1841 tl = NULL; 1842 rcu_read_unlock(); 1843 1844 return tl; 1845 } 1846 1847 static int print_ring(char *buf, int sz, struct i915_request *rq) 1848 { 1849 int len = 0; 1850 1851 if (!i915_request_signaled(rq)) { 1852 struct intel_timeline *tl = get_timeline(rq); 1853 1854 len = scnprintf(buf, sz, 1855 "ring:{start:%08x, hwsp:%08x, seqno:%08x, runtime:%llums}, ", 1856 i915_ggtt_offset(rq->ring->vma), 1857 tl ? tl->hwsp_offset : 0, 1858 hwsp_seqno(rq), 1859 DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context), 1860 1000 * 1000)); 1861 1862 if (tl) 1863 intel_timeline_put(tl); 1864 } 1865 1866 return len; 1867 } 1868 1869 static void hexdump(struct drm_printer *m, const void *buf, size_t len) 1870 { 1871 STUB(); 1872 #ifdef notyet 1873 const size_t rowsize = 8 * sizeof(u32); 1874 const void *prev = NULL; 1875 bool skip = false; 1876 size_t pos; 1877 1878 for (pos = 0; pos < len; pos += rowsize) { 1879 char line[128]; 1880 1881 if (prev && !memcmp(prev, buf + pos, rowsize)) { 1882 if (!skip) { 1883 drm_printf(m, "*\n"); 1884 skip = true; 1885 } 1886 continue; 1887 } 1888 1889 WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos, 1890 rowsize, sizeof(u32), 1891 line, sizeof(line), 1892 false) >= sizeof(line)); 1893 drm_printf(m, "[%04zx] %s\n", pos, line); 1894 1895 prev = buf + pos; 1896 skip = false; 1897 } 1898 #endif 1899 } 1900 1901 static const char *repr_timer(const struct timeout *t) 1902 { 1903 if (!READ_ONCE(t->to_time)) 1904 return "inactive"; 1905 1906 if (timer_pending(t)) 1907 return "active"; 1908 1909 return "expired"; 1910 } 1911 1912 static void intel_engine_print_registers(struct intel_engine_cs *engine, 1913 struct drm_printer *m) 1914 { 1915 struct drm_i915_private *dev_priv = engine->i915; 1916 struct intel_engine_execlists * const execlists = &engine->execlists; 1917 u64 addr; 1918 1919 if (engine->id == RENDER_CLASS && IS_GRAPHICS_VER(dev_priv, 4, 7)) 1920 drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID)); 1921 if (HAS_EXECLISTS(dev_priv)) { 1922 drm_printf(m, "\tEL_STAT_HI: 0x%08x\n", 1923 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI)); 1924 drm_printf(m, "\tEL_STAT_LO: 0x%08x\n", 1925 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO)); 1926 } 1927 drm_printf(m, "\tRING_START: 0x%08x\n", 1928 ENGINE_READ(engine, RING_START)); 1929 drm_printf(m, "\tRING_HEAD: 0x%08x\n", 1930 ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR); 1931 drm_printf(m, "\tRING_TAIL: 0x%08x\n", 1932 ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR); 1933 drm_printf(m, "\tRING_CTL: 0x%08x%s\n", 1934 ENGINE_READ(engine, RING_CTL), 1935 ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : ""); 1936 if (GRAPHICS_VER(engine->i915) > 2) { 1937 drm_printf(m, "\tRING_MODE: 0x%08x%s\n", 1938 ENGINE_READ(engine, RING_MI_MODE), 1939 ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : ""); 1940 } 1941 1942 if (GRAPHICS_VER(dev_priv) >= 6) { 1943 drm_printf(m, "\tRING_IMR: 0x%08x\n", 1944 ENGINE_READ(engine, RING_IMR)); 1945 drm_printf(m, "\tRING_ESR: 0x%08x\n", 1946 ENGINE_READ(engine, RING_ESR)); 1947 drm_printf(m, "\tRING_EMR: 0x%08x\n", 1948 ENGINE_READ(engine, RING_EMR)); 1949 drm_printf(m, "\tRING_EIR: 0x%08x\n", 1950 ENGINE_READ(engine, RING_EIR)); 1951 } 1952 1953 addr = intel_engine_get_active_head(engine); 1954 drm_printf(m, "\tACTHD: 0x%08x_%08x\n", 1955 upper_32_bits(addr), lower_32_bits(addr)); 1956 addr = intel_engine_get_last_batch_head(engine); 1957 drm_printf(m, "\tBBADDR: 0x%08x_%08x\n", 1958 upper_32_bits(addr), lower_32_bits(addr)); 1959 if (GRAPHICS_VER(dev_priv) >= 8) 1960 addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW); 1961 else if (GRAPHICS_VER(dev_priv) >= 4) 1962 addr = ENGINE_READ(engine, RING_DMA_FADD); 1963 else 1964 addr = ENGINE_READ(engine, DMA_FADD_I8XX); 1965 drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n", 1966 upper_32_bits(addr), lower_32_bits(addr)); 1967 if (GRAPHICS_VER(dev_priv) >= 4) { 1968 drm_printf(m, "\tIPEIR: 0x%08x\n", 1969 ENGINE_READ(engine, RING_IPEIR)); 1970 drm_printf(m, "\tIPEHR: 0x%08x\n", 1971 ENGINE_READ(engine, RING_IPEHR)); 1972 } else { 1973 drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR)); 1974 drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR)); 1975 } 1976 1977 if (HAS_EXECLISTS(dev_priv) && !intel_engine_uses_guc(engine)) { 1978 struct i915_request * const *port, *rq; 1979 const u32 *hws = 1980 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX]; 1981 const u8 num_entries = execlists->csb_size; 1982 unsigned int idx; 1983 u8 read, write; 1984 1985 drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? %s, timeslice? %s\n", 1986 str_yes_no(test_bit(TASKLET_STATE_SCHED, &engine->sched_engine->tasklet.state)), 1987 str_enabled_disabled(!atomic_read(&engine->sched_engine->tasklet.count)), 1988 repr_timer(&engine->execlists.preempt), 1989 repr_timer(&engine->execlists.timer)); 1990 1991 read = execlists->csb_head; 1992 write = READ_ONCE(*execlists->csb_write); 1993 1994 drm_printf(m, "\tExeclist status: 0x%08x %08x; CSB read:%d, write:%d, entries:%d\n", 1995 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO), 1996 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI), 1997 read, write, num_entries); 1998 1999 if (read >= num_entries) 2000 read = 0; 2001 if (write >= num_entries) 2002 write = 0; 2003 if (read > write) 2004 write += num_entries; 2005 while (read < write) { 2006 idx = ++read % num_entries; 2007 drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n", 2008 idx, hws[idx * 2], hws[idx * 2 + 1]); 2009 } 2010 2011 i915_sched_engine_active_lock_bh(engine->sched_engine); 2012 rcu_read_lock(); 2013 for (port = execlists->active; (rq = *port); port++) { 2014 char hdr[160]; 2015 int len; 2016 2017 len = scnprintf(hdr, sizeof(hdr), 2018 "\t\tActive[%d]: ccid:%08x%s%s, ", 2019 (int)(port - execlists->active), 2020 rq->context->lrc.ccid, 2021 intel_context_is_closed(rq->context) ? "!" : "", 2022 intel_context_is_banned(rq->context) ? "*" : ""); 2023 len += print_ring(hdr + len, sizeof(hdr) - len, rq); 2024 scnprintf(hdr + len, sizeof(hdr) - len, "rq: "); 2025 i915_request_show(m, rq, hdr, 0); 2026 } 2027 for (port = execlists->pending; (rq = *port); port++) { 2028 char hdr[160]; 2029 int len; 2030 2031 len = scnprintf(hdr, sizeof(hdr), 2032 "\t\tPending[%d]: ccid:%08x%s%s, ", 2033 (int)(port - execlists->pending), 2034 rq->context->lrc.ccid, 2035 intel_context_is_closed(rq->context) ? "!" : "", 2036 intel_context_is_banned(rq->context) ? "*" : ""); 2037 len += print_ring(hdr + len, sizeof(hdr) - len, rq); 2038 scnprintf(hdr + len, sizeof(hdr) - len, "rq: "); 2039 i915_request_show(m, rq, hdr, 0); 2040 } 2041 rcu_read_unlock(); 2042 i915_sched_engine_active_unlock_bh(engine->sched_engine); 2043 } else if (GRAPHICS_VER(dev_priv) > 6) { 2044 drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n", 2045 ENGINE_READ(engine, RING_PP_DIR_BASE)); 2046 drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n", 2047 ENGINE_READ(engine, RING_PP_DIR_BASE_READ)); 2048 drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n", 2049 ENGINE_READ(engine, RING_PP_DIR_DCLV)); 2050 } 2051 } 2052 2053 static void print_request_ring(struct drm_printer *m, struct i915_request *rq) 2054 { 2055 struct i915_vma_resource *vma_res = rq->batch_res; 2056 void *ring; 2057 int size; 2058 2059 drm_printf(m, 2060 "[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n", 2061 rq->head, rq->postfix, rq->tail, 2062 vma_res ? upper_32_bits(vma_res->start) : ~0u, 2063 vma_res ? lower_32_bits(vma_res->start) : ~0u); 2064 2065 size = rq->tail - rq->head; 2066 if (rq->tail < rq->head) 2067 size += rq->ring->size; 2068 2069 ring = kmalloc(size, GFP_ATOMIC); 2070 if (ring) { 2071 const void *vaddr = rq->ring->vaddr; 2072 unsigned int head = rq->head; 2073 unsigned int len = 0; 2074 2075 if (rq->tail < head) { 2076 len = rq->ring->size - head; 2077 memcpy(ring, vaddr + head, len); 2078 head = 0; 2079 } 2080 memcpy(ring + len, vaddr + head, size - len); 2081 2082 hexdump(m, ring, size); 2083 kfree(ring); 2084 } 2085 } 2086 2087 static unsigned long read_ul(void *p, size_t x) 2088 { 2089 return *(unsigned long *)(p + x); 2090 } 2091 2092 static void print_properties(struct intel_engine_cs *engine, 2093 struct drm_printer *m) 2094 { 2095 static const struct pmap { 2096 size_t offset; 2097 const char *name; 2098 } props[] = { 2099 #define P(x) { \ 2100 .offset = offsetof(typeof(engine->props), x), \ 2101 .name = #x \ 2102 } 2103 P(heartbeat_interval_ms), 2104 P(max_busywait_duration_ns), 2105 P(preempt_timeout_ms), 2106 P(stop_timeout_ms), 2107 P(timeslice_duration_ms), 2108 2109 {}, 2110 #undef P 2111 }; 2112 const struct pmap *p; 2113 2114 drm_printf(m, "\tProperties:\n"); 2115 for (p = props; p->name; p++) 2116 drm_printf(m, "\t\t%s: %lu [default %lu]\n", 2117 p->name, 2118 read_ul(&engine->props, p->offset), 2119 read_ul(&engine->defaults, p->offset)); 2120 } 2121 2122 static void engine_dump_request(struct i915_request *rq, struct drm_printer *m, const char *msg) 2123 { 2124 struct intel_timeline *tl = get_timeline(rq); 2125 2126 i915_request_show(m, rq, msg, 0); 2127 2128 drm_printf(m, "\t\tring->start: 0x%08x\n", 2129 i915_ggtt_offset(rq->ring->vma)); 2130 drm_printf(m, "\t\tring->head: 0x%08x\n", 2131 rq->ring->head); 2132 drm_printf(m, "\t\tring->tail: 0x%08x\n", 2133 rq->ring->tail); 2134 drm_printf(m, "\t\tring->emit: 0x%08x\n", 2135 rq->ring->emit); 2136 drm_printf(m, "\t\tring->space: 0x%08x\n", 2137 rq->ring->space); 2138 2139 if (tl) { 2140 drm_printf(m, "\t\tring->hwsp: 0x%08x\n", 2141 tl->hwsp_offset); 2142 intel_timeline_put(tl); 2143 } 2144 2145 print_request_ring(m, rq); 2146 2147 if (rq->context->lrc_reg_state) { 2148 drm_printf(m, "Logical Ring Context:\n"); 2149 hexdump(m, rq->context->lrc_reg_state, PAGE_SIZE); 2150 } 2151 } 2152 2153 void intel_engine_dump_active_requests(struct list_head *requests, 2154 struct i915_request *hung_rq, 2155 struct drm_printer *m) 2156 { 2157 struct i915_request *rq; 2158 const char *msg; 2159 enum i915_request_state state; 2160 2161 list_for_each_entry(rq, requests, sched.link) { 2162 if (rq == hung_rq) 2163 continue; 2164 2165 state = i915_test_request_state(rq); 2166 if (state < I915_REQUEST_QUEUED) 2167 continue; 2168 2169 if (state == I915_REQUEST_ACTIVE) 2170 msg = "\t\tactive on engine"; 2171 else 2172 msg = "\t\tactive in queue"; 2173 2174 engine_dump_request(rq, m, msg); 2175 } 2176 } 2177 2178 static void engine_dump_active_requests(struct intel_engine_cs *engine, 2179 struct drm_printer *m) 2180 { 2181 struct intel_context *hung_ce = NULL; 2182 struct i915_request *hung_rq = NULL; 2183 2184 /* 2185 * No need for an engine->irq_seqno_barrier() before the seqno reads. 2186 * The GPU is still running so requests are still executing and any 2187 * hardware reads will be out of date by the time they are reported. 2188 * But the intention here is just to report an instantaneous snapshot 2189 * so that's fine. 2190 */ 2191 intel_engine_get_hung_entity(engine, &hung_ce, &hung_rq); 2192 2193 drm_printf(m, "\tRequests:\n"); 2194 2195 if (hung_rq) 2196 engine_dump_request(hung_rq, m, "\t\thung"); 2197 else if (hung_ce) 2198 drm_printf(m, "\t\tGot hung ce but no hung rq!\n"); 2199 2200 if (intel_uc_uses_guc_submission(&engine->gt->uc)) 2201 intel_guc_dump_active_requests(engine, hung_rq, m); 2202 else 2203 intel_execlists_dump_active_requests(engine, hung_rq, m); 2204 2205 if (hung_rq) 2206 i915_request_put(hung_rq); 2207 } 2208 2209 void intel_engine_dump(struct intel_engine_cs *engine, 2210 struct drm_printer *m, 2211 const char *header, ...) 2212 { 2213 struct i915_gpu_error * const error = &engine->i915->gpu_error; 2214 struct i915_request *rq; 2215 intel_wakeref_t wakeref; 2216 ktime_t dummy; 2217 2218 if (header) { 2219 va_list ap; 2220 2221 va_start(ap, header); 2222 drm_vprintf(m, header, &ap); 2223 va_end(ap); 2224 } 2225 2226 if (intel_gt_is_wedged(engine->gt)) 2227 drm_printf(m, "*** WEDGED ***\n"); 2228 2229 drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count)); 2230 drm_printf(m, "\tBarriers?: %s\n", 2231 str_yes_no(!llist_empty(&engine->barrier_tasks))); 2232 drm_printf(m, "\tLatency: %luus\n", 2233 ewma__engine_latency_read(&engine->latency)); 2234 if (intel_engine_supports_stats(engine)) 2235 drm_printf(m, "\tRuntime: %llums\n", 2236 ktime_to_ms(intel_engine_get_busy_time(engine, 2237 &dummy))); 2238 drm_printf(m, "\tForcewake: %x domains, %d active\n", 2239 engine->fw_domain, READ_ONCE(engine->fw_active)); 2240 2241 rcu_read_lock(); 2242 rq = READ_ONCE(engine->heartbeat.systole); 2243 if (rq) 2244 drm_printf(m, "\tHeartbeat: %d ms ago\n", 2245 jiffies_to_msecs(jiffies - rq->emitted_jiffies)); 2246 rcu_read_unlock(); 2247 drm_printf(m, "\tReset count: %d (global %d)\n", 2248 i915_reset_engine_count(error, engine), 2249 i915_reset_count(error)); 2250 print_properties(engine, m); 2251 2252 engine_dump_active_requests(engine, m); 2253 2254 drm_printf(m, "\tMMIO base: 0x%08x\n", engine->mmio_base); 2255 wakeref = intel_runtime_pm_get_if_in_use(engine->uncore->rpm); 2256 if (wakeref) { 2257 intel_engine_print_registers(engine, m); 2258 intel_runtime_pm_put(engine->uncore->rpm, wakeref); 2259 } else { 2260 drm_printf(m, "\tDevice is asleep; skipping register dump\n"); 2261 } 2262 2263 intel_execlists_show_requests(engine, m, i915_request_show, 8); 2264 2265 drm_printf(m, "HWSP:\n"); 2266 hexdump(m, engine->status_page.addr, PAGE_SIZE); 2267 2268 drm_printf(m, "Idle? %s\n", str_yes_no(intel_engine_is_idle(engine))); 2269 2270 intel_engine_print_breadcrumbs(engine, m); 2271 } 2272 2273 /** 2274 * intel_engine_get_busy_time() - Return current accumulated engine busyness 2275 * @engine: engine to report on 2276 * @now: monotonic timestamp of sampling 2277 * 2278 * Returns accumulated time @engine was busy since engine stats were enabled. 2279 */ 2280 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now) 2281 { 2282 return engine->busyness(engine, now); 2283 } 2284 2285 struct intel_context * 2286 intel_engine_create_virtual(struct intel_engine_cs **siblings, 2287 unsigned int count, unsigned long flags) 2288 { 2289 if (count == 0) 2290 return ERR_PTR(-EINVAL); 2291 2292 if (count == 1 && !(flags & FORCE_VIRTUAL)) 2293 return intel_context_create(siblings[0]); 2294 2295 GEM_BUG_ON(!siblings[0]->cops->create_virtual); 2296 return siblings[0]->cops->create_virtual(siblings, count, flags); 2297 } 2298 2299 static struct i915_request *engine_execlist_find_hung_request(struct intel_engine_cs *engine) 2300 { 2301 struct i915_request *request, *active = NULL; 2302 2303 /* 2304 * This search does not work in GuC submission mode. However, the GuC 2305 * will report the hanging context directly to the driver itself. So 2306 * the driver should never get here when in GuC mode. 2307 */ 2308 GEM_BUG_ON(intel_uc_uses_guc_submission(&engine->gt->uc)); 2309 2310 /* 2311 * We are called by the error capture, reset and to dump engine 2312 * state at random points in time. In particular, note that neither is 2313 * crucially ordered with an interrupt. After a hang, the GPU is dead 2314 * and we assume that no more writes can happen (we waited long enough 2315 * for all writes that were in transaction to be flushed) - adding an 2316 * extra delay for a recent interrupt is pointless. Hence, we do 2317 * not need an engine->irq_seqno_barrier() before the seqno reads. 2318 * At all other times, we must assume the GPU is still running, but 2319 * we only care about the snapshot of this moment. 2320 */ 2321 lockdep_assert_held(&engine->sched_engine->lock); 2322 2323 rcu_read_lock(); 2324 request = execlists_active(&engine->execlists); 2325 if (request) { 2326 struct intel_timeline *tl = request->context->timeline; 2327 2328 list_for_each_entry_from_reverse(request, &tl->requests, link) { 2329 if (__i915_request_is_complete(request)) 2330 break; 2331 2332 active = request; 2333 } 2334 } 2335 rcu_read_unlock(); 2336 if (active) 2337 return active; 2338 2339 list_for_each_entry(request, &engine->sched_engine->requests, 2340 sched.link) { 2341 if (i915_test_request_state(request) != I915_REQUEST_ACTIVE) 2342 continue; 2343 2344 active = request; 2345 break; 2346 } 2347 2348 return active; 2349 } 2350 2351 void intel_engine_get_hung_entity(struct intel_engine_cs *engine, 2352 struct intel_context **ce, struct i915_request **rq) 2353 { 2354 unsigned long flags; 2355 2356 *ce = intel_engine_get_hung_context(engine); 2357 if (*ce) { 2358 intel_engine_clear_hung_context(engine); 2359 2360 *rq = intel_context_get_active_request(*ce); 2361 return; 2362 } 2363 2364 /* 2365 * Getting here with GuC enabled means it is a forced error capture 2366 * with no actual hang. So, no need to attempt the execlist search. 2367 */ 2368 if (intel_uc_uses_guc_submission(&engine->gt->uc)) 2369 return; 2370 2371 spin_lock_irqsave(&engine->sched_engine->lock, flags); 2372 *rq = engine_execlist_find_hung_request(engine); 2373 if (*rq) 2374 *rq = i915_request_get_rcu(*rq); 2375 spin_unlock_irqrestore(&engine->sched_engine->lock, flags); 2376 } 2377 2378 void xehp_enable_ccs_engines(struct intel_engine_cs *engine) 2379 { 2380 /* 2381 * If there are any non-fused-off CCS engines, we need to enable CCS 2382 * support in the RCU_MODE register. This only needs to be done once, 2383 * so for simplicity we'll take care of this in the RCS engine's 2384 * resume handler; since the RCS and all CCS engines belong to the 2385 * same reset domain and are reset together, this will also take care 2386 * of re-applying the setting after i915-triggered resets. 2387 */ 2388 if (!CCS_MASK(engine->gt)) 2389 return; 2390 2391 intel_uncore_write(engine->uncore, GEN12_RCU_MODE, 2392 _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE)); 2393 } 2394 2395 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 2396 #include "mock_engine.c" 2397 #include "selftest_engine.c" 2398 #include "selftest_engine_cs.c" 2399 #endif 2400