xref: /openbsd-src/sys/dev/pci/drm/i915/gt/intel_context_sseu.c (revision 1bb76ff151c0aba8e3312a604e4cd2e5195cf4b7)
1c349dbc7Sjsg // SPDX-License-Identifier: MIT
2c349dbc7Sjsg /*
3c349dbc7Sjsg  * Copyright © 2019 Intel Corporation
4c349dbc7Sjsg  */
5c349dbc7Sjsg 
6c349dbc7Sjsg #include "i915_drv.h"
7c349dbc7Sjsg #include "i915_vma.h"
8c349dbc7Sjsg #include "intel_context.h"
9c349dbc7Sjsg #include "intel_engine_pm.h"
10c349dbc7Sjsg #include "intel_gpu_commands.h"
11c349dbc7Sjsg #include "intel_lrc.h"
12*1bb76ff1Sjsg #include "intel_lrc_reg.h"
13c349dbc7Sjsg #include "intel_ring.h"
14c349dbc7Sjsg #include "intel_sseu.h"
15c349dbc7Sjsg 
gen8_emit_rpcs_config(struct i915_request * rq,const struct intel_context * ce,const struct intel_sseu sseu)16c349dbc7Sjsg static int gen8_emit_rpcs_config(struct i915_request *rq,
17c349dbc7Sjsg 				 const struct intel_context *ce,
18c349dbc7Sjsg 				 const struct intel_sseu sseu)
19c349dbc7Sjsg {
20c349dbc7Sjsg 	u64 offset;
21c349dbc7Sjsg 	u32 *cs;
22c349dbc7Sjsg 
23c349dbc7Sjsg 	cs = intel_ring_begin(rq, 4);
24c349dbc7Sjsg 	if (IS_ERR(cs))
25c349dbc7Sjsg 		return PTR_ERR(cs);
26c349dbc7Sjsg 
27c349dbc7Sjsg 	offset = i915_ggtt_offset(ce->state) +
28ad8b1aafSjsg 		 LRC_STATE_OFFSET + CTX_R_PWR_CLK_STATE * 4;
29c349dbc7Sjsg 
30c349dbc7Sjsg 	*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
31c349dbc7Sjsg 	*cs++ = lower_32_bits(offset);
32c349dbc7Sjsg 	*cs++ = upper_32_bits(offset);
33ad8b1aafSjsg 	*cs++ = intel_sseu_make_rpcs(rq->engine->gt, &sseu);
34c349dbc7Sjsg 
35c349dbc7Sjsg 	intel_ring_advance(rq, cs);
36c349dbc7Sjsg 
37c349dbc7Sjsg 	return 0;
38c349dbc7Sjsg }
39c349dbc7Sjsg 
40c349dbc7Sjsg static int
gen8_modify_rpcs(struct intel_context * ce,const struct intel_sseu sseu)41c349dbc7Sjsg gen8_modify_rpcs(struct intel_context *ce, const struct intel_sseu sseu)
42c349dbc7Sjsg {
43c349dbc7Sjsg 	struct i915_request *rq;
44c349dbc7Sjsg 	int ret;
45c349dbc7Sjsg 
46c349dbc7Sjsg 	lockdep_assert_held(&ce->pin_mutex);
47c349dbc7Sjsg 
48c349dbc7Sjsg 	/*
49c349dbc7Sjsg 	 * If the context is not idle, we have to submit an ordered request to
50c349dbc7Sjsg 	 * modify its context image via the kernel context (writing to our own
51c349dbc7Sjsg 	 * image, or into the registers directory, does not stick). Pristine
52c349dbc7Sjsg 	 * and idle contexts will be configured on pinning.
53c349dbc7Sjsg 	 */
54c349dbc7Sjsg 	if (!intel_context_pin_if_active(ce))
55c349dbc7Sjsg 		return 0;
56c349dbc7Sjsg 
57c349dbc7Sjsg 	rq = intel_engine_create_kernel_request(ce->engine);
58c349dbc7Sjsg 	if (IS_ERR(rq)) {
59c349dbc7Sjsg 		ret = PTR_ERR(rq);
60c349dbc7Sjsg 		goto out_unpin;
61c349dbc7Sjsg 	}
62c349dbc7Sjsg 
63c349dbc7Sjsg 	/* Serialise with the remote context */
64c349dbc7Sjsg 	ret = intel_context_prepare_remote_request(ce, rq);
65c349dbc7Sjsg 	if (ret == 0)
66c349dbc7Sjsg 		ret = gen8_emit_rpcs_config(rq, ce, sseu);
67c349dbc7Sjsg 
68c349dbc7Sjsg 	i915_request_add(rq);
69c349dbc7Sjsg out_unpin:
70c349dbc7Sjsg 	intel_context_unpin(ce);
71c349dbc7Sjsg 	return ret;
72c349dbc7Sjsg }
73c349dbc7Sjsg 
74c349dbc7Sjsg int
intel_context_reconfigure_sseu(struct intel_context * ce,const struct intel_sseu sseu)75c349dbc7Sjsg intel_context_reconfigure_sseu(struct intel_context *ce,
76c349dbc7Sjsg 			       const struct intel_sseu sseu)
77c349dbc7Sjsg {
78c349dbc7Sjsg 	int ret;
79c349dbc7Sjsg 
805ca02815Sjsg 	GEM_BUG_ON(GRAPHICS_VER(ce->engine->i915) < 8);
81c349dbc7Sjsg 
82c349dbc7Sjsg 	ret = intel_context_lock_pinned(ce);
83c349dbc7Sjsg 	if (ret)
84c349dbc7Sjsg 		return ret;
85c349dbc7Sjsg 
86c349dbc7Sjsg 	/* Nothing to do if unmodified. */
87c349dbc7Sjsg 	if (!memcmp(&ce->sseu, &sseu, sizeof(sseu)))
88c349dbc7Sjsg 		goto unlock;
89c349dbc7Sjsg 
90c349dbc7Sjsg 	ret = gen8_modify_rpcs(ce, sseu);
91c349dbc7Sjsg 	if (!ret)
92c349dbc7Sjsg 		ce->sseu = sseu;
93c349dbc7Sjsg 
94c349dbc7Sjsg unlock:
95c349dbc7Sjsg 	intel_context_unlock_pinned(ce);
96c349dbc7Sjsg 	return ret;
97c349dbc7Sjsg }
98