1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 */ 29 30 #include <linux/export.h> 31 #include <linux/i2c-algo-bit.h> 32 #include <linux/i2c.h> 33 34 #include <drm/display/drm_hdcp_helper.h> 35 36 #include "i915_drv.h" 37 #include "intel_de.h" 38 #include "intel_display_types.h" 39 #include "intel_gmbus.h" 40 #include "intel_gmbus_regs.h" 41 42 struct intel_gmbus { 43 struct i2c_adapter adapter; 44 #define GMBUS_FORCE_BIT_RETRY (1U << 31) 45 u32 force_bit; 46 u32 reg0; 47 i915_reg_t gpio_reg; 48 struct i2c_algo_bit_data bit_algo; 49 struct drm_i915_private *i915; 50 }; 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/i2c_bitbang.h> 54 55 struct gmbus_pin { 56 const char *name; 57 enum i915_gpio gpio; 58 }; 59 60 /* Map gmbus pin pairs to names and registers. */ 61 static const struct gmbus_pin gmbus_pins[] = { 62 [GMBUS_PIN_SSC] = { "ssc", GPIOB }, 63 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 64 [GMBUS_PIN_PANEL] = { "panel", GPIOC }, 65 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 66 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 67 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 68 }; 69 70 static const struct gmbus_pin gmbus_pins_bdw[] = { 71 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 72 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 73 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 74 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 75 }; 76 77 static const struct gmbus_pin gmbus_pins_skl[] = { 78 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 79 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 80 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 81 }; 82 83 static const struct gmbus_pin gmbus_pins_bxt[] = { 84 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 85 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 86 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 87 }; 88 89 static const struct gmbus_pin gmbus_pins_cnp[] = { 90 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 91 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 92 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 93 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 94 }; 95 96 static const struct gmbus_pin gmbus_pins_icp[] = { 97 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 98 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 99 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 100 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 101 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 102 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 103 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 104 [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION }, 105 [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO }, 106 }; 107 108 static const struct gmbus_pin gmbus_pins_dg1[] = { 109 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 110 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 111 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 112 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 113 }; 114 115 static const struct gmbus_pin gmbus_pins_dg2[] = { 116 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 117 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 118 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 119 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 120 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 121 }; 122 123 static const struct gmbus_pin gmbus_pins_mtp[] = { 124 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 125 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 126 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 127 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 128 [GMBUS_PIN_5_MTP] = { "dpe", GPIOF }, 129 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 130 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 131 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 132 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 133 }; 134 135 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915, 136 unsigned int pin) 137 { 138 const struct gmbus_pin *pins; 139 size_t size; 140 141 if (INTEL_PCH_TYPE(i915) >= PCH_DG2) { 142 pins = gmbus_pins_dg2; 143 size = ARRAY_SIZE(gmbus_pins_dg2); 144 } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) { 145 pins = gmbus_pins_dg1; 146 size = ARRAY_SIZE(gmbus_pins_dg1); 147 } else if (INTEL_PCH_TYPE(i915) >= PCH_MTP) { 148 pins = gmbus_pins_mtp; 149 size = ARRAY_SIZE(gmbus_pins_mtp); 150 } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) { 151 pins = gmbus_pins_icp; 152 size = ARRAY_SIZE(gmbus_pins_icp); 153 } else if (HAS_PCH_CNP(i915)) { 154 pins = gmbus_pins_cnp; 155 size = ARRAY_SIZE(gmbus_pins_cnp); 156 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { 157 pins = gmbus_pins_bxt; 158 size = ARRAY_SIZE(gmbus_pins_bxt); 159 } else if (DISPLAY_VER(i915) == 9) { 160 pins = gmbus_pins_skl; 161 size = ARRAY_SIZE(gmbus_pins_skl); 162 } else if (IS_BROADWELL(i915)) { 163 pins = gmbus_pins_bdw; 164 size = ARRAY_SIZE(gmbus_pins_bdw); 165 } else { 166 pins = gmbus_pins; 167 size = ARRAY_SIZE(gmbus_pins); 168 } 169 170 if (pin >= size || !pins[pin].name) 171 return NULL; 172 173 return &pins[pin]; 174 } 175 176 bool intel_gmbus_is_valid_pin(struct drm_i915_private *i915, unsigned int pin) 177 { 178 return get_gmbus_pin(i915, pin); 179 } 180 181 /* Intel GPIO access functions */ 182 183 #define I2C_RISEFALL_TIME 10 184 185 static inline struct intel_gmbus * 186 to_intel_gmbus(struct i2c_adapter *i2c) 187 { 188 return container_of(i2c, struct intel_gmbus, adapter); 189 } 190 191 void 192 intel_gmbus_reset(struct drm_i915_private *i915) 193 { 194 intel_de_write(i915, GMBUS0(i915), 0); 195 intel_de_write(i915, GMBUS4(i915), 0); 196 } 197 198 static void pnv_gmbus_clock_gating(struct drm_i915_private *i915, 199 bool enable) 200 { 201 u32 val; 202 203 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 204 val = intel_de_read(i915, DSPCLK_GATE_D(i915)); 205 if (!enable) 206 val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; 207 else 208 val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; 209 intel_de_write(i915, DSPCLK_GATE_D(i915), val); 210 } 211 212 static void pch_gmbus_clock_gating(struct drm_i915_private *i915, 213 bool enable) 214 { 215 u32 val; 216 217 val = intel_de_read(i915, SOUTH_DSPCLK_GATE_D); 218 if (!enable) 219 val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; 220 else 221 val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; 222 intel_de_write(i915, SOUTH_DSPCLK_GATE_D, val); 223 } 224 225 static void bxt_gmbus_clock_gating(struct drm_i915_private *i915, 226 bool enable) 227 { 228 u32 val; 229 230 val = intel_de_read(i915, GEN9_CLKGATE_DIS_4); 231 if (!enable) 232 val |= BXT_GMBUS_GATING_DIS; 233 else 234 val &= ~BXT_GMBUS_GATING_DIS; 235 intel_de_write(i915, GEN9_CLKGATE_DIS_4, val); 236 } 237 238 static u32 get_reserved(struct intel_gmbus *bus) 239 { 240 struct drm_i915_private *i915 = bus->i915; 241 struct intel_uncore *uncore = &i915->uncore; 242 u32 reserved = 0; 243 244 /* On most chips, these bits must be preserved in software. */ 245 if (!IS_I830(i915) && !IS_I845G(i915)) 246 reserved = intel_uncore_read_notrace(uncore, bus->gpio_reg) & 247 (GPIO_DATA_PULLUP_DISABLE | 248 GPIO_CLOCK_PULLUP_DISABLE); 249 250 return reserved; 251 } 252 253 static int get_clock(void *data) 254 { 255 struct intel_gmbus *bus = data; 256 struct intel_uncore *uncore = &bus->i915->uncore; 257 u32 reserved = get_reserved(bus); 258 259 intel_uncore_write_notrace(uncore, 260 bus->gpio_reg, 261 reserved | GPIO_CLOCK_DIR_MASK); 262 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved); 263 264 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) & 265 GPIO_CLOCK_VAL_IN) != 0; 266 } 267 268 static int get_data(void *data) 269 { 270 struct intel_gmbus *bus = data; 271 struct intel_uncore *uncore = &bus->i915->uncore; 272 u32 reserved = get_reserved(bus); 273 274 intel_uncore_write_notrace(uncore, 275 bus->gpio_reg, 276 reserved | GPIO_DATA_DIR_MASK); 277 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved); 278 279 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) & 280 GPIO_DATA_VAL_IN) != 0; 281 } 282 283 static void set_clock(void *data, int state_high) 284 { 285 struct intel_gmbus *bus = data; 286 struct intel_uncore *uncore = &bus->i915->uncore; 287 u32 reserved = get_reserved(bus); 288 u32 clock_bits; 289 290 if (state_high) 291 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 292 else 293 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 294 GPIO_CLOCK_VAL_MASK; 295 296 intel_uncore_write_notrace(uncore, 297 bus->gpio_reg, 298 reserved | clock_bits); 299 intel_uncore_posting_read(uncore, bus->gpio_reg); 300 } 301 302 static void set_data(void *data, int state_high) 303 { 304 struct intel_gmbus *bus = data; 305 struct intel_uncore *uncore = &bus->i915->uncore; 306 u32 reserved = get_reserved(bus); 307 u32 data_bits; 308 309 if (state_high) 310 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 311 else 312 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 313 GPIO_DATA_VAL_MASK; 314 315 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved | data_bits); 316 intel_uncore_posting_read(uncore, bus->gpio_reg); 317 } 318 319 static int 320 intel_gpio_pre_xfer(struct i2c_adapter *adapter) 321 { 322 struct intel_gmbus *bus = to_intel_gmbus(adapter); 323 struct drm_i915_private *i915 = bus->i915; 324 325 intel_gmbus_reset(i915); 326 327 if (IS_PINEVIEW(i915)) 328 pnv_gmbus_clock_gating(i915, false); 329 330 set_data(bus, 1); 331 set_clock(bus, 1); 332 udelay(I2C_RISEFALL_TIME); 333 return 0; 334 } 335 336 static void 337 intel_gpio_post_xfer(struct i2c_adapter *adapter) 338 { 339 struct intel_gmbus *bus = to_intel_gmbus(adapter); 340 struct drm_i915_private *i915 = bus->i915; 341 342 set_data(bus, 1); 343 set_clock(bus, 1); 344 345 if (IS_PINEVIEW(i915)) 346 pnv_gmbus_clock_gating(i915, true); 347 } 348 349 void intel_bb_set_bits(void *, uint32_t); 350 void intel_bb_set_dir(void *, uint32_t); 351 uint32_t intel_bb_read_bits(void *); 352 353 int intel_acquire_bus(void *, int); 354 void intel_release_bus(void *, int); 355 int intel_send_start(void *, int); 356 int intel_send_stop(void *, int); 357 int intel_initiate_xfer(void *, i2c_addr_t, int); 358 int intel_read_byte(void *, u_int8_t *, int); 359 int intel_write_byte(void *, u_int8_t, int); 360 361 #define INTEL_BB_SDA (1 << I2C_BIT_SDA) 362 #define INTEL_BB_SCL (1 << I2C_BIT_SCL) 363 364 struct i2c_bitbang_ops intel_bbops = { 365 intel_bb_set_bits, 366 intel_bb_set_dir, 367 intel_bb_read_bits, 368 { INTEL_BB_SDA, INTEL_BB_SCL, 0, 0 } 369 }; 370 371 void 372 intel_bb_set_bits(void *cookie, uint32_t bits) 373 { 374 set_clock(cookie, bits & INTEL_BB_SCL); 375 set_data(cookie, bits & INTEL_BB_SDA); 376 } 377 378 void 379 intel_bb_set_dir(void *cookie, uint32_t bits) 380 { 381 } 382 383 uint32_t 384 intel_bb_read_bits(void *cookie) 385 { 386 uint32_t bits = 0; 387 388 if (get_clock(cookie)) 389 bits |= INTEL_BB_SCL; 390 if (get_data(cookie)) 391 bits |= INTEL_BB_SDA; 392 393 return bits; 394 } 395 396 int 397 intel_acquire_bus(void *cookie, int flags) 398 { 399 struct intel_gmbus *bus = cookie; 400 401 intel_gpio_pre_xfer(&bus->adapter); 402 return (0); 403 } 404 405 void 406 intel_release_bus(void *cookie, int flags) 407 { 408 struct intel_gmbus *bus = cookie; 409 410 intel_gpio_post_xfer(&bus->adapter); 411 } 412 413 int 414 intel_send_start(void *cookie, int flags) 415 { 416 return (i2c_bitbang_send_start(cookie, flags, &intel_bbops)); 417 } 418 419 int 420 intel_send_stop(void *cookie, int flags) 421 { 422 return (i2c_bitbang_send_stop(cookie, flags, &intel_bbops)); 423 } 424 425 int 426 intel_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 427 { 428 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, &intel_bbops)); 429 } 430 431 int 432 intel_read_byte(void *cookie, u_int8_t *bytep, int flags) 433 { 434 return (i2c_bitbang_read_byte(cookie, bytep, flags, &intel_bbops)); 435 } 436 437 int 438 intel_write_byte(void *cookie, u_int8_t byte, int flags) 439 { 440 return (i2c_bitbang_write_byte(cookie, byte, flags, &intel_bbops)); 441 } 442 443 static void 444 intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg) 445 { 446 struct i2c_algo_bit_data *algo; 447 448 algo = &bus->bit_algo; 449 450 bus->gpio_reg = gpio_reg; 451 bus->adapter.algo_data = algo; 452 #ifdef __linux__ 453 algo->setsda = set_data; 454 algo->setscl = set_clock; 455 algo->getsda = get_data; 456 algo->getscl = get_clock; 457 algo->pre_xfer = intel_gpio_pre_xfer; 458 algo->post_xfer = intel_gpio_post_xfer; 459 algo->udelay = I2C_RISEFALL_TIME; 460 algo->timeout = usecs_to_jiffies(2200); 461 algo->data = bus; 462 #else 463 algo->ic.ic_cookie = bus; 464 algo->ic.ic_acquire_bus = intel_acquire_bus; 465 algo->ic.ic_release_bus = intel_release_bus; 466 algo->ic.ic_send_start = intel_send_start; 467 algo->ic.ic_send_stop = intel_send_stop; 468 algo->ic.ic_initiate_xfer = intel_initiate_xfer; 469 algo->ic.ic_read_byte = intel_read_byte; 470 algo->ic.ic_write_byte = intel_write_byte; 471 #endif 472 } 473 474 static bool has_gmbus_irq(struct drm_i915_private *i915) 475 { 476 /* 477 * encoder->shutdown() may want to use GMBUS 478 * after irqs have already been disabled. 479 */ 480 return HAS_GMBUS_IRQ(i915) && intel_irqs_enabled(i915); 481 } 482 483 static int gmbus_wait(struct drm_i915_private *i915, u32 status, u32 irq_en) 484 { 485 DEFINE_WAIT(wait); 486 u32 gmbus2; 487 int ret; 488 489 /* Important: The hw handles only the first bit, so set only one! Since 490 * we also need to check for NAKs besides the hw ready/idle signal, we 491 * need to wake up periodically and check that ourselves. 492 */ 493 if (!has_gmbus_irq(i915) || cold) 494 irq_en = 0; 495 496 add_wait_queue(&i915->display.gmbus.wait_queue, &wait); 497 intel_de_write_fw(i915, GMBUS4(i915), irq_en); 498 499 status |= GMBUS_SATOER; 500 ret = wait_for_us((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status, 501 2); 502 if (ret) 503 ret = wait_for((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status, 504 50); 505 506 intel_de_write_fw(i915, GMBUS4(i915), 0); 507 remove_wait_queue(&i915->display.gmbus.wait_queue, &wait); 508 509 if (gmbus2 & GMBUS_SATOER) 510 return -ENXIO; 511 512 return ret; 513 } 514 515 static int 516 gmbus_wait_idle(struct drm_i915_private *i915) 517 { 518 DEFINE_WAIT(wait); 519 u32 irq_enable; 520 int ret; 521 522 /* Important: The hw handles only the first bit, so set only one! */ 523 irq_enable = 0; 524 if (has_gmbus_irq(i915) && !cold) 525 irq_enable = GMBUS_IDLE_EN; 526 527 add_wait_queue(&i915->display.gmbus.wait_queue, &wait); 528 intel_de_write_fw(i915, GMBUS4(i915), irq_enable); 529 530 ret = intel_wait_for_register_fw(&i915->uncore, 531 GMBUS2(i915), GMBUS_ACTIVE, 0, 532 10); 533 534 intel_de_write_fw(i915, GMBUS4(i915), 0); 535 remove_wait_queue(&i915->display.gmbus.wait_queue, &wait); 536 537 return ret; 538 } 539 540 static unsigned int gmbus_max_xfer_size(struct drm_i915_private *i915) 541 { 542 return DISPLAY_VER(i915) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : 543 GMBUS_BYTE_COUNT_MAX; 544 } 545 546 static int 547 gmbus_xfer_read_chunk(struct drm_i915_private *i915, 548 unsigned short addr, u8 *buf, unsigned int len, 549 u32 gmbus0_reg, u32 gmbus1_index) 550 { 551 unsigned int size = len; 552 bool burst_read = len > gmbus_max_xfer_size(i915); 553 bool extra_byte_added = false; 554 555 if (burst_read) { 556 /* 557 * As per HW Spec, for 512Bytes need to read extra Byte and 558 * Ignore the extra byte read. 559 */ 560 if (len == 512) { 561 extra_byte_added = true; 562 len++; 563 } 564 size = len % 256 + 256; 565 intel_de_write_fw(i915, GMBUS0(i915), 566 gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); 567 } 568 569 intel_de_write_fw(i915, GMBUS1(i915), 570 gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); 571 while (len) { 572 int ret; 573 u32 val, loop = 0; 574 575 ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 576 if (ret) 577 return ret; 578 579 val = intel_de_read_fw(i915, GMBUS3(i915)); 580 do { 581 if (extra_byte_added && len == 1) 582 break; 583 584 *buf++ = val & 0xff; 585 val >>= 8; 586 } while (--len && ++loop < 4); 587 588 if (burst_read && len == size - 4) 589 /* Reset the override bit */ 590 intel_de_write_fw(i915, GMBUS0(i915), gmbus0_reg); 591 } 592 593 return 0; 594 } 595 596 /* 597 * HW spec says that 512Bytes in Burst read need special treatment. 598 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate 599 * an I2C slave, which supports such a lengthy burst read too for experiments. 600 * 601 * So until things get clarified on HW support, to avoid the burst read length 602 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes. 603 */ 604 #define INTEL_GMBUS_BURST_READ_MAX_LEN 767U 605 606 static int 607 gmbus_xfer_read(struct drm_i915_private *i915, struct i2c_msg *msg, 608 u32 gmbus0_reg, u32 gmbus1_index) 609 { 610 u8 *buf = msg->buf; 611 unsigned int rx_size = msg->len; 612 unsigned int len; 613 int ret; 614 615 do { 616 if (HAS_GMBUS_BURST_READ(i915)) 617 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN); 618 else 619 len = min(rx_size, gmbus_max_xfer_size(i915)); 620 621 ret = gmbus_xfer_read_chunk(i915, msg->addr, buf, len, 622 gmbus0_reg, gmbus1_index); 623 if (ret) 624 return ret; 625 626 rx_size -= len; 627 buf += len; 628 } while (rx_size != 0); 629 630 return 0; 631 } 632 633 static int 634 gmbus_xfer_write_chunk(struct drm_i915_private *i915, 635 unsigned short addr, u8 *buf, unsigned int len, 636 u32 gmbus1_index) 637 { 638 unsigned int chunk_size = len; 639 u32 val, loop; 640 641 val = loop = 0; 642 while (len && loop < 4) { 643 val |= *buf++ << (8 * loop++); 644 len -= 1; 645 } 646 647 intel_de_write_fw(i915, GMBUS3(i915), val); 648 intel_de_write_fw(i915, GMBUS1(i915), 649 gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 650 while (len) { 651 int ret; 652 653 val = loop = 0; 654 do { 655 val |= *buf++ << (8 * loop); 656 } while (--len && ++loop < 4); 657 658 intel_de_write_fw(i915, GMBUS3(i915), val); 659 660 ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 661 if (ret) 662 return ret; 663 } 664 665 return 0; 666 } 667 668 static int 669 gmbus_xfer_write(struct drm_i915_private *i915, struct i2c_msg *msg, 670 u32 gmbus1_index) 671 { 672 u8 *buf = msg->buf; 673 unsigned int tx_size = msg->len; 674 unsigned int len; 675 int ret; 676 677 do { 678 len = min(tx_size, gmbus_max_xfer_size(i915)); 679 680 ret = gmbus_xfer_write_chunk(i915, msg->addr, buf, len, 681 gmbus1_index); 682 if (ret) 683 return ret; 684 685 buf += len; 686 tx_size -= len; 687 } while (tx_size != 0); 688 689 return 0; 690 } 691 692 /* 693 * The gmbus controller can combine a 1 or 2 byte write with another read/write 694 * that immediately follows it by using an "INDEX" cycle. 695 */ 696 static bool 697 gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num) 698 { 699 return (i + 1 < num && 700 msgs[i].addr == msgs[i + 1].addr && 701 !(msgs[i].flags & I2C_M_RD) && 702 (msgs[i].len == 1 || msgs[i].len == 2) && 703 msgs[i + 1].len > 0); 704 } 705 706 static int 707 gmbus_index_xfer(struct drm_i915_private *i915, struct i2c_msg *msgs, 708 u32 gmbus0_reg) 709 { 710 u32 gmbus1_index = 0; 711 u32 gmbus5 = 0; 712 int ret; 713 714 if (msgs[0].len == 2) 715 gmbus5 = GMBUS_2BYTE_INDEX_EN | 716 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 717 if (msgs[0].len == 1) 718 gmbus1_index = GMBUS_CYCLE_INDEX | 719 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 720 721 /* GMBUS5 holds 16-bit index */ 722 if (gmbus5) 723 intel_de_write_fw(i915, GMBUS5(i915), gmbus5); 724 725 if (msgs[1].flags & I2C_M_RD) 726 ret = gmbus_xfer_read(i915, &msgs[1], gmbus0_reg, 727 gmbus1_index); 728 else 729 ret = gmbus_xfer_write(i915, &msgs[1], gmbus1_index); 730 731 /* Clear GMBUS5 after each index transfer */ 732 if (gmbus5) 733 intel_de_write_fw(i915, GMBUS5(i915), 0); 734 735 return ret; 736 } 737 738 static int 739 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, 740 u32 gmbus0_source) 741 { 742 struct intel_gmbus *bus = to_intel_gmbus(adapter); 743 struct drm_i915_private *i915 = bus->i915; 744 int i = 0, inc, try = 0; 745 int ret = 0; 746 747 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 748 if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) 749 bxt_gmbus_clock_gating(i915, false); 750 else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915)) 751 pch_gmbus_clock_gating(i915, false); 752 753 retry: 754 intel_de_write_fw(i915, GMBUS0(i915), gmbus0_source | bus->reg0); 755 756 for (; i < num; i += inc) { 757 inc = 1; 758 if (gmbus_is_index_xfer(msgs, i, num)) { 759 ret = gmbus_index_xfer(i915, &msgs[i], 760 gmbus0_source | bus->reg0); 761 inc = 2; /* an index transmission is two msgs */ 762 } else if (msgs[i].flags & I2C_M_RD) { 763 ret = gmbus_xfer_read(i915, &msgs[i], 764 gmbus0_source | bus->reg0, 0); 765 } else { 766 ret = gmbus_xfer_write(i915, &msgs[i], 0); 767 } 768 769 if (!ret) 770 ret = gmbus_wait(i915, 771 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN); 772 if (ret == -ETIMEDOUT) 773 goto timeout; 774 else if (ret) 775 goto clear_err; 776 } 777 778 /* Generate a STOP condition on the bus. Note that gmbus can't generata 779 * a STOP on the very first cycle. To simplify the code we 780 * unconditionally generate the STOP condition with an additional gmbus 781 * cycle. */ 782 intel_de_write_fw(i915, GMBUS1(i915), GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 783 784 /* Mark the GMBUS interface as disabled after waiting for idle. 785 * We will re-enable it at the start of the next xfer, 786 * till then let it sleep. 787 */ 788 if (gmbus_wait_idle(i915)) { 789 drm_dbg_kms(&i915->drm, 790 "GMBUS [%s] timed out waiting for idle\n", 791 adapter->name); 792 ret = -ETIMEDOUT; 793 } 794 intel_de_write_fw(i915, GMBUS0(i915), 0); 795 ret = ret ?: i; 796 goto out; 797 798 clear_err: 799 /* 800 * Wait for bus to IDLE before clearing NAK. 801 * If we clear the NAK while bus is still active, then it will stay 802 * active and the next transaction may fail. 803 * 804 * If no ACK is received during the address phase of a transaction, the 805 * adapter must report -ENXIO. It is not clear what to return if no ACK 806 * is received at other times. But we have to be careful to not return 807 * spurious -ENXIO because that will prevent i2c and drm edid functions 808 * from retrying. So return -ENXIO only when gmbus properly quiescents - 809 * timing out seems to happen when there _is_ a ddc chip present, but 810 * it's slow responding and only answers on the 2nd retry. 811 */ 812 ret = -ENXIO; 813 if (gmbus_wait_idle(i915)) { 814 drm_dbg_kms(&i915->drm, 815 "GMBUS [%s] timed out after NAK\n", 816 adapter->name); 817 ret = -ETIMEDOUT; 818 } 819 820 /* Toggle the Software Clear Interrupt bit. This has the effect 821 * of resetting the GMBUS controller and so clearing the 822 * BUS_ERROR raised by the slave's NAK. 823 */ 824 intel_de_write_fw(i915, GMBUS1(i915), GMBUS_SW_CLR_INT); 825 intel_de_write_fw(i915, GMBUS1(i915), 0); 826 intel_de_write_fw(i915, GMBUS0(i915), 0); 827 828 drm_dbg_kms(&i915->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n", 829 adapter->name, msgs[i].addr, 830 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 831 832 /* 833 * Passive adapters sometimes NAK the first probe. Retry the first 834 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm 835 * has retries internally. See also the retry loop in 836 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. 837 */ 838 if (ret == -ENXIO && i == 0 && try++ == 0) { 839 drm_dbg_kms(&i915->drm, 840 "GMBUS [%s] NAK on first message, retry\n", 841 adapter->name); 842 goto retry; 843 } 844 845 goto out; 846 847 timeout: 848 drm_dbg_kms(&i915->drm, 849 "GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 850 bus->adapter.name, bus->reg0 & 0xff); 851 intel_de_write_fw(i915, GMBUS0(i915), 0); 852 853 /* 854 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging 855 * instead. Use EAGAIN to have i2c core retry. 856 */ 857 ret = -EAGAIN; 858 859 out: 860 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 861 if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) 862 bxt_gmbus_clock_gating(i915, true); 863 else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915)) 864 pch_gmbus_clock_gating(i915, true); 865 866 return ret; 867 } 868 869 static int 870 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) 871 { 872 struct intel_gmbus *bus = to_intel_gmbus(adapter); 873 struct drm_i915_private *i915 = bus->i915; 874 intel_wakeref_t wakeref; 875 int ret; 876 877 wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS); 878 879 if (bus->force_bit) { 880 ret = i2c_bit_algo.master_xfer(adapter, msgs, num); 881 if (ret < 0) 882 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; 883 } else { 884 ret = do_gmbus_xfer(adapter, msgs, num, 0); 885 if (ret == -EAGAIN) 886 bus->force_bit |= GMBUS_FORCE_BIT_RETRY; 887 } 888 889 intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref); 890 891 return ret; 892 } 893 894 int intel_gmbus_output_aksv(struct i2c_adapter *adapter) 895 { 896 struct intel_gmbus *bus = to_intel_gmbus(adapter); 897 struct drm_i915_private *i915 = bus->i915; 898 u8 cmd = DRM_HDCP_DDC_AKSV; 899 u8 buf[DRM_HDCP_KSV_LEN] = { 0 }; 900 struct i2c_msg msgs[] = { 901 { 902 .addr = DRM_HDCP_DDC_ADDR, 903 .flags = 0, 904 .len = sizeof(cmd), 905 .buf = &cmd, 906 }, 907 { 908 .addr = DRM_HDCP_DDC_ADDR, 909 .flags = 0, 910 .len = sizeof(buf), 911 .buf = buf, 912 } 913 }; 914 intel_wakeref_t wakeref; 915 int ret; 916 917 wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS); 918 mutex_lock(&i915->display.gmbus.mutex); 919 920 /* 921 * In order to output Aksv to the receiver, use an indexed write to 922 * pass the i2c command, and tell GMBUS to use the HW-provided value 923 * instead of sourcing GMBUS3 for the data. 924 */ 925 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT); 926 927 mutex_unlock(&i915->display.gmbus.mutex); 928 intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref); 929 930 return ret; 931 } 932 933 static u32 gmbus_func(struct i2c_adapter *adapter) 934 { 935 return i2c_bit_algo.functionality(adapter) & 936 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 937 /* I2C_FUNC_10BIT_ADDR | */ 938 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 939 I2C_FUNC_SMBUS_BLOCK_PROC_CALL); 940 } 941 942 static const struct i2c_algorithm gmbus_algorithm = { 943 .master_xfer = gmbus_xfer, 944 .functionality = gmbus_func 945 }; 946 947 static void gmbus_lock_bus(struct i2c_adapter *adapter, 948 unsigned int flags) 949 { 950 struct intel_gmbus *bus = to_intel_gmbus(adapter); 951 struct drm_i915_private *i915 = bus->i915; 952 953 mutex_lock(&i915->display.gmbus.mutex); 954 } 955 956 static int gmbus_trylock_bus(struct i2c_adapter *adapter, 957 unsigned int flags) 958 { 959 struct intel_gmbus *bus = to_intel_gmbus(adapter); 960 struct drm_i915_private *i915 = bus->i915; 961 962 return mutex_trylock(&i915->display.gmbus.mutex); 963 } 964 965 static void gmbus_unlock_bus(struct i2c_adapter *adapter, 966 unsigned int flags) 967 { 968 struct intel_gmbus *bus = to_intel_gmbus(adapter); 969 struct drm_i915_private *i915 = bus->i915; 970 971 mutex_unlock(&i915->display.gmbus.mutex); 972 } 973 974 static const struct i2c_lock_operations gmbus_lock_ops = { 975 .lock_bus = gmbus_lock_bus, 976 .trylock_bus = gmbus_trylock_bus, 977 .unlock_bus = gmbus_unlock_bus, 978 }; 979 980 /** 981 * intel_gmbus_setup - instantiate all Intel i2c GMBuses 982 * @i915: i915 device private 983 */ 984 int intel_gmbus_setup(struct drm_i915_private *i915) 985 { 986 #ifdef notyet 987 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 988 #endif 989 unsigned int pin; 990 int ret; 991 992 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 993 i915->display.gmbus.mmio_base = VLV_DISPLAY_BASE; 994 else if (!HAS_GMCH(i915)) 995 /* 996 * Broxton uses the same PCH offsets for South Display Engine, 997 * even though it doesn't have a PCH. 998 */ 999 i915->display.gmbus.mmio_base = PCH_DISPLAY_BASE; 1000 1001 rw_init(&i915->display.gmbus.mutex, "gmbus"); 1002 init_waitqueue_head(&i915->display.gmbus.wait_queue); 1003 1004 for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) { 1005 const struct gmbus_pin *gmbus_pin; 1006 struct intel_gmbus *bus; 1007 1008 gmbus_pin = get_gmbus_pin(i915, pin); 1009 if (!gmbus_pin) 1010 continue; 1011 1012 bus = kzalloc(sizeof(*bus), GFP_KERNEL); 1013 if (!bus) { 1014 ret = -ENOMEM; 1015 goto err; 1016 } 1017 1018 #ifdef notyet 1019 bus->adapter.owner = THIS_MODULE; 1020 bus->adapter.class = I2C_CLASS_DDC; 1021 #endif 1022 snprintf(bus->adapter.name, 1023 sizeof(bus->adapter.name), 1024 "i915 gmbus %s", gmbus_pin->name); 1025 1026 #ifdef notyet 1027 bus->adapter.dev.parent = &pdev->dev; 1028 #endif 1029 bus->i915 = i915; 1030 1031 bus->adapter.algo = &gmbus_algorithm; 1032 bus->adapter.lock_ops = &gmbus_lock_ops; 1033 1034 /* 1035 * We wish to retry with bit banging 1036 * after a timed out GMBUS attempt. 1037 */ 1038 bus->adapter.retries = 1; 1039 1040 /* By default use a conservative clock rate */ 1041 bus->reg0 = pin | GMBUS_RATE_100KHZ; 1042 1043 /* gmbus seems to be broken on i830 */ 1044 if (IS_I830(i915)) 1045 bus->force_bit = 1; 1046 1047 intel_gpio_setup(bus, GPIO(i915, gmbus_pin->gpio)); 1048 1049 ret = i2c_add_adapter(&bus->adapter); 1050 if (ret) { 1051 kfree(bus); 1052 goto err; 1053 } 1054 1055 i915->display.gmbus.bus[pin] = bus; 1056 } 1057 1058 intel_gmbus_reset(i915); 1059 1060 return 0; 1061 1062 err: 1063 intel_gmbus_teardown(i915); 1064 1065 return ret; 1066 } 1067 1068 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *i915, 1069 unsigned int pin) 1070 { 1071 if (drm_WARN_ON(&i915->drm, pin >= ARRAY_SIZE(i915->display.gmbus.bus) || 1072 !i915->display.gmbus.bus[pin])) 1073 return NULL; 1074 1075 return &i915->display.gmbus.bus[pin]->adapter; 1076 } 1077 1078 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) 1079 { 1080 struct intel_gmbus *bus = to_intel_gmbus(adapter); 1081 struct drm_i915_private *i915 = bus->i915; 1082 1083 mutex_lock(&i915->display.gmbus.mutex); 1084 1085 bus->force_bit += force_bit ? 1 : -1; 1086 drm_dbg_kms(&i915->drm, 1087 "%sabling bit-banging on %s. force bit now %d\n", 1088 force_bit ? "en" : "dis", adapter->name, 1089 bus->force_bit); 1090 1091 mutex_unlock(&i915->display.gmbus.mutex); 1092 } 1093 1094 bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 1095 { 1096 struct intel_gmbus *bus = to_intel_gmbus(adapter); 1097 1098 return bus->force_bit; 1099 } 1100 1101 void intel_gmbus_teardown(struct drm_i915_private *i915) 1102 { 1103 unsigned int pin; 1104 1105 for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) { 1106 struct intel_gmbus *bus; 1107 1108 bus = i915->display.gmbus.bus[pin]; 1109 if (!bus) 1110 continue; 1111 1112 i2c_del_adapter(&bus->adapter); 1113 1114 kfree(bus); 1115 i915->display.gmbus.bus[pin] = NULL; 1116 } 1117 } 1118