1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 */ 29 30 #include <linux/export.h> 31 #include <linux/i2c-algo-bit.h> 32 #include <linux/i2c.h> 33 34 #include <drm/drm_hdcp.h> 35 36 #include "i915_drv.h" 37 #include "intel_de.h" 38 #include "intel_display_types.h" 39 #include "intel_gmbus.h" 40 41 #include <dev/i2c/i2cvar.h> 42 #include <dev/i2c/i2c_bitbang.h> 43 44 struct gmbus_pin { 45 const char *name; 46 enum i915_gpio gpio; 47 }; 48 49 /* Map gmbus pin pairs to names and registers. */ 50 static const struct gmbus_pin gmbus_pins[] = { 51 [GMBUS_PIN_SSC] = { "ssc", GPIOB }, 52 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 53 [GMBUS_PIN_PANEL] = { "panel", GPIOC }, 54 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 55 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 56 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 57 }; 58 59 static const struct gmbus_pin gmbus_pins_bdw[] = { 60 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 61 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 62 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 63 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 64 }; 65 66 static const struct gmbus_pin gmbus_pins_skl[] = { 67 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 68 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 69 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 70 }; 71 72 static const struct gmbus_pin gmbus_pins_bxt[] = { 73 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 74 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 75 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 76 }; 77 78 static const struct gmbus_pin gmbus_pins_cnp[] = { 79 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 80 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 81 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 82 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 83 }; 84 85 static const struct gmbus_pin gmbus_pins_icp[] = { 86 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 87 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 88 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 89 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 90 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 91 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 92 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 93 [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION }, 94 [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO }, 95 }; 96 97 static const struct gmbus_pin gmbus_pins_dg1[] = { 98 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 99 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 100 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 101 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 102 }; 103 104 /* pin is expected to be valid */ 105 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, 106 unsigned int pin) 107 { 108 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 109 return &gmbus_pins_dg1[pin]; 110 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 111 return &gmbus_pins_icp[pin]; 112 else if (HAS_PCH_CNP(dev_priv)) 113 return &gmbus_pins_cnp[pin]; 114 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 115 return &gmbus_pins_bxt[pin]; 116 else if (DISPLAY_VER(dev_priv) == 9) 117 return &gmbus_pins_skl[pin]; 118 else if (IS_BROADWELL(dev_priv)) 119 return &gmbus_pins_bdw[pin]; 120 else 121 return &gmbus_pins[pin]; 122 } 123 124 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, 125 unsigned int pin) 126 { 127 unsigned int size; 128 129 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 130 size = ARRAY_SIZE(gmbus_pins_dg1); 131 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 132 size = ARRAY_SIZE(gmbus_pins_icp); 133 else if (HAS_PCH_CNP(dev_priv)) 134 size = ARRAY_SIZE(gmbus_pins_cnp); 135 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 136 size = ARRAY_SIZE(gmbus_pins_bxt); 137 else if (DISPLAY_VER(dev_priv) == 9) 138 size = ARRAY_SIZE(gmbus_pins_skl); 139 else if (IS_BROADWELL(dev_priv)) 140 size = ARRAY_SIZE(gmbus_pins_bdw); 141 else 142 size = ARRAY_SIZE(gmbus_pins); 143 144 return pin < size && get_gmbus_pin(dev_priv, pin)->name; 145 } 146 147 /* Intel GPIO access functions */ 148 149 #define I2C_RISEFALL_TIME 10 150 151 static inline struct intel_gmbus * 152 to_intel_gmbus(struct i2c_adapter *i2c) 153 { 154 return container_of(i2c, struct intel_gmbus, adapter); 155 } 156 157 void 158 intel_gmbus_reset(struct drm_i915_private *dev_priv) 159 { 160 intel_de_write(dev_priv, GMBUS0, 0); 161 intel_de_write(dev_priv, GMBUS4, 0); 162 } 163 164 static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv, 165 bool enable) 166 { 167 u32 val; 168 169 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 170 val = intel_de_read(dev_priv, DSPCLK_GATE_D); 171 if (!enable) 172 val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; 173 else 174 val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; 175 intel_de_write(dev_priv, DSPCLK_GATE_D, val); 176 } 177 178 static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv, 179 bool enable) 180 { 181 u32 val; 182 183 val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D); 184 if (!enable) 185 val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; 186 else 187 val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; 188 intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val); 189 } 190 191 static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv, 192 bool enable) 193 { 194 u32 val; 195 196 val = intel_de_read(dev_priv, GEN9_CLKGATE_DIS_4); 197 if (!enable) 198 val |= BXT_GMBUS_GATING_DIS; 199 else 200 val &= ~BXT_GMBUS_GATING_DIS; 201 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_4, val); 202 } 203 204 static u32 get_reserved(struct intel_gmbus *bus) 205 { 206 struct drm_i915_private *i915 = bus->dev_priv; 207 struct intel_uncore *uncore = &i915->uncore; 208 u32 reserved = 0; 209 210 /* On most chips, these bits must be preserved in software. */ 211 if (!IS_I830(i915) && !IS_I845G(i915)) 212 reserved = intel_uncore_read_notrace(uncore, bus->gpio_reg) & 213 (GPIO_DATA_PULLUP_DISABLE | 214 GPIO_CLOCK_PULLUP_DISABLE); 215 216 return reserved; 217 } 218 219 static int get_clock(void *data) 220 { 221 struct intel_gmbus *bus = data; 222 struct intel_uncore *uncore = &bus->dev_priv->uncore; 223 u32 reserved = get_reserved(bus); 224 225 intel_uncore_write_notrace(uncore, 226 bus->gpio_reg, 227 reserved | GPIO_CLOCK_DIR_MASK); 228 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved); 229 230 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) & 231 GPIO_CLOCK_VAL_IN) != 0; 232 } 233 234 static int get_data(void *data) 235 { 236 struct intel_gmbus *bus = data; 237 struct intel_uncore *uncore = &bus->dev_priv->uncore; 238 u32 reserved = get_reserved(bus); 239 240 intel_uncore_write_notrace(uncore, 241 bus->gpio_reg, 242 reserved | GPIO_DATA_DIR_MASK); 243 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved); 244 245 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) & 246 GPIO_DATA_VAL_IN) != 0; 247 } 248 249 static void set_clock(void *data, int state_high) 250 { 251 struct intel_gmbus *bus = data; 252 struct intel_uncore *uncore = &bus->dev_priv->uncore; 253 u32 reserved = get_reserved(bus); 254 u32 clock_bits; 255 256 if (state_high) 257 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 258 else 259 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 260 GPIO_CLOCK_VAL_MASK; 261 262 intel_uncore_write_notrace(uncore, 263 bus->gpio_reg, 264 reserved | clock_bits); 265 intel_uncore_posting_read(uncore, bus->gpio_reg); 266 } 267 268 static void set_data(void *data, int state_high) 269 { 270 struct intel_gmbus *bus = data; 271 struct intel_uncore *uncore = &bus->dev_priv->uncore; 272 u32 reserved = get_reserved(bus); 273 u32 data_bits; 274 275 if (state_high) 276 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 277 else 278 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 279 GPIO_DATA_VAL_MASK; 280 281 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved | data_bits); 282 intel_uncore_posting_read(uncore, bus->gpio_reg); 283 } 284 285 static int 286 intel_gpio_pre_xfer(struct i2c_adapter *adapter) 287 { 288 struct intel_gmbus *bus = container_of(adapter, 289 struct intel_gmbus, 290 adapter); 291 struct drm_i915_private *dev_priv = bus->dev_priv; 292 293 intel_gmbus_reset(dev_priv); 294 295 if (IS_PINEVIEW(dev_priv)) 296 pnv_gmbus_clock_gating(dev_priv, false); 297 298 set_data(bus, 1); 299 set_clock(bus, 1); 300 udelay(I2C_RISEFALL_TIME); 301 return 0; 302 } 303 304 static void 305 intel_gpio_post_xfer(struct i2c_adapter *adapter) 306 { 307 struct intel_gmbus *bus = container_of(adapter, 308 struct intel_gmbus, 309 adapter); 310 struct drm_i915_private *dev_priv = bus->dev_priv; 311 312 set_data(bus, 1); 313 set_clock(bus, 1); 314 315 if (IS_PINEVIEW(dev_priv)) 316 pnv_gmbus_clock_gating(dev_priv, true); 317 } 318 319 void intel_bb_set_bits(void *, uint32_t); 320 void intel_bb_set_dir(void *, uint32_t); 321 uint32_t intel_bb_read_bits(void *); 322 323 int intel_acquire_bus(void *, int); 324 void intel_release_bus(void *, int); 325 int intel_send_start(void *, int); 326 int intel_send_stop(void *, int); 327 int intel_initiate_xfer(void *, i2c_addr_t, int); 328 int intel_read_byte(void *, u_int8_t *, int); 329 int intel_write_byte(void *, u_int8_t, int); 330 331 #define INTEL_BB_SDA (1 << I2C_BIT_SDA) 332 #define INTEL_BB_SCL (1 << I2C_BIT_SCL) 333 334 struct i2c_bitbang_ops intel_bbops = { 335 intel_bb_set_bits, 336 intel_bb_set_dir, 337 intel_bb_read_bits, 338 { INTEL_BB_SDA, INTEL_BB_SCL, 0, 0 } 339 }; 340 341 void 342 intel_bb_set_bits(void *cookie, uint32_t bits) 343 { 344 set_clock(cookie, bits & INTEL_BB_SCL); 345 set_data(cookie, bits & INTEL_BB_SDA); 346 } 347 348 void 349 intel_bb_set_dir(void *cookie, uint32_t bits) 350 { 351 } 352 353 uint32_t 354 intel_bb_read_bits(void *cookie) 355 { 356 uint32_t bits = 0; 357 358 if (get_clock(cookie)) 359 bits |= INTEL_BB_SCL; 360 if (get_data(cookie)) 361 bits |= INTEL_BB_SDA; 362 363 return bits; 364 } 365 366 int 367 intel_acquire_bus(void *cookie, int flags) 368 { 369 struct intel_gmbus *bus = cookie; 370 371 intel_gpio_pre_xfer(&bus->adapter); 372 return (0); 373 } 374 375 void 376 intel_release_bus(void *cookie, int flags) 377 { 378 struct intel_gmbus *bus = cookie; 379 380 intel_gpio_post_xfer(&bus->adapter); 381 } 382 383 int 384 intel_send_start(void *cookie, int flags) 385 { 386 return (i2c_bitbang_send_start(cookie, flags, &intel_bbops)); 387 } 388 389 int 390 intel_send_stop(void *cookie, int flags) 391 { 392 return (i2c_bitbang_send_stop(cookie, flags, &intel_bbops)); 393 } 394 395 int 396 intel_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 397 { 398 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, &intel_bbops)); 399 } 400 401 int 402 intel_read_byte(void *cookie, u_int8_t *bytep, int flags) 403 { 404 return (i2c_bitbang_read_byte(cookie, bytep, flags, &intel_bbops)); 405 } 406 407 int 408 intel_write_byte(void *cookie, u_int8_t byte, int flags) 409 { 410 return (i2c_bitbang_write_byte(cookie, byte, flags, &intel_bbops)); 411 } 412 413 static void 414 intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin) 415 { 416 struct drm_i915_private *dev_priv = bus->dev_priv; 417 struct i2c_algo_bit_data *algo; 418 419 algo = &bus->bit_algo; 420 421 bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio); 422 bus->adapter.algo_data = algo; 423 #ifdef __linux__ 424 algo->setsda = set_data; 425 algo->setscl = set_clock; 426 algo->getsda = get_data; 427 algo->getscl = get_clock; 428 algo->pre_xfer = intel_gpio_pre_xfer; 429 algo->post_xfer = intel_gpio_post_xfer; 430 algo->udelay = I2C_RISEFALL_TIME; 431 algo->timeout = usecs_to_jiffies(2200); 432 algo->data = bus; 433 #else 434 algo->ic.ic_cookie = bus; 435 algo->ic.ic_acquire_bus = intel_acquire_bus; 436 algo->ic.ic_release_bus = intel_release_bus; 437 algo->ic.ic_send_start = intel_send_start; 438 algo->ic.ic_send_stop = intel_send_stop; 439 algo->ic.ic_initiate_xfer = intel_initiate_xfer; 440 algo->ic.ic_read_byte = intel_read_byte; 441 algo->ic.ic_write_byte = intel_write_byte; 442 #endif 443 } 444 445 static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en) 446 { 447 DEFINE_WAIT(wait); 448 u32 gmbus2; 449 int ret; 450 451 /* Important: The hw handles only the first bit, so set only one! Since 452 * we also need to check for NAKs besides the hw ready/idle signal, we 453 * need to wake up periodically and check that ourselves. 454 */ 455 if (!HAS_GMBUS_IRQ(dev_priv) || cold) 456 irq_en = 0; 457 458 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 459 intel_de_write_fw(dev_priv, GMBUS4, irq_en); 460 461 status |= GMBUS_SATOER; 462 ret = wait_for_us((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status, 463 2); 464 if (ret) 465 ret = wait_for((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status, 466 50); 467 468 intel_de_write_fw(dev_priv, GMBUS4, 0); 469 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 470 471 if (gmbus2 & GMBUS_SATOER) 472 return -ENXIO; 473 474 return ret; 475 } 476 477 static int 478 gmbus_wait_idle(struct drm_i915_private *dev_priv) 479 { 480 DEFINE_WAIT(wait); 481 u32 irq_enable; 482 int ret; 483 484 /* Important: The hw handles only the first bit, so set only one! */ 485 irq_enable = 0; 486 if (HAS_GMBUS_IRQ(dev_priv) && !cold) 487 irq_enable = GMBUS_IDLE_EN; 488 489 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 490 intel_de_write_fw(dev_priv, GMBUS4, irq_enable); 491 492 ret = intel_wait_for_register_fw(&dev_priv->uncore, 493 GMBUS2, GMBUS_ACTIVE, 0, 494 10); 495 496 intel_de_write_fw(dev_priv, GMBUS4, 0); 497 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 498 499 return ret; 500 } 501 502 static unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv) 503 { 504 return DISPLAY_VER(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : 505 GMBUS_BYTE_COUNT_MAX; 506 } 507 508 static int 509 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, 510 unsigned short addr, u8 *buf, unsigned int len, 511 u32 gmbus0_reg, u32 gmbus1_index) 512 { 513 unsigned int size = len; 514 bool burst_read = len > gmbus_max_xfer_size(dev_priv); 515 bool extra_byte_added = false; 516 517 if (burst_read) { 518 /* 519 * As per HW Spec, for 512Bytes need to read extra Byte and 520 * Ignore the extra byte read. 521 */ 522 if (len == 512) { 523 extra_byte_added = true; 524 len++; 525 } 526 size = len % 256 + 256; 527 intel_de_write_fw(dev_priv, GMBUS0, 528 gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); 529 } 530 531 intel_de_write_fw(dev_priv, GMBUS1, 532 gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); 533 while (len) { 534 int ret; 535 u32 val, loop = 0; 536 537 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 538 if (ret) 539 return ret; 540 541 val = intel_de_read_fw(dev_priv, GMBUS3); 542 do { 543 if (extra_byte_added && len == 1) 544 break; 545 546 *buf++ = val & 0xff; 547 val >>= 8; 548 } while (--len && ++loop < 4); 549 550 if (burst_read && len == size - 4) 551 /* Reset the override bit */ 552 intel_de_write_fw(dev_priv, GMBUS0, gmbus0_reg); 553 } 554 555 return 0; 556 } 557 558 /* 559 * HW spec says that 512Bytes in Burst read need special treatment. 560 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate 561 * an I2C slave, which supports such a lengthy burst read too for experiments. 562 * 563 * So until things get clarified on HW support, to avoid the burst read length 564 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes. 565 */ 566 #define INTEL_GMBUS_BURST_READ_MAX_LEN 767U 567 568 static int 569 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, 570 u32 gmbus0_reg, u32 gmbus1_index) 571 { 572 u8 *buf = msg->buf; 573 unsigned int rx_size = msg->len; 574 unsigned int len; 575 int ret; 576 577 do { 578 if (HAS_GMBUS_BURST_READ(dev_priv)) 579 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN); 580 else 581 len = min(rx_size, gmbus_max_xfer_size(dev_priv)); 582 583 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len, 584 gmbus0_reg, gmbus1_index); 585 if (ret) 586 return ret; 587 588 rx_size -= len; 589 buf += len; 590 } while (rx_size != 0); 591 592 return 0; 593 } 594 595 static int 596 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, 597 unsigned short addr, u8 *buf, unsigned int len, 598 u32 gmbus1_index) 599 { 600 unsigned int chunk_size = len; 601 u32 val, loop; 602 603 val = loop = 0; 604 while (len && loop < 4) { 605 val |= *buf++ << (8 * loop++); 606 len -= 1; 607 } 608 609 intel_de_write_fw(dev_priv, GMBUS3, val); 610 intel_de_write_fw(dev_priv, GMBUS1, 611 gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 612 while (len) { 613 int ret; 614 615 val = loop = 0; 616 do { 617 val |= *buf++ << (8 * loop); 618 } while (--len && ++loop < 4); 619 620 intel_de_write_fw(dev_priv, GMBUS3, val); 621 622 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 623 if (ret) 624 return ret; 625 } 626 627 return 0; 628 } 629 630 static int 631 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg, 632 u32 gmbus1_index) 633 { 634 u8 *buf = msg->buf; 635 unsigned int tx_size = msg->len; 636 unsigned int len; 637 int ret; 638 639 do { 640 len = min(tx_size, gmbus_max_xfer_size(dev_priv)); 641 642 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len, 643 gmbus1_index); 644 if (ret) 645 return ret; 646 647 buf += len; 648 tx_size -= len; 649 } while (tx_size != 0); 650 651 return 0; 652 } 653 654 /* 655 * The gmbus controller can combine a 1 or 2 byte write with another read/write 656 * that immediately follows it by using an "INDEX" cycle. 657 */ 658 static bool 659 gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num) 660 { 661 return (i + 1 < num && 662 msgs[i].addr == msgs[i + 1].addr && 663 !(msgs[i].flags & I2C_M_RD) && 664 (msgs[i].len == 1 || msgs[i].len == 2) && 665 msgs[i + 1].len > 0); 666 } 667 668 static int 669 gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs, 670 u32 gmbus0_reg) 671 { 672 u32 gmbus1_index = 0; 673 u32 gmbus5 = 0; 674 int ret; 675 676 if (msgs[0].len == 2) 677 gmbus5 = GMBUS_2BYTE_INDEX_EN | 678 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 679 if (msgs[0].len == 1) 680 gmbus1_index = GMBUS_CYCLE_INDEX | 681 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 682 683 /* GMBUS5 holds 16-bit index */ 684 if (gmbus5) 685 intel_de_write_fw(dev_priv, GMBUS5, gmbus5); 686 687 if (msgs[1].flags & I2C_M_RD) 688 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg, 689 gmbus1_index); 690 else 691 ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index); 692 693 /* Clear GMBUS5 after each index transfer */ 694 if (gmbus5) 695 intel_de_write_fw(dev_priv, GMBUS5, 0); 696 697 return ret; 698 } 699 700 static int 701 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, 702 u32 gmbus0_source) 703 { 704 struct intel_gmbus *bus = container_of(adapter, 705 struct intel_gmbus, 706 adapter); 707 struct drm_i915_private *dev_priv = bus->dev_priv; 708 int i = 0, inc, try = 0; 709 int ret = 0; 710 711 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 712 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 713 bxt_gmbus_clock_gating(dev_priv, false); 714 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv)) 715 pch_gmbus_clock_gating(dev_priv, false); 716 717 retry: 718 intel_de_write_fw(dev_priv, GMBUS0, gmbus0_source | bus->reg0); 719 720 for (; i < num; i += inc) { 721 inc = 1; 722 if (gmbus_is_index_xfer(msgs, i, num)) { 723 ret = gmbus_index_xfer(dev_priv, &msgs[i], 724 gmbus0_source | bus->reg0); 725 inc = 2; /* an index transmission is two msgs */ 726 } else if (msgs[i].flags & I2C_M_RD) { 727 ret = gmbus_xfer_read(dev_priv, &msgs[i], 728 gmbus0_source | bus->reg0, 0); 729 } else { 730 ret = gmbus_xfer_write(dev_priv, &msgs[i], 0); 731 } 732 733 if (!ret) 734 ret = gmbus_wait(dev_priv, 735 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN); 736 if (ret == -ETIMEDOUT) 737 goto timeout; 738 else if (ret) 739 goto clear_err; 740 } 741 742 /* Generate a STOP condition on the bus. Note that gmbus can't generata 743 * a STOP on the very first cycle. To simplify the code we 744 * unconditionally generate the STOP condition with an additional gmbus 745 * cycle. */ 746 intel_de_write_fw(dev_priv, GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 747 748 /* Mark the GMBUS interface as disabled after waiting for idle. 749 * We will re-enable it at the start of the next xfer, 750 * till then let it sleep. 751 */ 752 if (gmbus_wait_idle(dev_priv)) { 753 drm_dbg_kms(&dev_priv->drm, 754 "GMBUS [%s] timed out waiting for idle\n", 755 adapter->name); 756 ret = -ETIMEDOUT; 757 } 758 intel_de_write_fw(dev_priv, GMBUS0, 0); 759 ret = ret ?: i; 760 goto out; 761 762 clear_err: 763 /* 764 * Wait for bus to IDLE before clearing NAK. 765 * If we clear the NAK while bus is still active, then it will stay 766 * active and the next transaction may fail. 767 * 768 * If no ACK is received during the address phase of a transaction, the 769 * adapter must report -ENXIO. It is not clear what to return if no ACK 770 * is received at other times. But we have to be careful to not return 771 * spurious -ENXIO because that will prevent i2c and drm edid functions 772 * from retrying. So return -ENXIO only when gmbus properly quiescents - 773 * timing out seems to happen when there _is_ a ddc chip present, but 774 * it's slow responding and only answers on the 2nd retry. 775 */ 776 ret = -ENXIO; 777 if (gmbus_wait_idle(dev_priv)) { 778 drm_dbg_kms(&dev_priv->drm, 779 "GMBUS [%s] timed out after NAK\n", 780 adapter->name); 781 ret = -ETIMEDOUT; 782 } 783 784 /* Toggle the Software Clear Interrupt bit. This has the effect 785 * of resetting the GMBUS controller and so clearing the 786 * BUS_ERROR raised by the slave's NAK. 787 */ 788 intel_de_write_fw(dev_priv, GMBUS1, GMBUS_SW_CLR_INT); 789 intel_de_write_fw(dev_priv, GMBUS1, 0); 790 intel_de_write_fw(dev_priv, GMBUS0, 0); 791 792 drm_dbg_kms(&dev_priv->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n", 793 adapter->name, msgs[i].addr, 794 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 795 796 /* 797 * Passive adapters sometimes NAK the first probe. Retry the first 798 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm 799 * has retries internally. See also the retry loop in 800 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. 801 */ 802 if (ret == -ENXIO && i == 0 && try++ == 0) { 803 drm_dbg_kms(&dev_priv->drm, 804 "GMBUS [%s] NAK on first message, retry\n", 805 adapter->name); 806 goto retry; 807 } 808 809 goto out; 810 811 timeout: 812 drm_dbg_kms(&dev_priv->drm, 813 "GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 814 bus->adapter.name, bus->reg0 & 0xff); 815 intel_de_write_fw(dev_priv, GMBUS0, 0); 816 817 /* 818 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging 819 * instead. Use EAGAIN to have i2c core retry. 820 */ 821 ret = -EAGAIN; 822 823 out: 824 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 825 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 826 bxt_gmbus_clock_gating(dev_priv, true); 827 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv)) 828 pch_gmbus_clock_gating(dev_priv, true); 829 830 return ret; 831 } 832 833 static int 834 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) 835 { 836 struct intel_gmbus *bus = 837 container_of(adapter, struct intel_gmbus, adapter); 838 struct drm_i915_private *dev_priv = bus->dev_priv; 839 intel_wakeref_t wakeref; 840 int ret; 841 842 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 843 844 if (bus->force_bit) { 845 ret = i2c_bit_algo.master_xfer(adapter, msgs, num); 846 if (ret < 0) 847 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; 848 } else { 849 ret = do_gmbus_xfer(adapter, msgs, num, 0); 850 if (ret == -EAGAIN) 851 bus->force_bit |= GMBUS_FORCE_BIT_RETRY; 852 } 853 854 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 855 856 return ret; 857 } 858 859 int intel_gmbus_output_aksv(struct i2c_adapter *adapter) 860 { 861 struct intel_gmbus *bus = 862 container_of(adapter, struct intel_gmbus, adapter); 863 struct drm_i915_private *dev_priv = bus->dev_priv; 864 u8 cmd = DRM_HDCP_DDC_AKSV; 865 u8 buf[DRM_HDCP_KSV_LEN] = { 0 }; 866 struct i2c_msg msgs[] = { 867 { 868 .addr = DRM_HDCP_DDC_ADDR, 869 .flags = 0, 870 .len = sizeof(cmd), 871 .buf = &cmd, 872 }, 873 { 874 .addr = DRM_HDCP_DDC_ADDR, 875 .flags = 0, 876 .len = sizeof(buf), 877 .buf = buf, 878 } 879 }; 880 intel_wakeref_t wakeref; 881 int ret; 882 883 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 884 mutex_lock(&dev_priv->gmbus_mutex); 885 886 /* 887 * In order to output Aksv to the receiver, use an indexed write to 888 * pass the i2c command, and tell GMBUS to use the HW-provided value 889 * instead of sourcing GMBUS3 for the data. 890 */ 891 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT); 892 893 mutex_unlock(&dev_priv->gmbus_mutex); 894 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 895 896 return ret; 897 } 898 899 static u32 gmbus_func(struct i2c_adapter *adapter) 900 { 901 return i2c_bit_algo.functionality(adapter) & 902 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 903 /* I2C_FUNC_10BIT_ADDR | */ 904 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 905 I2C_FUNC_SMBUS_BLOCK_PROC_CALL); 906 } 907 908 static const struct i2c_algorithm gmbus_algorithm = { 909 .master_xfer = gmbus_xfer, 910 .functionality = gmbus_func 911 }; 912 913 static void gmbus_lock_bus(struct i2c_adapter *adapter, 914 unsigned int flags) 915 { 916 struct intel_gmbus *bus = to_intel_gmbus(adapter); 917 struct drm_i915_private *dev_priv = bus->dev_priv; 918 919 mutex_lock(&dev_priv->gmbus_mutex); 920 } 921 922 static int gmbus_trylock_bus(struct i2c_adapter *adapter, 923 unsigned int flags) 924 { 925 struct intel_gmbus *bus = to_intel_gmbus(adapter); 926 struct drm_i915_private *dev_priv = bus->dev_priv; 927 928 return mutex_trylock(&dev_priv->gmbus_mutex); 929 } 930 931 static void gmbus_unlock_bus(struct i2c_adapter *adapter, 932 unsigned int flags) 933 { 934 struct intel_gmbus *bus = to_intel_gmbus(adapter); 935 struct drm_i915_private *dev_priv = bus->dev_priv; 936 937 mutex_unlock(&dev_priv->gmbus_mutex); 938 } 939 940 static const struct i2c_lock_operations gmbus_lock_ops = { 941 .lock_bus = gmbus_lock_bus, 942 .trylock_bus = gmbus_trylock_bus, 943 .unlock_bus = gmbus_unlock_bus, 944 }; 945 946 /** 947 * intel_gmbus_setup - instantiate all Intel i2c GMBuses 948 * @dev_priv: i915 device private 949 */ 950 int intel_gmbus_setup(struct drm_i915_private *dev_priv) 951 { 952 #ifdef notyet 953 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 954 #endif 955 struct intel_gmbus *bus; 956 unsigned int pin; 957 int ret; 958 959 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 960 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; 961 else if (!HAS_GMCH(dev_priv)) 962 /* 963 * Broxton uses the same PCH offsets for South Display Engine, 964 * even though it doesn't have a PCH. 965 */ 966 dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE; 967 968 rw_init(&dev_priv->gmbus_mutex, "gmbus"); 969 init_waitqueue_head(&dev_priv->gmbus_wait_queue); 970 971 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { 972 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) 973 continue; 974 975 bus = &dev_priv->gmbus[pin]; 976 977 #ifdef notyet 978 bus->adapter.owner = THIS_MODULE; 979 bus->adapter.class = I2C_CLASS_DDC; 980 #endif 981 snprintf(bus->adapter.name, 982 sizeof(bus->adapter.name), 983 "i915 gmbus %s", 984 get_gmbus_pin(dev_priv, pin)->name); 985 986 #ifdef notyet 987 bus->adapter.dev.parent = &pdev->dev; 988 #endif 989 bus->dev_priv = dev_priv; 990 991 bus->adapter.algo = &gmbus_algorithm; 992 bus->adapter.lock_ops = &gmbus_lock_ops; 993 994 /* 995 * We wish to retry with bit banging 996 * after a timed out GMBUS attempt. 997 */ 998 bus->adapter.retries = 1; 999 1000 /* By default use a conservative clock rate */ 1001 bus->reg0 = pin | GMBUS_RATE_100KHZ; 1002 1003 /* gmbus seems to be broken on i830 */ 1004 if (IS_I830(dev_priv)) 1005 bus->force_bit = 1; 1006 1007 intel_gpio_setup(bus, pin); 1008 1009 ret = i2c_add_adapter(&bus->adapter); 1010 if (ret) 1011 goto err; 1012 } 1013 1014 intel_gmbus_reset(dev_priv); 1015 1016 return 0; 1017 1018 err: 1019 while (pin--) { 1020 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) 1021 continue; 1022 1023 bus = &dev_priv->gmbus[pin]; 1024 i2c_del_adapter(&bus->adapter); 1025 } 1026 return ret; 1027 } 1028 1029 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, 1030 unsigned int pin) 1031 { 1032 if (drm_WARN_ON(&dev_priv->drm, 1033 !intel_gmbus_is_valid_pin(dev_priv, pin))) 1034 return NULL; 1035 1036 return &dev_priv->gmbus[pin].adapter; 1037 } 1038 1039 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed) 1040 { 1041 struct intel_gmbus *bus = to_intel_gmbus(adapter); 1042 1043 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed; 1044 } 1045 1046 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) 1047 { 1048 struct intel_gmbus *bus = to_intel_gmbus(adapter); 1049 struct drm_i915_private *dev_priv = bus->dev_priv; 1050 1051 mutex_lock(&dev_priv->gmbus_mutex); 1052 1053 bus->force_bit += force_bit ? 1 : -1; 1054 drm_dbg_kms(&dev_priv->drm, 1055 "%sabling bit-banging on %s. force bit now %d\n", 1056 force_bit ? "en" : "dis", adapter->name, 1057 bus->force_bit); 1058 1059 mutex_unlock(&dev_priv->gmbus_mutex); 1060 } 1061 1062 bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 1063 { 1064 struct intel_gmbus *bus = to_intel_gmbus(adapter); 1065 1066 return bus->force_bit; 1067 } 1068 1069 void intel_gmbus_teardown(struct drm_i915_private *dev_priv) 1070 { 1071 struct intel_gmbus *bus; 1072 unsigned int pin; 1073 1074 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { 1075 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) 1076 continue; 1077 1078 bus = &dev_priv->gmbus[pin]; 1079 i2c_del_adapter(&bus->adapter); 1080 } 1081 } 1082