1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 */ 29 30 #include <linux/export.h> 31 #include <linux/i2c-algo-bit.h> 32 #include <linux/i2c.h> 33 34 #include <drm/display/drm_hdcp_helper.h> 35 36 #include "i915_drv.h" 37 #include "i915_irq.h" 38 #include "i915_reg.h" 39 #include "intel_de.h" 40 #include "intel_display_types.h" 41 #include "intel_gmbus.h" 42 #include "intel_gmbus_regs.h" 43 44 struct intel_gmbus { 45 struct i2c_adapter adapter; 46 #define GMBUS_FORCE_BIT_RETRY (1U << 31) 47 u32 force_bit; 48 u32 reg0; 49 i915_reg_t gpio_reg; 50 struct i2c_algo_bit_data bit_algo; 51 struct drm_i915_private *i915; 52 }; 53 54 enum gmbus_gpio { 55 GPIOA, 56 GPIOB, 57 GPIOC, 58 GPIOD, 59 GPIOE, 60 GPIOF, 61 GPIOG, 62 GPIOH, 63 __GPIOI_UNUSED, 64 GPIOJ, 65 GPIOK, 66 GPIOL, 67 GPIOM, 68 GPION, 69 GPIOO, 70 }; 71 72 #include <dev/i2c/i2cvar.h> 73 #include <dev/i2c/i2c_bitbang.h> 74 75 struct gmbus_pin { 76 const char *name; 77 enum gmbus_gpio gpio; 78 }; 79 80 /* Map gmbus pin pairs to names and registers. */ 81 static const struct gmbus_pin gmbus_pins[] = { 82 [GMBUS_PIN_SSC] = { "ssc", GPIOB }, 83 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 84 [GMBUS_PIN_PANEL] = { "panel", GPIOC }, 85 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 86 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 87 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 88 }; 89 90 static const struct gmbus_pin gmbus_pins_bdw[] = { 91 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 92 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 93 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 94 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 95 }; 96 97 static const struct gmbus_pin gmbus_pins_skl[] = { 98 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 99 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 100 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 101 }; 102 103 static const struct gmbus_pin gmbus_pins_bxt[] = { 104 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 105 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 106 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 107 }; 108 109 static const struct gmbus_pin gmbus_pins_cnp[] = { 110 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 111 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 112 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 113 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 114 }; 115 116 static const struct gmbus_pin gmbus_pins_icp[] = { 117 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 118 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 119 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 120 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 121 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 122 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 123 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 124 [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION }, 125 [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO }, 126 }; 127 128 static const struct gmbus_pin gmbus_pins_dg1[] = { 129 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 130 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 131 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 132 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 133 }; 134 135 static const struct gmbus_pin gmbus_pins_dg2[] = { 136 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 137 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 138 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 139 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 140 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 141 }; 142 143 static const struct gmbus_pin gmbus_pins_mtp[] = { 144 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 145 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 146 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 147 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 148 [GMBUS_PIN_5_MTP] = { "dpe", GPIOF }, 149 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 150 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 151 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 152 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 153 }; 154 155 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915, 156 unsigned int pin) 157 { 158 const struct gmbus_pin *pins; 159 size_t size; 160 161 if (INTEL_PCH_TYPE(i915) >= PCH_DG2) { 162 pins = gmbus_pins_dg2; 163 size = ARRAY_SIZE(gmbus_pins_dg2); 164 } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) { 165 pins = gmbus_pins_dg1; 166 size = ARRAY_SIZE(gmbus_pins_dg1); 167 } else if (INTEL_PCH_TYPE(i915) >= PCH_MTP) { 168 pins = gmbus_pins_mtp; 169 size = ARRAY_SIZE(gmbus_pins_mtp); 170 } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) { 171 pins = gmbus_pins_icp; 172 size = ARRAY_SIZE(gmbus_pins_icp); 173 } else if (HAS_PCH_CNP(i915)) { 174 pins = gmbus_pins_cnp; 175 size = ARRAY_SIZE(gmbus_pins_cnp); 176 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { 177 pins = gmbus_pins_bxt; 178 size = ARRAY_SIZE(gmbus_pins_bxt); 179 } else if (DISPLAY_VER(i915) == 9) { 180 pins = gmbus_pins_skl; 181 size = ARRAY_SIZE(gmbus_pins_skl); 182 } else if (IS_BROADWELL(i915)) { 183 pins = gmbus_pins_bdw; 184 size = ARRAY_SIZE(gmbus_pins_bdw); 185 } else { 186 pins = gmbus_pins; 187 size = ARRAY_SIZE(gmbus_pins); 188 } 189 190 if (pin >= size || !pins[pin].name) 191 return NULL; 192 193 return &pins[pin]; 194 } 195 196 bool intel_gmbus_is_valid_pin(struct drm_i915_private *i915, unsigned int pin) 197 { 198 return get_gmbus_pin(i915, pin); 199 } 200 201 /* Intel GPIO access functions */ 202 203 #define I2C_RISEFALL_TIME 10 204 205 static inline struct intel_gmbus * 206 to_intel_gmbus(struct i2c_adapter *i2c) 207 { 208 return container_of(i2c, struct intel_gmbus, adapter); 209 } 210 211 void 212 intel_gmbus_reset(struct drm_i915_private *i915) 213 { 214 intel_de_write(i915, GMBUS0(i915), 0); 215 intel_de_write(i915, GMBUS4(i915), 0); 216 } 217 218 static void pnv_gmbus_clock_gating(struct drm_i915_private *i915, 219 bool enable) 220 { 221 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 222 intel_de_rmw(i915, DSPCLK_GATE_D(i915), PNV_GMBUSUNIT_CLOCK_GATE_DISABLE, 223 !enable ? PNV_GMBUSUNIT_CLOCK_GATE_DISABLE : 0); 224 } 225 226 static void pch_gmbus_clock_gating(struct drm_i915_private *i915, 227 bool enable) 228 { 229 intel_de_rmw(i915, SOUTH_DSPCLK_GATE_D, PCH_GMBUSUNIT_CLOCK_GATE_DISABLE, 230 !enable ? PCH_GMBUSUNIT_CLOCK_GATE_DISABLE : 0); 231 } 232 233 static void bxt_gmbus_clock_gating(struct drm_i915_private *i915, 234 bool enable) 235 { 236 intel_de_rmw(i915, GEN9_CLKGATE_DIS_4, BXT_GMBUS_GATING_DIS, 237 !enable ? BXT_GMBUS_GATING_DIS : 0); 238 } 239 240 static u32 get_reserved(struct intel_gmbus *bus) 241 { 242 struct drm_i915_private *i915 = bus->i915; 243 u32 reserved = 0; 244 245 /* On most chips, these bits must be preserved in software. */ 246 if (!IS_I830(i915) && !IS_I845G(i915)) 247 reserved = intel_de_read_notrace(i915, bus->gpio_reg) & 248 (GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE); 249 250 return reserved; 251 } 252 253 static int get_clock(void *data) 254 { 255 struct intel_gmbus *bus = data; 256 struct drm_i915_private *i915 = bus->i915; 257 u32 reserved = get_reserved(bus); 258 259 intel_de_write_notrace(i915, bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK); 260 intel_de_write_notrace(i915, bus->gpio_reg, reserved); 261 262 return (intel_de_read_notrace(i915, bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0; 263 } 264 265 static int get_data(void *data) 266 { 267 struct intel_gmbus *bus = data; 268 struct drm_i915_private *i915 = bus->i915; 269 u32 reserved = get_reserved(bus); 270 271 intel_de_write_notrace(i915, bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK); 272 intel_de_write_notrace(i915, bus->gpio_reg, reserved); 273 274 return (intel_de_read_notrace(i915, bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0; 275 } 276 277 static void set_clock(void *data, int state_high) 278 { 279 struct intel_gmbus *bus = data; 280 struct drm_i915_private *i915 = bus->i915; 281 u32 reserved = get_reserved(bus); 282 u32 clock_bits; 283 284 if (state_high) 285 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 286 else 287 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 288 GPIO_CLOCK_VAL_MASK; 289 290 intel_de_write_notrace(i915, bus->gpio_reg, reserved | clock_bits); 291 intel_de_posting_read(i915, bus->gpio_reg); 292 } 293 294 static void set_data(void *data, int state_high) 295 { 296 struct intel_gmbus *bus = data; 297 struct drm_i915_private *i915 = bus->i915; 298 u32 reserved = get_reserved(bus); 299 u32 data_bits; 300 301 if (state_high) 302 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 303 else 304 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 305 GPIO_DATA_VAL_MASK; 306 307 intel_de_write_notrace(i915, bus->gpio_reg, reserved | data_bits); 308 intel_de_posting_read(i915, bus->gpio_reg); 309 } 310 311 static int 312 intel_gpio_pre_xfer(struct i2c_adapter *adapter) 313 { 314 struct intel_gmbus *bus = to_intel_gmbus(adapter); 315 struct drm_i915_private *i915 = bus->i915; 316 317 intel_gmbus_reset(i915); 318 319 if (IS_PINEVIEW(i915)) 320 pnv_gmbus_clock_gating(i915, false); 321 322 set_data(bus, 1); 323 set_clock(bus, 1); 324 udelay(I2C_RISEFALL_TIME); 325 return 0; 326 } 327 328 static void 329 intel_gpio_post_xfer(struct i2c_adapter *adapter) 330 { 331 struct intel_gmbus *bus = to_intel_gmbus(adapter); 332 struct drm_i915_private *i915 = bus->i915; 333 334 set_data(bus, 1); 335 set_clock(bus, 1); 336 337 if (IS_PINEVIEW(i915)) 338 pnv_gmbus_clock_gating(i915, true); 339 } 340 341 void intel_bb_set_bits(void *, uint32_t); 342 void intel_bb_set_dir(void *, uint32_t); 343 uint32_t intel_bb_read_bits(void *); 344 345 int intel_acquire_bus(void *, int); 346 void intel_release_bus(void *, int); 347 int intel_send_start(void *, int); 348 int intel_send_stop(void *, int); 349 int intel_initiate_xfer(void *, i2c_addr_t, int); 350 int intel_read_byte(void *, u_int8_t *, int); 351 int intel_write_byte(void *, u_int8_t, int); 352 353 #define INTEL_BB_SDA (1 << I2C_BIT_SDA) 354 #define INTEL_BB_SCL (1 << I2C_BIT_SCL) 355 356 struct i2c_bitbang_ops intel_bbops = { 357 intel_bb_set_bits, 358 intel_bb_set_dir, 359 intel_bb_read_bits, 360 { INTEL_BB_SDA, INTEL_BB_SCL, 0, 0 } 361 }; 362 363 void 364 intel_bb_set_bits(void *cookie, uint32_t bits) 365 { 366 set_clock(cookie, bits & INTEL_BB_SCL); 367 set_data(cookie, bits & INTEL_BB_SDA); 368 } 369 370 void 371 intel_bb_set_dir(void *cookie, uint32_t bits) 372 { 373 } 374 375 uint32_t 376 intel_bb_read_bits(void *cookie) 377 { 378 uint32_t bits = 0; 379 380 if (get_clock(cookie)) 381 bits |= INTEL_BB_SCL; 382 if (get_data(cookie)) 383 bits |= INTEL_BB_SDA; 384 385 return bits; 386 } 387 388 int 389 intel_acquire_bus(void *cookie, int flags) 390 { 391 struct intel_gmbus *bus = cookie; 392 393 intel_gpio_pre_xfer(&bus->adapter); 394 return (0); 395 } 396 397 void 398 intel_release_bus(void *cookie, int flags) 399 { 400 struct intel_gmbus *bus = cookie; 401 402 intel_gpio_post_xfer(&bus->adapter); 403 } 404 405 int 406 intel_send_start(void *cookie, int flags) 407 { 408 return (i2c_bitbang_send_start(cookie, flags, &intel_bbops)); 409 } 410 411 int 412 intel_send_stop(void *cookie, int flags) 413 { 414 return (i2c_bitbang_send_stop(cookie, flags, &intel_bbops)); 415 } 416 417 int 418 intel_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 419 { 420 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, &intel_bbops)); 421 } 422 423 int 424 intel_read_byte(void *cookie, u_int8_t *bytep, int flags) 425 { 426 return (i2c_bitbang_read_byte(cookie, bytep, flags, &intel_bbops)); 427 } 428 429 int 430 intel_write_byte(void *cookie, u_int8_t byte, int flags) 431 { 432 return (i2c_bitbang_write_byte(cookie, byte, flags, &intel_bbops)); 433 } 434 435 static void 436 intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg) 437 { 438 struct i2c_algo_bit_data *algo; 439 440 algo = &bus->bit_algo; 441 442 bus->gpio_reg = gpio_reg; 443 bus->adapter.algo_data = algo; 444 #ifdef __linux__ 445 algo->setsda = set_data; 446 algo->setscl = set_clock; 447 algo->getsda = get_data; 448 algo->getscl = get_clock; 449 algo->pre_xfer = intel_gpio_pre_xfer; 450 algo->post_xfer = intel_gpio_post_xfer; 451 algo->udelay = I2C_RISEFALL_TIME; 452 algo->timeout = usecs_to_jiffies(2200); 453 algo->data = bus; 454 #else 455 algo->ic.ic_cookie = bus; 456 algo->ic.ic_acquire_bus = intel_acquire_bus; 457 algo->ic.ic_release_bus = intel_release_bus; 458 algo->ic.ic_send_start = intel_send_start; 459 algo->ic.ic_send_stop = intel_send_stop; 460 algo->ic.ic_initiate_xfer = intel_initiate_xfer; 461 algo->ic.ic_read_byte = intel_read_byte; 462 algo->ic.ic_write_byte = intel_write_byte; 463 #endif 464 } 465 466 static bool has_gmbus_irq(struct drm_i915_private *i915) 467 { 468 /* 469 * encoder->shutdown() may want to use GMBUS 470 * after irqs have already been disabled. 471 */ 472 return HAS_GMBUS_IRQ(i915) && intel_irqs_enabled(i915); 473 } 474 475 static int gmbus_wait(struct drm_i915_private *i915, u32 status, u32 irq_en) 476 { 477 DEFINE_WAIT(wait); 478 u32 gmbus2; 479 int ret; 480 481 /* Important: The hw handles only the first bit, so set only one! Since 482 * we also need to check for NAKs besides the hw ready/idle signal, we 483 * need to wake up periodically and check that ourselves. 484 */ 485 if (!has_gmbus_irq(i915) || cold) 486 irq_en = 0; 487 488 add_wait_queue(&i915->display.gmbus.wait_queue, &wait); 489 intel_de_write_fw(i915, GMBUS4(i915), irq_en); 490 491 status |= GMBUS_SATOER; 492 ret = wait_for_us((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status, 493 2); 494 if (ret) 495 ret = wait_for((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status, 496 50); 497 498 intel_de_write_fw(i915, GMBUS4(i915), 0); 499 remove_wait_queue(&i915->display.gmbus.wait_queue, &wait); 500 501 if (gmbus2 & GMBUS_SATOER) 502 return -ENXIO; 503 504 return ret; 505 } 506 507 static int 508 gmbus_wait_idle(struct drm_i915_private *i915) 509 { 510 DEFINE_WAIT(wait); 511 u32 irq_enable; 512 int ret; 513 514 /* Important: The hw handles only the first bit, so set only one! */ 515 irq_enable = 0; 516 if (has_gmbus_irq(i915) && !cold) 517 irq_enable = GMBUS_IDLE_EN; 518 519 add_wait_queue(&i915->display.gmbus.wait_queue, &wait); 520 intel_de_write_fw(i915, GMBUS4(i915), irq_enable); 521 522 ret = intel_de_wait_for_register_fw(i915, GMBUS2(i915), GMBUS_ACTIVE, 0, 10); 523 524 intel_de_write_fw(i915, GMBUS4(i915), 0); 525 remove_wait_queue(&i915->display.gmbus.wait_queue, &wait); 526 527 return ret; 528 } 529 530 static unsigned int gmbus_max_xfer_size(struct drm_i915_private *i915) 531 { 532 return DISPLAY_VER(i915) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : 533 GMBUS_BYTE_COUNT_MAX; 534 } 535 536 static int 537 gmbus_xfer_read_chunk(struct drm_i915_private *i915, 538 unsigned short addr, u8 *buf, unsigned int len, 539 u32 gmbus0_reg, u32 gmbus1_index) 540 { 541 unsigned int size = len; 542 bool burst_read = len > gmbus_max_xfer_size(i915); 543 bool extra_byte_added = false; 544 545 if (burst_read) { 546 /* 547 * As per HW Spec, for 512Bytes need to read extra Byte and 548 * Ignore the extra byte read. 549 */ 550 if (len == 512) { 551 extra_byte_added = true; 552 len++; 553 } 554 size = len % 256 + 256; 555 intel_de_write_fw(i915, GMBUS0(i915), 556 gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); 557 } 558 559 intel_de_write_fw(i915, GMBUS1(i915), 560 gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); 561 while (len) { 562 int ret; 563 u32 val, loop = 0; 564 565 ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 566 if (ret) 567 return ret; 568 569 val = intel_de_read_fw(i915, GMBUS3(i915)); 570 do { 571 if (extra_byte_added && len == 1) 572 break; 573 574 *buf++ = val & 0xff; 575 val >>= 8; 576 } while (--len && ++loop < 4); 577 578 if (burst_read && len == size - 4) 579 /* Reset the override bit */ 580 intel_de_write_fw(i915, GMBUS0(i915), gmbus0_reg); 581 } 582 583 return 0; 584 } 585 586 /* 587 * HW spec says that 512Bytes in Burst read need special treatment. 588 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate 589 * an I2C slave, which supports such a lengthy burst read too for experiments. 590 * 591 * So until things get clarified on HW support, to avoid the burst read length 592 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes. 593 */ 594 #define INTEL_GMBUS_BURST_READ_MAX_LEN 767U 595 596 static int 597 gmbus_xfer_read(struct drm_i915_private *i915, struct i2c_msg *msg, 598 u32 gmbus0_reg, u32 gmbus1_index) 599 { 600 u8 *buf = msg->buf; 601 unsigned int rx_size = msg->len; 602 unsigned int len; 603 int ret; 604 605 do { 606 if (HAS_GMBUS_BURST_READ(i915)) 607 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN); 608 else 609 len = min(rx_size, gmbus_max_xfer_size(i915)); 610 611 ret = gmbus_xfer_read_chunk(i915, msg->addr, buf, len, 612 gmbus0_reg, gmbus1_index); 613 if (ret) 614 return ret; 615 616 rx_size -= len; 617 buf += len; 618 } while (rx_size != 0); 619 620 return 0; 621 } 622 623 static int 624 gmbus_xfer_write_chunk(struct drm_i915_private *i915, 625 unsigned short addr, u8 *buf, unsigned int len, 626 u32 gmbus1_index) 627 { 628 unsigned int chunk_size = len; 629 u32 val, loop; 630 631 val = loop = 0; 632 while (len && loop < 4) { 633 val |= *buf++ << (8 * loop++); 634 len -= 1; 635 } 636 637 intel_de_write_fw(i915, GMBUS3(i915), val); 638 intel_de_write_fw(i915, GMBUS1(i915), 639 gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 640 while (len) { 641 int ret; 642 643 val = loop = 0; 644 do { 645 val |= *buf++ << (8 * loop); 646 } while (--len && ++loop < 4); 647 648 intel_de_write_fw(i915, GMBUS3(i915), val); 649 650 ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 651 if (ret) 652 return ret; 653 } 654 655 return 0; 656 } 657 658 static int 659 gmbus_xfer_write(struct drm_i915_private *i915, struct i2c_msg *msg, 660 u32 gmbus1_index) 661 { 662 u8 *buf = msg->buf; 663 unsigned int tx_size = msg->len; 664 unsigned int len; 665 int ret; 666 667 do { 668 len = min(tx_size, gmbus_max_xfer_size(i915)); 669 670 ret = gmbus_xfer_write_chunk(i915, msg->addr, buf, len, 671 gmbus1_index); 672 if (ret) 673 return ret; 674 675 buf += len; 676 tx_size -= len; 677 } while (tx_size != 0); 678 679 return 0; 680 } 681 682 /* 683 * The gmbus controller can combine a 1 or 2 byte write with another read/write 684 * that immediately follows it by using an "INDEX" cycle. 685 */ 686 static bool 687 gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num) 688 { 689 return (i + 1 < num && 690 msgs[i].addr == msgs[i + 1].addr && 691 !(msgs[i].flags & I2C_M_RD) && 692 (msgs[i].len == 1 || msgs[i].len == 2) && 693 msgs[i + 1].len > 0); 694 } 695 696 static int 697 gmbus_index_xfer(struct drm_i915_private *i915, struct i2c_msg *msgs, 698 u32 gmbus0_reg) 699 { 700 u32 gmbus1_index = 0; 701 u32 gmbus5 = 0; 702 int ret; 703 704 if (msgs[0].len == 2) 705 gmbus5 = GMBUS_2BYTE_INDEX_EN | 706 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 707 if (msgs[0].len == 1) 708 gmbus1_index = GMBUS_CYCLE_INDEX | 709 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 710 711 /* GMBUS5 holds 16-bit index */ 712 if (gmbus5) 713 intel_de_write_fw(i915, GMBUS5(i915), gmbus5); 714 715 if (msgs[1].flags & I2C_M_RD) 716 ret = gmbus_xfer_read(i915, &msgs[1], gmbus0_reg, 717 gmbus1_index); 718 else 719 ret = gmbus_xfer_write(i915, &msgs[1], gmbus1_index); 720 721 /* Clear GMBUS5 after each index transfer */ 722 if (gmbus5) 723 intel_de_write_fw(i915, GMBUS5(i915), 0); 724 725 return ret; 726 } 727 728 static int 729 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, 730 u32 gmbus0_source) 731 { 732 struct intel_gmbus *bus = to_intel_gmbus(adapter); 733 struct drm_i915_private *i915 = bus->i915; 734 int i = 0, inc, try = 0; 735 int ret = 0; 736 737 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 738 if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) 739 bxt_gmbus_clock_gating(i915, false); 740 else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915)) 741 pch_gmbus_clock_gating(i915, false); 742 743 retry: 744 intel_de_write_fw(i915, GMBUS0(i915), gmbus0_source | bus->reg0); 745 746 for (; i < num; i += inc) { 747 inc = 1; 748 if (gmbus_is_index_xfer(msgs, i, num)) { 749 ret = gmbus_index_xfer(i915, &msgs[i], 750 gmbus0_source | bus->reg0); 751 inc = 2; /* an index transmission is two msgs */ 752 } else if (msgs[i].flags & I2C_M_RD) { 753 ret = gmbus_xfer_read(i915, &msgs[i], 754 gmbus0_source | bus->reg0, 0); 755 } else { 756 ret = gmbus_xfer_write(i915, &msgs[i], 0); 757 } 758 759 if (!ret) 760 ret = gmbus_wait(i915, 761 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN); 762 if (ret == -ETIMEDOUT) 763 goto timeout; 764 else if (ret) 765 goto clear_err; 766 } 767 768 /* Generate a STOP condition on the bus. Note that gmbus can't generata 769 * a STOP on the very first cycle. To simplify the code we 770 * unconditionally generate the STOP condition with an additional gmbus 771 * cycle. */ 772 intel_de_write_fw(i915, GMBUS1(i915), GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 773 774 /* Mark the GMBUS interface as disabled after waiting for idle. 775 * We will re-enable it at the start of the next xfer, 776 * till then let it sleep. 777 */ 778 if (gmbus_wait_idle(i915)) { 779 drm_dbg_kms(&i915->drm, 780 "GMBUS [%s] timed out waiting for idle\n", 781 adapter->name); 782 ret = -ETIMEDOUT; 783 } 784 intel_de_write_fw(i915, GMBUS0(i915), 0); 785 ret = ret ?: i; 786 goto out; 787 788 clear_err: 789 /* 790 * Wait for bus to IDLE before clearing NAK. 791 * If we clear the NAK while bus is still active, then it will stay 792 * active and the next transaction may fail. 793 * 794 * If no ACK is received during the address phase of a transaction, the 795 * adapter must report -ENXIO. It is not clear what to return if no ACK 796 * is received at other times. But we have to be careful to not return 797 * spurious -ENXIO because that will prevent i2c and drm edid functions 798 * from retrying. So return -ENXIO only when gmbus properly quiescents - 799 * timing out seems to happen when there _is_ a ddc chip present, but 800 * it's slow responding and only answers on the 2nd retry. 801 */ 802 ret = -ENXIO; 803 if (gmbus_wait_idle(i915)) { 804 drm_dbg_kms(&i915->drm, 805 "GMBUS [%s] timed out after NAK\n", 806 adapter->name); 807 ret = -ETIMEDOUT; 808 } 809 810 /* Toggle the Software Clear Interrupt bit. This has the effect 811 * of resetting the GMBUS controller and so clearing the 812 * BUS_ERROR raised by the slave's NAK. 813 */ 814 intel_de_write_fw(i915, GMBUS1(i915), GMBUS_SW_CLR_INT); 815 intel_de_write_fw(i915, GMBUS1(i915), 0); 816 intel_de_write_fw(i915, GMBUS0(i915), 0); 817 818 drm_dbg_kms(&i915->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n", 819 adapter->name, msgs[i].addr, 820 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 821 822 /* 823 * Passive adapters sometimes NAK the first probe. Retry the first 824 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm 825 * has retries internally. See also the retry loop in 826 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. 827 */ 828 if (ret == -ENXIO && i == 0 && try++ == 0) { 829 drm_dbg_kms(&i915->drm, 830 "GMBUS [%s] NAK on first message, retry\n", 831 adapter->name); 832 goto retry; 833 } 834 835 goto out; 836 837 timeout: 838 drm_dbg_kms(&i915->drm, 839 "GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 840 bus->adapter.name, bus->reg0 & 0xff); 841 intel_de_write_fw(i915, GMBUS0(i915), 0); 842 843 /* 844 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging 845 * instead. Use EAGAIN to have i2c core retry. 846 */ 847 ret = -EAGAIN; 848 849 out: 850 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 851 if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) 852 bxt_gmbus_clock_gating(i915, true); 853 else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915)) 854 pch_gmbus_clock_gating(i915, true); 855 856 return ret; 857 } 858 859 static int 860 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) 861 { 862 struct intel_gmbus *bus = to_intel_gmbus(adapter); 863 struct drm_i915_private *i915 = bus->i915; 864 intel_wakeref_t wakeref; 865 int ret; 866 867 wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS); 868 869 if (bus->force_bit) { 870 ret = i2c_bit_algo.master_xfer(adapter, msgs, num); 871 if (ret < 0) 872 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; 873 } else { 874 ret = do_gmbus_xfer(adapter, msgs, num, 0); 875 if (ret == -EAGAIN) 876 bus->force_bit |= GMBUS_FORCE_BIT_RETRY; 877 } 878 879 intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref); 880 881 return ret; 882 } 883 884 int intel_gmbus_output_aksv(struct i2c_adapter *adapter) 885 { 886 struct intel_gmbus *bus = to_intel_gmbus(adapter); 887 struct drm_i915_private *i915 = bus->i915; 888 u8 cmd = DRM_HDCP_DDC_AKSV; 889 u8 buf[DRM_HDCP_KSV_LEN] = { 0 }; 890 struct i2c_msg msgs[] = { 891 { 892 .addr = DRM_HDCP_DDC_ADDR, 893 .flags = 0, 894 .len = sizeof(cmd), 895 .buf = &cmd, 896 }, 897 { 898 .addr = DRM_HDCP_DDC_ADDR, 899 .flags = 0, 900 .len = sizeof(buf), 901 .buf = buf, 902 } 903 }; 904 intel_wakeref_t wakeref; 905 int ret; 906 907 wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS); 908 mutex_lock(&i915->display.gmbus.mutex); 909 910 /* 911 * In order to output Aksv to the receiver, use an indexed write to 912 * pass the i2c command, and tell GMBUS to use the HW-provided value 913 * instead of sourcing GMBUS3 for the data. 914 */ 915 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT); 916 917 mutex_unlock(&i915->display.gmbus.mutex); 918 intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref); 919 920 return ret; 921 } 922 923 static u32 gmbus_func(struct i2c_adapter *adapter) 924 { 925 return i2c_bit_algo.functionality(adapter) & 926 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 927 /* I2C_FUNC_10BIT_ADDR | */ 928 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 929 I2C_FUNC_SMBUS_BLOCK_PROC_CALL); 930 } 931 932 static const struct i2c_algorithm gmbus_algorithm = { 933 .master_xfer = gmbus_xfer, 934 .functionality = gmbus_func 935 }; 936 937 static void gmbus_lock_bus(struct i2c_adapter *adapter, 938 unsigned int flags) 939 { 940 struct intel_gmbus *bus = to_intel_gmbus(adapter); 941 struct drm_i915_private *i915 = bus->i915; 942 943 mutex_lock(&i915->display.gmbus.mutex); 944 } 945 946 static int gmbus_trylock_bus(struct i2c_adapter *adapter, 947 unsigned int flags) 948 { 949 struct intel_gmbus *bus = to_intel_gmbus(adapter); 950 struct drm_i915_private *i915 = bus->i915; 951 952 return mutex_trylock(&i915->display.gmbus.mutex); 953 } 954 955 static void gmbus_unlock_bus(struct i2c_adapter *adapter, 956 unsigned int flags) 957 { 958 struct intel_gmbus *bus = to_intel_gmbus(adapter); 959 struct drm_i915_private *i915 = bus->i915; 960 961 mutex_unlock(&i915->display.gmbus.mutex); 962 } 963 964 static const struct i2c_lock_operations gmbus_lock_ops = { 965 .lock_bus = gmbus_lock_bus, 966 .trylock_bus = gmbus_trylock_bus, 967 .unlock_bus = gmbus_unlock_bus, 968 }; 969 970 /** 971 * intel_gmbus_setup - instantiate all Intel i2c GMBuses 972 * @i915: i915 device private 973 */ 974 int intel_gmbus_setup(struct drm_i915_private *i915) 975 { 976 #ifdef notyet 977 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 978 #endif 979 unsigned int pin; 980 int ret; 981 982 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 983 i915->display.gmbus.mmio_base = VLV_DISPLAY_BASE; 984 else if (!HAS_GMCH(i915)) 985 /* 986 * Broxton uses the same PCH offsets for South Display Engine, 987 * even though it doesn't have a PCH. 988 */ 989 i915->display.gmbus.mmio_base = PCH_DISPLAY_BASE; 990 991 rw_init(&i915->display.gmbus.mutex, "gmbus"); 992 init_waitqueue_head(&i915->display.gmbus.wait_queue); 993 994 for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) { 995 const struct gmbus_pin *gmbus_pin; 996 struct intel_gmbus *bus; 997 998 gmbus_pin = get_gmbus_pin(i915, pin); 999 if (!gmbus_pin) 1000 continue; 1001 1002 bus = kzalloc(sizeof(*bus), GFP_KERNEL); 1003 if (!bus) { 1004 ret = -ENOMEM; 1005 goto err; 1006 } 1007 1008 #ifdef notyet 1009 bus->adapter.owner = THIS_MODULE; 1010 bus->adapter.class = I2C_CLASS_DDC; 1011 #endif 1012 snprintf(bus->adapter.name, 1013 sizeof(bus->adapter.name), 1014 "i915 gmbus %s", gmbus_pin->name); 1015 1016 #ifdef notyet 1017 bus->adapter.dev.parent = &pdev->dev; 1018 #endif 1019 bus->i915 = i915; 1020 1021 bus->adapter.algo = &gmbus_algorithm; 1022 bus->adapter.lock_ops = &gmbus_lock_ops; 1023 1024 /* 1025 * We wish to retry with bit banging 1026 * after a timed out GMBUS attempt. 1027 */ 1028 bus->adapter.retries = 1; 1029 1030 /* By default use a conservative clock rate */ 1031 bus->reg0 = pin | GMBUS_RATE_100KHZ; 1032 1033 /* gmbus seems to be broken on i830 */ 1034 if (IS_I830(i915)) 1035 bus->force_bit = 1; 1036 1037 intel_gpio_setup(bus, GPIO(i915, gmbus_pin->gpio)); 1038 1039 ret = i2c_add_adapter(&bus->adapter); 1040 if (ret) { 1041 kfree(bus); 1042 goto err; 1043 } 1044 1045 i915->display.gmbus.bus[pin] = bus; 1046 } 1047 1048 intel_gmbus_reset(i915); 1049 1050 return 0; 1051 1052 err: 1053 intel_gmbus_teardown(i915); 1054 1055 return ret; 1056 } 1057 1058 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *i915, 1059 unsigned int pin) 1060 { 1061 if (drm_WARN_ON(&i915->drm, pin >= ARRAY_SIZE(i915->display.gmbus.bus) || 1062 !i915->display.gmbus.bus[pin])) 1063 return NULL; 1064 1065 return &i915->display.gmbus.bus[pin]->adapter; 1066 } 1067 1068 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) 1069 { 1070 struct intel_gmbus *bus = to_intel_gmbus(adapter); 1071 struct drm_i915_private *i915 = bus->i915; 1072 1073 mutex_lock(&i915->display.gmbus.mutex); 1074 1075 bus->force_bit += force_bit ? 1 : -1; 1076 drm_dbg_kms(&i915->drm, 1077 "%sabling bit-banging on %s. force bit now %d\n", 1078 force_bit ? "en" : "dis", adapter->name, 1079 bus->force_bit); 1080 1081 mutex_unlock(&i915->display.gmbus.mutex); 1082 } 1083 1084 bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 1085 { 1086 struct intel_gmbus *bus = to_intel_gmbus(adapter); 1087 1088 return bus->force_bit; 1089 } 1090 1091 void intel_gmbus_teardown(struct drm_i915_private *i915) 1092 { 1093 unsigned int pin; 1094 1095 for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) { 1096 struct intel_gmbus *bus; 1097 1098 bus = i915->display.gmbus.bus[pin]; 1099 if (!bus) 1100 continue; 1101 1102 i2c_del_adapter(&bus->adapter); 1103 1104 kfree(bus); 1105 i915->display.gmbus.bus[pin] = NULL; 1106 } 1107 } 1108 1109 void intel_gmbus_irq_handler(struct drm_i915_private *i915) 1110 { 1111 wake_up_all(&i915->display.gmbus.wait_queue); 1112 } 1113