1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 */ 29 30 #include <linux/export.h> 31 #include <linux/i2c-algo-bit.h> 32 #include <linux/i2c.h> 33 34 #include <drm/drm_hdcp.h> 35 36 #include "i915_drv.h" 37 #include "intel_display_types.h" 38 #include "intel_gmbus.h" 39 40 #include <dev/i2c/i2cvar.h> 41 #include <dev/i2c/i2c_bitbang.h> 42 43 struct gmbus_pin { 44 const char *name; 45 enum i915_gpio gpio; 46 }; 47 48 /* Map gmbus pin pairs to names and registers. */ 49 static const struct gmbus_pin gmbus_pins[] = { 50 [GMBUS_PIN_SSC] = { "ssc", GPIOB }, 51 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 52 [GMBUS_PIN_PANEL] = { "panel", GPIOC }, 53 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 54 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 55 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 56 }; 57 58 static const struct gmbus_pin gmbus_pins_bdw[] = { 59 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 60 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 61 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 62 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 63 }; 64 65 static const struct gmbus_pin gmbus_pins_skl[] = { 66 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 67 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 68 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 69 }; 70 71 static const struct gmbus_pin gmbus_pins_bxt[] = { 72 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 73 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 74 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 75 }; 76 77 static const struct gmbus_pin gmbus_pins_cnp[] = { 78 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 79 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 80 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 81 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 82 }; 83 84 static const struct gmbus_pin gmbus_pins_icp[] = { 85 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 86 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 87 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 88 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 89 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 90 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 91 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 92 [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION }, 93 [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO }, 94 }; 95 96 /* pin is expected to be valid */ 97 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, 98 unsigned int pin) 99 { 100 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 101 return &gmbus_pins_icp[pin]; 102 else if (HAS_PCH_CNP(dev_priv)) 103 return &gmbus_pins_cnp[pin]; 104 else if (IS_GEN9_LP(dev_priv)) 105 return &gmbus_pins_bxt[pin]; 106 else if (IS_GEN9_BC(dev_priv)) 107 return &gmbus_pins_skl[pin]; 108 else if (IS_BROADWELL(dev_priv)) 109 return &gmbus_pins_bdw[pin]; 110 else 111 return &gmbus_pins[pin]; 112 } 113 114 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, 115 unsigned int pin) 116 { 117 unsigned int size; 118 119 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 120 size = ARRAY_SIZE(gmbus_pins_icp); 121 else if (HAS_PCH_CNP(dev_priv)) 122 size = ARRAY_SIZE(gmbus_pins_cnp); 123 else if (IS_GEN9_LP(dev_priv)) 124 size = ARRAY_SIZE(gmbus_pins_bxt); 125 else if (IS_GEN9_BC(dev_priv)) 126 size = ARRAY_SIZE(gmbus_pins_skl); 127 else if (IS_BROADWELL(dev_priv)) 128 size = ARRAY_SIZE(gmbus_pins_bdw); 129 else 130 size = ARRAY_SIZE(gmbus_pins); 131 132 return pin < size && get_gmbus_pin(dev_priv, pin)->name; 133 } 134 135 /* Intel GPIO access functions */ 136 137 #define I2C_RISEFALL_TIME 10 138 139 static inline struct intel_gmbus * 140 to_intel_gmbus(struct i2c_adapter *i2c) 141 { 142 return container_of(i2c, struct intel_gmbus, adapter); 143 } 144 145 void 146 intel_gmbus_reset(struct drm_i915_private *dev_priv) 147 { 148 intel_de_write(dev_priv, GMBUS0, 0); 149 intel_de_write(dev_priv, GMBUS4, 0); 150 } 151 152 static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv, 153 bool enable) 154 { 155 u32 val; 156 157 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 158 val = intel_de_read(dev_priv, DSPCLK_GATE_D); 159 if (!enable) 160 val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; 161 else 162 val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; 163 intel_de_write(dev_priv, DSPCLK_GATE_D, val); 164 } 165 166 static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv, 167 bool enable) 168 { 169 u32 val; 170 171 val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D); 172 if (!enable) 173 val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; 174 else 175 val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; 176 intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val); 177 } 178 179 static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv, 180 bool enable) 181 { 182 u32 val; 183 184 val = intel_de_read(dev_priv, GEN9_CLKGATE_DIS_4); 185 if (!enable) 186 val |= BXT_GMBUS_GATING_DIS; 187 else 188 val &= ~BXT_GMBUS_GATING_DIS; 189 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_4, val); 190 } 191 192 static u32 get_reserved(struct intel_gmbus *bus) 193 { 194 struct drm_i915_private *i915 = bus->dev_priv; 195 struct intel_uncore *uncore = &i915->uncore; 196 u32 reserved = 0; 197 198 /* On most chips, these bits must be preserved in software. */ 199 if (!IS_I830(i915) && !IS_I845G(i915)) 200 reserved = intel_uncore_read_notrace(uncore, bus->gpio_reg) & 201 (GPIO_DATA_PULLUP_DISABLE | 202 GPIO_CLOCK_PULLUP_DISABLE); 203 204 return reserved; 205 } 206 207 static int get_clock(void *data) 208 { 209 struct intel_gmbus *bus = data; 210 struct intel_uncore *uncore = &bus->dev_priv->uncore; 211 u32 reserved = get_reserved(bus); 212 213 intel_uncore_write_notrace(uncore, 214 bus->gpio_reg, 215 reserved | GPIO_CLOCK_DIR_MASK); 216 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved); 217 218 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) & 219 GPIO_CLOCK_VAL_IN) != 0; 220 } 221 222 static int get_data(void *data) 223 { 224 struct intel_gmbus *bus = data; 225 struct intel_uncore *uncore = &bus->dev_priv->uncore; 226 u32 reserved = get_reserved(bus); 227 228 intel_uncore_write_notrace(uncore, 229 bus->gpio_reg, 230 reserved | GPIO_DATA_DIR_MASK); 231 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved); 232 233 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) & 234 GPIO_DATA_VAL_IN) != 0; 235 } 236 237 static void set_clock(void *data, int state_high) 238 { 239 struct intel_gmbus *bus = data; 240 struct intel_uncore *uncore = &bus->dev_priv->uncore; 241 u32 reserved = get_reserved(bus); 242 u32 clock_bits; 243 244 if (state_high) 245 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 246 else 247 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 248 GPIO_CLOCK_VAL_MASK; 249 250 intel_uncore_write_notrace(uncore, 251 bus->gpio_reg, 252 reserved | clock_bits); 253 intel_uncore_posting_read(uncore, bus->gpio_reg); 254 } 255 256 static void set_data(void *data, int state_high) 257 { 258 struct intel_gmbus *bus = data; 259 struct intel_uncore *uncore = &bus->dev_priv->uncore; 260 u32 reserved = get_reserved(bus); 261 u32 data_bits; 262 263 if (state_high) 264 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 265 else 266 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 267 GPIO_DATA_VAL_MASK; 268 269 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved | data_bits); 270 intel_uncore_posting_read(uncore, bus->gpio_reg); 271 } 272 273 static int 274 intel_gpio_pre_xfer(struct i2c_adapter *adapter) 275 { 276 struct intel_gmbus *bus = container_of(adapter, 277 struct intel_gmbus, 278 adapter); 279 struct drm_i915_private *dev_priv = bus->dev_priv; 280 281 intel_gmbus_reset(dev_priv); 282 283 if (IS_PINEVIEW(dev_priv)) 284 pnv_gmbus_clock_gating(dev_priv, false); 285 286 set_data(bus, 1); 287 set_clock(bus, 1); 288 udelay(I2C_RISEFALL_TIME); 289 return 0; 290 } 291 292 static void 293 intel_gpio_post_xfer(struct i2c_adapter *adapter) 294 { 295 struct intel_gmbus *bus = container_of(adapter, 296 struct intel_gmbus, 297 adapter); 298 struct drm_i915_private *dev_priv = bus->dev_priv; 299 300 set_data(bus, 1); 301 set_clock(bus, 1); 302 303 if (IS_PINEVIEW(dev_priv)) 304 pnv_gmbus_clock_gating(dev_priv, true); 305 } 306 307 void intel_bb_set_bits(void *, uint32_t); 308 void intel_bb_set_dir(void *, uint32_t); 309 uint32_t intel_bb_read_bits(void *); 310 311 int intel_acquire_bus(void *, int); 312 void intel_release_bus(void *, int); 313 int intel_send_start(void *, int); 314 int intel_send_stop(void *, int); 315 int intel_initiate_xfer(void *, i2c_addr_t, int); 316 int intel_read_byte(void *, u_int8_t *, int); 317 int intel_write_byte(void *, u_int8_t, int); 318 319 #define INTEL_BB_SDA (1 << I2C_BIT_SDA) 320 #define INTEL_BB_SCL (1 << I2C_BIT_SCL) 321 322 struct i2c_bitbang_ops intel_bbops = { 323 intel_bb_set_bits, 324 intel_bb_set_dir, 325 intel_bb_read_bits, 326 { INTEL_BB_SDA, INTEL_BB_SCL, 0, 0 } 327 }; 328 329 void 330 intel_bb_set_bits(void *cookie, uint32_t bits) 331 { 332 set_clock(cookie, bits & INTEL_BB_SCL); 333 set_data(cookie, bits & INTEL_BB_SDA); 334 } 335 336 void 337 intel_bb_set_dir(void *cookie, uint32_t bits) 338 { 339 } 340 341 uint32_t 342 intel_bb_read_bits(void *cookie) 343 { 344 uint32_t bits = 0; 345 346 if (get_clock(cookie)) 347 bits |= INTEL_BB_SCL; 348 if (get_data(cookie)) 349 bits |= INTEL_BB_SDA; 350 351 return bits; 352 } 353 354 int 355 intel_acquire_bus(void *cookie, int flags) 356 { 357 struct intel_gmbus *bus = cookie; 358 359 intel_gpio_pre_xfer(&bus->adapter); 360 return (0); 361 } 362 363 void 364 intel_release_bus(void *cookie, int flags) 365 { 366 struct intel_gmbus *bus = cookie; 367 368 intel_gpio_post_xfer(&bus->adapter); 369 } 370 371 int 372 intel_send_start(void *cookie, int flags) 373 { 374 return (i2c_bitbang_send_start(cookie, flags, &intel_bbops)); 375 } 376 377 int 378 intel_send_stop(void *cookie, int flags) 379 { 380 return (i2c_bitbang_send_stop(cookie, flags, &intel_bbops)); 381 } 382 383 int 384 intel_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 385 { 386 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, &intel_bbops)); 387 } 388 389 int 390 intel_read_byte(void *cookie, u_int8_t *bytep, int flags) 391 { 392 return (i2c_bitbang_read_byte(cookie, bytep, flags, &intel_bbops)); 393 } 394 395 int 396 intel_write_byte(void *cookie, u_int8_t byte, int flags) 397 { 398 return (i2c_bitbang_write_byte(cookie, byte, flags, &intel_bbops)); 399 } 400 401 static void 402 intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin) 403 { 404 struct drm_i915_private *dev_priv = bus->dev_priv; 405 struct i2c_algo_bit_data *algo; 406 407 algo = &bus->bit_algo; 408 409 bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio); 410 bus->adapter.algo_data = algo; 411 #ifdef __linux__ 412 algo->setsda = set_data; 413 algo->setscl = set_clock; 414 algo->getsda = get_data; 415 algo->getscl = get_clock; 416 algo->pre_xfer = intel_gpio_pre_xfer; 417 algo->post_xfer = intel_gpio_post_xfer; 418 algo->udelay = I2C_RISEFALL_TIME; 419 algo->timeout = usecs_to_jiffies(2200); 420 algo->data = bus; 421 #else 422 algo->ic.ic_cookie = bus; 423 algo->ic.ic_acquire_bus = intel_acquire_bus; 424 algo->ic.ic_release_bus = intel_release_bus; 425 algo->ic.ic_send_start = intel_send_start; 426 algo->ic.ic_send_stop = intel_send_stop; 427 algo->ic.ic_initiate_xfer = intel_initiate_xfer; 428 algo->ic.ic_read_byte = intel_read_byte; 429 algo->ic.ic_write_byte = intel_write_byte; 430 #endif 431 } 432 433 static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en) 434 { 435 DEFINE_WAIT(wait); 436 u32 gmbus2; 437 int ret; 438 439 /* Important: The hw handles only the first bit, so set only one! Since 440 * we also need to check for NAKs besides the hw ready/idle signal, we 441 * need to wake up periodically and check that ourselves. 442 */ 443 if (!HAS_GMBUS_IRQ(dev_priv) || cold) 444 irq_en = 0; 445 446 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 447 intel_de_write_fw(dev_priv, GMBUS4, irq_en); 448 449 status |= GMBUS_SATOER; 450 ret = wait_for_us((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status, 451 2); 452 if (ret) 453 ret = wait_for((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status, 454 50); 455 456 intel_de_write_fw(dev_priv, GMBUS4, 0); 457 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 458 459 if (gmbus2 & GMBUS_SATOER) 460 return -ENXIO; 461 462 return ret; 463 } 464 465 static int 466 gmbus_wait_idle(struct drm_i915_private *dev_priv) 467 { 468 DEFINE_WAIT(wait); 469 u32 irq_enable; 470 int ret; 471 472 /* Important: The hw handles only the first bit, so set only one! */ 473 irq_enable = 0; 474 if (HAS_GMBUS_IRQ(dev_priv) && !cold) 475 irq_enable = GMBUS_IDLE_EN; 476 477 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 478 intel_de_write_fw(dev_priv, GMBUS4, irq_enable); 479 480 ret = intel_wait_for_register_fw(&dev_priv->uncore, 481 GMBUS2, GMBUS_ACTIVE, 0, 482 10); 483 484 intel_de_write_fw(dev_priv, GMBUS4, 0); 485 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 486 487 return ret; 488 } 489 490 static unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv) 491 { 492 return INTEL_GEN(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : 493 GMBUS_BYTE_COUNT_MAX; 494 } 495 496 static int 497 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, 498 unsigned short addr, u8 *buf, unsigned int len, 499 u32 gmbus0_reg, u32 gmbus1_index) 500 { 501 unsigned int size = len; 502 bool burst_read = len > gmbus_max_xfer_size(dev_priv); 503 bool extra_byte_added = false; 504 505 if (burst_read) { 506 /* 507 * As per HW Spec, for 512Bytes need to read extra Byte and 508 * Ignore the extra byte read. 509 */ 510 if (len == 512) { 511 extra_byte_added = true; 512 len++; 513 } 514 size = len % 256 + 256; 515 intel_de_write_fw(dev_priv, GMBUS0, 516 gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); 517 } 518 519 intel_de_write_fw(dev_priv, GMBUS1, 520 gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); 521 while (len) { 522 int ret; 523 u32 val, loop = 0; 524 525 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 526 if (ret) 527 return ret; 528 529 val = intel_de_read_fw(dev_priv, GMBUS3); 530 do { 531 if (extra_byte_added && len == 1) 532 break; 533 534 *buf++ = val & 0xff; 535 val >>= 8; 536 } while (--len && ++loop < 4); 537 538 if (burst_read && len == size - 4) 539 /* Reset the override bit */ 540 intel_de_write_fw(dev_priv, GMBUS0, gmbus0_reg); 541 } 542 543 return 0; 544 } 545 546 /* 547 * HW spec says that 512Bytes in Burst read need special treatment. 548 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate 549 * an I2C slave, which supports such a lengthy burst read too for experiments. 550 * 551 * So until things get clarified on HW support, to avoid the burst read length 552 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes. 553 */ 554 #define INTEL_GMBUS_BURST_READ_MAX_LEN 767U 555 556 static int 557 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, 558 u32 gmbus0_reg, u32 gmbus1_index) 559 { 560 u8 *buf = msg->buf; 561 unsigned int rx_size = msg->len; 562 unsigned int len; 563 int ret; 564 565 do { 566 if (HAS_GMBUS_BURST_READ(dev_priv)) 567 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN); 568 else 569 len = min(rx_size, gmbus_max_xfer_size(dev_priv)); 570 571 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len, 572 gmbus0_reg, gmbus1_index); 573 if (ret) 574 return ret; 575 576 rx_size -= len; 577 buf += len; 578 } while (rx_size != 0); 579 580 return 0; 581 } 582 583 static int 584 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, 585 unsigned short addr, u8 *buf, unsigned int len, 586 u32 gmbus1_index) 587 { 588 unsigned int chunk_size = len; 589 u32 val, loop; 590 591 val = loop = 0; 592 while (len && loop < 4) { 593 val |= *buf++ << (8 * loop++); 594 len -= 1; 595 } 596 597 intel_de_write_fw(dev_priv, GMBUS3, val); 598 intel_de_write_fw(dev_priv, GMBUS1, 599 gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 600 while (len) { 601 int ret; 602 603 val = loop = 0; 604 do { 605 val |= *buf++ << (8 * loop); 606 } while (--len && ++loop < 4); 607 608 intel_de_write_fw(dev_priv, GMBUS3, val); 609 610 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 611 if (ret) 612 return ret; 613 } 614 615 return 0; 616 } 617 618 static int 619 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg, 620 u32 gmbus1_index) 621 { 622 u8 *buf = msg->buf; 623 unsigned int tx_size = msg->len; 624 unsigned int len; 625 int ret; 626 627 do { 628 len = min(tx_size, gmbus_max_xfer_size(dev_priv)); 629 630 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len, 631 gmbus1_index); 632 if (ret) 633 return ret; 634 635 buf += len; 636 tx_size -= len; 637 } while (tx_size != 0); 638 639 return 0; 640 } 641 642 /* 643 * The gmbus controller can combine a 1 or 2 byte write with another read/write 644 * that immediately follows it by using an "INDEX" cycle. 645 */ 646 static bool 647 gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num) 648 { 649 return (i + 1 < num && 650 msgs[i].addr == msgs[i + 1].addr && 651 !(msgs[i].flags & I2C_M_RD) && 652 (msgs[i].len == 1 || msgs[i].len == 2) && 653 msgs[i + 1].len > 0); 654 } 655 656 static int 657 gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs, 658 u32 gmbus0_reg) 659 { 660 u32 gmbus1_index = 0; 661 u32 gmbus5 = 0; 662 int ret; 663 664 if (msgs[0].len == 2) 665 gmbus5 = GMBUS_2BYTE_INDEX_EN | 666 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 667 if (msgs[0].len == 1) 668 gmbus1_index = GMBUS_CYCLE_INDEX | 669 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 670 671 /* GMBUS5 holds 16-bit index */ 672 if (gmbus5) 673 intel_de_write_fw(dev_priv, GMBUS5, gmbus5); 674 675 if (msgs[1].flags & I2C_M_RD) 676 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg, 677 gmbus1_index); 678 else 679 ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index); 680 681 /* Clear GMBUS5 after each index transfer */ 682 if (gmbus5) 683 intel_de_write_fw(dev_priv, GMBUS5, 0); 684 685 return ret; 686 } 687 688 static int 689 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, 690 u32 gmbus0_source) 691 { 692 struct intel_gmbus *bus = container_of(adapter, 693 struct intel_gmbus, 694 adapter); 695 struct drm_i915_private *dev_priv = bus->dev_priv; 696 int i = 0, inc, try = 0; 697 int ret = 0; 698 699 /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */ 700 if (IS_GEN9_LP(dev_priv)) 701 bxt_gmbus_clock_gating(dev_priv, false); 702 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv)) 703 pch_gmbus_clock_gating(dev_priv, false); 704 705 retry: 706 intel_de_write_fw(dev_priv, GMBUS0, gmbus0_source | bus->reg0); 707 708 for (; i < num; i += inc) { 709 inc = 1; 710 if (gmbus_is_index_xfer(msgs, i, num)) { 711 ret = gmbus_index_xfer(dev_priv, &msgs[i], 712 gmbus0_source | bus->reg0); 713 inc = 2; /* an index transmission is two msgs */ 714 } else if (msgs[i].flags & I2C_M_RD) { 715 ret = gmbus_xfer_read(dev_priv, &msgs[i], 716 gmbus0_source | bus->reg0, 0); 717 } else { 718 ret = gmbus_xfer_write(dev_priv, &msgs[i], 0); 719 } 720 721 if (!ret) 722 ret = gmbus_wait(dev_priv, 723 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN); 724 if (ret == -ETIMEDOUT) 725 goto timeout; 726 else if (ret) 727 goto clear_err; 728 } 729 730 /* Generate a STOP condition on the bus. Note that gmbus can't generata 731 * a STOP on the very first cycle. To simplify the code we 732 * unconditionally generate the STOP condition with an additional gmbus 733 * cycle. */ 734 intel_de_write_fw(dev_priv, GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 735 736 /* Mark the GMBUS interface as disabled after waiting for idle. 737 * We will re-enable it at the start of the next xfer, 738 * till then let it sleep. 739 */ 740 if (gmbus_wait_idle(dev_priv)) { 741 drm_dbg_kms(&dev_priv->drm, 742 "GMBUS [%s] timed out waiting for idle\n", 743 adapter->name); 744 ret = -ETIMEDOUT; 745 } 746 intel_de_write_fw(dev_priv, GMBUS0, 0); 747 ret = ret ?: i; 748 goto out; 749 750 clear_err: 751 /* 752 * Wait for bus to IDLE before clearing NAK. 753 * If we clear the NAK while bus is still active, then it will stay 754 * active and the next transaction may fail. 755 * 756 * If no ACK is received during the address phase of a transaction, the 757 * adapter must report -ENXIO. It is not clear what to return if no ACK 758 * is received at other times. But we have to be careful to not return 759 * spurious -ENXIO because that will prevent i2c and drm edid functions 760 * from retrying. So return -ENXIO only when gmbus properly quiescents - 761 * timing out seems to happen when there _is_ a ddc chip present, but 762 * it's slow responding and only answers on the 2nd retry. 763 */ 764 ret = -ENXIO; 765 if (gmbus_wait_idle(dev_priv)) { 766 drm_dbg_kms(&dev_priv->drm, 767 "GMBUS [%s] timed out after NAK\n", 768 adapter->name); 769 ret = -ETIMEDOUT; 770 } 771 772 /* Toggle the Software Clear Interrupt bit. This has the effect 773 * of resetting the GMBUS controller and so clearing the 774 * BUS_ERROR raised by the slave's NAK. 775 */ 776 intel_de_write_fw(dev_priv, GMBUS1, GMBUS_SW_CLR_INT); 777 intel_de_write_fw(dev_priv, GMBUS1, 0); 778 intel_de_write_fw(dev_priv, GMBUS0, 0); 779 780 drm_dbg_kms(&dev_priv->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n", 781 adapter->name, msgs[i].addr, 782 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 783 784 /* 785 * Passive adapters sometimes NAK the first probe. Retry the first 786 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm 787 * has retries internally. See also the retry loop in 788 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. 789 */ 790 if (ret == -ENXIO && i == 0 && try++ == 0) { 791 drm_dbg_kms(&dev_priv->drm, 792 "GMBUS [%s] NAK on first message, retry\n", 793 adapter->name); 794 goto retry; 795 } 796 797 goto out; 798 799 timeout: 800 drm_dbg_kms(&dev_priv->drm, 801 "GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 802 bus->adapter.name, bus->reg0 & 0xff); 803 intel_de_write_fw(dev_priv, GMBUS0, 0); 804 805 /* 806 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging 807 * instead. Use EAGAIN to have i2c core retry. 808 */ 809 ret = -EAGAIN; 810 811 out: 812 /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */ 813 if (IS_GEN9_LP(dev_priv)) 814 bxt_gmbus_clock_gating(dev_priv, true); 815 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv)) 816 pch_gmbus_clock_gating(dev_priv, true); 817 818 return ret; 819 } 820 821 static int 822 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) 823 { 824 struct intel_gmbus *bus = 825 container_of(adapter, struct intel_gmbus, adapter); 826 struct drm_i915_private *dev_priv = bus->dev_priv; 827 intel_wakeref_t wakeref; 828 int ret; 829 830 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 831 832 if (bus->force_bit) { 833 ret = i2c_bit_algo.master_xfer(adapter, msgs, num); 834 if (ret < 0) 835 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; 836 } else { 837 ret = do_gmbus_xfer(adapter, msgs, num, 0); 838 if (ret == -EAGAIN) 839 bus->force_bit |= GMBUS_FORCE_BIT_RETRY; 840 } 841 842 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 843 844 return ret; 845 } 846 847 int intel_gmbus_output_aksv(struct i2c_adapter *adapter) 848 { 849 struct intel_gmbus *bus = 850 container_of(adapter, struct intel_gmbus, adapter); 851 struct drm_i915_private *dev_priv = bus->dev_priv; 852 u8 cmd = DRM_HDCP_DDC_AKSV; 853 u8 buf[DRM_HDCP_KSV_LEN] = { 0 }; 854 struct i2c_msg msgs[] = { 855 { 856 .addr = DRM_HDCP_DDC_ADDR, 857 .flags = 0, 858 .len = sizeof(cmd), 859 .buf = &cmd, 860 }, 861 { 862 .addr = DRM_HDCP_DDC_ADDR, 863 .flags = 0, 864 .len = sizeof(buf), 865 .buf = buf, 866 } 867 }; 868 intel_wakeref_t wakeref; 869 int ret; 870 871 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 872 mutex_lock(&dev_priv->gmbus_mutex); 873 874 /* 875 * In order to output Aksv to the receiver, use an indexed write to 876 * pass the i2c command, and tell GMBUS to use the HW-provided value 877 * instead of sourcing GMBUS3 for the data. 878 */ 879 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT); 880 881 mutex_unlock(&dev_priv->gmbus_mutex); 882 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 883 884 return ret; 885 } 886 887 static u32 gmbus_func(struct i2c_adapter *adapter) 888 { 889 return i2c_bit_algo.functionality(adapter) & 890 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 891 /* I2C_FUNC_10BIT_ADDR | */ 892 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 893 I2C_FUNC_SMBUS_BLOCK_PROC_CALL); 894 } 895 896 static const struct i2c_algorithm gmbus_algorithm = { 897 .master_xfer = gmbus_xfer, 898 .functionality = gmbus_func 899 }; 900 901 static void gmbus_lock_bus(struct i2c_adapter *adapter, 902 unsigned int flags) 903 { 904 struct intel_gmbus *bus = to_intel_gmbus(adapter); 905 struct drm_i915_private *dev_priv = bus->dev_priv; 906 907 mutex_lock(&dev_priv->gmbus_mutex); 908 } 909 910 static int gmbus_trylock_bus(struct i2c_adapter *adapter, 911 unsigned int flags) 912 { 913 struct intel_gmbus *bus = to_intel_gmbus(adapter); 914 struct drm_i915_private *dev_priv = bus->dev_priv; 915 916 return mutex_trylock(&dev_priv->gmbus_mutex); 917 } 918 919 static void gmbus_unlock_bus(struct i2c_adapter *adapter, 920 unsigned int flags) 921 { 922 struct intel_gmbus *bus = to_intel_gmbus(adapter); 923 struct drm_i915_private *dev_priv = bus->dev_priv; 924 925 mutex_unlock(&dev_priv->gmbus_mutex); 926 } 927 928 static const struct i2c_lock_operations gmbus_lock_ops = { 929 .lock_bus = gmbus_lock_bus, 930 .trylock_bus = gmbus_trylock_bus, 931 .unlock_bus = gmbus_unlock_bus, 932 }; 933 934 /** 935 * intel_gmbus_setup - instantiate all Intel i2c GMBuses 936 * @dev_priv: i915 device private 937 */ 938 int intel_gmbus_setup(struct drm_i915_private *dev_priv) 939 { 940 #ifdef notyet 941 struct pci_dev *pdev = dev_priv->drm.pdev; 942 #endif 943 struct intel_gmbus *bus; 944 unsigned int pin; 945 int ret; 946 947 if (!HAS_DISPLAY(dev_priv)) 948 return 0; 949 950 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 951 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; 952 else if (!HAS_GMCH(dev_priv)) 953 /* 954 * Broxton uses the same PCH offsets for South Display Engine, 955 * even though it doesn't have a PCH. 956 */ 957 dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE; 958 959 rw_init(&dev_priv->gmbus_mutex, "gmbus"); 960 init_waitqueue_head(&dev_priv->gmbus_wait_queue); 961 962 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { 963 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) 964 continue; 965 966 bus = &dev_priv->gmbus[pin]; 967 968 #ifdef notyet 969 bus->adapter.owner = THIS_MODULE; 970 bus->adapter.class = I2C_CLASS_DDC; 971 #endif 972 snprintf(bus->adapter.name, 973 sizeof(bus->adapter.name), 974 "i915 gmbus %s", 975 get_gmbus_pin(dev_priv, pin)->name); 976 977 #ifdef notyet 978 bus->adapter.dev.parent = &pdev->dev; 979 #endif 980 bus->dev_priv = dev_priv; 981 982 bus->adapter.algo = &gmbus_algorithm; 983 bus->adapter.lock_ops = &gmbus_lock_ops; 984 985 /* 986 * We wish to retry with bit banging 987 * after a timed out GMBUS attempt. 988 */ 989 bus->adapter.retries = 1; 990 991 /* By default use a conservative clock rate */ 992 bus->reg0 = pin | GMBUS_RATE_100KHZ; 993 994 /* gmbus seems to be broken on i830 */ 995 if (IS_I830(dev_priv)) 996 bus->force_bit = 1; 997 998 intel_gpio_setup(bus, pin); 999 1000 ret = i2c_add_adapter(&bus->adapter); 1001 if (ret) 1002 goto err; 1003 } 1004 1005 intel_gmbus_reset(dev_priv); 1006 1007 return 0; 1008 1009 err: 1010 while (pin--) { 1011 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) 1012 continue; 1013 1014 bus = &dev_priv->gmbus[pin]; 1015 i2c_del_adapter(&bus->adapter); 1016 } 1017 return ret; 1018 } 1019 1020 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, 1021 unsigned int pin) 1022 { 1023 if (drm_WARN_ON(&dev_priv->drm, 1024 !intel_gmbus_is_valid_pin(dev_priv, pin))) 1025 return NULL; 1026 1027 return &dev_priv->gmbus[pin].adapter; 1028 } 1029 1030 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed) 1031 { 1032 struct intel_gmbus *bus = to_intel_gmbus(adapter); 1033 1034 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed; 1035 } 1036 1037 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) 1038 { 1039 struct intel_gmbus *bus = to_intel_gmbus(adapter); 1040 struct drm_i915_private *dev_priv = bus->dev_priv; 1041 1042 mutex_lock(&dev_priv->gmbus_mutex); 1043 1044 bus->force_bit += force_bit ? 1 : -1; 1045 drm_dbg_kms(&dev_priv->drm, 1046 "%sabling bit-banging on %s. force bit now %d\n", 1047 force_bit ? "en" : "dis", adapter->name, 1048 bus->force_bit); 1049 1050 mutex_unlock(&dev_priv->gmbus_mutex); 1051 } 1052 1053 bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 1054 { 1055 struct intel_gmbus *bus = to_intel_gmbus(adapter); 1056 1057 return bus->force_bit; 1058 } 1059 1060 void intel_gmbus_teardown(struct drm_i915_private *dev_priv) 1061 { 1062 struct intel_gmbus *bus; 1063 unsigned int pin; 1064 1065 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { 1066 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) 1067 continue; 1068 1069 bus = &dev_priv->gmbus[pin]; 1070 i2c_del_adapter(&bus->adapter); 1071 } 1072 } 1073