1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Shobhit Kumar <shobhit.kumar@intel.com> 24 * 25 */ 26 27 #include <linux/gpio/consumer.h> 28 #ifdef notyet 29 #include <linux/gpio/machine.h> 30 #include <linux/mfd/intel_soc_pmic.h> 31 #include <linux/pinctrl/consumer.h> 32 #include <linux/pinctrl/machine.h> 33 #endif 34 #include <linux/slab.h> 35 #include <linux/string_helpers.h> 36 37 #include <asm/unaligned.h> 38 39 #include <drm/drm_crtc.h> 40 #include <drm/drm_edid.h> 41 42 #include <video/mipi_display.h> 43 44 #include "i915_drv.h" 45 #include "i915_reg.h" 46 #include "intel_de.h" 47 #include "intel_display_types.h" 48 #include "intel_dsi.h" 49 #include "intel_dsi_vbt.h" 50 #include "intel_gmbus_regs.h" 51 #include "intel_pps_regs.h" 52 #include "vlv_dsi.h" 53 #include "vlv_dsi_regs.h" 54 #include "vlv_sideband.h" 55 56 #define MIPI_TRANSFER_MODE_SHIFT 0 57 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1 58 #define MIPI_PORT_SHIFT 3 59 60 /* base offsets for gpio pads */ 61 #define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130 62 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120 63 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110 64 #define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140 65 #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150 66 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160 67 #define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180 68 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190 69 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170 70 #define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100 71 #define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0 72 #define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0 73 74 #define VLV_GPIO_PCONF0(base_offset) (base_offset) 75 #define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8) 76 77 struct gpio_map { 78 u16 base_offset; 79 bool init; 80 }; 81 82 static struct gpio_map vlv_gpio_table[] = { 83 { VLV_GPIO_NC_0_HV_DDI0_HPD }, 84 { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA }, 85 { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL }, 86 { VLV_GPIO_NC_3_PANEL0_VDDEN }, 87 { VLV_GPIO_NC_4_PANEL0_BKLTEN }, 88 { VLV_GPIO_NC_5_PANEL0_BKLTCTL }, 89 { VLV_GPIO_NC_6_HV_DDI1_HPD }, 90 { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA }, 91 { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL }, 92 { VLV_GPIO_NC_9_PANEL1_VDDEN }, 93 { VLV_GPIO_NC_10_PANEL1_BKLTEN }, 94 { VLV_GPIO_NC_11_PANEL1_BKLTCTL }, 95 }; 96 97 struct i2c_adapter_lookup { 98 u16 slave_addr; 99 struct intel_dsi *intel_dsi; 100 #ifdef notyet 101 acpi_handle dev_handle; 102 #endif 103 }; 104 105 #define CHV_GPIO_IDX_START_N 0 106 #define CHV_GPIO_IDX_START_E 73 107 #define CHV_GPIO_IDX_START_SW 100 108 #define CHV_GPIO_IDX_START_SE 198 109 110 #define CHV_VBT_MAX_PINS_PER_FMLY 15 111 112 #define CHV_GPIO_PAD_CFG0(f, i) (0x4400 + (f) * 0x400 + (i) * 8) 113 #define CHV_GPIO_GPIOEN (1 << 15) 114 #define CHV_GPIO_GPIOCFG_GPIO (0 << 8) 115 #define CHV_GPIO_GPIOCFG_GPO (1 << 8) 116 #define CHV_GPIO_GPIOCFG_GPI (2 << 8) 117 #define CHV_GPIO_GPIOCFG_HIZ (3 << 8) 118 #define CHV_GPIO_GPIOTXSTATE(state) ((!!(state)) << 1) 119 120 #define CHV_GPIO_PAD_CFG1(f, i) (0x4400 + (f) * 0x400 + (i) * 8 + 4) 121 #define CHV_GPIO_CFGLOCK (1 << 31) 122 123 /* ICL DSI Display GPIO Pins */ 124 #define ICL_GPIO_DDSP_HPD_A 0 125 #define ICL_GPIO_L_VDDEN_1 1 126 #define ICL_GPIO_L_BKLTEN_1 2 127 #define ICL_GPIO_DDPA_CTRLCLK_1 3 128 #define ICL_GPIO_DDPA_CTRLDATA_1 4 129 #define ICL_GPIO_DDSP_HPD_B 5 130 #define ICL_GPIO_L_VDDEN_2 6 131 #define ICL_GPIO_L_BKLTEN_2 7 132 #define ICL_GPIO_DDPA_CTRLCLK_2 8 133 #define ICL_GPIO_DDPA_CTRLDATA_2 9 134 135 static enum port intel_dsi_seq_port_to_port(struct intel_dsi *intel_dsi, 136 u8 seq_port) 137 { 138 /* 139 * If single link DSI is being used on any port, the VBT sequence block 140 * send packet apparently always has 0 for the port. Just use the port 141 * we have configured, and ignore the sequence block port. 142 */ 143 if (hweight8(intel_dsi->ports) == 1) 144 return ffs(intel_dsi->ports) - 1; 145 146 if (seq_port) { 147 if (intel_dsi->ports & BIT(PORT_B)) 148 return PORT_B; 149 else if (intel_dsi->ports & BIT(PORT_C)) 150 return PORT_C; 151 } 152 153 return PORT_A; 154 } 155 156 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, 157 const u8 *data) 158 { 159 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 160 struct mipi_dsi_device *dsi_device; 161 u8 type, flags, seq_port; 162 u16 len; 163 enum port port; 164 165 drm_dbg_kms(&dev_priv->drm, "\n"); 166 167 flags = *data++; 168 type = *data++; 169 170 len = *((u16 *) data); 171 data += 2; 172 173 seq_port = (flags >> MIPI_PORT_SHIFT) & 3; 174 175 port = intel_dsi_seq_port_to_port(intel_dsi, seq_port); 176 177 if (drm_WARN_ON(&dev_priv->drm, !intel_dsi->dsi_hosts[port])) 178 goto out; 179 180 dsi_device = intel_dsi->dsi_hosts[port]->device; 181 if (!dsi_device) { 182 drm_dbg_kms(&dev_priv->drm, "no dsi device for port %c\n", 183 port_name(port)); 184 goto out; 185 } 186 187 if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1) 188 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM; 189 else 190 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM; 191 192 dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3; 193 194 switch (type) { 195 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: 196 mipi_dsi_generic_write(dsi_device, NULL, 0); 197 break; 198 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: 199 mipi_dsi_generic_write(dsi_device, data, 1); 200 break; 201 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: 202 mipi_dsi_generic_write(dsi_device, data, 2); 203 break; 204 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: 205 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: 206 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: 207 drm_dbg(&dev_priv->drm, 208 "Generic Read not yet implemented or used\n"); 209 break; 210 case MIPI_DSI_GENERIC_LONG_WRITE: 211 mipi_dsi_generic_write(dsi_device, data, len); 212 break; 213 case MIPI_DSI_DCS_SHORT_WRITE: 214 mipi_dsi_dcs_write_buffer(dsi_device, data, 1); 215 break; 216 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 217 mipi_dsi_dcs_write_buffer(dsi_device, data, 2); 218 break; 219 case MIPI_DSI_DCS_READ: 220 drm_dbg(&dev_priv->drm, 221 "DCS Read not yet implemented or used\n"); 222 break; 223 case MIPI_DSI_DCS_LONG_WRITE: 224 mipi_dsi_dcs_write_buffer(dsi_device, data, len); 225 break; 226 } 227 228 if (DISPLAY_VER(dev_priv) < 11) 229 vlv_dsi_wait_for_fifo_empty(intel_dsi, port); 230 231 out: 232 data += len; 233 234 return data; 235 } 236 237 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) 238 { 239 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 240 u32 delay = *((const u32 *) data); 241 242 drm_dbg_kms(&i915->drm, "%d usecs\n", delay); 243 244 usleep_range(delay, delay + 10); 245 data += 4; 246 247 return data; 248 } 249 250 static void vlv_exec_gpio(struct intel_connector *connector, 251 u8 gpio_source, u8 gpio_index, bool value) 252 { 253 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 254 struct gpio_map *map; 255 u16 pconf0, padval; 256 u32 tmp; 257 u8 port; 258 259 if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) { 260 drm_dbg_kms(&dev_priv->drm, "unknown gpio index %u\n", 261 gpio_index); 262 return; 263 } 264 265 map = &vlv_gpio_table[gpio_index]; 266 267 if (connector->panel.vbt.dsi.seq_version >= 3) { 268 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */ 269 port = IOSF_PORT_GPIO_NC; 270 } else { 271 if (gpio_source == 0) { 272 port = IOSF_PORT_GPIO_NC; 273 } else if (gpio_source == 1) { 274 drm_dbg_kms(&dev_priv->drm, "SC gpio not supported\n"); 275 return; 276 } else { 277 drm_dbg_kms(&dev_priv->drm, 278 "unknown gpio source %u\n", gpio_source); 279 return; 280 } 281 } 282 283 pconf0 = VLV_GPIO_PCONF0(map->base_offset); 284 padval = VLV_GPIO_PAD_VAL(map->base_offset); 285 286 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 287 if (!map->init) { 288 /* FIXME: remove constant below */ 289 vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00); 290 map->init = true; 291 } 292 293 tmp = 0x4 | value; 294 vlv_iosf_sb_write(dev_priv, port, padval, tmp); 295 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 296 } 297 298 static void chv_exec_gpio(struct intel_connector *connector, 299 u8 gpio_source, u8 gpio_index, bool value) 300 { 301 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 302 u16 cfg0, cfg1; 303 u16 family_num; 304 u8 port; 305 306 if (connector->panel.vbt.dsi.seq_version >= 3) { 307 if (gpio_index >= CHV_GPIO_IDX_START_SE) { 308 /* XXX: it's unclear whether 255->57 is part of SE. */ 309 gpio_index -= CHV_GPIO_IDX_START_SE; 310 port = CHV_IOSF_PORT_GPIO_SE; 311 } else if (gpio_index >= CHV_GPIO_IDX_START_SW) { 312 gpio_index -= CHV_GPIO_IDX_START_SW; 313 port = CHV_IOSF_PORT_GPIO_SW; 314 } else if (gpio_index >= CHV_GPIO_IDX_START_E) { 315 gpio_index -= CHV_GPIO_IDX_START_E; 316 port = CHV_IOSF_PORT_GPIO_E; 317 } else { 318 port = CHV_IOSF_PORT_GPIO_N; 319 } 320 } else { 321 /* XXX: The spec is unclear about CHV GPIO on seq v2 */ 322 if (gpio_source != 0) { 323 drm_dbg_kms(&dev_priv->drm, 324 "unknown gpio source %u\n", gpio_source); 325 return; 326 } 327 328 if (gpio_index >= CHV_GPIO_IDX_START_E) { 329 drm_dbg_kms(&dev_priv->drm, 330 "invalid gpio index %u for GPIO N\n", 331 gpio_index); 332 return; 333 } 334 335 port = CHV_IOSF_PORT_GPIO_N; 336 } 337 338 family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY; 339 gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY; 340 341 cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index); 342 cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index); 343 344 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 345 vlv_iosf_sb_write(dev_priv, port, cfg1, 0); 346 vlv_iosf_sb_write(dev_priv, port, cfg0, 347 CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO | 348 CHV_GPIO_GPIOTXSTATE(value)); 349 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 350 } 351 352 static void bxt_exec_gpio(struct intel_connector *connector, 353 u8 gpio_source, u8 gpio_index, bool value) 354 { 355 STUB(); 356 #ifdef __linux__ 357 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 358 /* XXX: this table is a quick ugly hack. */ 359 static struct gpio_desc *bxt_gpio_table[U8_MAX + 1]; 360 struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index]; 361 362 if (!gpio_desc) { 363 gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev, 364 NULL, gpio_index, 365 value ? GPIOD_OUT_LOW : 366 GPIOD_OUT_HIGH); 367 368 if (IS_ERR_OR_NULL(gpio_desc)) { 369 drm_err(&dev_priv->drm, 370 "GPIO index %u request failed (%ld)\n", 371 gpio_index, PTR_ERR(gpio_desc)); 372 return; 373 } 374 375 bxt_gpio_table[gpio_index] = gpio_desc; 376 } 377 378 gpiod_set_value(gpio_desc, value); 379 #endif 380 } 381 382 static void icl_exec_gpio(struct intel_connector *connector, 383 u8 gpio_source, u8 gpio_index, bool value) 384 { 385 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 386 387 drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n"); 388 } 389 390 enum { 391 MIPI_RESET_1 = 0, 392 MIPI_AVDD_EN_1, 393 MIPI_BKLT_EN_1, 394 MIPI_AVEE_EN_1, 395 MIPI_VIO_EN_1, 396 MIPI_RESET_2, 397 MIPI_AVDD_EN_2, 398 MIPI_BKLT_EN_2, 399 MIPI_AVEE_EN_2, 400 MIPI_VIO_EN_2, 401 }; 402 403 static void icl_native_gpio_set_value(struct drm_i915_private *dev_priv, 404 int gpio, bool value) 405 { 406 int index; 407 408 if (drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 11 && gpio >= MIPI_RESET_2)) 409 return; 410 411 switch (gpio) { 412 case MIPI_RESET_1: 413 case MIPI_RESET_2: 414 index = gpio == MIPI_RESET_1 ? HPD_PORT_A : HPD_PORT_B; 415 416 /* 417 * Disable HPD to set the pin to output, and set output 418 * value. The HPD pin should not be enabled for DSI anyway, 419 * assuming the board design and VBT are sane, and the pin isn't 420 * used by a non-DSI encoder. 421 * 422 * The locking protects against concurrent SHOTPLUG_CTL_DDI 423 * modifications in irq setup and handling. 424 */ 425 spin_lock_irq(&dev_priv->irq_lock); 426 intel_de_rmw(dev_priv, SHOTPLUG_CTL_DDI, 427 SHOTPLUG_CTL_DDI_HPD_ENABLE(index) | 428 SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(index), 429 value ? SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(index) : 0); 430 spin_unlock_irq(&dev_priv->irq_lock); 431 break; 432 case MIPI_AVDD_EN_1: 433 case MIPI_AVDD_EN_2: 434 index = gpio == MIPI_AVDD_EN_1 ? 0 : 1; 435 436 intel_de_rmw(dev_priv, PP_CONTROL(index), PANEL_POWER_ON, 437 value ? PANEL_POWER_ON : 0); 438 break; 439 case MIPI_BKLT_EN_1: 440 case MIPI_BKLT_EN_2: 441 index = gpio == MIPI_BKLT_EN_1 ? 0 : 1; 442 443 intel_de_rmw(dev_priv, PP_CONTROL(index), EDP_BLC_ENABLE, 444 value ? EDP_BLC_ENABLE : 0); 445 break; 446 case MIPI_AVEE_EN_1: 447 case MIPI_AVEE_EN_2: 448 index = gpio == MIPI_AVEE_EN_1 ? 1 : 2; 449 450 intel_de_rmw(dev_priv, GPIO(dev_priv, index), 451 GPIO_CLOCK_VAL_OUT, 452 GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT | 453 GPIO_CLOCK_VAL_MASK | (value ? GPIO_CLOCK_VAL_OUT : 0)); 454 break; 455 case MIPI_VIO_EN_1: 456 case MIPI_VIO_EN_2: 457 index = gpio == MIPI_VIO_EN_1 ? 1 : 2; 458 459 intel_de_rmw(dev_priv, GPIO(dev_priv, index), 460 GPIO_DATA_VAL_OUT, 461 GPIO_DATA_DIR_MASK | GPIO_DATA_DIR_OUT | 462 GPIO_DATA_VAL_MASK | (value ? GPIO_DATA_VAL_OUT : 0)); 463 break; 464 default: 465 MISSING_CASE(gpio); 466 } 467 } 468 469 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) 470 { 471 struct drm_device *dev = intel_dsi->base.base.dev; 472 struct drm_i915_private *dev_priv = to_i915(dev); 473 struct intel_connector *connector = intel_dsi->attached_connector; 474 u8 gpio_source, gpio_index = 0, gpio_number; 475 bool value; 476 bool native = DISPLAY_VER(dev_priv) >= 11; 477 478 if (connector->panel.vbt.dsi.seq_version >= 3) 479 gpio_index = *data++; 480 481 gpio_number = *data++; 482 483 /* gpio source in sequence v2 only */ 484 if (connector->panel.vbt.dsi.seq_version == 2) 485 gpio_source = (*data >> 1) & 3; 486 else 487 gpio_source = 0; 488 489 if (connector->panel.vbt.dsi.seq_version >= 4 && *data & BIT(1)) 490 native = false; 491 492 /* pull up/down */ 493 value = *data++ & 1; 494 495 drm_dbg_kms(&dev_priv->drm, "GPIO index %u, number %u, source %u, native %s, set to %s\n", 496 gpio_index, gpio_number, gpio_source, str_yes_no(native), str_on_off(value)); 497 498 if (native) 499 icl_native_gpio_set_value(dev_priv, gpio_number, value); 500 else if (DISPLAY_VER(dev_priv) >= 11) 501 icl_exec_gpio(connector, gpio_source, gpio_index, value); 502 else if (IS_VALLEYVIEW(dev_priv)) 503 vlv_exec_gpio(connector, gpio_source, gpio_number, value); 504 else if (IS_CHERRYVIEW(dev_priv)) 505 chv_exec_gpio(connector, gpio_source, gpio_number, value); 506 else 507 bxt_exec_gpio(connector, gpio_source, gpio_index, value); 508 509 return data; 510 } 511 512 #if defined(CONFIG_ACPI) && defined(__linux__) 513 static int i2c_adapter_lookup(struct acpi_resource *ares, void *data) 514 { 515 struct i2c_adapter_lookup *lookup = data; 516 struct intel_dsi *intel_dsi = lookup->intel_dsi; 517 struct acpi_resource_i2c_serialbus *sb; 518 struct i2c_adapter *adapter; 519 acpi_handle adapter_handle; 520 acpi_status status; 521 522 if (!i2c_acpi_get_i2c_resource(ares, &sb)) 523 return 1; 524 525 if (lookup->slave_addr != sb->slave_address) 526 return 1; 527 528 status = acpi_get_handle(lookup->dev_handle, 529 sb->resource_source.string_ptr, 530 &adapter_handle); 531 if (ACPI_FAILURE(status)) 532 return 1; 533 534 adapter = i2c_acpi_find_adapter_by_handle(adapter_handle); 535 if (adapter) 536 intel_dsi->i2c_bus_num = adapter->nr; 537 538 return 1; 539 } 540 541 static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, 542 const u16 slave_addr) 543 { 544 struct drm_device *drm_dev = intel_dsi->base.base.dev; 545 struct acpi_device *adev = ACPI_COMPANION(drm_dev->dev); 546 struct i2c_adapter_lookup lookup = { 547 .slave_addr = slave_addr, 548 .intel_dsi = intel_dsi, 549 .dev_handle = acpi_device_handle(adev), 550 }; 551 LIST_HEAD(resource_list); 552 553 acpi_dev_get_resources(adev, &resource_list, i2c_adapter_lookup, &lookup); 554 acpi_dev_free_resource_list(&resource_list); 555 } 556 #else 557 static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, 558 const u16 slave_addr) 559 { 560 } 561 #endif 562 563 static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data) 564 { 565 STUB(); 566 return NULL; 567 #ifdef notyet 568 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 569 struct i2c_adapter *adapter; 570 struct i2c_msg msg; 571 int ret; 572 u8 vbt_i2c_bus_num = *(data + 2); 573 u16 slave_addr = *(u16 *)(data + 3); 574 u8 reg_offset = *(data + 5); 575 u8 payload_size = *(data + 6); 576 u8 *payload_data; 577 578 if (intel_dsi->i2c_bus_num < 0) { 579 intel_dsi->i2c_bus_num = vbt_i2c_bus_num; 580 i2c_acpi_find_adapter(intel_dsi, slave_addr); 581 } 582 583 adapter = i2c_get_adapter(intel_dsi->i2c_bus_num); 584 if (!adapter) { 585 drm_err(&i915->drm, "Cannot find a valid i2c bus for xfer\n"); 586 goto err_bus; 587 } 588 589 payload_data = kzalloc(payload_size + 1, GFP_KERNEL); 590 if (!payload_data) 591 goto err_alloc; 592 593 payload_data[0] = reg_offset; 594 memcpy(&payload_data[1], (data + 7), payload_size); 595 596 msg.addr = slave_addr; 597 msg.flags = 0; 598 msg.len = payload_size + 1; 599 msg.buf = payload_data; 600 601 ret = i2c_transfer(adapter, &msg, 1); 602 if (ret < 0) 603 drm_err(&i915->drm, 604 "Failed to xfer payload of size (%u) to reg (%u)\n", 605 payload_size, reg_offset); 606 607 kfree(payload_data); 608 err_alloc: 609 i2c_put_adapter(adapter); 610 err_bus: 611 return data + payload_size + 7; 612 #endif 613 } 614 615 static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data) 616 { 617 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 618 619 drm_dbg_kms(&i915->drm, "Skipping SPI element execution\n"); 620 621 return data + *(data + 5) + 6; 622 } 623 624 static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data) 625 { 626 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 627 #ifdef CONFIG_PMIC_OPREGION 628 u32 value, mask, reg_address; 629 u16 i2c_address; 630 int ret; 631 632 /* byte 0 aka PMIC Flag is reserved */ 633 i2c_address = get_unaligned_le16(data + 1); 634 reg_address = get_unaligned_le32(data + 3); 635 value = get_unaligned_le32(data + 7); 636 mask = get_unaligned_le32(data + 11); 637 638 ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address, 639 reg_address, 640 value, mask); 641 if (ret) 642 drm_err(&i915->drm, "%s failed, error: %d\n", __func__, ret); 643 #else 644 drm_err(&i915->drm, 645 "Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n"); 646 #endif 647 648 return data + 15; 649 } 650 651 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi, 652 const u8 *data); 653 static const fn_mipi_elem_exec exec_elem[] = { 654 [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet, 655 [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay, 656 [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio, 657 [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c, 658 [MIPI_SEQ_ELEM_SPI] = mipi_exec_spi, 659 [MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic, 660 }; 661 662 /* 663 * MIPI Sequence from VBT #53 parsing logic 664 * We have already separated each seqence during bios parsing 665 * Following is generic execution function for any sequence 666 */ 667 668 static const char * const seq_name[] = { 669 [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET", 670 [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP", 671 [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON", 672 [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF", 673 [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET", 674 [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON", 675 [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF", 676 [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON", 677 [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF", 678 [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON", 679 [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF", 680 }; 681 682 static const char *sequence_name(enum mipi_seq seq_id) 683 { 684 if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id]) 685 return seq_name[seq_id]; 686 else 687 return "(unknown)"; 688 } 689 690 static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi, 691 enum mipi_seq seq_id) 692 { 693 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 694 struct intel_connector *connector = intel_dsi->attached_connector; 695 const u8 *data; 696 fn_mipi_elem_exec mipi_elem_exec; 697 698 if (drm_WARN_ON(&dev_priv->drm, 699 seq_id >= ARRAY_SIZE(connector->panel.vbt.dsi.sequence))) 700 return; 701 702 data = connector->panel.vbt.dsi.sequence[seq_id]; 703 if (!data) 704 return; 705 706 drm_WARN_ON(&dev_priv->drm, *data != seq_id); 707 708 drm_dbg_kms(&dev_priv->drm, "Starting MIPI sequence %d - %s\n", 709 seq_id, sequence_name(seq_id)); 710 711 /* Skip Sequence Byte. */ 712 data++; 713 714 /* Skip Size of Sequence. */ 715 if (connector->panel.vbt.dsi.seq_version >= 3) 716 data += 4; 717 718 while (1) { 719 u8 operation_byte = *data++; 720 u8 operation_size = 0; 721 722 if (operation_byte == MIPI_SEQ_ELEM_END) 723 break; 724 725 if (operation_byte < ARRAY_SIZE(exec_elem)) 726 mipi_elem_exec = exec_elem[operation_byte]; 727 else 728 mipi_elem_exec = NULL; 729 730 /* Size of Operation. */ 731 if (connector->panel.vbt.dsi.seq_version >= 3) 732 operation_size = *data++; 733 734 if (mipi_elem_exec) { 735 const u8 *next = data + operation_size; 736 737 data = mipi_elem_exec(intel_dsi, data); 738 739 /* Consistency check if we have size. */ 740 if (operation_size && data != next) { 741 drm_err(&dev_priv->drm, 742 "Inconsistent operation size\n"); 743 return; 744 } 745 } else if (operation_size) { 746 /* We have size, skip. */ 747 drm_dbg_kms(&dev_priv->drm, 748 "Unsupported MIPI operation byte %u\n", 749 operation_byte); 750 data += operation_size; 751 } else { 752 /* No size, can't skip without parsing. */ 753 drm_err(&dev_priv->drm, 754 "Unsupported MIPI operation byte %u\n", 755 operation_byte); 756 return; 757 } 758 } 759 } 760 761 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi, 762 enum mipi_seq seq_id) 763 { 764 STUB(); 765 #ifdef notyet 766 if (seq_id == MIPI_SEQ_POWER_ON && intel_dsi->gpio_panel) 767 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); 768 if (seq_id == MIPI_SEQ_BACKLIGHT_ON && intel_dsi->gpio_backlight) 769 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 1); 770 771 intel_dsi_vbt_exec(intel_dsi, seq_id); 772 773 if (seq_id == MIPI_SEQ_POWER_OFF && intel_dsi->gpio_panel) 774 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); 775 if (seq_id == MIPI_SEQ_BACKLIGHT_OFF && intel_dsi->gpio_backlight) 776 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 0); 777 #endif 778 } 779 780 void intel_dsi_log_params(struct intel_dsi *intel_dsi) 781 { 782 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 783 784 drm_dbg_kms(&i915->drm, "Pclk %d\n", intel_dsi->pclk); 785 drm_dbg_kms(&i915->drm, "Pixel overlap %d\n", 786 intel_dsi->pixel_overlap); 787 drm_dbg_kms(&i915->drm, "Lane count %d\n", intel_dsi->lane_count); 788 drm_dbg_kms(&i915->drm, "DPHY param reg 0x%x\n", intel_dsi->dphy_reg); 789 drm_dbg_kms(&i915->drm, "Video mode format %s\n", 790 intel_dsi->video_mode == NON_BURST_SYNC_PULSE ? 791 "non-burst with sync pulse" : 792 intel_dsi->video_mode == NON_BURST_SYNC_EVENTS ? 793 "non-burst with sync events" : 794 intel_dsi->video_mode == BURST_MODE ? 795 "burst" : "<unknown>"); 796 drm_dbg_kms(&i915->drm, "Burst mode ratio %d\n", 797 intel_dsi->burst_mode_ratio); 798 drm_dbg_kms(&i915->drm, "Reset timer %d\n", intel_dsi->rst_timer_val); 799 drm_dbg_kms(&i915->drm, "Eot %s\n", 800 str_enabled_disabled(intel_dsi->eotp_pkt)); 801 drm_dbg_kms(&i915->drm, "Clockstop %s\n", 802 str_enabled_disabled(!intel_dsi->clock_stop)); 803 drm_dbg_kms(&i915->drm, "Mode %s\n", 804 intel_dsi->operation_mode ? "command" : "video"); 805 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 806 drm_dbg_kms(&i915->drm, 807 "Dual link: DSI_DUAL_LINK_FRONT_BACK\n"); 808 else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT) 809 drm_dbg_kms(&i915->drm, 810 "Dual link: DSI_DUAL_LINK_PIXEL_ALT\n"); 811 else 812 drm_dbg_kms(&i915->drm, "Dual link: NONE\n"); 813 drm_dbg_kms(&i915->drm, "Pixel Format %d\n", intel_dsi->pixel_format); 814 drm_dbg_kms(&i915->drm, "TLPX %d\n", intel_dsi->escape_clk_div); 815 drm_dbg_kms(&i915->drm, "LP RX Timeout 0x%x\n", 816 intel_dsi->lp_rx_timeout); 817 drm_dbg_kms(&i915->drm, "Turnaround Timeout 0x%x\n", 818 intel_dsi->turn_arnd_val); 819 drm_dbg_kms(&i915->drm, "Init Count 0x%x\n", intel_dsi->init_count); 820 drm_dbg_kms(&i915->drm, "HS to LP Count 0x%x\n", 821 intel_dsi->hs_to_lp_count); 822 drm_dbg_kms(&i915->drm, "LP Byte Clock %d\n", intel_dsi->lp_byte_clk); 823 drm_dbg_kms(&i915->drm, "DBI BW Timer 0x%x\n", intel_dsi->bw_timer); 824 drm_dbg_kms(&i915->drm, "LP to HS Clock Count 0x%x\n", 825 intel_dsi->clk_lp_to_hs_count); 826 drm_dbg_kms(&i915->drm, "HS to LP Clock Count 0x%x\n", 827 intel_dsi->clk_hs_to_lp_count); 828 drm_dbg_kms(&i915->drm, "BTA %s\n", 829 str_enabled_disabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA))); 830 } 831 832 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) 833 { 834 struct drm_device *dev = intel_dsi->base.base.dev; 835 struct drm_i915_private *dev_priv = to_i915(dev); 836 struct intel_connector *connector = intel_dsi->attached_connector; 837 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 838 struct mipi_pps_data *pps = connector->panel.vbt.dsi.pps; 839 struct drm_display_mode *mode = connector->panel.vbt.lfp_lvds_vbt_mode; 840 u16 burst_mode_ratio; 841 enum port port; 842 843 drm_dbg_kms(&dev_priv->drm, "\n"); 844 845 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1; 846 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0; 847 intel_dsi->lane_count = mipi_config->lane_cnt + 1; 848 intel_dsi->pixel_format = 849 pixel_format_from_register_bits( 850 mipi_config->videomode_color_format << 7); 851 852 intel_dsi->dual_link = mipi_config->dual_link; 853 intel_dsi->pixel_overlap = mipi_config->pixel_overlap; 854 intel_dsi->operation_mode = mipi_config->is_cmd_mode; 855 intel_dsi->video_mode = mipi_config->video_transfer_mode; 856 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel; 857 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout; 858 intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout; 859 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout; 860 intel_dsi->rst_timer_val = mipi_config->device_reset_timer; 861 intel_dsi->init_count = mipi_config->master_init_timer; 862 intel_dsi->bw_timer = mipi_config->dbi_bw_timer; 863 intel_dsi->video_frmt_cfg_bits = 864 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0; 865 intel_dsi->bgr_enabled = mipi_config->rgb_flip; 866 867 /* Starting point, adjusted depending on dual link and burst mode */ 868 intel_dsi->pclk = mode->clock; 869 870 /* In dual link mode each port needs half of pixel clock */ 871 if (intel_dsi->dual_link) { 872 intel_dsi->pclk /= 2; 873 874 /* we can enable pixel_overlap if needed by panel. In this 875 * case we need to increase the pixelclock for extra pixels 876 */ 877 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 878 intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000); 879 } 880 } 881 882 /* Burst Mode Ratio 883 * Target ddr frequency from VBT / non burst ddr freq 884 * multiply by 100 to preserve remainder 885 */ 886 if (intel_dsi->video_mode == BURST_MODE) { 887 if (mipi_config->target_burst_mode_freq) { 888 u32 bitrate = intel_dsi_bitrate(intel_dsi); 889 890 /* 891 * Sometimes the VBT contains a slightly lower clock, 892 * then the bitrate we have calculated, in this case 893 * just replace it with the calculated bitrate. 894 */ 895 if (mipi_config->target_burst_mode_freq < bitrate && 896 intel_fuzzy_clock_check( 897 mipi_config->target_burst_mode_freq, 898 bitrate)) 899 mipi_config->target_burst_mode_freq = bitrate; 900 901 if (mipi_config->target_burst_mode_freq < bitrate) { 902 drm_err(&dev_priv->drm, 903 "Burst mode freq is less than computed\n"); 904 return false; 905 } 906 907 burst_mode_ratio = DIV_ROUND_UP( 908 mipi_config->target_burst_mode_freq * 100, 909 bitrate); 910 911 intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100); 912 } else { 913 drm_err(&dev_priv->drm, 914 "Burst mode target is not set\n"); 915 return false; 916 } 917 } else 918 burst_mode_ratio = 100; 919 920 intel_dsi->burst_mode_ratio = burst_mode_ratio; 921 922 /* delays in VBT are in unit of 100us, so need to convert 923 * here in ms 924 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */ 925 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10; 926 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10; 927 intel_dsi->panel_on_delay = pps->panel_on_delay / 10; 928 intel_dsi->panel_off_delay = pps->panel_off_delay / 10; 929 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10; 930 931 intel_dsi->i2c_bus_num = -1; 932 933 /* a regular driver would get the device in probe */ 934 for_each_dsi_port(port, intel_dsi->ports) { 935 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device); 936 } 937 938 return true; 939 } 940 941 #ifdef notyet 942 943 /* 944 * On some BYT/CHT devs some sequences are incomplete and we need to manually 945 * control some GPIOs. We need to add a GPIO lookup table before we get these. 946 * If the GOP did not initialize the panel (HDMI inserted) we may need to also 947 * change the pinmux for the SoC's PWM0 pin from GPIO to PWM. 948 */ 949 static struct gpiod_lookup_table pmic_panel_gpio_table = { 950 /* Intel GFX is consumer */ 951 .dev_id = "0000:00:02.0", 952 .table = { 953 /* Panel EN/DISABLE */ 954 GPIO_LOOKUP("gpio_crystalcove", 94, "panel", GPIO_ACTIVE_HIGH), 955 { } 956 }, 957 }; 958 959 static struct gpiod_lookup_table soc_panel_gpio_table = { 960 .dev_id = "0000:00:02.0", 961 .table = { 962 GPIO_LOOKUP("INT33FC:01", 10, "backlight", GPIO_ACTIVE_HIGH), 963 GPIO_LOOKUP("INT33FC:01", 11, "panel", GPIO_ACTIVE_HIGH), 964 { } 965 }, 966 }; 967 968 static const struct pinctrl_map soc_pwm_pinctrl_map[] = { 969 PIN_MAP_MUX_GROUP("0000:00:02.0", "soc_pwm0", "INT33FC:00", 970 "pwm0_grp", "pwm"), 971 }; 972 973 #endif /* notyet */ 974 975 void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on) 976 { 977 STUB(); 978 #ifdef notyet 979 struct drm_device *dev = intel_dsi->base.base.dev; 980 struct drm_i915_private *dev_priv = to_i915(dev); 981 struct intel_connector *connector = intel_dsi->attached_connector; 982 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 983 enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW; 984 bool want_backlight_gpio = false; 985 bool want_panel_gpio = false; 986 struct pinctrl *pinctrl; 987 int ret; 988 989 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 990 mipi_config->pwm_blc == PPS_BLC_PMIC) { 991 gpiod_add_lookup_table(&pmic_panel_gpio_table); 992 want_panel_gpio = true; 993 } 994 995 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { 996 gpiod_add_lookup_table(&soc_panel_gpio_table); 997 want_panel_gpio = true; 998 want_backlight_gpio = true; 999 1000 /* Ensure PWM0 pin is muxed as PWM instead of GPIO */ 1001 ret = pinctrl_register_mappings(soc_pwm_pinctrl_map, 1002 ARRAY_SIZE(soc_pwm_pinctrl_map)); 1003 if (ret) 1004 drm_err(&dev_priv->drm, 1005 "Failed to register pwm0 pinmux mapping\n"); 1006 1007 pinctrl = devm_pinctrl_get_select(dev->dev, "soc_pwm0"); 1008 if (IS_ERR(pinctrl)) 1009 drm_err(&dev_priv->drm, 1010 "Failed to set pinmux to PWM\n"); 1011 } 1012 1013 if (want_panel_gpio) { 1014 intel_dsi->gpio_panel = gpiod_get(dev->dev, "panel", flags); 1015 if (IS_ERR(intel_dsi->gpio_panel)) { 1016 drm_err(&dev_priv->drm, 1017 "Failed to own gpio for panel control\n"); 1018 intel_dsi->gpio_panel = NULL; 1019 } 1020 } 1021 1022 if (want_backlight_gpio) { 1023 intel_dsi->gpio_backlight = 1024 gpiod_get(dev->dev, "backlight", flags); 1025 if (IS_ERR(intel_dsi->gpio_backlight)) { 1026 drm_err(&dev_priv->drm, 1027 "Failed to own gpio for backlight control\n"); 1028 intel_dsi->gpio_backlight = NULL; 1029 } 1030 } 1031 #endif 1032 } 1033 1034 void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi) 1035 { 1036 STUB(); 1037 #ifdef notyet 1038 struct drm_device *dev = intel_dsi->base.base.dev; 1039 struct drm_i915_private *dev_priv = to_i915(dev); 1040 struct intel_connector *connector = intel_dsi->attached_connector; 1041 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 1042 1043 if (intel_dsi->gpio_panel) { 1044 gpiod_put(intel_dsi->gpio_panel); 1045 intel_dsi->gpio_panel = NULL; 1046 } 1047 1048 if (intel_dsi->gpio_backlight) { 1049 gpiod_put(intel_dsi->gpio_backlight); 1050 intel_dsi->gpio_backlight = NULL; 1051 } 1052 1053 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 1054 mipi_config->pwm_blc == PPS_BLC_PMIC) 1055 gpiod_remove_lookup_table(&pmic_panel_gpio_table); 1056 1057 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { 1058 pinctrl_unregister_mappings(soc_pwm_pinctrl_map); 1059 gpiod_remove_lookup_table(&soc_panel_gpio_table); 1060 } 1061 #endif 1062 } 1063