xref: /openbsd-src/sys/dev/pci/drm/i915/display/intel_display_limits.h (revision f005ef32267c16bdb134f0e9fa4477dbe07c263a)
1*f005ef32Sjsg /* SPDX-License-Identifier: MIT */
2*f005ef32Sjsg /*
3*f005ef32Sjsg  * Copyright © 2022 Intel Corporation
4*f005ef32Sjsg  */
5*f005ef32Sjsg 
6*f005ef32Sjsg #ifndef __INTEL_DISPLAY_LIMITS_H__
7*f005ef32Sjsg #define __INTEL_DISPLAY_LIMITS_H__
8*f005ef32Sjsg 
9*f005ef32Sjsg /*
10*f005ef32Sjsg  * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
11*f005ef32Sjsg  * rest have consecutive values and match the enum values of transcoders
12*f005ef32Sjsg  * with a 1:1 transcoder -> pipe mapping.
13*f005ef32Sjsg  */
14*f005ef32Sjsg enum pipe {
15*f005ef32Sjsg 	INVALID_PIPE = -1,
16*f005ef32Sjsg 
17*f005ef32Sjsg 	PIPE_A = 0,
18*f005ef32Sjsg 	PIPE_B,
19*f005ef32Sjsg 	PIPE_C,
20*f005ef32Sjsg 	PIPE_D,
21*f005ef32Sjsg 	_PIPE_EDP,
22*f005ef32Sjsg 
23*f005ef32Sjsg 	I915_MAX_PIPES = _PIPE_EDP
24*f005ef32Sjsg };
25*f005ef32Sjsg 
26*f005ef32Sjsg enum transcoder {
27*f005ef32Sjsg 	INVALID_TRANSCODER = -1,
28*f005ef32Sjsg 	/*
29*f005ef32Sjsg 	 * The following transcoders have a 1:1 transcoder -> pipe mapping,
30*f005ef32Sjsg 	 * keep their values fixed: the code assumes that TRANSCODER_A=0, the
31*f005ef32Sjsg 	 * rest have consecutive values and match the enum values of the pipes
32*f005ef32Sjsg 	 * they map to.
33*f005ef32Sjsg 	 */
34*f005ef32Sjsg 	TRANSCODER_A = PIPE_A,
35*f005ef32Sjsg 	TRANSCODER_B = PIPE_B,
36*f005ef32Sjsg 	TRANSCODER_C = PIPE_C,
37*f005ef32Sjsg 	TRANSCODER_D = PIPE_D,
38*f005ef32Sjsg 
39*f005ef32Sjsg 	/*
40*f005ef32Sjsg 	 * The following transcoders can map to any pipe, their enum value
41*f005ef32Sjsg 	 * doesn't need to stay fixed.
42*f005ef32Sjsg 	 */
43*f005ef32Sjsg 	TRANSCODER_EDP,
44*f005ef32Sjsg 	TRANSCODER_DSI_0,
45*f005ef32Sjsg 	TRANSCODER_DSI_1,
46*f005ef32Sjsg 	TRANSCODER_DSI_A = TRANSCODER_DSI_0,	/* legacy DSI */
47*f005ef32Sjsg 	TRANSCODER_DSI_C = TRANSCODER_DSI_1,	/* legacy DSI */
48*f005ef32Sjsg 
49*f005ef32Sjsg 	I915_MAX_TRANSCODERS
50*f005ef32Sjsg };
51*f005ef32Sjsg 
52*f005ef32Sjsg /*
53*f005ef32Sjsg  * Per-pipe plane identifier.
54*f005ef32Sjsg  * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
55*f005ef32Sjsg  * number of planes per CRTC.  Not all platforms really have this many planes,
56*f005ef32Sjsg  * which means some arrays of size I915_MAX_PLANES may have unused entries
57*f005ef32Sjsg  * between the topmost sprite plane and the cursor plane.
58*f005ef32Sjsg  *
59*f005ef32Sjsg  * This is expected to be passed to various register macros
60*f005ef32Sjsg  * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
61*f005ef32Sjsg  */
62*f005ef32Sjsg enum plane_id {
63*f005ef32Sjsg 	PLANE_PRIMARY,
64*f005ef32Sjsg 	PLANE_SPRITE0,
65*f005ef32Sjsg 	PLANE_SPRITE1,
66*f005ef32Sjsg 	PLANE_SPRITE2,
67*f005ef32Sjsg 	PLANE_SPRITE3,
68*f005ef32Sjsg 	PLANE_SPRITE4,
69*f005ef32Sjsg 	PLANE_SPRITE5,
70*f005ef32Sjsg 	PLANE_CURSOR,
71*f005ef32Sjsg 
72*f005ef32Sjsg 	I915_MAX_PLANES,
73*f005ef32Sjsg };
74*f005ef32Sjsg 
75*f005ef32Sjsg enum port {
76*f005ef32Sjsg 	PORT_NONE = -1,
77*f005ef32Sjsg 
78*f005ef32Sjsg 	PORT_A = 0,
79*f005ef32Sjsg 	PORT_B,
80*f005ef32Sjsg 	PORT_C,
81*f005ef32Sjsg 	PORT_D,
82*f005ef32Sjsg 	PORT_E,
83*f005ef32Sjsg 	PORT_F,
84*f005ef32Sjsg 	PORT_G,
85*f005ef32Sjsg 	PORT_H,
86*f005ef32Sjsg 	PORT_I,
87*f005ef32Sjsg 
88*f005ef32Sjsg 	/* tgl+ */
89*f005ef32Sjsg 	PORT_TC1 = PORT_D,
90*f005ef32Sjsg 	PORT_TC2,
91*f005ef32Sjsg 	PORT_TC3,
92*f005ef32Sjsg 	PORT_TC4,
93*f005ef32Sjsg 	PORT_TC5,
94*f005ef32Sjsg 	PORT_TC6,
95*f005ef32Sjsg 
96*f005ef32Sjsg 	/* XE_LPD repositions D/E offsets and bitfields */
97*f005ef32Sjsg 	PORT_D_XELPD = PORT_TC5,
98*f005ef32Sjsg 	PORT_E_XELPD,
99*f005ef32Sjsg 
100*f005ef32Sjsg 	I915_MAX_PORTS
101*f005ef32Sjsg };
102*f005ef32Sjsg 
103*f005ef32Sjsg enum hpd_pin {
104*f005ef32Sjsg 	HPD_NONE = 0,
105*f005ef32Sjsg 	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
106*f005ef32Sjsg 	HPD_CRT,
107*f005ef32Sjsg 	HPD_SDVO_B,
108*f005ef32Sjsg 	HPD_SDVO_C,
109*f005ef32Sjsg 	HPD_PORT_A,
110*f005ef32Sjsg 	HPD_PORT_B,
111*f005ef32Sjsg 	HPD_PORT_C,
112*f005ef32Sjsg 	HPD_PORT_D,
113*f005ef32Sjsg 	HPD_PORT_E,
114*f005ef32Sjsg 	HPD_PORT_TC1,
115*f005ef32Sjsg 	HPD_PORT_TC2,
116*f005ef32Sjsg 	HPD_PORT_TC3,
117*f005ef32Sjsg 	HPD_PORT_TC4,
118*f005ef32Sjsg 	HPD_PORT_TC5,
119*f005ef32Sjsg 	HPD_PORT_TC6,
120*f005ef32Sjsg 
121*f005ef32Sjsg 	HPD_NUM_PINS
122*f005ef32Sjsg };
123*f005ef32Sjsg 
124*f005ef32Sjsg #endif /* __INTEL_DISPLAY_LIMITS_H__ */
125