1 /* 2 * Copyright © 2006-2019 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DISPLAY_H_ 26 #define _INTEL_DISPLAY_H_ 27 28 #include <drm/drm_util.h> 29 30 #define drm_i915_private inteldrm_softc 31 32 #include "i915_reg_defs.h" 33 34 enum drm_scaling_filter; 35 struct dpll; 36 struct drm_connector; 37 struct drm_device; 38 struct drm_display_mode; 39 struct drm_encoder; 40 struct drm_file; 41 struct drm_format_info; 42 struct drm_framebuffer; 43 struct drm_i915_gem_object; 44 struct drm_i915_private; 45 struct drm_mode_fb_cmd2; 46 struct drm_modeset_acquire_ctx; 47 struct drm_plane; 48 struct drm_plane_state; 49 struct i915_address_space; 50 struct i915_gtt_view; 51 struct intel_atomic_state; 52 struct intel_crtc; 53 struct intel_crtc_state; 54 struct intel_digital_port; 55 struct intel_dp; 56 struct intel_encoder; 57 struct intel_initial_plane_config; 58 struct intel_load_detect_pipe; 59 struct intel_plane; 60 struct intel_plane_state; 61 struct intel_power_domain_mask; 62 struct intel_remapped_info; 63 struct intel_rotation_info; 64 struct pci_dev; 65 66 enum i915_gpio { 67 GPIOA, 68 GPIOB, 69 GPIOC, 70 GPIOD, 71 GPIOE, 72 GPIOF, 73 GPIOG, 74 GPIOH, 75 __GPIOI_UNUSED, 76 GPIOJ, 77 GPIOK, 78 GPIOL, 79 GPIOM, 80 GPION, 81 GPIOO, 82 }; 83 84 /* 85 * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the 86 * rest have consecutive values and match the enum values of transcoders 87 * with a 1:1 transcoder -> pipe mapping. 88 */ 89 enum pipe { 90 INVALID_PIPE = -1, 91 92 PIPE_A = 0, 93 PIPE_B, 94 PIPE_C, 95 PIPE_D, 96 _PIPE_EDP, 97 98 I915_MAX_PIPES = _PIPE_EDP 99 }; 100 101 #define pipe_name(p) ((p) + 'A') 102 103 enum transcoder { 104 INVALID_TRANSCODER = -1, 105 /* 106 * The following transcoders have a 1:1 transcoder -> pipe mapping, 107 * keep their values fixed: the code assumes that TRANSCODER_A=0, the 108 * rest have consecutive values and match the enum values of the pipes 109 * they map to. 110 */ 111 TRANSCODER_A = PIPE_A, 112 TRANSCODER_B = PIPE_B, 113 TRANSCODER_C = PIPE_C, 114 TRANSCODER_D = PIPE_D, 115 116 /* 117 * The following transcoders can map to any pipe, their enum value 118 * doesn't need to stay fixed. 119 */ 120 TRANSCODER_EDP, 121 TRANSCODER_DSI_0, 122 TRANSCODER_DSI_1, 123 TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */ 124 TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */ 125 126 I915_MAX_TRANSCODERS 127 }; 128 129 static inline const char *transcoder_name(enum transcoder transcoder) 130 { 131 switch (transcoder) { 132 case TRANSCODER_A: 133 return "A"; 134 case TRANSCODER_B: 135 return "B"; 136 case TRANSCODER_C: 137 return "C"; 138 case TRANSCODER_D: 139 return "D"; 140 case TRANSCODER_EDP: 141 return "EDP"; 142 case TRANSCODER_DSI_A: 143 return "DSI A"; 144 case TRANSCODER_DSI_C: 145 return "DSI C"; 146 default: 147 return "<invalid>"; 148 } 149 } 150 151 static inline bool transcoder_is_dsi(enum transcoder transcoder) 152 { 153 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; 154 } 155 156 /* 157 * Global legacy plane identifier. Valid only for primary/sprite 158 * planes on pre-g4x, and only for primary planes on g4x-bdw. 159 */ 160 enum i9xx_plane_id { 161 PLANE_A, 162 PLANE_B, 163 PLANE_C, 164 }; 165 166 #define plane_name(p) ((p) + 'A') 167 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A') 168 169 /* 170 * Per-pipe plane identifier. 171 * I915_MAX_PLANES in the enum below is the maximum (across all platforms) 172 * number of planes per CRTC. Not all platforms really have this many planes, 173 * which means some arrays of size I915_MAX_PLANES may have unused entries 174 * between the topmost sprite plane and the cursor plane. 175 * 176 * This is expected to be passed to various register macros 177 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care. 178 */ 179 enum plane_id { 180 PLANE_PRIMARY, 181 PLANE_SPRITE0, 182 PLANE_SPRITE1, 183 PLANE_SPRITE2, 184 PLANE_SPRITE3, 185 PLANE_SPRITE4, 186 PLANE_SPRITE5, 187 PLANE_CURSOR, 188 189 I915_MAX_PLANES, 190 }; 191 192 #define for_each_plane_id_on_crtc(__crtc, __p) \ 193 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \ 194 for_each_if((__crtc)->plane_ids_mask & BIT(__p)) 195 196 #define for_each_dbuf_slice(__dev_priv, __slice) \ 197 for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \ 198 for_each_if(INTEL_INFO(__dev_priv)->display.dbuf.slice_mask & BIT(__slice)) 199 200 #define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \ 201 for_each_dbuf_slice((__dev_priv), (__slice)) \ 202 for_each_if((__mask) & BIT(__slice)) 203 204 enum port { 205 PORT_NONE = -1, 206 207 PORT_A = 0, 208 PORT_B, 209 PORT_C, 210 PORT_D, 211 PORT_E, 212 PORT_F, 213 PORT_G, 214 PORT_H, 215 PORT_I, 216 217 /* tgl+ */ 218 PORT_TC1 = PORT_D, 219 PORT_TC2, 220 PORT_TC3, 221 PORT_TC4, 222 PORT_TC5, 223 PORT_TC6, 224 225 /* XE_LPD repositions D/E offsets and bitfields */ 226 PORT_D_XELPD = PORT_TC5, 227 PORT_E_XELPD, 228 229 I915_MAX_PORTS 230 }; 231 232 #define port_name(p) ((p) + 'A') 233 234 /* 235 * Ports identifier referenced from other drivers. 236 * Expected to remain stable over time 237 */ 238 static inline const char *port_identifier(enum port port) 239 { 240 switch (port) { 241 case PORT_A: 242 return "Port A"; 243 case PORT_B: 244 return "Port B"; 245 case PORT_C: 246 return "Port C"; 247 case PORT_D: 248 return "Port D"; 249 case PORT_E: 250 return "Port E"; 251 case PORT_F: 252 return "Port F"; 253 case PORT_G: 254 return "Port G"; 255 case PORT_H: 256 return "Port H"; 257 case PORT_I: 258 return "Port I"; 259 default: 260 return "<invalid>"; 261 } 262 } 263 264 enum tc_port { 265 TC_PORT_NONE = -1, 266 267 TC_PORT_1 = 0, 268 TC_PORT_2, 269 TC_PORT_3, 270 TC_PORT_4, 271 TC_PORT_5, 272 TC_PORT_6, 273 274 I915_MAX_TC_PORTS 275 }; 276 277 enum tc_port_mode { 278 TC_PORT_DISCONNECTED, 279 TC_PORT_TBT_ALT, 280 TC_PORT_DP_ALT, 281 TC_PORT_LEGACY, 282 }; 283 284 enum dpio_channel { 285 DPIO_CH0, 286 DPIO_CH1 287 }; 288 289 enum dpio_phy { 290 DPIO_PHY0, 291 DPIO_PHY1, 292 DPIO_PHY2, 293 }; 294 295 enum aux_ch { 296 AUX_CH_A, 297 AUX_CH_B, 298 AUX_CH_C, 299 AUX_CH_D, 300 AUX_CH_E, /* ICL+ */ 301 AUX_CH_F, 302 AUX_CH_G, 303 AUX_CH_H, 304 AUX_CH_I, 305 306 /* tgl+ */ 307 AUX_CH_USBC1 = AUX_CH_D, 308 AUX_CH_USBC2, 309 AUX_CH_USBC3, 310 AUX_CH_USBC4, 311 AUX_CH_USBC5, 312 AUX_CH_USBC6, 313 314 /* XE_LPD repositions D/E offsets and bitfields */ 315 AUX_CH_D_XELPD = AUX_CH_USBC5, 316 AUX_CH_E_XELPD, 317 }; 318 319 #define aux_ch_name(a) ((a) + 'A') 320 321 /* Used by dp and fdi links */ 322 struct intel_link_m_n { 323 u32 tu; 324 u32 data_m; 325 u32 data_n; 326 u32 link_m; 327 u32 link_n; 328 }; 329 330 enum phy { 331 PHY_NONE = -1, 332 333 PHY_A = 0, 334 PHY_B, 335 PHY_C, 336 PHY_D, 337 PHY_E, 338 PHY_F, 339 PHY_G, 340 PHY_H, 341 PHY_I, 342 343 I915_MAX_PHYS 344 }; 345 346 #define phy_name(a) ((a) + 'A') 347 348 enum phy_fia { 349 FIA1, 350 FIA2, 351 FIA3, 352 }; 353 354 enum hpd_pin { 355 HPD_NONE = 0, 356 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 357 HPD_CRT, 358 HPD_SDVO_B, 359 HPD_SDVO_C, 360 HPD_PORT_A, 361 HPD_PORT_B, 362 HPD_PORT_C, 363 HPD_PORT_D, 364 HPD_PORT_E, 365 HPD_PORT_TC1, 366 HPD_PORT_TC2, 367 HPD_PORT_TC3, 368 HPD_PORT_TC4, 369 HPD_PORT_TC5, 370 HPD_PORT_TC6, 371 372 HPD_NUM_PINS 373 }; 374 375 #define for_each_hpd_pin(__pin) \ 376 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) 377 378 #define for_each_pipe(__dev_priv, __p) \ 379 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \ 380 for_each_if(RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p)) 381 382 #define for_each_pipe_masked(__dev_priv, __p, __mask) \ 383 for_each_pipe(__dev_priv, __p) \ 384 for_each_if((__mask) & BIT(__p)) 385 386 #define for_each_cpu_transcoder(__dev_priv, __t) \ 387 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \ 388 for_each_if (RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t)) 389 390 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \ 391 for_each_cpu_transcoder(__dev_priv, __t) \ 392 for_each_if ((__mask) & BIT(__t)) 393 394 #define for_each_sprite(__dev_priv, __p, __s) \ 395 for ((__s) = 0; \ 396 (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \ 397 (__s)++) 398 399 #define for_each_port(__port) \ 400 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) 401 402 #define for_each_port_masked(__port, __ports_mask) \ 403 for_each_port(__port) \ 404 for_each_if((__ports_mask) & BIT(__port)) 405 406 #define for_each_phy_masked(__phy, __phys_mask) \ 407 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ 408 for_each_if((__phys_mask) & BIT(__phy)) 409 410 #define for_each_crtc(dev, crtc) \ 411 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) 412 413 #define for_each_intel_plane(dev, intel_plane) \ 414 list_for_each_entry(intel_plane, \ 415 &(dev)->mode_config.plane_list, \ 416 base.head) 417 418 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ 419 list_for_each_entry(intel_plane, \ 420 &(dev)->mode_config.plane_list, \ 421 base.head) \ 422 for_each_if((plane_mask) & \ 423 drm_plane_mask(&intel_plane->base)) 424 425 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ 426 list_for_each_entry(intel_plane, \ 427 &(dev)->mode_config.plane_list, \ 428 base.head) \ 429 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe) 430 431 #define for_each_intel_crtc(dev, intel_crtc) \ 432 list_for_each_entry(intel_crtc, \ 433 &(dev)->mode_config.crtc_list, \ 434 base.head) 435 436 #define for_each_intel_crtc_in_pipe_mask(dev, intel_crtc, pipe_mask) \ 437 list_for_each_entry(intel_crtc, \ 438 &(dev)->mode_config.crtc_list, \ 439 base.head) \ 440 for_each_if((pipe_mask) & BIT(intel_crtc->pipe)) 441 442 #define for_each_intel_encoder(dev, intel_encoder) \ 443 list_for_each_entry(intel_encoder, \ 444 &(dev)->mode_config.encoder_list, \ 445 base.head) 446 447 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \ 448 list_for_each_entry(intel_encoder, \ 449 &(dev)->mode_config.encoder_list, \ 450 base.head) \ 451 for_each_if((encoder_mask) & \ 452 drm_encoder_mask(&intel_encoder->base)) 453 454 #define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \ 455 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 456 for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \ 457 intel_encoder_can_psr(intel_encoder)) 458 459 #define for_each_intel_dp(dev, intel_encoder) \ 460 for_each_intel_encoder(dev, intel_encoder) \ 461 for_each_if(intel_encoder_is_dp(intel_encoder)) 462 463 #define for_each_intel_encoder_with_psr(dev, intel_encoder) \ 464 for_each_intel_encoder((dev), (intel_encoder)) \ 465 for_each_if(intel_encoder_can_psr(intel_encoder)) 466 467 #define for_each_intel_connector_iter(intel_connector, iter) \ 468 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter)))) 469 470 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 471 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 472 for_each_if((intel_encoder)->base.crtc == (__crtc)) 473 474 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ 475 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ 476 for_each_if((intel_connector)->base.encoder == (__encoder)) 477 478 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \ 479 for ((__i) = 0; \ 480 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 481 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 482 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \ 483 (__i)++) \ 484 for_each_if(plane) 485 486 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \ 487 for ((__i) = 0; \ 488 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 489 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 490 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 491 (__i)++) \ 492 for_each_if(plane) 493 494 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \ 495 for ((__i) = 0; \ 496 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 497 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 498 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 499 (__i)++) \ 500 for_each_if(crtc) 501 502 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \ 503 for ((__i) = 0; \ 504 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 505 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 506 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \ 507 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 508 (__i)++) \ 509 for_each_if(plane) 510 511 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 512 for ((__i) = 0; \ 513 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 514 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 515 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 516 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 517 (__i)++) \ 518 for_each_if(crtc) 519 520 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 521 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \ 522 (__i) >= 0 && \ 523 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 524 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 525 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 526 (__i)--) \ 527 for_each_if(crtc) 528 529 #define intel_atomic_crtc_state_for_each_plane_state( \ 530 plane, plane_state, \ 531 crtc_state) \ 532 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \ 533 ((crtc_state)->uapi.plane_mask)) \ 534 for_each_if ((plane_state = \ 535 to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base)))) 536 537 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \ 538 for ((__i) = 0; \ 539 (__i) < (__state)->base.num_connector; \ 540 (__i)++) \ 541 for_each_if ((__state)->base.connectors[__i].ptr && \ 542 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \ 543 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1)) 544 545 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 546 struct intel_crtc *crtc); 547 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 548 u8 active_pipes); 549 void intel_link_compute_m_n(u16 bpp, int nlanes, 550 int pixel_clock, int link_clock, 551 struct intel_link_m_n *m_n, 552 bool fec_enable); 553 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 554 u32 pixel_format, u64 modifier); 555 enum drm_mode_status 556 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 557 const struct drm_display_mode *mode, 558 bool bigjoiner); 559 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); 560 bool is_trans_port_sync_mode(const struct intel_crtc_state *state); 561 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state); 562 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state); 563 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state); 564 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state); 565 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state); 566 bool intel_pipe_config_compare(const struct intel_crtc_state *current_config, 567 const struct intel_crtc_state *pipe_config, 568 bool fastset); 569 void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state); 570 571 void intel_plane_destroy(struct drm_plane *plane); 572 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); 573 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state); 574 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state); 575 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state); 576 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 577 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 578 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); 579 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 580 const char *name, u32 reg, int ref_freq); 581 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 582 const char *name, u32 reg); 583 void intel_init_display_hooks(struct drm_i915_private *dev_priv); 584 unsigned int intel_fb_xy_to_linear(int x, int y, 585 const struct intel_plane_state *state, 586 int plane); 587 void intel_add_fb_offsets(int *x, int *y, 588 const struct intel_plane_state *state, int plane); 589 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); 590 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info); 591 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv); 592 int intel_display_suspend(struct drm_device *dev); 593 void intel_encoder_destroy(struct drm_encoder *encoder); 594 struct drm_display_mode * 595 intel_encoder_current_mode(struct intel_encoder *encoder); 596 void intel_encoder_get_config(struct intel_encoder *encoder, 597 struct intel_crtc_state *crtc_state); 598 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy); 599 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy); 600 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy); 601 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, 602 enum port port); 603 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 604 struct drm_file *file_priv); 605 606 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp); 607 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 608 struct intel_digital_port *dig_port, 609 unsigned int expected_mask); 610 int intel_get_load_detect_pipe(struct drm_connector *connector, 611 struct intel_load_detect_pipe *old, 612 struct drm_modeset_acquire_ctx *ctx); 613 void intel_release_load_detect_pipe(struct drm_connector *connector, 614 struct intel_load_detect_pipe *old, 615 struct drm_modeset_acquire_ctx *ctx); 616 struct drm_framebuffer * 617 intel_framebuffer_create(struct drm_i915_gem_object *obj, 618 struct drm_mode_fb_cmd2 *mode_cmd); 619 620 bool intel_fuzzy_clock_check(int clock1, int clock2); 621 622 void intel_display_prepare_reset(struct drm_i915_private *dev_priv); 623 void intel_display_finish_reset(struct drm_i915_private *dev_priv); 624 void intel_zero_m_n(struct intel_link_m_n *m_n); 625 void intel_set_m_n(struct drm_i915_private *i915, 626 const struct intel_link_m_n *m_n, 627 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 628 i915_reg_t link_m_reg, i915_reg_t link_n_reg); 629 void intel_get_m_n(struct drm_i915_private *i915, 630 struct intel_link_m_n *m_n, 631 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 632 i915_reg_t link_m_reg, i915_reg_t link_n_reg); 633 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 634 enum transcoder transcoder); 635 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 636 enum transcoder cpu_transcoder, 637 const struct intel_link_m_n *m_n); 638 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 639 enum transcoder cpu_transcoder, 640 const struct intel_link_m_n *m_n); 641 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 642 enum transcoder cpu_transcoder, 643 struct intel_link_m_n *m_n); 644 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 645 enum transcoder cpu_transcoder, 646 struct intel_link_m_n *m_n); 647 void i9xx_crtc_clock_get(struct intel_crtc *crtc, 648 struct intel_crtc_state *pipe_config); 649 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); 650 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config); 651 enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port); 652 enum intel_display_power_domain 653 intel_aux_power_domain(struct intel_digital_port *dig_port); 654 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 655 struct intel_crtc_state *crtc_state); 656 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state); 657 658 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc); 659 unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state); 660 661 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state); 662 663 struct intel_encoder * 664 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 665 const struct intel_crtc_state *crtc_state); 666 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 667 struct intel_plane *plane); 668 void intel_set_plane_visible(struct intel_crtc_state *crtc_state, 669 struct intel_plane_state *plane_state, 670 bool visible); 671 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state); 672 673 void intel_display_driver_register(struct drm_i915_private *i915); 674 void intel_display_driver_unregister(struct drm_i915_private *i915); 675 676 void intel_update_watermarks(struct drm_i915_private *i915); 677 678 /* modesetting */ 679 bool intel_modeset_probe_defer(struct pci_dev *pdev); 680 void intel_modeset_init_hw(struct drm_i915_private *i915); 681 int intel_modeset_init_noirq(struct drm_i915_private *i915); 682 int intel_modeset_init_nogem(struct drm_i915_private *i915); 683 int intel_modeset_init(struct drm_i915_private *i915); 684 void intel_modeset_driver_remove(struct drm_i915_private *i915); 685 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915); 686 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915); 687 void intel_display_resume(struct drm_device *dev); 688 int intel_modeset_all_pipes(struct intel_atomic_state *state); 689 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 690 struct intel_power_domain_mask *old_domains); 691 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, 692 struct intel_power_domain_mask *domains); 693 694 /* modesetting asserts */ 695 void assert_transcoder(struct drm_i915_private *dev_priv, 696 enum transcoder cpu_transcoder, bool state); 697 #define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true) 698 #define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false) 699 700 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and 701 * WARN_ON()) for hw state sanity checks to check for unexpected conditions 702 * which may not necessarily be a user visible problem. This will either 703 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to 704 * enable distros and users to tailor their preferred amount of i915 abrt 705 * spam. 706 */ 707 #define I915_STATE_WARN(condition, format...) ({ \ 708 int __ret_warn_on = !!(condition); \ 709 if (unlikely(__ret_warn_on)) \ 710 if (!WARN(i915_modparams.verbose_state_checks, format)) \ 711 DRM_ERROR(format); \ 712 unlikely(__ret_warn_on); \ 713 }) 714 715 #define I915_STATE_WARN_ON(x) \ 716 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") 717 718 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915); 719 720 #endif 721