1 /* 2 * Copyright © 2006-2019 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DISPLAY_H_ 26 #define _INTEL_DISPLAY_H_ 27 28 #include <drm/drm_util.h> 29 30 #define drm_i915_private inteldrm_softc 31 32 enum link_m_n_set; 33 struct dpll; 34 struct drm_connector; 35 struct drm_device; 36 struct drm_display_mode; 37 struct drm_encoder; 38 struct drm_file; 39 struct drm_format_info; 40 struct drm_framebuffer; 41 struct drm_i915_error_state_buf; 42 struct drm_i915_gem_object; 43 struct drm_i915_private; 44 struct drm_mode_fb_cmd2; 45 struct drm_modeset_acquire_ctx; 46 struct drm_plane; 47 struct drm_plane_state; 48 struct i915_ggtt_view; 49 struct intel_atomic_state; 50 struct intel_crtc; 51 struct intel_crtc_state; 52 struct intel_crtc_state; 53 struct intel_digital_port; 54 struct intel_dp; 55 struct intel_encoder; 56 struct intel_load_detect_pipe; 57 struct intel_plane; 58 struct intel_plane_state; 59 struct intel_remapped_info; 60 struct intel_rotation_info; 61 62 enum i915_gpio { 63 GPIOA, 64 GPIOB, 65 GPIOC, 66 GPIOD, 67 GPIOE, 68 GPIOF, 69 GPIOG, 70 GPIOH, 71 __GPIOI_UNUSED, 72 GPIOJ, 73 GPIOK, 74 GPIOL, 75 GPIOM, 76 GPION, 77 GPIOO, 78 }; 79 80 /* 81 * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the 82 * rest have consecutive values and match the enum values of transcoders 83 * with a 1:1 transcoder -> pipe mapping. 84 */ 85 enum pipe { 86 INVALID_PIPE = -1, 87 88 PIPE_A = 0, 89 PIPE_B, 90 PIPE_C, 91 PIPE_D, 92 _PIPE_EDP, 93 94 I915_MAX_PIPES = _PIPE_EDP 95 }; 96 97 #define pipe_name(p) ((p) + 'A') 98 99 enum transcoder { 100 INVALID_TRANSCODER = -1, 101 /* 102 * The following transcoders have a 1:1 transcoder -> pipe mapping, 103 * keep their values fixed: the code assumes that TRANSCODER_A=0, the 104 * rest have consecutive values and match the enum values of the pipes 105 * they map to. 106 */ 107 TRANSCODER_A = PIPE_A, 108 TRANSCODER_B = PIPE_B, 109 TRANSCODER_C = PIPE_C, 110 TRANSCODER_D = PIPE_D, 111 112 /* 113 * The following transcoders can map to any pipe, their enum value 114 * doesn't need to stay fixed. 115 */ 116 TRANSCODER_EDP, 117 TRANSCODER_DSI_0, 118 TRANSCODER_DSI_1, 119 TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */ 120 TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */ 121 122 I915_MAX_TRANSCODERS 123 }; 124 125 static inline const char *transcoder_name(enum transcoder transcoder) 126 { 127 switch (transcoder) { 128 case TRANSCODER_A: 129 return "A"; 130 case TRANSCODER_B: 131 return "B"; 132 case TRANSCODER_C: 133 return "C"; 134 case TRANSCODER_D: 135 return "D"; 136 case TRANSCODER_EDP: 137 return "EDP"; 138 case TRANSCODER_DSI_A: 139 return "DSI A"; 140 case TRANSCODER_DSI_C: 141 return "DSI C"; 142 default: 143 return "<invalid>"; 144 } 145 } 146 147 static inline bool transcoder_is_dsi(enum transcoder transcoder) 148 { 149 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; 150 } 151 152 /* 153 * Global legacy plane identifier. Valid only for primary/sprite 154 * planes on pre-g4x, and only for primary planes on g4x-bdw. 155 */ 156 enum i9xx_plane_id { 157 PLANE_A, 158 PLANE_B, 159 PLANE_C, 160 }; 161 162 #define plane_name(p) ((p) + 'A') 163 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A') 164 165 /* 166 * Per-pipe plane identifier. 167 * I915_MAX_PLANES in the enum below is the maximum (across all platforms) 168 * number of planes per CRTC. Not all platforms really have this many planes, 169 * which means some arrays of size I915_MAX_PLANES may have unused entries 170 * between the topmost sprite plane and the cursor plane. 171 * 172 * This is expected to be passed to various register macros 173 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care. 174 */ 175 enum plane_id { 176 PLANE_PRIMARY, 177 PLANE_SPRITE0, 178 PLANE_SPRITE1, 179 PLANE_SPRITE2, 180 PLANE_SPRITE3, 181 PLANE_SPRITE4, 182 PLANE_SPRITE5, 183 PLANE_CURSOR, 184 185 I915_MAX_PLANES, 186 }; 187 188 #define for_each_plane_id_on_crtc(__crtc, __p) \ 189 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \ 190 for_each_if((__crtc)->plane_ids_mask & BIT(__p)) 191 192 enum port { 193 PORT_NONE = -1, 194 195 PORT_A = 0, 196 PORT_B, 197 PORT_C, 198 PORT_D, 199 PORT_E, 200 PORT_F, 201 PORT_G, 202 PORT_H, 203 PORT_I, 204 205 I915_MAX_PORTS 206 }; 207 208 #define port_name(p) ((p) + 'A') 209 210 /* 211 * Ports identifier referenced from other drivers. 212 * Expected to remain stable over time 213 */ 214 static inline const char *port_identifier(enum port port) 215 { 216 switch (port) { 217 case PORT_A: 218 return "Port A"; 219 case PORT_B: 220 return "Port B"; 221 case PORT_C: 222 return "Port C"; 223 case PORT_D: 224 return "Port D"; 225 case PORT_E: 226 return "Port E"; 227 case PORT_F: 228 return "Port F"; 229 case PORT_G: 230 return "Port G"; 231 case PORT_H: 232 return "Port H"; 233 case PORT_I: 234 return "Port I"; 235 default: 236 return "<invalid>"; 237 } 238 } 239 240 enum tc_port { 241 PORT_TC_NONE = -1, 242 243 PORT_TC1 = 0, 244 PORT_TC2, 245 PORT_TC3, 246 PORT_TC4, 247 PORT_TC5, 248 PORT_TC6, 249 250 I915_MAX_TC_PORTS 251 }; 252 253 enum tc_port_mode { 254 TC_PORT_TBT_ALT, 255 TC_PORT_DP_ALT, 256 TC_PORT_LEGACY, 257 }; 258 259 enum dpio_channel { 260 DPIO_CH0, 261 DPIO_CH1 262 }; 263 264 enum dpio_phy { 265 DPIO_PHY0, 266 DPIO_PHY1, 267 DPIO_PHY2, 268 }; 269 270 #define I915_NUM_PHYS_VLV 2 271 272 enum aux_ch { 273 AUX_CH_A, 274 AUX_CH_B, 275 AUX_CH_C, 276 AUX_CH_D, 277 AUX_CH_E, /* ICL+ */ 278 AUX_CH_F, 279 AUX_CH_G, 280 }; 281 282 #define aux_ch_name(a) ((a) + 'A') 283 284 /* Used by dp and fdi links */ 285 struct intel_link_m_n { 286 u32 tu; 287 u32 gmch_m; 288 u32 gmch_n; 289 u32 link_m; 290 u32 link_n; 291 }; 292 293 enum phy { 294 PHY_NONE = -1, 295 296 PHY_A = 0, 297 PHY_B, 298 PHY_C, 299 PHY_D, 300 PHY_E, 301 PHY_F, 302 PHY_G, 303 PHY_H, 304 PHY_I, 305 306 I915_MAX_PHYS 307 }; 308 309 #define phy_name(a) ((a) + 'A') 310 311 enum phy_fia { 312 FIA1, 313 FIA2, 314 FIA3, 315 }; 316 317 #define for_each_pipe(__dev_priv, __p) \ 318 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \ 319 for_each_if(INTEL_INFO(__dev_priv)->pipe_mask & BIT(__p)) 320 321 #define for_each_pipe_masked(__dev_priv, __p, __mask) \ 322 for_each_pipe(__dev_priv, __p) \ 323 for_each_if((__mask) & BIT(__p)) 324 325 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \ 326 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \ 327 for_each_if ((__mask) & (1 << (__t))) 328 329 #define for_each_universal_plane(__dev_priv, __pipe, __p) \ 330 for ((__p) = 0; \ 331 (__p) < RUNTIME_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ 332 (__p)++) 333 334 #define for_each_sprite(__dev_priv, __p, __s) \ 335 for ((__s) = 0; \ 336 (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \ 337 (__s)++) 338 339 #define for_each_port(__port) \ 340 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) 341 342 #define for_each_port_masked(__port, __ports_mask) \ 343 for_each_port(__port) \ 344 for_each_if((__ports_mask) & BIT(__port)) 345 346 #define for_each_phy_masked(__phy, __phys_mask) \ 347 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ 348 for_each_if((__phys_mask) & BIT(__phy)) 349 350 #define for_each_crtc(dev, crtc) \ 351 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) 352 353 #define for_each_intel_plane(dev, intel_plane) \ 354 list_for_each_entry(intel_plane, \ 355 &(dev)->mode_config.plane_list, \ 356 base.head) 357 358 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ 359 list_for_each_entry(intel_plane, \ 360 &(dev)->mode_config.plane_list, \ 361 base.head) \ 362 for_each_if((plane_mask) & \ 363 drm_plane_mask(&intel_plane->base)) 364 365 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ 366 list_for_each_entry(intel_plane, \ 367 &(dev)->mode_config.plane_list, \ 368 base.head) \ 369 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe) 370 371 #define for_each_intel_crtc(dev, intel_crtc) \ 372 list_for_each_entry(intel_crtc, \ 373 &(dev)->mode_config.crtc_list, \ 374 base.head) 375 376 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \ 377 list_for_each_entry(intel_crtc, \ 378 &(dev)->mode_config.crtc_list, \ 379 base.head) \ 380 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base)) 381 382 #define for_each_intel_encoder(dev, intel_encoder) \ 383 list_for_each_entry(intel_encoder, \ 384 &(dev)->mode_config.encoder_list, \ 385 base.head) 386 387 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \ 388 list_for_each_entry(intel_encoder, \ 389 &(dev)->mode_config.encoder_list, \ 390 base.head) \ 391 for_each_if((encoder_mask) & \ 392 drm_encoder_mask(&intel_encoder->base)) 393 394 #define for_each_intel_dp(dev, intel_encoder) \ 395 for_each_intel_encoder(dev, intel_encoder) \ 396 for_each_if(intel_encoder_is_dp(intel_encoder)) 397 398 #define for_each_intel_connector_iter(intel_connector, iter) \ 399 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter)))) 400 401 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 402 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 403 for_each_if((intel_encoder)->base.crtc == (__crtc)) 404 405 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ 406 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ 407 for_each_if((intel_connector)->base.encoder == (__encoder)) 408 409 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \ 410 for ((__i) = 0; \ 411 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 412 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 413 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \ 414 (__i)++) \ 415 for_each_if(plane) 416 417 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \ 418 for ((__i) = 0; \ 419 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 420 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 421 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 422 (__i)++) \ 423 for_each_if(plane) 424 425 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \ 426 for ((__i) = 0; \ 427 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 428 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 429 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 430 (__i)++) \ 431 for_each_if(crtc) 432 433 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \ 434 for ((__i) = 0; \ 435 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 436 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 437 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \ 438 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 439 (__i)++) \ 440 for_each_if(plane) 441 442 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 443 for ((__i) = 0; \ 444 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 445 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 446 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 447 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 448 (__i)++) \ 449 for_each_if(crtc) 450 451 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 452 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \ 453 (__i) >= 0 && \ 454 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 455 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 456 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 457 (__i)--) \ 458 for_each_if(crtc) 459 460 #define intel_atomic_crtc_state_for_each_plane_state( \ 461 plane, plane_state, \ 462 crtc_state) \ 463 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \ 464 ((crtc_state)->uapi.plane_mask)) \ 465 for_each_if ((plane_state = \ 466 to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base)))) 467 468 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \ 469 for ((__i) = 0; \ 470 (__i) < (__state)->base.num_connector; \ 471 (__i)++) \ 472 for_each_if ((__state)->base.connectors[__i].ptr && \ 473 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \ 474 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1)) 475 476 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 477 u8 active_pipes); 478 void intel_link_compute_m_n(u16 bpp, int nlanes, 479 int pixel_clock, int link_clock, 480 struct intel_link_m_n *m_n, 481 bool constant_n, bool fec_enable); 482 bool is_ccs_modifier(u64 modifier); 483 int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane); 484 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv); 485 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 486 u32 pixel_format, u64 modifier); 487 bool intel_plane_can_remap(const struct intel_plane_state *plane_state); 488 enum drm_mode_status 489 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 490 const struct drm_display_mode *mode); 491 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); 492 bool is_trans_port_sync_mode(const struct intel_crtc_state *state); 493 494 void intel_plane_destroy(struct drm_plane *plane); 495 void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state); 496 void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state); 497 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 498 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 499 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc); 500 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); 501 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 502 const char *name, u32 reg, int ref_freq); 503 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 504 const char *name, u32 reg); 505 void lpt_pch_enable(const struct intel_crtc_state *crtc_state); 506 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv); 507 void lpt_disable_iclkip(struct drm_i915_private *dev_priv); 508 void intel_init_display_hooks(struct drm_i915_private *dev_priv); 509 unsigned int intel_fb_xy_to_linear(int x, int y, 510 const struct intel_plane_state *state, 511 int plane); 512 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb, 513 int color_plane, unsigned int height); 514 void intel_add_fb_offsets(int *x, int *y, 515 const struct intel_plane_state *state, int plane); 516 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); 517 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info); 518 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv); 519 int intel_display_suspend(struct drm_device *dev); 520 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv); 521 void intel_encoder_destroy(struct drm_encoder *encoder); 522 struct drm_display_mode * 523 intel_encoder_current_mode(struct intel_encoder *encoder); 524 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy); 525 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy); 526 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, 527 enum port port); 528 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 529 struct drm_file *file_priv); 530 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc); 531 void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state); 532 void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state); 533 534 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp); 535 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 536 struct intel_digital_port *dport, 537 unsigned int expected_mask); 538 int intel_get_load_detect_pipe(struct drm_connector *connector, 539 struct intel_load_detect_pipe *old, 540 struct drm_modeset_acquire_ctx *ctx); 541 void intel_release_load_detect_pipe(struct drm_connector *connector, 542 struct intel_load_detect_pipe *old, 543 struct drm_modeset_acquire_ctx *ctx); 544 struct i915_vma * 545 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, 546 const struct i915_ggtt_view *view, 547 bool uses_fence, 548 unsigned long *out_flags); 549 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags); 550 struct drm_framebuffer * 551 intel_framebuffer_create(struct drm_i915_gem_object *obj, 552 struct drm_mode_fb_cmd2 *mode_cmd); 553 int intel_prepare_plane_fb(struct drm_plane *plane, 554 struct drm_plane_state *new_state); 555 void intel_cleanup_plane_fb(struct drm_plane *plane, 556 struct drm_plane_state *old_state); 557 558 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, 559 enum pipe pipe); 560 561 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, 562 const struct dpll *dpll); 563 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe); 564 int lpt_get_iclkip(struct drm_i915_private *dev_priv); 565 bool intel_fuzzy_clock_check(int clock1, int clock2); 566 567 void intel_prepare_reset(struct drm_i915_private *dev_priv); 568 void intel_finish_reset(struct drm_i915_private *dev_priv); 569 void intel_dp_get_m_n(struct intel_crtc *crtc, 570 struct intel_crtc_state *pipe_config); 571 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, 572 enum link_m_n_set m_n); 573 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); 574 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, 575 struct dpll *best_clock); 576 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock); 577 578 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state); 579 void hsw_enable_ips(const struct intel_crtc_state *crtc_state); 580 void hsw_disable_ips(const struct intel_crtc_state *crtc_state); 581 enum intel_display_power_domain intel_port_to_power_domain(enum port port); 582 enum intel_display_power_domain 583 intel_aux_power_domain(struct intel_digital_port *dig_port); 584 void intel_mode_from_pipe_config(struct drm_display_mode *mode, 585 struct intel_crtc_state *pipe_config); 586 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 587 struct intel_crtc_state *crtc_state); 588 589 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center); 590 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state); 591 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state); 592 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state); 593 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, 594 const struct intel_plane_state *plane_state); 595 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state); 596 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, 597 const struct intel_plane_state *plane_state); 598 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state); 599 u32 skl_plane_stride(const struct intel_plane_state *plane_state, 600 int plane); 601 int skl_check_plane_surface(struct intel_plane_state *plane_state); 602 int i9xx_check_plane_surface(struct intel_plane_state *plane_state); 603 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha); 604 unsigned int i9xx_plane_max_stride(struct intel_plane *plane, 605 u32 pixel_format, u64 modifier, 606 unsigned int rotation); 607 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc); 608 609 struct intel_display_error_state * 610 intel_display_capture_error_state(struct drm_i915_private *dev_priv); 611 void intel_display_print_error_state(struct drm_i915_error_state_buf *e, 612 struct intel_display_error_state *error); 613 614 bool 615 intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info, 616 uint64_t modifier); 617 618 /* modesetting */ 619 void intel_modeset_init_hw(struct drm_i915_private *i915); 620 int intel_modeset_init_noirq(struct drm_i915_private *i915); 621 int intel_modeset_init(struct drm_i915_private *i915); 622 void intel_modeset_driver_remove(struct drm_i915_private *i915); 623 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915); 624 void intel_display_resume(struct drm_device *dev); 625 void intel_init_pch_refclk(struct drm_i915_private *dev_priv); 626 627 /* modesetting asserts */ 628 void assert_panel_unlocked(struct drm_i915_private *dev_priv, 629 enum pipe pipe); 630 void assert_pll(struct drm_i915_private *dev_priv, 631 enum pipe pipe, bool state); 632 #define assert_pll_enabled(d, p) assert_pll(d, p, true) 633 #define assert_pll_disabled(d, p) assert_pll(d, p, false) 634 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state); 635 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) 636 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) 637 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, 638 enum pipe pipe, bool state); 639 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) 640 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) 641 void assert_pipe(struct drm_i915_private *dev_priv, 642 enum transcoder cpu_transcoder, bool state); 643 #define assert_pipe_enabled(d, t) assert_pipe(d, t, true) 644 #define assert_pipe_disabled(d, t) assert_pipe(d, t, false) 645 646 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and 647 * WARN_ON()) for hw state sanity checks to check for unexpected conditions 648 * which may not necessarily be a user visible problem. This will either 649 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to 650 * enable distros and users to tailor their preferred amount of i915 abrt 651 * spam. 652 */ 653 #define I915_STATE_WARN(condition, format...) ({ \ 654 int __ret_warn_on = !!(condition); \ 655 if (unlikely(__ret_warn_on)) \ 656 if (!WARN(i915_modparams.verbose_state_checks, format)) \ 657 DRM_ERROR(format); \ 658 unlikely(__ret_warn_on); \ 659 }) 660 661 #define I915_STATE_WARN_ON(x) \ 662 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") 663 664 #endif 665