1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <drm/drm_scdc_helper.h> 29 30 #include "i915_drv.h" 31 #include "intel_audio.h" 32 #include "intel_combo_phy.h" 33 #include "intel_connector.h" 34 #include "intel_crtc.h" 35 #include "intel_ddi.h" 36 #include "intel_ddi_buf_trans.h" 37 #include "intel_de.h" 38 #include "intel_display_types.h" 39 #include "intel_dp.h" 40 #include "intel_dp_link_training.h" 41 #include "intel_dp_mst.h" 42 #include "intel_dpio_phy.h" 43 #include "intel_drrs.h" 44 #include "intel_dsi.h" 45 #include "intel_fdi.h" 46 #include "intel_fifo_underrun.h" 47 #include "intel_gmbus.h" 48 #include "intel_hdcp.h" 49 #include "intel_hdmi.h" 50 #include "intel_hotplug.h" 51 #include "intel_lspcon.h" 52 #include "intel_panel.h" 53 #include "intel_pps.h" 54 #include "intel_psr.h" 55 #include "intel_snps_phy.h" 56 #include "intel_sprite.h" 57 #include "intel_tc.h" 58 #include "intel_vdsc.h" 59 #include "intel_vrr.h" 60 #include "skl_scaler.h" 61 #include "skl_universal_plane.h" 62 63 static const u8 index_to_dp_signal_levels[] = { 64 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 65 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 66 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 67 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 68 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 69 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 70 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 71 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 72 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 73 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 74 }; 75 76 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 77 const struct intel_crtc_state *crtc_state) 78 { 79 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 80 int n_entries, level, default_entry; 81 82 n_entries = intel_ddi_hdmi_num_entries(encoder, crtc_state, &default_entry); 83 if (n_entries == 0) 84 return 0; 85 level = intel_bios_hdmi_level_shift(encoder); 86 if (level < 0) 87 level = default_entry; 88 89 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 90 level = n_entries - 1; 91 92 return level; 93 } 94 95 /* 96 * Starting with Haswell, DDI port buffers must be programmed with correct 97 * values in advance. This function programs the correct values for 98 * DP/eDP/FDI use cases. 99 */ 100 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 101 const struct intel_crtc_state *crtc_state) 102 { 103 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 104 u32 iboost_bit = 0; 105 int i, n_entries; 106 enum port port = encoder->port; 107 const struct intel_ddi_buf_trans *ddi_translations; 108 109 ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 110 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 111 return; 112 113 /* If we're boosting the current, set bit 31 of trans1 */ 114 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) && 115 intel_bios_encoder_dp_boost_level(encoder->devdata)) 116 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 117 118 for (i = 0; i < n_entries; i++) { 119 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 120 ddi_translations->entries[i].hsw.trans1 | iboost_bit); 121 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 122 ddi_translations->entries[i].hsw.trans2); 123 } 124 } 125 126 /* 127 * Starting with Haswell, DDI port buffers must be programmed with correct 128 * values in advance. This function programs the correct values for 129 * HDMI/DVI use cases. 130 */ 131 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 132 const struct intel_crtc_state *crtc_state, 133 int level) 134 { 135 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 136 u32 iboost_bit = 0; 137 int n_entries; 138 enum port port = encoder->port; 139 const struct intel_ddi_buf_trans *ddi_translations; 140 141 ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 142 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 143 return; 144 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 145 level = n_entries - 1; 146 147 /* If we're boosting the current, set bit 31 of trans1 */ 148 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) && 149 intel_bios_encoder_hdmi_boost_level(encoder->devdata)) 150 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 151 152 /* Entry 9 is for HDMI: */ 153 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 154 ddi_translations->entries[level].hsw.trans1 | iboost_bit); 155 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 156 ddi_translations->entries[level].hsw.trans2); 157 } 158 159 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 160 enum port port) 161 { 162 if (IS_BROXTON(dev_priv)) { 163 udelay(16); 164 return; 165 } 166 167 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 168 DDI_BUF_IS_IDLE), 8)) 169 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 170 port_name(port)); 171 } 172 173 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, 174 enum port port) 175 { 176 int ret; 177 178 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 179 if (DISPLAY_VER(dev_priv) < 10) { 180 usleep_range(518, 1000); 181 return; 182 } 183 184 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 185 DDI_BUF_IS_IDLE), IS_DG2(dev_priv) ? 1200 : 500, 10, 10); 186 187 if (ret) 188 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 189 port_name(port)); 190 } 191 192 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 193 { 194 switch (pll->info->id) { 195 case DPLL_ID_WRPLL1: 196 return PORT_CLK_SEL_WRPLL1; 197 case DPLL_ID_WRPLL2: 198 return PORT_CLK_SEL_WRPLL2; 199 case DPLL_ID_SPLL: 200 return PORT_CLK_SEL_SPLL; 201 case DPLL_ID_LCPLL_810: 202 return PORT_CLK_SEL_LCPLL_810; 203 case DPLL_ID_LCPLL_1350: 204 return PORT_CLK_SEL_LCPLL_1350; 205 case DPLL_ID_LCPLL_2700: 206 return PORT_CLK_SEL_LCPLL_2700; 207 default: 208 MISSING_CASE(pll->info->id); 209 return PORT_CLK_SEL_NONE; 210 } 211 } 212 213 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 214 const struct intel_crtc_state *crtc_state) 215 { 216 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 217 int clock = crtc_state->port_clock; 218 const enum intel_dpll_id id = pll->info->id; 219 220 switch (id) { 221 default: 222 /* 223 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 224 * here, so do warn if this get passed in 225 */ 226 MISSING_CASE(id); 227 return DDI_CLK_SEL_NONE; 228 case DPLL_ID_ICL_TBTPLL: 229 switch (clock) { 230 case 162000: 231 return DDI_CLK_SEL_TBT_162; 232 case 270000: 233 return DDI_CLK_SEL_TBT_270; 234 case 540000: 235 return DDI_CLK_SEL_TBT_540; 236 case 810000: 237 return DDI_CLK_SEL_TBT_810; 238 default: 239 MISSING_CASE(clock); 240 return DDI_CLK_SEL_NONE; 241 } 242 case DPLL_ID_ICL_MGPLL1: 243 case DPLL_ID_ICL_MGPLL2: 244 case DPLL_ID_ICL_MGPLL3: 245 case DPLL_ID_ICL_MGPLL4: 246 case DPLL_ID_TGL_MGPLL5: 247 case DPLL_ID_TGL_MGPLL6: 248 return DDI_CLK_SEL_MG; 249 } 250 } 251 252 static u32 ddi_buf_phy_link_rate(int port_clock) 253 { 254 switch (port_clock) { 255 case 162000: 256 return DDI_BUF_PHY_LINK_RATE(0); 257 case 216000: 258 return DDI_BUF_PHY_LINK_RATE(4); 259 case 243000: 260 return DDI_BUF_PHY_LINK_RATE(5); 261 case 270000: 262 return DDI_BUF_PHY_LINK_RATE(1); 263 case 324000: 264 return DDI_BUF_PHY_LINK_RATE(6); 265 case 432000: 266 return DDI_BUF_PHY_LINK_RATE(7); 267 case 540000: 268 return DDI_BUF_PHY_LINK_RATE(2); 269 case 810000: 270 return DDI_BUF_PHY_LINK_RATE(3); 271 default: 272 MISSING_CASE(port_clock); 273 return DDI_BUF_PHY_LINK_RATE(0); 274 } 275 } 276 277 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 278 const struct intel_crtc_state *crtc_state) 279 { 280 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 281 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 282 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 283 enum phy phy = intel_port_to_phy(i915, encoder->port); 284 285 intel_dp->DP = dig_port->saved_port_bits | 286 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); 287 intel_dp->DP |= DDI_PORT_WIDTH(crtc_state->lane_count); 288 289 if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) { 290 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 291 if (dig_port->tc_mode != TC_PORT_TBT_ALT) 292 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 293 } 294 } 295 296 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 297 enum port port) 298 { 299 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 300 301 switch (val) { 302 case DDI_CLK_SEL_NONE: 303 return 0; 304 case DDI_CLK_SEL_TBT_162: 305 return 162000; 306 case DDI_CLK_SEL_TBT_270: 307 return 270000; 308 case DDI_CLK_SEL_TBT_540: 309 return 540000; 310 case DDI_CLK_SEL_TBT_810: 311 return 810000; 312 default: 313 MISSING_CASE(val); 314 return 0; 315 } 316 } 317 318 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 319 { 320 int dotclock; 321 322 if (pipe_config->has_pch_encoder) 323 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 324 &pipe_config->fdi_m_n); 325 else if (intel_crtc_has_dp_encoder(pipe_config)) 326 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 327 &pipe_config->dp_m_n); 328 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 329 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; 330 else 331 dotclock = pipe_config->port_clock; 332 333 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 334 !intel_crtc_has_dp_encoder(pipe_config)) 335 dotclock *= 2; 336 337 if (pipe_config->pixel_multiplier) 338 dotclock /= pipe_config->pixel_multiplier; 339 340 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 341 } 342 343 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 344 const struct drm_connector_state *conn_state) 345 { 346 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 347 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 348 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 349 u32 temp; 350 351 if (!intel_crtc_has_dp_encoder(crtc_state)) 352 return; 353 354 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 355 356 temp = DP_MSA_MISC_SYNC_CLOCK; 357 358 switch (crtc_state->pipe_bpp) { 359 case 18: 360 temp |= DP_MSA_MISC_6_BPC; 361 break; 362 case 24: 363 temp |= DP_MSA_MISC_8_BPC; 364 break; 365 case 30: 366 temp |= DP_MSA_MISC_10_BPC; 367 break; 368 case 36: 369 temp |= DP_MSA_MISC_12_BPC; 370 break; 371 default: 372 MISSING_CASE(crtc_state->pipe_bpp); 373 break; 374 } 375 376 /* nonsense combination */ 377 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 378 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 379 380 if (crtc_state->limited_color_range) 381 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 382 383 /* 384 * As per DP 1.2 spec section 2.3.4.3 while sending 385 * YCBCR 444 signals we should program MSA MISC1/0 fields with 386 * colorspace information. 387 */ 388 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 389 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 390 391 /* 392 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 393 * of Color Encoding Format and Content Color Gamut] while sending 394 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 395 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 396 */ 397 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 398 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 399 400 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 401 } 402 403 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 404 { 405 if (master_transcoder == TRANSCODER_EDP) 406 return 0; 407 else 408 return master_transcoder + 1; 409 } 410 411 /* 412 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 413 * 414 * Only intended to be used by intel_ddi_enable_transcoder_func() and 415 * intel_ddi_config_transcoder_func(). 416 */ 417 static u32 418 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 419 const struct intel_crtc_state *crtc_state) 420 { 421 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 422 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 423 enum pipe pipe = crtc->pipe; 424 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 425 enum port port = encoder->port; 426 u32 temp; 427 428 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 429 temp = TRANS_DDI_FUNC_ENABLE; 430 if (DISPLAY_VER(dev_priv) >= 12) 431 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 432 else 433 temp |= TRANS_DDI_SELECT_PORT(port); 434 435 switch (crtc_state->pipe_bpp) { 436 case 18: 437 temp |= TRANS_DDI_BPC_6; 438 break; 439 case 24: 440 temp |= TRANS_DDI_BPC_8; 441 break; 442 case 30: 443 temp |= TRANS_DDI_BPC_10; 444 break; 445 case 36: 446 temp |= TRANS_DDI_BPC_12; 447 break; 448 default: 449 BUG(); 450 } 451 452 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 453 temp |= TRANS_DDI_PVSYNC; 454 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 455 temp |= TRANS_DDI_PHSYNC; 456 457 if (cpu_transcoder == TRANSCODER_EDP) { 458 switch (pipe) { 459 case PIPE_A: 460 /* On Haswell, can only use the always-on power well for 461 * eDP when not using the panel fitter, and when not 462 * using motion blur mitigation (which we don't 463 * support). */ 464 if (crtc_state->pch_pfit.force_thru) 465 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 466 else 467 temp |= TRANS_DDI_EDP_INPUT_A_ON; 468 break; 469 case PIPE_B: 470 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 471 break; 472 case PIPE_C: 473 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 474 break; 475 default: 476 BUG(); 477 break; 478 } 479 } 480 481 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 482 if (crtc_state->has_hdmi_sink) 483 temp |= TRANS_DDI_MODE_SELECT_HDMI; 484 else 485 temp |= TRANS_DDI_MODE_SELECT_DVI; 486 487 if (crtc_state->hdmi_scrambling) 488 temp |= TRANS_DDI_HDMI_SCRAMBLING; 489 if (crtc_state->hdmi_high_tmds_clock_ratio) 490 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 491 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 492 temp |= TRANS_DDI_MODE_SELECT_FDI; 493 temp |= (crtc_state->fdi_lanes - 1) << 1; 494 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 495 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 496 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 497 498 if (DISPLAY_VER(dev_priv) >= 12) { 499 enum transcoder master; 500 501 master = crtc_state->mst_master_transcoder; 502 drm_WARN_ON(&dev_priv->drm, 503 master == INVALID_TRANSCODER); 504 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 505 } 506 } else { 507 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 508 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 509 } 510 511 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 512 crtc_state->master_transcoder != INVALID_TRANSCODER) { 513 u8 master_select = 514 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 515 516 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 517 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 518 } 519 520 return temp; 521 } 522 523 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 524 const struct intel_crtc_state *crtc_state) 525 { 526 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 527 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 528 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 529 530 if (DISPLAY_VER(dev_priv) >= 11) { 531 enum transcoder master_transcoder = crtc_state->master_transcoder; 532 u32 ctl2 = 0; 533 534 if (master_transcoder != INVALID_TRANSCODER) { 535 u8 master_select = 536 bdw_trans_port_sync_master_select(master_transcoder); 537 538 ctl2 |= PORT_SYNC_MODE_ENABLE | 539 PORT_SYNC_MODE_MASTER_SELECT(master_select); 540 } 541 542 intel_de_write(dev_priv, 543 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); 544 } 545 546 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 547 intel_ddi_transcoder_func_reg_val_get(encoder, 548 crtc_state)); 549 } 550 551 /* 552 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 553 * bit. 554 */ 555 static void 556 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 557 const struct intel_crtc_state *crtc_state) 558 { 559 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 560 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 561 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 562 u32 ctl; 563 564 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 565 ctl &= ~TRANS_DDI_FUNC_ENABLE; 566 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 567 } 568 569 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 570 { 571 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 572 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 573 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 574 u32 ctl; 575 576 if (DISPLAY_VER(dev_priv) >= 11) 577 intel_de_write(dev_priv, 578 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); 579 580 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 581 582 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 583 584 ctl &= ~TRANS_DDI_FUNC_ENABLE; 585 586 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 587 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 588 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 589 590 if (DISPLAY_VER(dev_priv) >= 12) { 591 if (!intel_dp_mst_is_master_trans(crtc_state)) { 592 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 593 TRANS_DDI_MODE_SELECT_MASK); 594 } 595 } else { 596 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 597 } 598 599 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 600 601 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && 602 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 603 drm_dbg_kms(&dev_priv->drm, 604 "Quirk Increase DDI disabled time\n"); 605 /* Quirk time at 100ms for reliable operation */ 606 drm_msleep(100); 607 } 608 } 609 610 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 611 enum transcoder cpu_transcoder, 612 bool enable, u32 hdcp_mask) 613 { 614 struct drm_device *dev = intel_encoder->base.dev; 615 struct drm_i915_private *dev_priv = to_i915(dev); 616 intel_wakeref_t wakeref; 617 int ret = 0; 618 u32 tmp; 619 620 wakeref = intel_display_power_get_if_enabled(dev_priv, 621 intel_encoder->power_domain); 622 if (drm_WARN_ON(dev, !wakeref)) 623 return -ENXIO; 624 625 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 626 if (enable) 627 tmp |= hdcp_mask; 628 else 629 tmp &= ~hdcp_mask; 630 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp); 631 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 632 return ret; 633 } 634 635 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 636 { 637 struct drm_device *dev = intel_connector->base.dev; 638 struct drm_i915_private *dev_priv = to_i915(dev); 639 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 640 int type = intel_connector->base.connector_type; 641 enum port port = encoder->port; 642 enum transcoder cpu_transcoder; 643 intel_wakeref_t wakeref; 644 enum pipe pipe = 0; 645 u32 tmp; 646 bool ret; 647 648 wakeref = intel_display_power_get_if_enabled(dev_priv, 649 encoder->power_domain); 650 if (!wakeref) 651 return false; 652 653 if (!encoder->get_hw_state(encoder, &pipe)) { 654 ret = false; 655 goto out; 656 } 657 658 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 659 cpu_transcoder = TRANSCODER_EDP; 660 else 661 cpu_transcoder = (enum transcoder) pipe; 662 663 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 664 665 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 666 case TRANS_DDI_MODE_SELECT_HDMI: 667 case TRANS_DDI_MODE_SELECT_DVI: 668 ret = type == DRM_MODE_CONNECTOR_HDMIA; 669 break; 670 671 case TRANS_DDI_MODE_SELECT_DP_SST: 672 ret = type == DRM_MODE_CONNECTOR_eDP || 673 type == DRM_MODE_CONNECTOR_DisplayPort; 674 break; 675 676 case TRANS_DDI_MODE_SELECT_DP_MST: 677 /* if the transcoder is in MST state then 678 * connector isn't connected */ 679 ret = false; 680 break; 681 682 case TRANS_DDI_MODE_SELECT_FDI: 683 ret = type == DRM_MODE_CONNECTOR_VGA; 684 break; 685 686 default: 687 ret = false; 688 break; 689 } 690 691 out: 692 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 693 694 return ret; 695 } 696 697 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 698 u8 *pipe_mask, bool *is_dp_mst) 699 { 700 struct drm_device *dev = encoder->base.dev; 701 struct drm_i915_private *dev_priv = to_i915(dev); 702 enum port port = encoder->port; 703 intel_wakeref_t wakeref; 704 enum pipe p; 705 u32 tmp; 706 u8 mst_pipe_mask; 707 708 *pipe_mask = 0; 709 *is_dp_mst = false; 710 711 wakeref = intel_display_power_get_if_enabled(dev_priv, 712 encoder->power_domain); 713 if (!wakeref) 714 return; 715 716 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 717 if (!(tmp & DDI_BUF_CTL_ENABLE)) 718 goto out; 719 720 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 721 tmp = intel_de_read(dev_priv, 722 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 723 724 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 725 default: 726 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 727 fallthrough; 728 case TRANS_DDI_EDP_INPUT_A_ON: 729 case TRANS_DDI_EDP_INPUT_A_ONOFF: 730 *pipe_mask = BIT(PIPE_A); 731 break; 732 case TRANS_DDI_EDP_INPUT_B_ONOFF: 733 *pipe_mask = BIT(PIPE_B); 734 break; 735 case TRANS_DDI_EDP_INPUT_C_ONOFF: 736 *pipe_mask = BIT(PIPE_C); 737 break; 738 } 739 740 goto out; 741 } 742 743 mst_pipe_mask = 0; 744 for_each_pipe(dev_priv, p) { 745 enum transcoder cpu_transcoder = (enum transcoder)p; 746 unsigned int port_mask, ddi_select; 747 intel_wakeref_t trans_wakeref; 748 749 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 750 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 751 if (!trans_wakeref) 752 continue; 753 754 if (DISPLAY_VER(dev_priv) >= 12) { 755 port_mask = TGL_TRANS_DDI_PORT_MASK; 756 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 757 } else { 758 port_mask = TRANS_DDI_PORT_MASK; 759 ddi_select = TRANS_DDI_SELECT_PORT(port); 760 } 761 762 tmp = intel_de_read(dev_priv, 763 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 764 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 765 trans_wakeref); 766 767 if ((tmp & port_mask) != ddi_select) 768 continue; 769 770 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == 771 TRANS_DDI_MODE_SELECT_DP_MST) 772 mst_pipe_mask |= BIT(p); 773 774 *pipe_mask |= BIT(p); 775 } 776 777 if (!*pipe_mask) 778 drm_dbg_kms(&dev_priv->drm, 779 "No pipe for [ENCODER:%d:%s] found\n", 780 encoder->base.base.id, encoder->base.name); 781 782 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 783 drm_dbg_kms(&dev_priv->drm, 784 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 785 encoder->base.base.id, encoder->base.name, 786 *pipe_mask); 787 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 788 } 789 790 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 791 drm_dbg_kms(&dev_priv->drm, 792 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 793 encoder->base.base.id, encoder->base.name, 794 *pipe_mask, mst_pipe_mask); 795 else 796 *is_dp_mst = mst_pipe_mask; 797 798 out: 799 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 800 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 801 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 802 BXT_PHY_LANE_POWERDOWN_ACK | 803 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 804 drm_err(&dev_priv->drm, 805 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 806 encoder->base.base.id, encoder->base.name, tmp); 807 } 808 809 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 810 } 811 812 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 813 enum pipe *pipe) 814 { 815 u8 pipe_mask; 816 bool is_mst; 817 818 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 819 820 if (is_mst || !pipe_mask) 821 return false; 822 823 *pipe = ffs(pipe_mask) - 1; 824 825 return true; 826 } 827 828 static enum intel_display_power_domain 829 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port) 830 { 831 /* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 832 * DC states enabled at the same time, while for driver initiated AUX 833 * transfers we need the same AUX IOs to be powered but with DC states 834 * disabled. Accordingly use the AUX power domain here which leaves DC 835 * states enabled. 836 * However, for non-A AUX ports the corresponding non-EDP transcoders 837 * would have already enabled power well 2 and DC_OFF. This means we can 838 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a 839 * specific AUX_IO reference without powering up any extra wells. 840 * Note that PSR is enabled only on Port A even though this function 841 * returns the correct domain for other ports too. 842 */ 843 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A : 844 intel_aux_power_domain(dig_port); 845 } 846 847 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 848 struct intel_crtc_state *crtc_state) 849 { 850 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 851 struct intel_digital_port *dig_port; 852 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 853 854 /* 855 * TODO: Add support for MST encoders. Atm, the following should never 856 * happen since fake-MST encoders don't set their get_power_domains() 857 * hook. 858 */ 859 if (drm_WARN_ON(&dev_priv->drm, 860 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 861 return; 862 863 dig_port = enc_to_dig_port(encoder); 864 865 if (!intel_phy_is_tc(dev_priv, phy) || 866 dig_port->tc_mode != TC_PORT_TBT_ALT) { 867 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 868 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 869 dig_port->ddi_io_power_domain); 870 } 871 872 /* 873 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC 874 * ports. 875 */ 876 if (intel_crtc_has_dp_encoder(crtc_state) || 877 intel_phy_is_tc(dev_priv, phy)) { 878 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref); 879 dig_port->aux_wakeref = 880 intel_display_power_get(dev_priv, 881 intel_ddi_main_link_aux_domain(dig_port)); 882 } 883 } 884 885 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder, 886 const struct intel_crtc_state *crtc_state) 887 { 888 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 889 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 890 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 891 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 892 u32 val; 893 894 if (cpu_transcoder != TRANSCODER_EDP) { 895 if (DISPLAY_VER(dev_priv) >= 13) 896 val = TGL_TRANS_CLK_SEL_PORT(phy); 897 else if (DISPLAY_VER(dev_priv) >= 12) 898 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 899 else 900 val = TRANS_CLK_SEL_PORT(encoder->port); 901 902 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 903 } 904 } 905 906 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) 907 { 908 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 909 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 910 911 if (cpu_transcoder != TRANSCODER_EDP) { 912 if (DISPLAY_VER(dev_priv) >= 12) 913 intel_de_write(dev_priv, 914 TRANS_CLK_SEL(cpu_transcoder), 915 TGL_TRANS_CLK_SEL_DISABLED); 916 else 917 intel_de_write(dev_priv, 918 TRANS_CLK_SEL(cpu_transcoder), 919 TRANS_CLK_SEL_DISABLED); 920 } 921 } 922 923 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 924 enum port port, u8 iboost) 925 { 926 u32 tmp; 927 928 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 929 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 930 if (iboost) 931 tmp |= iboost << BALANCE_LEG_SHIFT(port); 932 else 933 tmp |= BALANCE_LEG_DISABLE(port); 934 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 935 } 936 937 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 938 const struct intel_crtc_state *crtc_state, 939 int level) 940 { 941 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 942 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 943 u8 iboost; 944 945 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 946 iboost = intel_bios_encoder_hdmi_boost_level(encoder->devdata); 947 else 948 iboost = intel_bios_encoder_dp_boost_level(encoder->devdata); 949 950 if (iboost == 0) { 951 const struct intel_ddi_buf_trans *ddi_translations; 952 int n_entries; 953 954 ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 955 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 956 return; 957 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 958 level = n_entries - 1; 959 960 iboost = ddi_translations->entries[level].hsw.i_boost; 961 } 962 963 /* Make sure that the requested I_boost is valid */ 964 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 965 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 966 return; 967 } 968 969 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 970 971 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 972 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 973 } 974 975 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, 976 const struct intel_crtc_state *crtc_state, 977 int level) 978 { 979 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 980 const struct intel_ddi_buf_trans *ddi_translations; 981 enum port port = encoder->port; 982 int n_entries; 983 984 ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 985 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 986 return; 987 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 988 level = n_entries - 1; 989 990 bxt_ddi_phy_set_signal_level(dev_priv, port, 991 ddi_translations->entries[level].bxt.margin, 992 ddi_translations->entries[level].bxt.scale, 993 ddi_translations->entries[level].bxt.enable, 994 ddi_translations->entries[level].bxt.deemphasis); 995 } 996 997 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 998 const struct intel_crtc_state *crtc_state) 999 { 1000 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1001 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1002 int n_entries; 1003 1004 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1005 1006 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1007 n_entries = 1; 1008 if (drm_WARN_ON(&dev_priv->drm, 1009 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1010 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1011 1012 return index_to_dp_signal_levels[n_entries - 1] & 1013 DP_TRAIN_VOLTAGE_SWING_MASK; 1014 } 1015 1016 /* 1017 * We assume that the full set of pre-emphasis values can be 1018 * used on all DDI platforms. Should that change we need to 1019 * rethink this code. 1020 */ 1021 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1022 { 1023 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1024 } 1025 1026 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1027 const struct intel_crtc_state *crtc_state, 1028 int level) 1029 { 1030 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1031 const struct intel_ddi_buf_trans *ddi_translations; 1032 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1033 int n_entries, ln; 1034 u32 val; 1035 1036 ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1037 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 1038 return; 1039 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1040 level = n_entries - 1; 1041 1042 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1043 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1044 1045 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1046 intel_dp->hobl_active = is_hobl_buf_trans(ddi_translations); 1047 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1048 intel_dp->hobl_active ? val : 0); 1049 } 1050 1051 /* Set PORT_TX_DW5 */ 1052 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 1053 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1054 TAP2_DISABLE | TAP3_DISABLE); 1055 val |= SCALING_MODE_SEL(0x2); 1056 val |= RTERM_SELECT(0x6); 1057 val |= TAP3_DISABLE; 1058 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1059 1060 /* Program PORT_TX_DW2 */ 1061 val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); 1062 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 1063 RCOMP_SCALAR_MASK); 1064 val |= SWING_SEL_UPPER(ddi_translations->entries[level].icl.dw2_swing_sel); 1065 val |= SWING_SEL_LOWER(ddi_translations->entries[level].icl.dw2_swing_sel); 1066 /* Program Rcomp scalar for every table entry */ 1067 val |= RCOMP_SCALAR(0x98); 1068 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val); 1069 1070 /* Program PORT_TX_DW4 */ 1071 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1072 for (ln = 0; ln <= 3; ln++) { 1073 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); 1074 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 1075 CURSOR_COEFF_MASK); 1076 val |= POST_CURSOR_1(ddi_translations->entries[level].icl.dw4_post_cursor_1); 1077 val |= POST_CURSOR_2(ddi_translations->entries[level].icl.dw4_post_cursor_2); 1078 val |= CURSOR_COEFF(ddi_translations->entries[level].icl.dw4_cursor_coeff); 1079 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); 1080 } 1081 1082 /* Program PORT_TX_DW7 */ 1083 val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy)); 1084 val &= ~N_SCALAR_MASK; 1085 val |= N_SCALAR(ddi_translations->entries[level].icl.dw7_n_scalar); 1086 intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val); 1087 } 1088 1089 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 1090 const struct intel_crtc_state *crtc_state, 1091 int level) 1092 { 1093 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1094 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1095 int width, rate, ln; 1096 u32 val; 1097 1098 width = crtc_state->lane_count; 1099 rate = crtc_state->port_clock; 1100 1101 /* 1102 * 1. If port type is eDP or DP, 1103 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1104 * else clear to 0b. 1105 */ 1106 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy)); 1107 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1108 val &= ~COMMON_KEEPER_EN; 1109 else 1110 val |= COMMON_KEEPER_EN; 1111 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1112 1113 /* 2. Program loadgen select */ 1114 /* 1115 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 1116 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1117 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1118 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1119 */ 1120 for (ln = 0; ln <= 3; ln++) { 1121 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); 1122 val &= ~LOADGEN_SELECT; 1123 1124 if ((rate <= 600000 && width == 4 && ln >= 1) || 1125 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 1126 val |= LOADGEN_SELECT; 1127 } 1128 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); 1129 } 1130 1131 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1132 val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); 1133 val |= SUS_CLOCK_CONFIG; 1134 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); 1135 1136 /* 4. Clear training enable to change swing values */ 1137 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 1138 val &= ~TX_TRAINING_EN; 1139 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1140 1141 /* 5. Program swing and de-emphasis */ 1142 icl_ddi_combo_vswing_program(encoder, crtc_state, level); 1143 1144 /* 6. Set training enable to trigger update */ 1145 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 1146 val |= TX_TRAINING_EN; 1147 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1148 } 1149 1150 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 1151 const struct intel_crtc_state *crtc_state, 1152 int level) 1153 { 1154 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1155 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1156 const struct intel_ddi_buf_trans *ddi_translations; 1157 int n_entries, ln; 1158 u32 val; 1159 1160 if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT) 1161 return; 1162 1163 ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1164 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 1165 return; 1166 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1167 level = n_entries - 1; 1168 1169 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */ 1170 for (ln = 0; ln < 2; ln++) { 1171 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port)); 1172 val &= ~CRI_USE_FS32; 1173 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val); 1174 1175 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port)); 1176 val &= ~CRI_USE_FS32; 1177 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val); 1178 } 1179 1180 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1181 for (ln = 0; ln < 2; ln++) { 1182 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port)); 1183 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 1184 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 1185 ddi_translations->entries[level].mg.cri_txdeemph_override_17_12); 1186 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val); 1187 1188 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port)); 1189 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 1190 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 1191 ddi_translations->entries[level].mg.cri_txdeemph_override_17_12); 1192 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val); 1193 } 1194 1195 /* Program MG_TX_DRVCTRL with values from vswing table */ 1196 for (ln = 0; ln < 2; ln++) { 1197 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port)); 1198 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1199 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 1200 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 1201 ddi_translations->entries[level].mg.cri_txdeemph_override_5_0) | 1202 CRI_TXDEEMPH_OVERRIDE_11_6( 1203 ddi_translations->entries[level].mg.cri_txdeemph_override_11_6) | 1204 CRI_TXDEEMPH_OVERRIDE_EN; 1205 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val); 1206 1207 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port)); 1208 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1209 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 1210 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 1211 ddi_translations->entries[level].mg.cri_txdeemph_override_5_0) | 1212 CRI_TXDEEMPH_OVERRIDE_11_6( 1213 ddi_translations->entries[level].mg.cri_txdeemph_override_11_6) | 1214 CRI_TXDEEMPH_OVERRIDE_EN; 1215 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val); 1216 1217 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1218 } 1219 1220 /* 1221 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1222 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1223 * values from table for which TX1 and TX2 enabled. 1224 */ 1225 for (ln = 0; ln < 2; ln++) { 1226 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port)); 1227 if (crtc_state->port_clock < 300000) 1228 val |= CFG_LOW_RATE_LKREN_EN; 1229 else 1230 val &= ~CFG_LOW_RATE_LKREN_EN; 1231 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val); 1232 } 1233 1234 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1235 for (ln = 0; ln < 2; ln++) { 1236 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port)); 1237 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 1238 if (crtc_state->port_clock <= 500000) { 1239 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 1240 } else { 1241 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 1242 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 1243 } 1244 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val); 1245 1246 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port)); 1247 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 1248 if (crtc_state->port_clock <= 500000) { 1249 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 1250 } else { 1251 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 1252 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 1253 } 1254 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val); 1255 } 1256 1257 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1258 for (ln = 0; ln < 2; ln++) { 1259 val = intel_de_read(dev_priv, 1260 MG_TX1_PISO_READLOAD(ln, tc_port)); 1261 val |= CRI_CALCINIT; 1262 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1263 val); 1264 1265 val = intel_de_read(dev_priv, 1266 MG_TX2_PISO_READLOAD(ln, tc_port)); 1267 val |= CRI_CALCINIT; 1268 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1269 val); 1270 } 1271 } 1272 1273 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, 1274 const struct intel_crtc_state *crtc_state, 1275 int level) 1276 { 1277 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1278 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1279 1280 if (intel_phy_is_combo(dev_priv, phy)) 1281 icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level); 1282 else 1283 icl_mg_phy_ddi_vswing_sequence(encoder, crtc_state, level); 1284 } 1285 1286 static void 1287 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 1288 const struct intel_crtc_state *crtc_state, 1289 int level) 1290 { 1291 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1292 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1293 const struct intel_ddi_buf_trans *ddi_translations; 1294 u32 val, dpcnt_mask, dpcnt_val; 1295 int n_entries, ln; 1296 1297 if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT) 1298 return; 1299 1300 ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1301 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 1302 return; 1303 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1304 level = n_entries - 1; 1305 1306 dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK | 1307 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1308 DKL_TX_VSWING_CONTROL_MASK); 1309 dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations->entries[level].dkl.dkl_vswing_control); 1310 dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations->entries[level].dkl.dkl_de_emphasis_control); 1311 dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations->entries[level].dkl.dkl_preshoot_control); 1312 1313 for (ln = 0; ln < 2; ln++) { 1314 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 1315 HIP_INDEX_VAL(tc_port, ln)); 1316 1317 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0); 1318 1319 /* All the registers are RMW */ 1320 val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port)); 1321 val &= ~dpcnt_mask; 1322 val |= dpcnt_val; 1323 intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val); 1324 1325 val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port)); 1326 val &= ~dpcnt_mask; 1327 val |= dpcnt_val; 1328 intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val); 1329 1330 val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port)); 1331 val &= ~DKL_TX_DP20BITMODE; 1332 intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val); 1333 1334 if ((intel_crtc_has_dp_encoder(crtc_state) && 1335 crtc_state->port_clock == 162000) || 1336 (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 1337 crtc_state->port_clock == 594000)) 1338 val |= DKL_TX_LOADGEN_SHARING_PMD_DISABLE; 1339 else 1340 val &= ~DKL_TX_LOADGEN_SHARING_PMD_DISABLE; 1341 } 1342 } 1343 1344 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder, 1345 const struct intel_crtc_state *crtc_state, 1346 int level) 1347 { 1348 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1349 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1350 1351 if (intel_phy_is_combo(dev_priv, phy)) 1352 icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level); 1353 else 1354 tgl_dkl_phy_ddi_vswing_sequence(encoder, crtc_state, level); 1355 } 1356 1357 static int translate_signal_level(struct intel_dp *intel_dp, 1358 u8 signal_levels) 1359 { 1360 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1361 int i; 1362 1363 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1364 if (index_to_dp_signal_levels[i] == signal_levels) 1365 return i; 1366 } 1367 1368 drm_WARN(&i915->drm, 1, 1369 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1370 signal_levels); 1371 1372 return 0; 1373 } 1374 1375 static int intel_ddi_dp_level(struct intel_dp *intel_dp) 1376 { 1377 u8 train_set = intel_dp->train_set[0]; 1378 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1379 DP_TRAIN_PRE_EMPHASIS_MASK); 1380 1381 return translate_signal_level(intel_dp, signal_levels); 1382 } 1383 1384 static void 1385 dg2_set_signal_levels(struct intel_dp *intel_dp, 1386 const struct intel_crtc_state *crtc_state) 1387 { 1388 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1389 int level = intel_ddi_dp_level(intel_dp); 1390 1391 intel_snps_phy_ddi_vswing_sequence(encoder, level); 1392 } 1393 1394 static void 1395 tgl_set_signal_levels(struct intel_dp *intel_dp, 1396 const struct intel_crtc_state *crtc_state) 1397 { 1398 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1399 int level = intel_ddi_dp_level(intel_dp); 1400 1401 tgl_ddi_vswing_sequence(encoder, crtc_state, level); 1402 } 1403 1404 static void 1405 icl_set_signal_levels(struct intel_dp *intel_dp, 1406 const struct intel_crtc_state *crtc_state) 1407 { 1408 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1409 int level = intel_ddi_dp_level(intel_dp); 1410 1411 icl_ddi_vswing_sequence(encoder, crtc_state, level); 1412 } 1413 1414 static void 1415 bxt_set_signal_levels(struct intel_dp *intel_dp, 1416 const struct intel_crtc_state *crtc_state) 1417 { 1418 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1419 int level = intel_ddi_dp_level(intel_dp); 1420 1421 bxt_ddi_vswing_sequence(encoder, crtc_state, level); 1422 } 1423 1424 static void 1425 hsw_set_signal_levels(struct intel_dp *intel_dp, 1426 const struct intel_crtc_state *crtc_state) 1427 { 1428 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1429 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1430 int level = intel_ddi_dp_level(intel_dp); 1431 enum port port = encoder->port; 1432 u32 signal_levels; 1433 1434 signal_levels = DDI_BUF_TRANS_SELECT(level); 1435 1436 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1437 signal_levels); 1438 1439 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1440 intel_dp->DP |= signal_levels; 1441 1442 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 1443 skl_ddi_set_iboost(encoder, crtc_state, level); 1444 1445 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1446 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1447 } 1448 1449 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1450 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1451 { 1452 mutex_lock(&i915->dpll.lock); 1453 1454 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1455 1456 /* 1457 * "This step and the step before must be 1458 * done with separate register writes." 1459 */ 1460 intel_de_rmw(i915, reg, clk_off, 0); 1461 1462 mutex_unlock(&i915->dpll.lock); 1463 } 1464 1465 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1466 u32 clk_off) 1467 { 1468 mutex_lock(&i915->dpll.lock); 1469 1470 intel_de_rmw(i915, reg, 0, clk_off); 1471 1472 mutex_unlock(&i915->dpll.lock); 1473 } 1474 1475 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1476 u32 clk_off) 1477 { 1478 return !(intel_de_read(i915, reg) & clk_off); 1479 } 1480 1481 static struct intel_shared_dpll * 1482 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, 1483 u32 clk_sel_mask, u32 clk_sel_shift) 1484 { 1485 enum intel_dpll_id id; 1486 1487 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; 1488 1489 return intel_get_shared_dpll_by_id(i915, id); 1490 } 1491 1492 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1493 const struct intel_crtc_state *crtc_state) 1494 { 1495 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1496 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1497 enum phy phy = intel_port_to_phy(i915, encoder->port); 1498 1499 if (drm_WARN_ON(&i915->drm, !pll)) 1500 return; 1501 1502 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1503 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1504 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1505 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1506 } 1507 1508 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1509 { 1510 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1511 enum phy phy = intel_port_to_phy(i915, encoder->port); 1512 1513 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1514 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1515 } 1516 1517 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1518 { 1519 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1520 enum phy phy = intel_port_to_phy(i915, encoder->port); 1521 1522 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1523 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1524 } 1525 1526 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1527 { 1528 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1529 enum phy phy = intel_port_to_phy(i915, encoder->port); 1530 1531 return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), 1532 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1533 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1534 } 1535 1536 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1537 const struct intel_crtc_state *crtc_state) 1538 { 1539 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1540 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1541 enum phy phy = intel_port_to_phy(i915, encoder->port); 1542 1543 if (drm_WARN_ON(&i915->drm, !pll)) 1544 return; 1545 1546 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1547 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1548 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1549 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1550 } 1551 1552 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1553 { 1554 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1555 enum phy phy = intel_port_to_phy(i915, encoder->port); 1556 1557 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1558 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1559 } 1560 1561 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1562 { 1563 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1564 enum phy phy = intel_port_to_phy(i915, encoder->port); 1565 1566 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1567 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1568 } 1569 1570 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1571 { 1572 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1573 enum phy phy = intel_port_to_phy(i915, encoder->port); 1574 1575 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1576 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1577 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1578 } 1579 1580 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1581 const struct intel_crtc_state *crtc_state) 1582 { 1583 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1584 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1585 enum phy phy = intel_port_to_phy(i915, encoder->port); 1586 1587 if (drm_WARN_ON(&i915->drm, !pll)) 1588 return; 1589 1590 /* 1591 * If we fail this, something went very wrong: first 2 PLLs should be 1592 * used by first 2 phys and last 2 PLLs by last phys 1593 */ 1594 if (drm_WARN_ON(&i915->drm, 1595 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1596 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1597 return; 1598 1599 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1600 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1601 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1602 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1603 } 1604 1605 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1606 { 1607 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1608 enum phy phy = intel_port_to_phy(i915, encoder->port); 1609 1610 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1611 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1612 } 1613 1614 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1615 { 1616 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1617 enum phy phy = intel_port_to_phy(i915, encoder->port); 1618 1619 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1620 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1621 } 1622 1623 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1624 { 1625 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1626 enum phy phy = intel_port_to_phy(i915, encoder->port); 1627 enum intel_dpll_id id; 1628 u32 val; 1629 1630 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)); 1631 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1632 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1633 id = val; 1634 1635 /* 1636 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1637 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1638 * bit for phy C and D. 1639 */ 1640 if (phy >= PHY_C) 1641 id += DPLL_ID_DG1_DPLL2; 1642 1643 return intel_get_shared_dpll_by_id(i915, id); 1644 } 1645 1646 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1647 const struct intel_crtc_state *crtc_state) 1648 { 1649 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1650 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1651 enum phy phy = intel_port_to_phy(i915, encoder->port); 1652 1653 if (drm_WARN_ON(&i915->drm, !pll)) 1654 return; 1655 1656 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1657 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1658 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1659 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1660 } 1661 1662 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1663 { 1664 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1665 enum phy phy = intel_port_to_phy(i915, encoder->port); 1666 1667 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1668 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1669 } 1670 1671 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1672 { 1673 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1674 enum phy phy = intel_port_to_phy(i915, encoder->port); 1675 1676 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1677 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1678 } 1679 1680 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1681 { 1682 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1683 enum phy phy = intel_port_to_phy(i915, encoder->port); 1684 1685 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1686 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1687 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1688 } 1689 1690 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1691 const struct intel_crtc_state *crtc_state) 1692 { 1693 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1694 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1695 enum port port = encoder->port; 1696 1697 if (drm_WARN_ON(&i915->drm, !pll)) 1698 return; 1699 1700 /* 1701 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1702 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1703 */ 1704 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1705 1706 icl_ddi_combo_enable_clock(encoder, crtc_state); 1707 } 1708 1709 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1710 { 1711 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1712 enum port port = encoder->port; 1713 1714 icl_ddi_combo_disable_clock(encoder); 1715 1716 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1717 } 1718 1719 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1720 { 1721 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1722 enum port port = encoder->port; 1723 u32 tmp; 1724 1725 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1726 1727 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1728 return false; 1729 1730 return icl_ddi_combo_is_clock_enabled(encoder); 1731 } 1732 1733 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1734 const struct intel_crtc_state *crtc_state) 1735 { 1736 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1737 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1738 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1739 enum port port = encoder->port; 1740 1741 if (drm_WARN_ON(&i915->drm, !pll)) 1742 return; 1743 1744 intel_de_write(i915, DDI_CLK_SEL(port), 1745 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1746 1747 mutex_lock(&i915->dpll.lock); 1748 1749 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1750 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1751 1752 mutex_unlock(&i915->dpll.lock); 1753 } 1754 1755 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1756 { 1757 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1758 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1759 enum port port = encoder->port; 1760 1761 mutex_lock(&i915->dpll.lock); 1762 1763 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1764 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1765 1766 mutex_unlock(&i915->dpll.lock); 1767 1768 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1769 } 1770 1771 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1772 { 1773 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1774 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1775 enum port port = encoder->port; 1776 u32 tmp; 1777 1778 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1779 1780 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1781 return false; 1782 1783 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1784 1785 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1786 } 1787 1788 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1789 { 1790 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1791 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1792 enum port port = encoder->port; 1793 enum intel_dpll_id id; 1794 u32 tmp; 1795 1796 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1797 1798 switch (tmp & DDI_CLK_SEL_MASK) { 1799 case DDI_CLK_SEL_TBT_162: 1800 case DDI_CLK_SEL_TBT_270: 1801 case DDI_CLK_SEL_TBT_540: 1802 case DDI_CLK_SEL_TBT_810: 1803 id = DPLL_ID_ICL_TBTPLL; 1804 break; 1805 case DDI_CLK_SEL_MG: 1806 id = icl_tc_port_to_pll_id(tc_port); 1807 break; 1808 default: 1809 MISSING_CASE(tmp); 1810 fallthrough; 1811 case DDI_CLK_SEL_NONE: 1812 return NULL; 1813 } 1814 1815 return intel_get_shared_dpll_by_id(i915, id); 1816 } 1817 1818 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1819 { 1820 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1821 enum intel_dpll_id id; 1822 1823 switch (encoder->port) { 1824 case PORT_A: 1825 id = DPLL_ID_SKL_DPLL0; 1826 break; 1827 case PORT_B: 1828 id = DPLL_ID_SKL_DPLL1; 1829 break; 1830 case PORT_C: 1831 id = DPLL_ID_SKL_DPLL2; 1832 break; 1833 default: 1834 MISSING_CASE(encoder->port); 1835 return NULL; 1836 } 1837 1838 return intel_get_shared_dpll_by_id(i915, id); 1839 } 1840 1841 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1842 const struct intel_crtc_state *crtc_state) 1843 { 1844 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1845 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1846 enum port port = encoder->port; 1847 1848 if (drm_WARN_ON(&i915->drm, !pll)) 1849 return; 1850 1851 mutex_lock(&i915->dpll.lock); 1852 1853 intel_de_rmw(i915, DPLL_CTRL2, 1854 DPLL_CTRL2_DDI_CLK_OFF(port) | 1855 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1856 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1857 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1858 1859 mutex_unlock(&i915->dpll.lock); 1860 } 1861 1862 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1863 { 1864 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1865 enum port port = encoder->port; 1866 1867 mutex_lock(&i915->dpll.lock); 1868 1869 intel_de_rmw(i915, DPLL_CTRL2, 1870 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1871 1872 mutex_unlock(&i915->dpll.lock); 1873 } 1874 1875 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1876 { 1877 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1878 enum port port = encoder->port; 1879 1880 /* 1881 * FIXME Not sure if the override affects both 1882 * the PLL selection and the CLK_OFF bit. 1883 */ 1884 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1885 } 1886 1887 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1888 { 1889 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1890 enum port port = encoder->port; 1891 enum intel_dpll_id id; 1892 u32 tmp; 1893 1894 tmp = intel_de_read(i915, DPLL_CTRL2); 1895 1896 /* 1897 * FIXME Not sure if the override affects both 1898 * the PLL selection and the CLK_OFF bit. 1899 */ 1900 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1901 return NULL; 1902 1903 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1904 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1905 1906 return intel_get_shared_dpll_by_id(i915, id); 1907 } 1908 1909 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 1910 const struct intel_crtc_state *crtc_state) 1911 { 1912 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1913 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1914 enum port port = encoder->port; 1915 1916 if (drm_WARN_ON(&i915->drm, !pll)) 1917 return; 1918 1919 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 1920 } 1921 1922 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 1923 { 1924 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1925 enum port port = encoder->port; 1926 1927 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1928 } 1929 1930 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 1931 { 1932 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1933 enum port port = encoder->port; 1934 1935 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 1936 } 1937 1938 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 1939 { 1940 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1941 enum port port = encoder->port; 1942 enum intel_dpll_id id; 1943 u32 tmp; 1944 1945 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); 1946 1947 switch (tmp & PORT_CLK_SEL_MASK) { 1948 case PORT_CLK_SEL_WRPLL1: 1949 id = DPLL_ID_WRPLL1; 1950 break; 1951 case PORT_CLK_SEL_WRPLL2: 1952 id = DPLL_ID_WRPLL2; 1953 break; 1954 case PORT_CLK_SEL_SPLL: 1955 id = DPLL_ID_SPLL; 1956 break; 1957 case PORT_CLK_SEL_LCPLL_810: 1958 id = DPLL_ID_LCPLL_810; 1959 break; 1960 case PORT_CLK_SEL_LCPLL_1350: 1961 id = DPLL_ID_LCPLL_1350; 1962 break; 1963 case PORT_CLK_SEL_LCPLL_2700: 1964 id = DPLL_ID_LCPLL_2700; 1965 break; 1966 default: 1967 MISSING_CASE(tmp); 1968 fallthrough; 1969 case PORT_CLK_SEL_NONE: 1970 return NULL; 1971 } 1972 1973 return intel_get_shared_dpll_by_id(i915, id); 1974 } 1975 1976 void intel_ddi_enable_clock(struct intel_encoder *encoder, 1977 const struct intel_crtc_state *crtc_state) 1978 { 1979 if (encoder->enable_clock) 1980 encoder->enable_clock(encoder, crtc_state); 1981 } 1982 1983 static void intel_ddi_disable_clock(struct intel_encoder *encoder) 1984 { 1985 if (encoder->disable_clock) 1986 encoder->disable_clock(encoder); 1987 } 1988 1989 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 1990 { 1991 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1992 u32 port_mask; 1993 bool ddi_clk_needed; 1994 1995 /* 1996 * In case of DP MST, we sanitize the primary encoder only, not the 1997 * virtual ones. 1998 */ 1999 if (encoder->type == INTEL_OUTPUT_DP_MST) 2000 return; 2001 2002 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2003 u8 pipe_mask; 2004 bool is_mst; 2005 2006 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2007 /* 2008 * In the unlikely case that BIOS enables DP in MST mode, just 2009 * warn since our MST HW readout is incomplete. 2010 */ 2011 if (drm_WARN_ON(&i915->drm, is_mst)) 2012 return; 2013 } 2014 2015 port_mask = BIT(encoder->port); 2016 ddi_clk_needed = encoder->base.crtc; 2017 2018 if (encoder->type == INTEL_OUTPUT_DSI) { 2019 struct intel_encoder *other_encoder; 2020 2021 port_mask = intel_dsi_encoder_ports(encoder); 2022 /* 2023 * Sanity check that we haven't incorrectly registered another 2024 * encoder using any of the ports of this DSI encoder. 2025 */ 2026 for_each_intel_encoder(&i915->drm, other_encoder) { 2027 if (other_encoder == encoder) 2028 continue; 2029 2030 if (drm_WARN_ON(&i915->drm, 2031 port_mask & BIT(other_encoder->port))) 2032 return; 2033 } 2034 /* 2035 * For DSI we keep the ddi clocks gated 2036 * except during enable/disable sequence. 2037 */ 2038 ddi_clk_needed = false; 2039 } 2040 2041 if (ddi_clk_needed || !encoder->is_clock_enabled || 2042 !encoder->is_clock_enabled(encoder)) 2043 return; 2044 2045 drm_notice(&i915->drm, 2046 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2047 encoder->base.base.id, encoder->base.name); 2048 2049 encoder->disable_clock(encoder); 2050 } 2051 2052 static void 2053 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2054 const struct intel_crtc_state *crtc_state) 2055 { 2056 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2057 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); 2058 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 2059 u32 ln0, ln1, pin_assignment; 2060 u8 width; 2061 2062 if (!intel_phy_is_tc(dev_priv, phy) || 2063 dig_port->tc_mode == TC_PORT_TBT_ALT) 2064 return; 2065 2066 if (DISPLAY_VER(dev_priv) >= 12) { 2067 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2068 HIP_INDEX_VAL(tc_port, 0x0)); 2069 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 2070 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2071 HIP_INDEX_VAL(tc_port, 0x1)); 2072 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 2073 } else { 2074 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2075 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2076 } 2077 2078 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2079 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2080 2081 /* DPPATC */ 2082 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2083 width = crtc_state->lane_count; 2084 2085 switch (pin_assignment) { 2086 case 0x0: 2087 drm_WARN_ON(&dev_priv->drm, 2088 dig_port->tc_mode != TC_PORT_LEGACY); 2089 if (width == 1) { 2090 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2091 } else { 2092 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2093 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2094 } 2095 break; 2096 case 0x1: 2097 if (width == 4) { 2098 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2099 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2100 } 2101 break; 2102 case 0x2: 2103 if (width == 2) { 2104 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2105 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2106 } 2107 break; 2108 case 0x3: 2109 case 0x5: 2110 if (width == 1) { 2111 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2112 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2113 } else { 2114 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2115 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2116 } 2117 break; 2118 case 0x4: 2119 case 0x6: 2120 if (width == 1) { 2121 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2122 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2123 } else { 2124 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2125 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2126 } 2127 break; 2128 default: 2129 MISSING_CASE(pin_assignment); 2130 } 2131 2132 if (DISPLAY_VER(dev_priv) >= 12) { 2133 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2134 HIP_INDEX_VAL(tc_port, 0x0)); 2135 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0); 2136 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2137 HIP_INDEX_VAL(tc_port, 0x1)); 2138 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1); 2139 } else { 2140 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2141 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2142 } 2143 } 2144 2145 static enum transcoder 2146 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2147 { 2148 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2149 return crtc_state->mst_master_transcoder; 2150 else 2151 return crtc_state->cpu_transcoder; 2152 } 2153 2154 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2155 const struct intel_crtc_state *crtc_state) 2156 { 2157 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2158 2159 if (DISPLAY_VER(dev_priv) >= 12) 2160 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state)); 2161 else 2162 return DP_TP_CTL(encoder->port); 2163 } 2164 2165 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2166 const struct intel_crtc_state *crtc_state) 2167 { 2168 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2169 2170 if (DISPLAY_VER(dev_priv) >= 12) 2171 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state)); 2172 else 2173 return DP_TP_STATUS(encoder->port); 2174 } 2175 2176 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2177 const struct intel_crtc_state *crtc_state, 2178 bool enable) 2179 { 2180 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2181 2182 if (!crtc_state->vrr.enable) 2183 return; 2184 2185 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2186 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2187 drm_dbg_kms(&i915->drm, 2188 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2189 enabledisable(enable)); 2190 } 2191 2192 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2193 const struct intel_crtc_state *crtc_state) 2194 { 2195 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2196 2197 if (!crtc_state->fec_enable) 2198 return; 2199 2200 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) 2201 drm_dbg_kms(&i915->drm, 2202 "Failed to set FEC_READY in the sink\n"); 2203 } 2204 2205 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2206 const struct intel_crtc_state *crtc_state) 2207 { 2208 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2209 struct intel_dp *intel_dp; 2210 u32 val; 2211 2212 if (!crtc_state->fec_enable) 2213 return; 2214 2215 intel_dp = enc_to_intel_dp(encoder); 2216 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2217 val |= DP_TP_CTL_FEC_ENABLE; 2218 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2219 } 2220 2221 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 2222 const struct intel_crtc_state *crtc_state) 2223 { 2224 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2225 struct intel_dp *intel_dp; 2226 u32 val; 2227 2228 if (!crtc_state->fec_enable) 2229 return; 2230 2231 intel_dp = enc_to_intel_dp(encoder); 2232 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2233 val &= ~DP_TP_CTL_FEC_ENABLE; 2234 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2235 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2236 } 2237 2238 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2239 const struct intel_crtc_state *crtc_state) 2240 { 2241 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2242 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2243 enum phy phy = intel_port_to_phy(i915, encoder->port); 2244 2245 if (intel_phy_is_combo(i915, phy)) { 2246 bool lane_reversal = 2247 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 2248 2249 intel_combo_phy_power_up_lanes(i915, phy, false, 2250 crtc_state->lane_count, 2251 lane_reversal); 2252 } 2253 } 2254 2255 /* Splitter enable for eDP MSO is limited to certain pipes. */ 2256 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) 2257 { 2258 if (IS_ALDERLAKE_P(i915)) 2259 return BIT(PIPE_A) | BIT(PIPE_B); 2260 else 2261 return BIT(PIPE_A); 2262 } 2263 2264 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2265 struct intel_crtc_state *pipe_config) 2266 { 2267 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2268 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2269 enum pipe pipe = crtc->pipe; 2270 u32 dss1; 2271 2272 if (!HAS_MSO(i915)) 2273 return; 2274 2275 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2276 2277 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2278 if (!pipe_config->splitter.enable) 2279 return; 2280 2281 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { 2282 pipe_config->splitter.enable = false; 2283 return; 2284 } 2285 2286 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2287 default: 2288 drm_WARN(&i915->drm, true, 2289 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2290 fallthrough; 2291 case SPLITTER_CONFIGURATION_2_SEGMENT: 2292 pipe_config->splitter.link_count = 2; 2293 break; 2294 case SPLITTER_CONFIGURATION_4_SEGMENT: 2295 pipe_config->splitter.link_count = 4; 2296 break; 2297 } 2298 2299 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2300 } 2301 2302 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2303 { 2304 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2305 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2306 enum pipe pipe = crtc->pipe; 2307 u32 dss1 = 0; 2308 2309 if (!HAS_MSO(i915)) 2310 return; 2311 2312 if (crtc_state->splitter.enable) { 2313 dss1 |= SPLITTER_ENABLE; 2314 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2315 if (crtc_state->splitter.link_count == 2) 2316 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2317 else 2318 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2319 } 2320 2321 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2322 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2323 OVERLAP_PIXELS_MASK, dss1); 2324 } 2325 2326 static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state, 2327 struct intel_encoder *encoder, 2328 const struct intel_crtc_state *crtc_state, 2329 const struct drm_connector_state *conn_state) 2330 { 2331 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2332 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2333 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2334 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2335 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2336 int level = intel_ddi_dp_level(intel_dp); 2337 2338 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, 2339 crtc_state->lane_count); 2340 2341 /* 2342 * 1. Enable Power Wells 2343 * 2344 * This was handled at the beginning of intel_atomic_commit_tail(), 2345 * before we called down into this function. 2346 */ 2347 2348 /* 2. Enable Panel Power if PPS is required */ 2349 intel_pps_on(intel_dp); 2350 2351 /* 2352 * 3. Enable the port PLL. 2353 */ 2354 intel_ddi_enable_clock(encoder, crtc_state); 2355 2356 /* 4. Enable IO power */ 2357 if (!intel_phy_is_tc(dev_priv, phy) || 2358 dig_port->tc_mode != TC_PORT_TBT_ALT) 2359 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2360 dig_port->ddi_io_power_domain); 2361 2362 /* 2363 * 5. The rest of the below are substeps under the bspec's "Enable and 2364 * Train Display Port" step. Note that steps that are specific to 2365 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2366 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2367 * us when active_mst_links==0, so any steps designated for "single 2368 * stream or multi-stream master transcoder" can just be performed 2369 * unconditionally here. 2370 */ 2371 2372 /* 2373 * 5.a Configure Transcoder Clock Select to direct the Port clock to the 2374 * Transcoder. 2375 */ 2376 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2377 2378 /* 5.b Not relevant to i915 for now */ 2379 2380 /* 2381 * 5.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2382 * Transport Select 2383 */ 2384 intel_ddi_config_transcoder_func(encoder, crtc_state); 2385 2386 /* 2387 * 5.d Configure & enable DP_TP_CTL with link training pattern 1 2388 * selected 2389 * 2390 * This will be handled by the intel_dp_start_link_train() farther 2391 * down this function. 2392 */ 2393 2394 /* 5.e Configure voltage swing and related IO settings */ 2395 intel_snps_phy_ddi_vswing_sequence(encoder, level); 2396 2397 /* 2398 * 5.f Configure and enable DDI_BUF_CTL 2399 * 5.g Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout 2400 * after 1200 us. 2401 * 2402 * We only configure what the register value will be here. Actual 2403 * enabling happens during link training farther down. 2404 */ 2405 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2406 2407 if (!is_mst) 2408 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2409 2410 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 2411 /* 2412 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2413 * in the FEC_CONFIGURATION register to 1 before initiating link 2414 * training 2415 */ 2416 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2417 2418 /* 2419 * 5.h Follow DisplayPort specification training sequence (see notes for 2420 * failure handling) 2421 * 5.i If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2422 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2423 * (timeout after 800 us) 2424 */ 2425 intel_dp_start_link_train(intel_dp, crtc_state); 2426 2427 /* 5.j Set DP_TP_CTL link training to Normal */ 2428 if (!is_trans_port_sync_mode(crtc_state)) 2429 intel_dp_stop_link_train(intel_dp, crtc_state); 2430 2431 /* 5.k Configure and enable FEC if needed */ 2432 intel_ddi_enable_fec(encoder, crtc_state); 2433 intel_dsc_enable(encoder, crtc_state); 2434 } 2435 2436 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2437 struct intel_encoder *encoder, 2438 const struct intel_crtc_state *crtc_state, 2439 const struct drm_connector_state *conn_state) 2440 { 2441 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2442 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2443 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2444 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2445 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2446 int level = intel_ddi_dp_level(intel_dp); 2447 2448 intel_dp_set_link_params(intel_dp, 2449 crtc_state->port_clock, 2450 crtc_state->lane_count); 2451 2452 /* 2453 * 1. Enable Power Wells 2454 * 2455 * This was handled at the beginning of intel_atomic_commit_tail(), 2456 * before we called down into this function. 2457 */ 2458 2459 /* 2. Enable Panel Power if PPS is required */ 2460 intel_pps_on(intel_dp); 2461 2462 /* 2463 * 3. For non-TBT Type-C ports, set FIA lane count 2464 * (DFLEXDPSP.DPX4TXLATC) 2465 * 2466 * This was done before tgl_ddi_pre_enable_dp by 2467 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2468 */ 2469 2470 /* 2471 * 4. Enable the port PLL. 2472 * 2473 * The PLL enabling itself was already done before this function by 2474 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2475 * configure the PLL to port mapping here. 2476 */ 2477 intel_ddi_enable_clock(encoder, crtc_state); 2478 2479 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2480 if (!intel_phy_is_tc(dev_priv, phy) || 2481 dig_port->tc_mode != TC_PORT_TBT_ALT) { 2482 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2483 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2484 dig_port->ddi_io_power_domain); 2485 } 2486 2487 /* 6. Program DP_MODE */ 2488 icl_program_mg_dp_mode(dig_port, crtc_state); 2489 2490 /* 2491 * 7. The rest of the below are substeps under the bspec's "Enable and 2492 * Train Display Port" step. Note that steps that are specific to 2493 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2494 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2495 * us when active_mst_links==0, so any steps designated for "single 2496 * stream or multi-stream master transcoder" can just be performed 2497 * unconditionally here. 2498 */ 2499 2500 /* 2501 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2502 * Transcoder. 2503 */ 2504 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2505 2506 /* 2507 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2508 * Transport Select 2509 */ 2510 intel_ddi_config_transcoder_func(encoder, crtc_state); 2511 2512 /* 2513 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2514 * selected 2515 * 2516 * This will be handled by the intel_dp_start_link_train() farther 2517 * down this function. 2518 */ 2519 2520 /* 7.e Configure voltage swing and related IO settings */ 2521 tgl_ddi_vswing_sequence(encoder, crtc_state, level); 2522 2523 /* 2524 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2525 * the used lanes of the DDI. 2526 */ 2527 intel_ddi_power_up_lanes(encoder, crtc_state); 2528 2529 /* 2530 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2531 */ 2532 intel_ddi_mso_configure(crtc_state); 2533 2534 /* 2535 * 7.g Configure and enable DDI_BUF_CTL 2536 * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout 2537 * after 500 us. 2538 * 2539 * We only configure what the register value will be here. Actual 2540 * enabling happens during link training farther down. 2541 */ 2542 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2543 2544 if (!is_mst) 2545 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2546 2547 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2548 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 2549 /* 2550 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2551 * in the FEC_CONFIGURATION register to 1 before initiating link 2552 * training 2553 */ 2554 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2555 2556 intel_dp_check_frl_training(intel_dp); 2557 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2558 2559 /* 2560 * 7.i Follow DisplayPort specification training sequence (see notes for 2561 * failure handling) 2562 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2563 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2564 * (timeout after 800 us) 2565 */ 2566 intel_dp_start_link_train(intel_dp, crtc_state); 2567 2568 /* 7.k Set DP_TP_CTL link training to Normal */ 2569 if (!is_trans_port_sync_mode(crtc_state)) 2570 intel_dp_stop_link_train(intel_dp, crtc_state); 2571 2572 /* 7.l Configure and enable FEC if needed */ 2573 intel_ddi_enable_fec(encoder, crtc_state); 2574 if (!crtc_state->bigjoiner) 2575 intel_dsc_enable(encoder, crtc_state); 2576 } 2577 2578 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2579 struct intel_encoder *encoder, 2580 const struct intel_crtc_state *crtc_state, 2581 const struct drm_connector_state *conn_state) 2582 { 2583 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2584 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2585 enum port port = encoder->port; 2586 enum phy phy = intel_port_to_phy(dev_priv, port); 2587 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2588 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2589 int level = intel_ddi_dp_level(intel_dp); 2590 2591 if (DISPLAY_VER(dev_priv) < 11) 2592 drm_WARN_ON(&dev_priv->drm, 2593 is_mst && (port == PORT_A || port == PORT_E)); 2594 else 2595 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2596 2597 intel_dp_set_link_params(intel_dp, 2598 crtc_state->port_clock, 2599 crtc_state->lane_count); 2600 2601 intel_pps_on(intel_dp); 2602 2603 intel_ddi_enable_clock(encoder, crtc_state); 2604 2605 if (!intel_phy_is_tc(dev_priv, phy) || 2606 dig_port->tc_mode != TC_PORT_TBT_ALT) { 2607 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2608 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2609 dig_port->ddi_io_power_domain); 2610 } 2611 2612 icl_program_mg_dp_mode(dig_port, crtc_state); 2613 2614 if (DISPLAY_VER(dev_priv) >= 11) 2615 icl_ddi_vswing_sequence(encoder, crtc_state, level); 2616 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 2617 bxt_ddi_vswing_sequence(encoder, crtc_state, level); 2618 else 2619 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2620 2621 intel_ddi_power_up_lanes(encoder, crtc_state); 2622 2623 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2624 if (!is_mst) 2625 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2626 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2627 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, 2628 true); 2629 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2630 intel_dp_start_link_train(intel_dp, crtc_state); 2631 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2632 !is_trans_port_sync_mode(crtc_state)) 2633 intel_dp_stop_link_train(intel_dp, crtc_state); 2634 2635 intel_ddi_enable_fec(encoder, crtc_state); 2636 2637 if (!is_mst) 2638 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2639 2640 if (!crtc_state->bigjoiner) 2641 intel_dsc_enable(encoder, crtc_state); 2642 } 2643 2644 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2645 struct intel_encoder *encoder, 2646 const struct intel_crtc_state *crtc_state, 2647 const struct drm_connector_state *conn_state) 2648 { 2649 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2650 2651 if (IS_DG2(dev_priv)) 2652 dg2_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2653 else if (DISPLAY_VER(dev_priv) >= 12) 2654 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2655 else 2656 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2657 2658 /* MST will call a setting of MSA after an allocating of Virtual Channel 2659 * from MST encoder pre_enable callback. 2660 */ 2661 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 2662 intel_ddi_set_dp_msa(crtc_state, conn_state); 2663 2664 intel_dp_set_m_n(crtc_state, M1_N1); 2665 } 2666 } 2667 2668 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2669 struct intel_encoder *encoder, 2670 const struct intel_crtc_state *crtc_state, 2671 const struct drm_connector_state *conn_state) 2672 { 2673 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2674 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2675 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2676 2677 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2678 intel_ddi_enable_clock(encoder, crtc_state); 2679 2680 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2681 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2682 dig_port->ddi_io_power_domain); 2683 2684 icl_program_mg_dp_mode(dig_port, crtc_state); 2685 2686 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2687 2688 dig_port->set_infoframes(encoder, 2689 crtc_state->has_infoframe, 2690 crtc_state, conn_state); 2691 } 2692 2693 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2694 struct intel_encoder *encoder, 2695 const struct intel_crtc_state *crtc_state, 2696 const struct drm_connector_state *conn_state) 2697 { 2698 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2699 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2700 enum pipe pipe = crtc->pipe; 2701 2702 /* 2703 * When called from DP MST code: 2704 * - conn_state will be NULL 2705 * - encoder will be the main encoder (ie. mst->primary) 2706 * - the main connector associated with this port 2707 * won't be active or linked to a crtc 2708 * - crtc_state will be the state of the first stream to 2709 * be activated on this port, and it may not be the same 2710 * stream that will be deactivated last, but each stream 2711 * should have a state that is identical when it comes to 2712 * the DP link parameteres 2713 */ 2714 2715 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 2716 2717 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2718 2719 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2720 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 2721 conn_state); 2722 } else { 2723 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2724 2725 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 2726 conn_state); 2727 2728 /* FIXME precompute everything properly */ 2729 /* FIXME how do we turn infoframes off again? */ 2730 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 2731 dig_port->set_infoframes(encoder, 2732 crtc_state->has_infoframe, 2733 crtc_state, conn_state); 2734 } 2735 } 2736 2737 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 2738 const struct intel_crtc_state *crtc_state) 2739 { 2740 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2741 enum port port = encoder->port; 2742 bool wait = false; 2743 u32 val; 2744 2745 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2746 if (val & DDI_BUF_CTL_ENABLE) { 2747 val &= ~DDI_BUF_CTL_ENABLE; 2748 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2749 wait = true; 2750 } 2751 2752 if (intel_crtc_has_dp_encoder(crtc_state)) { 2753 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2754 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 2755 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 2756 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2757 } 2758 2759 /* Disable FEC in DP Sink */ 2760 intel_ddi_disable_fec_state(encoder, crtc_state); 2761 2762 if (wait) 2763 intel_wait_ddi_buf_idle(dev_priv, port); 2764 } 2765 2766 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 2767 struct intel_encoder *encoder, 2768 const struct intel_crtc_state *old_crtc_state, 2769 const struct drm_connector_state *old_conn_state) 2770 { 2771 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2772 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2773 struct intel_dp *intel_dp = &dig_port->dp; 2774 bool is_mst = intel_crtc_has_type(old_crtc_state, 2775 INTEL_OUTPUT_DP_MST); 2776 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2777 2778 if (!is_mst) 2779 intel_dp_set_infoframes(encoder, false, 2780 old_crtc_state, old_conn_state); 2781 2782 /* 2783 * Power down sink before disabling the port, otherwise we end 2784 * up getting interrupts from the sink on detecting link loss. 2785 */ 2786 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 2787 2788 if (DISPLAY_VER(dev_priv) >= 12) { 2789 if (is_mst) { 2790 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 2791 u32 val; 2792 2793 val = intel_de_read(dev_priv, 2794 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2795 val &= ~(TGL_TRANS_DDI_PORT_MASK | 2796 TRANS_DDI_MODE_SELECT_MASK); 2797 intel_de_write(dev_priv, 2798 TRANS_DDI_FUNC_CTL(cpu_transcoder), 2799 val); 2800 } 2801 } else { 2802 if (!is_mst) 2803 intel_ddi_disable_pipe_clock(old_crtc_state); 2804 } 2805 2806 intel_disable_ddi_buf(encoder, old_crtc_state); 2807 2808 /* 2809 * From TGL spec: "If single stream or multi-stream master transcoder: 2810 * Configure Transcoder Clock select to direct no clock to the 2811 * transcoder" 2812 */ 2813 if (DISPLAY_VER(dev_priv) >= 12) 2814 intel_ddi_disable_pipe_clock(old_crtc_state); 2815 2816 intel_pps_vdd_on(intel_dp); 2817 intel_pps_off(intel_dp); 2818 2819 if (!intel_phy_is_tc(dev_priv, phy) || 2820 dig_port->tc_mode != TC_PORT_TBT_ALT) 2821 intel_display_power_put(dev_priv, 2822 dig_port->ddi_io_power_domain, 2823 fetch_and_zero(&dig_port->ddi_io_wakeref)); 2824 2825 intel_ddi_disable_clock(encoder); 2826 } 2827 2828 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 2829 struct intel_encoder *encoder, 2830 const struct intel_crtc_state *old_crtc_state, 2831 const struct drm_connector_state *old_conn_state) 2832 { 2833 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2834 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2835 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2836 2837 dig_port->set_infoframes(encoder, false, 2838 old_crtc_state, old_conn_state); 2839 2840 intel_ddi_disable_pipe_clock(old_crtc_state); 2841 2842 intel_disable_ddi_buf(encoder, old_crtc_state); 2843 2844 intel_display_power_put(dev_priv, 2845 dig_port->ddi_io_power_domain, 2846 fetch_and_zero(&dig_port->ddi_io_wakeref)); 2847 2848 intel_ddi_disable_clock(encoder); 2849 2850 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 2851 } 2852 2853 static void intel_ddi_post_disable(struct intel_atomic_state *state, 2854 struct intel_encoder *encoder, 2855 const struct intel_crtc_state *old_crtc_state, 2856 const struct drm_connector_state *old_conn_state) 2857 { 2858 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2859 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2860 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2861 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 2862 2863 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { 2864 intel_crtc_vblank_off(old_crtc_state); 2865 2866 intel_disable_pipe(old_crtc_state); 2867 2868 intel_vrr_disable(old_crtc_state); 2869 2870 intel_ddi_disable_transcoder_func(old_crtc_state); 2871 2872 intel_dsc_disable(old_crtc_state); 2873 2874 if (DISPLAY_VER(dev_priv) >= 9) 2875 skl_scaler_disable(old_crtc_state); 2876 else 2877 ilk_pfit_disable(old_crtc_state); 2878 } 2879 2880 if (old_crtc_state->bigjoiner_linked_crtc) { 2881 struct intel_atomic_state *state = 2882 to_intel_atomic_state(old_crtc_state->uapi.state); 2883 struct intel_crtc *slave = 2884 old_crtc_state->bigjoiner_linked_crtc; 2885 const struct intel_crtc_state *old_slave_crtc_state = 2886 intel_atomic_get_old_crtc_state(state, slave); 2887 2888 intel_crtc_vblank_off(old_slave_crtc_state); 2889 2890 intel_dsc_disable(old_slave_crtc_state); 2891 skl_scaler_disable(old_slave_crtc_state); 2892 } 2893 2894 /* 2895 * When called from DP MST code: 2896 * - old_conn_state will be NULL 2897 * - encoder will be the main encoder (ie. mst->primary) 2898 * - the main connector associated with this port 2899 * won't be active or linked to a crtc 2900 * - old_crtc_state will be the state of the last stream to 2901 * be deactivated on this port, and it may not be the same 2902 * stream that was activated last, but each stream 2903 * should have a state that is identical when it comes to 2904 * the DP link parameteres 2905 */ 2906 2907 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 2908 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 2909 old_conn_state); 2910 else 2911 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 2912 old_conn_state); 2913 2914 if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port) 2915 intel_display_power_put(dev_priv, 2916 intel_ddi_main_link_aux_domain(dig_port), 2917 fetch_and_zero(&dig_port->aux_wakeref)); 2918 2919 if (is_tc_port) 2920 intel_tc_port_put_link(dig_port); 2921 } 2922 2923 void intel_ddi_fdi_post_disable(struct intel_atomic_state *state, 2924 struct intel_encoder *encoder, 2925 const struct intel_crtc_state *old_crtc_state, 2926 const struct drm_connector_state *old_conn_state) 2927 { 2928 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2929 u32 val; 2930 2931 /* 2932 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) 2933 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN, 2934 * step 13 is the correct place for it. Step 18 is where it was 2935 * originally before the BUN. 2936 */ 2937 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 2938 val &= ~FDI_RX_ENABLE; 2939 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 2940 2941 intel_disable_ddi_buf(encoder, old_crtc_state); 2942 intel_ddi_disable_clock(encoder); 2943 2944 val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 2945 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 2946 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 2947 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val); 2948 2949 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 2950 val &= ~FDI_PCDCLK; 2951 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 2952 2953 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 2954 val &= ~FDI_RX_PLL_ENABLE; 2955 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 2956 } 2957 2958 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 2959 struct intel_encoder *encoder, 2960 const struct intel_crtc_state *crtc_state) 2961 { 2962 const struct drm_connector_state *conn_state; 2963 struct drm_connector *conn; 2964 int i; 2965 2966 if (!crtc_state->sync_mode_slaves_mask) 2967 return; 2968 2969 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 2970 struct intel_encoder *slave_encoder = 2971 to_intel_encoder(conn_state->best_encoder); 2972 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 2973 const struct intel_crtc_state *slave_crtc_state; 2974 2975 if (!slave_crtc) 2976 continue; 2977 2978 slave_crtc_state = 2979 intel_atomic_get_new_crtc_state(state, slave_crtc); 2980 2981 if (slave_crtc_state->master_transcoder != 2982 crtc_state->cpu_transcoder) 2983 continue; 2984 2985 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 2986 slave_crtc_state); 2987 } 2988 2989 usleep_range(200, 400); 2990 2991 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 2992 crtc_state); 2993 } 2994 2995 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 2996 struct intel_encoder *encoder, 2997 const struct intel_crtc_state *crtc_state, 2998 const struct drm_connector_state *conn_state) 2999 { 3000 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3001 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3002 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3003 enum port port = encoder->port; 3004 3005 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 3006 intel_dp_stop_link_train(intel_dp, crtc_state); 3007 3008 intel_edp_backlight_on(crtc_state, conn_state); 3009 intel_psr_enable(intel_dp, crtc_state, conn_state); 3010 3011 if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink) 3012 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3013 3014 intel_edp_drrs_enable(intel_dp, crtc_state); 3015 3016 if (crtc_state->has_audio) 3017 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3018 3019 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3020 } 3021 3022 static i915_reg_t 3023 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 3024 enum port port) 3025 { 3026 static const enum transcoder trans[] = { 3027 [PORT_A] = TRANSCODER_EDP, 3028 [PORT_B] = TRANSCODER_A, 3029 [PORT_C] = TRANSCODER_B, 3030 [PORT_D] = TRANSCODER_C, 3031 [PORT_E] = TRANSCODER_A, 3032 }; 3033 3034 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9); 3035 3036 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 3037 port = PORT_A; 3038 3039 return CHICKEN_TRANS(trans[port]); 3040 } 3041 3042 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 3043 struct intel_encoder *encoder, 3044 const struct intel_crtc_state *crtc_state, 3045 const struct drm_connector_state *conn_state) 3046 { 3047 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3048 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3049 struct drm_connector *connector = conn_state->connector; 3050 int level = intel_ddi_hdmi_level(encoder, crtc_state); 3051 enum port port = encoder->port; 3052 3053 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3054 crtc_state->hdmi_high_tmds_clock_ratio, 3055 crtc_state->hdmi_scrambling)) 3056 drm_dbg_kms(&dev_priv->drm, 3057 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3058 connector->base.id, connector->name); 3059 3060 if (IS_DG2(dev_priv)) 3061 intel_snps_phy_ddi_vswing_sequence(encoder, U32_MAX); 3062 else if (DISPLAY_VER(dev_priv) >= 12) 3063 tgl_ddi_vswing_sequence(encoder, crtc_state, level); 3064 else if (DISPLAY_VER(dev_priv) == 11) 3065 icl_ddi_vswing_sequence(encoder, crtc_state, level); 3066 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3067 bxt_ddi_vswing_sequence(encoder, crtc_state, level); 3068 else 3069 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state, level); 3070 3071 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 3072 skl_ddi_set_iboost(encoder, crtc_state, level); 3073 3074 /* Display WA #1143: skl,kbl,cfl */ 3075 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 3076 /* 3077 * For some reason these chicken bits have been 3078 * stuffed into a transcoder register, event though 3079 * the bits affect a specific DDI port rather than 3080 * a specific transcoder. 3081 */ 3082 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 3083 u32 val; 3084 3085 val = intel_de_read(dev_priv, reg); 3086 3087 if (port == PORT_E) 3088 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3089 DDIE_TRAINING_OVERRIDE_VALUE; 3090 else 3091 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3092 DDI_TRAINING_OVERRIDE_VALUE; 3093 3094 intel_de_write(dev_priv, reg, val); 3095 intel_de_posting_read(dev_priv, reg); 3096 3097 udelay(1); 3098 3099 if (port == PORT_E) 3100 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3101 DDIE_TRAINING_OVERRIDE_VALUE); 3102 else 3103 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3104 DDI_TRAINING_OVERRIDE_VALUE); 3105 3106 intel_de_write(dev_priv, reg, val); 3107 } 3108 3109 intel_ddi_power_up_lanes(encoder, crtc_state); 3110 3111 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3112 * are ignored so nothing special needs to be done besides 3113 * enabling the port. 3114 * 3115 * On ADL_P the PHY link rate and lane count must be programmed but 3116 * these are both 0 for HDMI. 3117 */ 3118 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3119 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE); 3120 3121 if (crtc_state->has_audio) 3122 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3123 } 3124 3125 static void intel_enable_ddi(struct intel_atomic_state *state, 3126 struct intel_encoder *encoder, 3127 const struct intel_crtc_state *crtc_state, 3128 const struct drm_connector_state *conn_state) 3129 { 3130 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 3131 3132 if (!crtc_state->bigjoiner_slave) 3133 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3134 3135 intel_vrr_enable(encoder, crtc_state); 3136 3137 intel_enable_pipe(crtc_state); 3138 3139 intel_crtc_vblank_on(crtc_state); 3140 3141 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3142 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 3143 else 3144 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 3145 3146 /* Enable hdcp if it's desired */ 3147 if (conn_state->content_protection == 3148 DRM_MODE_CONTENT_PROTECTION_DESIRED) 3149 intel_hdcp_enable(to_intel_connector(conn_state->connector), 3150 crtc_state, 3151 (u8)conn_state->hdcp_content_type); 3152 } 3153 3154 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 3155 struct intel_encoder *encoder, 3156 const struct intel_crtc_state *old_crtc_state, 3157 const struct drm_connector_state *old_conn_state) 3158 { 3159 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3160 3161 intel_dp->link_trained = false; 3162 3163 intel_edp_backlight_off(old_conn_state); 3164 /* Disable the decompression in DP Sink */ 3165 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, 3166 false); 3167 /* Disable Ignore_MSA bit in DP Sink */ 3168 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3169 false); 3170 } 3171 3172 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 3173 struct intel_encoder *encoder, 3174 const struct intel_crtc_state *old_crtc_state, 3175 const struct drm_connector_state *old_conn_state) 3176 { 3177 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3178 struct drm_connector *connector = old_conn_state->connector; 3179 3180 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3181 false, false)) 3182 drm_dbg_kms(&i915->drm, 3183 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3184 connector->base.id, connector->name); 3185 } 3186 3187 static void intel_pre_disable_ddi(struct intel_atomic_state *state, 3188 struct intel_encoder *encoder, 3189 const struct intel_crtc_state *old_crtc_state, 3190 const struct drm_connector_state *old_conn_state) 3191 { 3192 struct intel_dp *intel_dp; 3193 3194 if (old_crtc_state->has_audio) 3195 intel_audio_codec_disable(encoder, old_crtc_state, 3196 old_conn_state); 3197 3198 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3199 return; 3200 3201 intel_dp = enc_to_intel_dp(encoder); 3202 intel_edp_drrs_disable(intel_dp, old_crtc_state); 3203 intel_psr_disable(intel_dp, old_crtc_state); 3204 } 3205 3206 static void intel_disable_ddi(struct intel_atomic_state *state, 3207 struct intel_encoder *encoder, 3208 const struct intel_crtc_state *old_crtc_state, 3209 const struct drm_connector_state *old_conn_state) 3210 { 3211 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3212 3213 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3214 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 3215 old_conn_state); 3216 else 3217 intel_disable_ddi_dp(state, encoder, old_crtc_state, 3218 old_conn_state); 3219 } 3220 3221 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3222 struct intel_encoder *encoder, 3223 const struct intel_crtc_state *crtc_state, 3224 const struct drm_connector_state *conn_state) 3225 { 3226 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3227 3228 intel_ddi_set_dp_msa(crtc_state, conn_state); 3229 3230 intel_psr_update(intel_dp, crtc_state, conn_state); 3231 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3232 intel_edp_drrs_update(intel_dp, crtc_state); 3233 3234 intel_panel_update_backlight(state, encoder, crtc_state, conn_state); 3235 } 3236 3237 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3238 struct intel_encoder *encoder, 3239 const struct intel_crtc_state *crtc_state, 3240 const struct drm_connector_state *conn_state) 3241 { 3242 3243 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3244 !intel_encoder_is_mst(encoder)) 3245 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3246 conn_state); 3247 3248 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3249 } 3250 3251 static void 3252 intel_ddi_update_prepare(struct intel_atomic_state *state, 3253 struct intel_encoder *encoder, 3254 struct intel_crtc *crtc) 3255 { 3256 struct intel_crtc_state *crtc_state = 3257 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL; 3258 int required_lanes = crtc_state ? crtc_state->lane_count : 1; 3259 3260 drm_WARN_ON(state->base.dev, crtc && crtc->active); 3261 3262 intel_tc_port_get_link(enc_to_dig_port(encoder), 3263 required_lanes); 3264 if (crtc_state && crtc_state->hw.active) 3265 intel_update_active_dpll(state, crtc, encoder); 3266 } 3267 3268 static void 3269 intel_ddi_update_complete(struct intel_atomic_state *state, 3270 struct intel_encoder *encoder, 3271 struct intel_crtc *crtc) 3272 { 3273 intel_tc_port_put_link(enc_to_dig_port(encoder)); 3274 } 3275 3276 static void 3277 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3278 struct intel_encoder *encoder, 3279 const struct intel_crtc_state *crtc_state, 3280 const struct drm_connector_state *conn_state) 3281 { 3282 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3283 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3284 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3285 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3286 3287 if (is_tc_port) 3288 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3289 3290 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) { 3291 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref); 3292 dig_port->aux_wakeref = 3293 intel_display_power_get(dev_priv, 3294 intel_ddi_main_link_aux_domain(dig_port)); 3295 } 3296 3297 if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT) 3298 /* 3299 * Program the lane count for static/dynamic connections on 3300 * Type-C ports. Skip this step for TBT. 3301 */ 3302 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3303 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3304 bxt_ddi_phy_set_lane_optim_mask(encoder, 3305 crtc_state->lane_lat_optim_mask); 3306 } 3307 3308 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3309 const struct intel_crtc_state *crtc_state) 3310 { 3311 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3312 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3313 enum port port = encoder->port; 3314 u32 dp_tp_ctl, ddi_buf_ctl; 3315 bool wait = false; 3316 3317 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3318 3319 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3320 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3321 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3322 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3323 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3324 wait = true; 3325 } 3326 3327 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3328 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1; 3329 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3330 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3331 3332 if (wait) 3333 intel_wait_ddi_buf_idle(dev_priv, port); 3334 } 3335 3336 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3337 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3338 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3339 } else { 3340 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3341 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 3342 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3343 } 3344 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3345 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3346 3347 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3348 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3349 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3350 3351 intel_wait_ddi_buf_active(dev_priv, port); 3352 } 3353 3354 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3355 const struct intel_crtc_state *crtc_state, 3356 u8 dp_train_pat) 3357 { 3358 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3359 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3360 u32 temp; 3361 3362 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3363 3364 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3365 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3366 case DP_TRAINING_PATTERN_DISABLE: 3367 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3368 break; 3369 case DP_TRAINING_PATTERN_1: 3370 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3371 break; 3372 case DP_TRAINING_PATTERN_2: 3373 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3374 break; 3375 case DP_TRAINING_PATTERN_3: 3376 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3377 break; 3378 case DP_TRAINING_PATTERN_4: 3379 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3380 break; 3381 } 3382 3383 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3384 } 3385 3386 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3387 const struct intel_crtc_state *crtc_state) 3388 { 3389 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3390 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3391 enum port port = encoder->port; 3392 u32 val; 3393 3394 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3395 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3396 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 3397 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 3398 3399 /* 3400 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3401 * reason we need to set idle transmission mode is to work around a HW 3402 * issue where we enable the pipe while not in idle link-training mode. 3403 * In this case there is requirement to wait for a minimum number of 3404 * idle patterns to be sent. 3405 */ 3406 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3407 return; 3408 3409 if (intel_de_wait_for_set(dev_priv, 3410 dp_tp_status_reg(encoder, crtc_state), 3411 DP_TP_STATUS_IDLE_DONE, 1)) 3412 drm_err(&dev_priv->drm, 3413 "Timed out waiting for DP idle patterns\n"); 3414 } 3415 3416 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3417 enum transcoder cpu_transcoder) 3418 { 3419 if (cpu_transcoder == TRANSCODER_EDP) 3420 return false; 3421 3422 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO)) 3423 return false; 3424 3425 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3426 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3427 } 3428 3429 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 3430 struct intel_crtc_state *crtc_state) 3431 { 3432 if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000) 3433 crtc_state->min_voltage_level = 2; 3434 else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000) 3435 crtc_state->min_voltage_level = 3; 3436 else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000) 3437 crtc_state->min_voltage_level = 1; 3438 } 3439 3440 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3441 enum transcoder cpu_transcoder) 3442 { 3443 u32 master_select; 3444 3445 if (DISPLAY_VER(dev_priv) >= 11) { 3446 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); 3447 3448 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3449 return INVALID_TRANSCODER; 3450 3451 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3452 } else { 3453 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3454 3455 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3456 return INVALID_TRANSCODER; 3457 3458 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3459 } 3460 3461 if (master_select == 0) 3462 return TRANSCODER_EDP; 3463 else 3464 return master_select - 1; 3465 } 3466 3467 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3468 { 3469 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3470 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3471 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3472 enum transcoder cpu_transcoder; 3473 3474 crtc_state->master_transcoder = 3475 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3476 3477 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3478 enum intel_display_power_domain power_domain; 3479 intel_wakeref_t trans_wakeref; 3480 3481 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3482 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 3483 power_domain); 3484 3485 if (!trans_wakeref) 3486 continue; 3487 3488 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3489 crtc_state->cpu_transcoder) 3490 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3491 3492 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 3493 } 3494 3495 drm_WARN_ON(&dev_priv->drm, 3496 crtc_state->master_transcoder != INVALID_TRANSCODER && 3497 crtc_state->sync_mode_slaves_mask); 3498 } 3499 3500 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 3501 struct intel_crtc_state *pipe_config) 3502 { 3503 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3504 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3505 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3506 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3507 u32 temp, flags = 0; 3508 3509 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3510 if (temp & TRANS_DDI_PHSYNC) 3511 flags |= DRM_MODE_FLAG_PHSYNC; 3512 else 3513 flags |= DRM_MODE_FLAG_NHSYNC; 3514 if (temp & TRANS_DDI_PVSYNC) 3515 flags |= DRM_MODE_FLAG_PVSYNC; 3516 else 3517 flags |= DRM_MODE_FLAG_NVSYNC; 3518 3519 pipe_config->hw.adjusted_mode.flags |= flags; 3520 3521 switch (temp & TRANS_DDI_BPC_MASK) { 3522 case TRANS_DDI_BPC_6: 3523 pipe_config->pipe_bpp = 18; 3524 break; 3525 case TRANS_DDI_BPC_8: 3526 pipe_config->pipe_bpp = 24; 3527 break; 3528 case TRANS_DDI_BPC_10: 3529 pipe_config->pipe_bpp = 30; 3530 break; 3531 case TRANS_DDI_BPC_12: 3532 pipe_config->pipe_bpp = 36; 3533 break; 3534 default: 3535 break; 3536 } 3537 3538 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3539 case TRANS_DDI_MODE_SELECT_HDMI: 3540 pipe_config->has_hdmi_sink = true; 3541 3542 pipe_config->infoframes.enable |= 3543 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3544 3545 if (pipe_config->infoframes.enable) 3546 pipe_config->has_infoframe = true; 3547 3548 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 3549 pipe_config->hdmi_scrambling = true; 3550 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3551 pipe_config->hdmi_high_tmds_clock_ratio = true; 3552 fallthrough; 3553 case TRANS_DDI_MODE_SELECT_DVI: 3554 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 3555 pipe_config->lane_count = 4; 3556 break; 3557 case TRANS_DDI_MODE_SELECT_FDI: 3558 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3559 break; 3560 case TRANS_DDI_MODE_SELECT_DP_SST: 3561 if (encoder->type == INTEL_OUTPUT_EDP) 3562 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3563 else 3564 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3565 pipe_config->lane_count = 3566 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3567 intel_dp_get_m_n(crtc, pipe_config); 3568 3569 if (DISPLAY_VER(dev_priv) >= 11) { 3570 i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config); 3571 3572 pipe_config->fec_enable = 3573 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; 3574 3575 drm_dbg_kms(&dev_priv->drm, 3576 "[ENCODER:%d:%s] Fec status: %u\n", 3577 encoder->base.base.id, encoder->base.name, 3578 pipe_config->fec_enable); 3579 } 3580 3581 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 3582 pipe_config->infoframes.enable |= 3583 intel_lspcon_infoframes_enabled(encoder, pipe_config); 3584 else 3585 pipe_config->infoframes.enable |= 3586 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3587 break; 3588 case TRANS_DDI_MODE_SELECT_DP_MST: 3589 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 3590 pipe_config->lane_count = 3591 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3592 3593 if (DISPLAY_VER(dev_priv) >= 12) 3594 pipe_config->mst_master_transcoder = 3595 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 3596 3597 intel_dp_get_m_n(crtc, pipe_config); 3598 3599 pipe_config->infoframes.enable |= 3600 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3601 break; 3602 default: 3603 break; 3604 } 3605 } 3606 3607 static void intel_ddi_get_config(struct intel_encoder *encoder, 3608 struct intel_crtc_state *pipe_config) 3609 { 3610 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3611 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3612 3613 /* XXX: DSI transcoder paranoia */ 3614 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 3615 return; 3616 3617 if (pipe_config->bigjoiner_slave) { 3618 /* read out pipe settings from master */ 3619 enum transcoder save = pipe_config->cpu_transcoder; 3620 3621 /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */ 3622 WARN_ON(pipe_config->output_types); 3623 pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe; 3624 intel_ddi_read_func_ctl(encoder, pipe_config); 3625 pipe_config->cpu_transcoder = save; 3626 } else { 3627 intel_ddi_read_func_ctl(encoder, pipe_config); 3628 } 3629 3630 intel_ddi_mso_get_config(encoder, pipe_config); 3631 3632 pipe_config->has_audio = 3633 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 3634 3635 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && 3636 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 3637 /* 3638 * This is a big fat ugly hack. 3639 * 3640 * Some machines in UEFI boot mode provide us a VBT that has 18 3641 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 3642 * unknown we fail to light up. Yet the same BIOS boots up with 3643 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 3644 * max, not what it tells us to use. 3645 * 3646 * Note: This will still be broken if the eDP panel is not lit 3647 * up by the BIOS, and thus we can't get the mode at module 3648 * load. 3649 */ 3650 drm_dbg_kms(&dev_priv->drm, 3651 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 3652 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 3653 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 3654 } 3655 3656 if (!pipe_config->bigjoiner_slave) 3657 ddi_dotclock_get(pipe_config); 3658 3659 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3660 pipe_config->lane_lat_optim_mask = 3661 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 3662 3663 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3664 3665 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 3666 3667 intel_read_infoframe(encoder, pipe_config, 3668 HDMI_INFOFRAME_TYPE_AVI, 3669 &pipe_config->infoframes.avi); 3670 intel_read_infoframe(encoder, pipe_config, 3671 HDMI_INFOFRAME_TYPE_SPD, 3672 &pipe_config->infoframes.spd); 3673 intel_read_infoframe(encoder, pipe_config, 3674 HDMI_INFOFRAME_TYPE_VENDOR, 3675 &pipe_config->infoframes.hdmi); 3676 intel_read_infoframe(encoder, pipe_config, 3677 HDMI_INFOFRAME_TYPE_DRM, 3678 &pipe_config->infoframes.drm); 3679 3680 if (DISPLAY_VER(dev_priv) >= 8) 3681 bdw_get_trans_port_sync_config(pipe_config); 3682 3683 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 3684 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 3685 3686 intel_psr_get_config(encoder, pipe_config); 3687 } 3688 3689 void intel_ddi_get_clock(struct intel_encoder *encoder, 3690 struct intel_crtc_state *crtc_state, 3691 struct intel_shared_dpll *pll) 3692 { 3693 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3694 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3695 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3696 bool pll_active; 3697 3698 if (drm_WARN_ON(&i915->drm, !pll)) 3699 return; 3700 3701 port_dpll->pll = pll; 3702 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3703 drm_WARN_ON(&i915->drm, !pll_active); 3704 3705 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3706 3707 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3708 &crtc_state->dpll_hw_state); 3709 } 3710 3711 static void dg2_ddi_get_config(struct intel_encoder *encoder, 3712 struct intel_crtc_state *crtc_state) 3713 { 3714 intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state); 3715 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state); 3716 3717 intel_ddi_get_config(encoder, crtc_state); 3718 } 3719 3720 static void adls_ddi_get_config(struct intel_encoder *encoder, 3721 struct intel_crtc_state *crtc_state) 3722 { 3723 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 3724 intel_ddi_get_config(encoder, crtc_state); 3725 } 3726 3727 static void rkl_ddi_get_config(struct intel_encoder *encoder, 3728 struct intel_crtc_state *crtc_state) 3729 { 3730 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 3731 intel_ddi_get_config(encoder, crtc_state); 3732 } 3733 3734 static void dg1_ddi_get_config(struct intel_encoder *encoder, 3735 struct intel_crtc_state *crtc_state) 3736 { 3737 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 3738 intel_ddi_get_config(encoder, crtc_state); 3739 } 3740 3741 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 3742 struct intel_crtc_state *crtc_state) 3743 { 3744 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 3745 intel_ddi_get_config(encoder, crtc_state); 3746 } 3747 3748 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 3749 struct intel_crtc_state *crtc_state, 3750 struct intel_shared_dpll *pll) 3751 { 3752 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3753 enum icl_port_dpll_id port_dpll_id; 3754 struct icl_port_dpll *port_dpll; 3755 bool pll_active; 3756 3757 if (drm_WARN_ON(&i915->drm, !pll)) 3758 return; 3759 3760 if (intel_get_shared_dpll_id(i915, pll) == DPLL_ID_ICL_TBTPLL) 3761 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3762 else 3763 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 3764 3765 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3766 3767 port_dpll->pll = pll; 3768 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3769 drm_WARN_ON(&i915->drm, !pll_active); 3770 3771 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3772 3773 if (intel_get_shared_dpll_id(i915, crtc_state->shared_dpll) == DPLL_ID_ICL_TBTPLL) 3774 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); 3775 else 3776 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3777 &crtc_state->dpll_hw_state); 3778 } 3779 3780 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 3781 struct intel_crtc_state *crtc_state) 3782 { 3783 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 3784 intel_ddi_get_config(encoder, crtc_state); 3785 } 3786 3787 static void bxt_ddi_get_config(struct intel_encoder *encoder, 3788 struct intel_crtc_state *crtc_state) 3789 { 3790 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 3791 intel_ddi_get_config(encoder, crtc_state); 3792 } 3793 3794 static void skl_ddi_get_config(struct intel_encoder *encoder, 3795 struct intel_crtc_state *crtc_state) 3796 { 3797 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 3798 intel_ddi_get_config(encoder, crtc_state); 3799 } 3800 3801 void hsw_ddi_get_config(struct intel_encoder *encoder, 3802 struct intel_crtc_state *crtc_state) 3803 { 3804 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 3805 intel_ddi_get_config(encoder, crtc_state); 3806 } 3807 3808 static void intel_ddi_sync_state(struct intel_encoder *encoder, 3809 const struct intel_crtc_state *crtc_state) 3810 { 3811 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3812 enum phy phy = intel_port_to_phy(i915, encoder->port); 3813 3814 if (intel_phy_is_tc(i915, phy)) 3815 intel_tc_port_sanitize(enc_to_dig_port(encoder)); 3816 3817 if (crtc_state && intel_crtc_has_dp_encoder(crtc_state)) 3818 intel_dp_sync_state(encoder, crtc_state); 3819 } 3820 3821 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 3822 struct intel_crtc_state *crtc_state) 3823 { 3824 if (intel_crtc_has_dp_encoder(crtc_state)) 3825 return intel_dp_initial_fastset_check(encoder, crtc_state); 3826 3827 return true; 3828 } 3829 3830 static enum intel_output_type 3831 intel_ddi_compute_output_type(struct intel_encoder *encoder, 3832 struct intel_crtc_state *crtc_state, 3833 struct drm_connector_state *conn_state) 3834 { 3835 switch (conn_state->connector->connector_type) { 3836 case DRM_MODE_CONNECTOR_HDMIA: 3837 return INTEL_OUTPUT_HDMI; 3838 case DRM_MODE_CONNECTOR_eDP: 3839 return INTEL_OUTPUT_EDP; 3840 case DRM_MODE_CONNECTOR_DisplayPort: 3841 return INTEL_OUTPUT_DP; 3842 default: 3843 MISSING_CASE(conn_state->connector->connector_type); 3844 return INTEL_OUTPUT_UNUSED; 3845 } 3846 } 3847 3848 static int intel_ddi_compute_config(struct intel_encoder *encoder, 3849 struct intel_crtc_state *pipe_config, 3850 struct drm_connector_state *conn_state) 3851 { 3852 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3853 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3854 enum port port = encoder->port; 3855 int ret; 3856 3857 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 3858 pipe_config->cpu_transcoder = TRANSCODER_EDP; 3859 3860 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 3861 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 3862 } else { 3863 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 3864 } 3865 3866 if (ret) 3867 return ret; 3868 3869 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 3870 pipe_config->cpu_transcoder == TRANSCODER_EDP) 3871 pipe_config->pch_pfit.force_thru = 3872 pipe_config->pch_pfit.enabled || 3873 pipe_config->crc_enabled; 3874 3875 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3876 pipe_config->lane_lat_optim_mask = 3877 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 3878 3879 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3880 3881 return 0; 3882 } 3883 3884 static bool mode_equal(const struct drm_display_mode *mode1, 3885 const struct drm_display_mode *mode2) 3886 { 3887 return drm_mode_match(mode1, mode2, 3888 DRM_MODE_MATCH_TIMINGS | 3889 DRM_MODE_MATCH_FLAGS | 3890 DRM_MODE_MATCH_3D_FLAGS) && 3891 mode1->clock == mode2->clock; /* we want an exact match */ 3892 } 3893 3894 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 3895 const struct intel_link_m_n *m_n_2) 3896 { 3897 return m_n_1->tu == m_n_2->tu && 3898 m_n_1->gmch_m == m_n_2->gmch_m && 3899 m_n_1->gmch_n == m_n_2->gmch_n && 3900 m_n_1->link_m == m_n_2->link_m && 3901 m_n_1->link_n == m_n_2->link_n; 3902 } 3903 3904 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 3905 const struct intel_crtc_state *crtc_state2) 3906 { 3907 return crtc_state1->hw.active && crtc_state2->hw.active && 3908 crtc_state1->output_types == crtc_state2->output_types && 3909 crtc_state1->output_format == crtc_state2->output_format && 3910 crtc_state1->lane_count == crtc_state2->lane_count && 3911 crtc_state1->port_clock == crtc_state2->port_clock && 3912 mode_equal(&crtc_state1->hw.adjusted_mode, 3913 &crtc_state2->hw.adjusted_mode) && 3914 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 3915 } 3916 3917 static u8 3918 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 3919 int tile_group_id) 3920 { 3921 struct drm_connector *connector; 3922 const struct drm_connector_state *conn_state; 3923 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 3924 struct intel_atomic_state *state = 3925 to_intel_atomic_state(ref_crtc_state->uapi.state); 3926 u8 transcoders = 0; 3927 int i; 3928 3929 /* 3930 * We don't enable port sync on BDW due to missing w/as and 3931 * due to not having adjusted the modeset sequence appropriately. 3932 */ 3933 if (DISPLAY_VER(dev_priv) < 9) 3934 return 0; 3935 3936 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 3937 return 0; 3938 3939 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 3940 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 3941 const struct intel_crtc_state *crtc_state; 3942 3943 if (!crtc) 3944 continue; 3945 3946 if (!connector->has_tile || 3947 connector->tile_group->id != 3948 tile_group_id) 3949 continue; 3950 crtc_state = intel_atomic_get_new_crtc_state(state, 3951 crtc); 3952 if (!crtcs_port_sync_compatible(ref_crtc_state, 3953 crtc_state)) 3954 continue; 3955 transcoders |= BIT(crtc_state->cpu_transcoder); 3956 } 3957 3958 return transcoders; 3959 } 3960 3961 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 3962 struct intel_crtc_state *crtc_state, 3963 struct drm_connector_state *conn_state) 3964 { 3965 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3966 struct drm_connector *connector = conn_state->connector; 3967 u8 port_sync_transcoders = 0; 3968 3969 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]", 3970 encoder->base.base.id, encoder->base.name, 3971 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 3972 3973 if (connector->has_tile) 3974 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 3975 connector->tile_group->id); 3976 3977 /* 3978 * EDP Transcoders cannot be ensalved 3979 * make them a master always when present 3980 */ 3981 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 3982 crtc_state->master_transcoder = TRANSCODER_EDP; 3983 else 3984 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 3985 3986 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 3987 crtc_state->master_transcoder = INVALID_TRANSCODER; 3988 crtc_state->sync_mode_slaves_mask = 3989 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 3990 } 3991 3992 return 0; 3993 } 3994 3995 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 3996 { 3997 struct drm_i915_private *i915 = to_i915(encoder->dev); 3998 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 3999 4000 intel_dp_encoder_flush_work(encoder); 4001 intel_display_power_flush_work(i915); 4002 4003 drm_encoder_cleanup(encoder); 4004 if (dig_port) 4005 kfree(dig_port->hdcp_port_data.streams); 4006 kfree(dig_port); 4007 } 4008 4009 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4010 { 4011 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4012 4013 intel_dp->reset_link_params = true; 4014 4015 intel_pps_encoder_reset(intel_dp); 4016 } 4017 4018 static const struct drm_encoder_funcs intel_ddi_funcs = { 4019 .reset = intel_ddi_encoder_reset, 4020 .destroy = intel_ddi_encoder_destroy, 4021 }; 4022 4023 static struct intel_connector * 4024 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4025 { 4026 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4027 struct intel_connector *connector; 4028 enum port port = dig_port->base.port; 4029 4030 connector = intel_connector_alloc(); 4031 if (!connector) 4032 return NULL; 4033 4034 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4035 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4036 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4037 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4038 4039 if (IS_DG2(dev_priv)) 4040 dig_port->dp.set_signal_levels = dg2_set_signal_levels; 4041 else if (DISPLAY_VER(dev_priv) >= 12) 4042 dig_port->dp.set_signal_levels = tgl_set_signal_levels; 4043 else if (DISPLAY_VER(dev_priv) >= 11) 4044 dig_port->dp.set_signal_levels = icl_set_signal_levels; 4045 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4046 dig_port->dp.set_signal_levels = bxt_set_signal_levels; 4047 else 4048 dig_port->dp.set_signal_levels = hsw_set_signal_levels; 4049 4050 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4051 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4052 4053 if (!intel_dp_init_connector(dig_port, connector)) { 4054 kfree(connector); 4055 return NULL; 4056 } 4057 4058 return connector; 4059 } 4060 4061 static int modeset_pipe(struct drm_crtc *crtc, 4062 struct drm_modeset_acquire_ctx *ctx) 4063 { 4064 struct drm_atomic_state *state; 4065 struct drm_crtc_state *crtc_state; 4066 int ret; 4067 4068 state = drm_atomic_state_alloc(crtc->dev); 4069 if (!state) 4070 return -ENOMEM; 4071 4072 state->acquire_ctx = ctx; 4073 4074 crtc_state = drm_atomic_get_crtc_state(state, crtc); 4075 if (IS_ERR(crtc_state)) { 4076 ret = PTR_ERR(crtc_state); 4077 goto out; 4078 } 4079 4080 crtc_state->connectors_changed = true; 4081 4082 ret = drm_atomic_commit(state); 4083 out: 4084 drm_atomic_state_put(state); 4085 4086 return ret; 4087 } 4088 4089 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4090 struct drm_modeset_acquire_ctx *ctx) 4091 { 4092 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4093 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4094 struct intel_connector *connector = hdmi->attached_connector; 4095 struct i2c_adapter *adapter = 4096 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 4097 struct drm_connector_state *conn_state; 4098 struct intel_crtc_state *crtc_state; 4099 struct intel_crtc *crtc; 4100 u8 config; 4101 int ret; 4102 4103 if (!connector || connector->base.status != connector_status_connected) 4104 return 0; 4105 4106 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4107 ctx); 4108 if (ret) 4109 return ret; 4110 4111 conn_state = connector->base.state; 4112 4113 crtc = to_intel_crtc(conn_state->crtc); 4114 if (!crtc) 4115 return 0; 4116 4117 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4118 if (ret) 4119 return ret; 4120 4121 crtc_state = to_intel_crtc_state(crtc->base.state); 4122 4123 drm_WARN_ON(&dev_priv->drm, 4124 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4125 4126 if (!crtc_state->hw.active) 4127 return 0; 4128 4129 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4130 !crtc_state->hdmi_scrambling) 4131 return 0; 4132 4133 if (conn_state->commit && 4134 !try_wait_for_completion(&conn_state->commit->hw_done)) 4135 return 0; 4136 4137 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 4138 if (ret < 0) { 4139 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n", 4140 ret); 4141 return 0; 4142 } 4143 4144 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4145 crtc_state->hdmi_high_tmds_clock_ratio && 4146 !!(config & SCDC_SCRAMBLING_ENABLE) == 4147 crtc_state->hdmi_scrambling) 4148 return 0; 4149 4150 /* 4151 * HDMI 2.0 says that one should not send scrambled data 4152 * prior to configuring the sink scrambling, and that 4153 * TMDS clock/data transmission should be suspended when 4154 * changing the TMDS clock rate in the sink. So let's 4155 * just do a full modeset here, even though some sinks 4156 * would be perfectly happy if were to just reconfigure 4157 * the SCDC settings on the fly. 4158 */ 4159 return modeset_pipe(&crtc->base, ctx); 4160 } 4161 4162 static enum intel_hotplug_state 4163 intel_ddi_hotplug(struct intel_encoder *encoder, 4164 struct intel_connector *connector) 4165 { 4166 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4167 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4168 struct intel_dp *intel_dp = &dig_port->dp; 4169 enum phy phy = intel_port_to_phy(i915, encoder->port); 4170 bool is_tc = intel_phy_is_tc(i915, phy); 4171 struct drm_modeset_acquire_ctx ctx; 4172 enum intel_hotplug_state state; 4173 int ret; 4174 4175 if (intel_dp->compliance.test_active && 4176 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { 4177 intel_dp_phy_test(encoder); 4178 /* just do the PHY test and nothing else */ 4179 return INTEL_HOTPLUG_UNCHANGED; 4180 } 4181 4182 state = intel_encoder_hotplug(encoder, connector); 4183 4184 drm_modeset_acquire_init(&ctx, 0); 4185 4186 for (;;) { 4187 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4188 ret = intel_hdmi_reset_link(encoder, &ctx); 4189 else 4190 ret = intel_dp_retrain_link(encoder, &ctx); 4191 4192 if (ret == -EDEADLK) { 4193 drm_modeset_backoff(&ctx); 4194 continue; 4195 } 4196 4197 break; 4198 } 4199 4200 drm_modeset_drop_locks(&ctx); 4201 drm_modeset_acquire_fini(&ctx); 4202 drm_WARN(encoder->base.dev, ret, 4203 "Acquiring modeset locks failed with %i\n", ret); 4204 4205 /* 4206 * Unpowered type-c dongles can take some time to boot and be 4207 * responsible, so here giving some time to those dongles to power up 4208 * and then retrying the probe. 4209 * 4210 * On many platforms the HDMI live state signal is known to be 4211 * unreliable, so we can't use it to detect if a sink is connected or 4212 * not. Instead we detect if it's connected based on whether we can 4213 * read the EDID or not. That in turn has a problem during disconnect, 4214 * since the HPD interrupt may be raised before the DDC lines get 4215 * disconnected (due to how the required length of DDC vs. HPD 4216 * connector pins are specified) and so we'll still be able to get a 4217 * valid EDID. To solve this schedule another detection cycle if this 4218 * time around we didn't detect any change in the sink's connection 4219 * status. 4220 * 4221 * Type-c connectors which get their HPD signal deasserted then 4222 * reasserted, without unplugging/replugging the sink from the 4223 * connector, introduce a delay until the AUX channel communication 4224 * becomes functional. Retry the detection for 5 seconds on type-c 4225 * connectors to account for this delay. 4226 */ 4227 if (state == INTEL_HOTPLUG_UNCHANGED && 4228 connector->hotplug_retries < (is_tc ? 5 : 1) && 4229 !dig_port->dp.is_mst) 4230 state = INTEL_HOTPLUG_RETRY; 4231 4232 return state; 4233 } 4234 4235 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4236 { 4237 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4238 u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin]; 4239 4240 return intel_de_read(dev_priv, SDEISR) & bit; 4241 } 4242 4243 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4244 { 4245 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4246 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4247 4248 return intel_de_read(dev_priv, DEISR) & bit; 4249 } 4250 4251 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4252 { 4253 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4254 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4255 4256 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4257 } 4258 4259 static struct intel_connector * 4260 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4261 { 4262 struct intel_connector *connector; 4263 enum port port = dig_port->base.port; 4264 4265 connector = intel_connector_alloc(); 4266 if (!connector) 4267 return NULL; 4268 4269 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4270 intel_hdmi_init_connector(dig_port, connector); 4271 4272 return connector; 4273 } 4274 4275 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4276 { 4277 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4278 4279 if (dig_port->base.port != PORT_A) 4280 return false; 4281 4282 if (dig_port->saved_port_bits & DDI_A_4_LANES) 4283 return false; 4284 4285 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4286 * supported configuration 4287 */ 4288 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4289 return true; 4290 4291 return false; 4292 } 4293 4294 static int 4295 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4296 { 4297 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4298 enum port port = dig_port->base.port; 4299 int max_lanes = 4; 4300 4301 if (DISPLAY_VER(dev_priv) >= 11) 4302 return max_lanes; 4303 4304 if (port == PORT_A || port == PORT_E) { 4305 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4306 max_lanes = port == PORT_A ? 4 : 0; 4307 else 4308 /* Both A and E share 2 lanes */ 4309 max_lanes = 2; 4310 } 4311 4312 /* 4313 * Some BIOS might fail to set this bit on port A if eDP 4314 * wasn't lit up at boot. Force this bit set when needed 4315 * so we use the proper lane count for our calculations. 4316 */ 4317 if (intel_ddi_a_force_4_lanes(dig_port)) { 4318 drm_dbg_kms(&dev_priv->drm, 4319 "Forcing DDI_A_4_LANES for port A\n"); 4320 dig_port->saved_port_bits |= DDI_A_4_LANES; 4321 max_lanes = 4; 4322 } 4323 4324 return max_lanes; 4325 } 4326 4327 static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy) 4328 { 4329 return i915->hti_state & HDPORT_ENABLED && 4330 i915->hti_state & HDPORT_DDI_USED(phy); 4331 } 4332 4333 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4334 enum port port) 4335 { 4336 if (port >= PORT_D_XELPD) 4337 return HPD_PORT_D + port - PORT_D_XELPD; 4338 else if (port >= PORT_TC1) 4339 return HPD_PORT_TC1 + port - PORT_TC1; 4340 else 4341 return HPD_PORT_A + port - PORT_A; 4342 } 4343 4344 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4345 enum port port) 4346 { 4347 if (port >= PORT_TC1) 4348 return HPD_PORT_C + port - PORT_TC1; 4349 else 4350 return HPD_PORT_A + port - PORT_A; 4351 } 4352 4353 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4354 enum port port) 4355 { 4356 if (port >= PORT_TC1) 4357 return HPD_PORT_TC1 + port - PORT_TC1; 4358 else 4359 return HPD_PORT_A + port - PORT_A; 4360 } 4361 4362 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4363 enum port port) 4364 { 4365 if (HAS_PCH_TGP(dev_priv)) 4366 return tgl_hpd_pin(dev_priv, port); 4367 4368 if (port >= PORT_TC1) 4369 return HPD_PORT_C + port - PORT_TC1; 4370 else 4371 return HPD_PORT_A + port - PORT_A; 4372 } 4373 4374 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4375 enum port port) 4376 { 4377 if (port >= PORT_C) 4378 return HPD_PORT_TC1 + port - PORT_C; 4379 else 4380 return HPD_PORT_A + port - PORT_A; 4381 } 4382 4383 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4384 enum port port) 4385 { 4386 if (port == PORT_D) 4387 return HPD_PORT_A; 4388 4389 if (HAS_PCH_MCC(dev_priv)) 4390 return icl_hpd_pin(dev_priv, port); 4391 4392 return HPD_PORT_A + port - PORT_A; 4393 } 4394 4395 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4396 { 4397 if (HAS_PCH_TGP(dev_priv)) 4398 return icl_hpd_pin(dev_priv, port); 4399 4400 return HPD_PORT_A + port - PORT_A; 4401 } 4402 4403 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4404 { 4405 if (DISPLAY_VER(i915) >= 12) 4406 return port >= PORT_TC1; 4407 else if (DISPLAY_VER(i915) >= 11) 4408 return port >= PORT_C; 4409 else 4410 return false; 4411 } 4412 4413 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4414 { 4415 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4416 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4417 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4418 enum phy phy = intel_port_to_phy(i915, encoder->port); 4419 4420 intel_dp_encoder_suspend(encoder); 4421 4422 if (!intel_phy_is_tc(i915, phy)) 4423 return; 4424 4425 intel_tc_port_disconnect_phy(dig_port); 4426 } 4427 4428 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 4429 { 4430 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4431 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4432 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4433 enum phy phy = intel_port_to_phy(i915, encoder->port); 4434 4435 intel_dp_encoder_shutdown(encoder); 4436 intel_hdmi_encoder_shutdown(encoder); 4437 4438 if (!intel_phy_is_tc(i915, phy)) 4439 return; 4440 4441 intel_tc_port_disconnect_phy(dig_port); 4442 } 4443 4444 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 4445 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 4446 4447 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 4448 { 4449 struct intel_digital_port *dig_port; 4450 struct intel_encoder *encoder; 4451 const struct intel_bios_encoder_data *devdata; 4452 bool init_hdmi, init_dp; 4453 enum phy phy = intel_port_to_phy(dev_priv, port); 4454 4455 /* 4456 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 4457 * have taken over some of the PHYs and made them unavailable to the 4458 * driver. In that case we should skip initializing the corresponding 4459 * outputs. 4460 */ 4461 if (hti_uses_phy(dev_priv, phy)) { 4462 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 4463 port_name(port), phy_name(phy)); 4464 return; 4465 } 4466 4467 devdata = intel_bios_encoder_data_lookup(dev_priv, port); 4468 if (!devdata) { 4469 drm_dbg_kms(&dev_priv->drm, 4470 "VBT says port %c is not present\n", 4471 port_name(port)); 4472 return; 4473 } 4474 4475 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 4476 intel_bios_encoder_supports_hdmi(devdata); 4477 init_dp = intel_bios_encoder_supports_dp(devdata); 4478 4479 if (intel_bios_is_lspcon_present(dev_priv, port)) { 4480 /* 4481 * Lspcon device needs to be driven with DP connector 4482 * with special detection sequence. So make sure DP 4483 * is initialized before lspcon. 4484 */ 4485 init_dp = true; 4486 init_hdmi = false; 4487 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 4488 port_name(port)); 4489 } 4490 4491 if (!init_dp && !init_hdmi) { 4492 drm_dbg_kms(&dev_priv->drm, 4493 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4494 port_name(port)); 4495 return; 4496 } 4497 4498 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 4499 if (!dig_port) 4500 return; 4501 4502 encoder = &dig_port->base; 4503 encoder->devdata = devdata; 4504 4505 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 4506 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4507 DRM_MODE_ENCODER_TMDS, 4508 "DDI %c/PHY %c", 4509 port_name(port - PORT_D_XELPD + PORT_D), 4510 phy_name(phy)); 4511 } else if (DISPLAY_VER(dev_priv) >= 12) { 4512 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4513 4514 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4515 DRM_MODE_ENCODER_TMDS, 4516 "DDI %s%c/PHY %s%c", 4517 port >= PORT_TC1 ? "TC" : "", 4518 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 4519 tc_port != TC_PORT_NONE ? "TC" : "", 4520 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4521 } else if (DISPLAY_VER(dev_priv) >= 11) { 4522 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4523 4524 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4525 DRM_MODE_ENCODER_TMDS, 4526 "DDI %c%s/PHY %s%c", 4527 port_name(port), 4528 port >= PORT_C ? " (TC)" : "", 4529 tc_port != TC_PORT_NONE ? "TC" : "", 4530 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4531 } else { 4532 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4533 DRM_MODE_ENCODER_TMDS, 4534 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 4535 } 4536 4537 rw_init(&dig_port->hdcp_mutex, "dhdcp"); 4538 dig_port->num_hdcp_streams = 0; 4539 4540 encoder->hotplug = intel_ddi_hotplug; 4541 encoder->compute_output_type = intel_ddi_compute_output_type; 4542 encoder->compute_config = intel_ddi_compute_config; 4543 encoder->compute_config_late = intel_ddi_compute_config_late; 4544 encoder->enable = intel_enable_ddi; 4545 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4546 encoder->pre_enable = intel_ddi_pre_enable; 4547 encoder->pre_disable = intel_pre_disable_ddi; 4548 encoder->disable = intel_disable_ddi; 4549 encoder->post_disable = intel_ddi_post_disable; 4550 encoder->update_pipe = intel_ddi_update_pipe; 4551 encoder->get_hw_state = intel_ddi_get_hw_state; 4552 encoder->sync_state = intel_ddi_sync_state; 4553 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 4554 encoder->suspend = intel_ddi_encoder_suspend; 4555 encoder->shutdown = intel_ddi_encoder_shutdown; 4556 encoder->get_power_domains = intel_ddi_get_power_domains; 4557 4558 encoder->type = INTEL_OUTPUT_DDI; 4559 encoder->power_domain = intel_port_to_power_domain(port); 4560 encoder->port = port; 4561 encoder->cloneable = 0; 4562 encoder->pipe_mask = ~0; 4563 4564 if (IS_DG2(dev_priv)) { 4565 encoder->enable_clock = intel_mpllb_enable; 4566 encoder->disable_clock = intel_mpllb_disable; 4567 encoder->get_config = dg2_ddi_get_config; 4568 } else if (IS_ALDERLAKE_S(dev_priv)) { 4569 encoder->enable_clock = adls_ddi_enable_clock; 4570 encoder->disable_clock = adls_ddi_disable_clock; 4571 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 4572 encoder->get_config = adls_ddi_get_config; 4573 } else if (IS_ROCKETLAKE(dev_priv)) { 4574 encoder->enable_clock = rkl_ddi_enable_clock; 4575 encoder->disable_clock = rkl_ddi_disable_clock; 4576 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 4577 encoder->get_config = rkl_ddi_get_config; 4578 } else if (IS_DG1(dev_priv)) { 4579 encoder->enable_clock = dg1_ddi_enable_clock; 4580 encoder->disable_clock = dg1_ddi_disable_clock; 4581 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 4582 encoder->get_config = dg1_ddi_get_config; 4583 } else if (IS_JSL_EHL(dev_priv)) { 4584 if (intel_ddi_is_tc(dev_priv, port)) { 4585 encoder->enable_clock = jsl_ddi_tc_enable_clock; 4586 encoder->disable_clock = jsl_ddi_tc_disable_clock; 4587 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 4588 encoder->get_config = icl_ddi_combo_get_config; 4589 } else { 4590 encoder->enable_clock = icl_ddi_combo_enable_clock; 4591 encoder->disable_clock = icl_ddi_combo_disable_clock; 4592 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4593 encoder->get_config = icl_ddi_combo_get_config; 4594 } 4595 } else if (DISPLAY_VER(dev_priv) >= 11) { 4596 if (intel_ddi_is_tc(dev_priv, port)) { 4597 encoder->enable_clock = icl_ddi_tc_enable_clock; 4598 encoder->disable_clock = icl_ddi_tc_disable_clock; 4599 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 4600 encoder->get_config = icl_ddi_tc_get_config; 4601 } else { 4602 encoder->enable_clock = icl_ddi_combo_enable_clock; 4603 encoder->disable_clock = icl_ddi_combo_disable_clock; 4604 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4605 encoder->get_config = icl_ddi_combo_get_config; 4606 } 4607 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4608 /* BXT/GLK have fixed PLL->port mapping */ 4609 encoder->get_config = bxt_ddi_get_config; 4610 } else if (DISPLAY_VER(dev_priv) == 9) { 4611 encoder->enable_clock = skl_ddi_enable_clock; 4612 encoder->disable_clock = skl_ddi_disable_clock; 4613 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 4614 encoder->get_config = skl_ddi_get_config; 4615 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4616 encoder->enable_clock = hsw_ddi_enable_clock; 4617 encoder->disable_clock = hsw_ddi_disable_clock; 4618 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 4619 encoder->get_config = hsw_ddi_get_config; 4620 } 4621 4622 intel_ddi_buf_trans_init(encoder); 4623 4624 if (DISPLAY_VER(dev_priv) >= 13) 4625 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 4626 else if (IS_DG1(dev_priv)) 4627 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 4628 else if (IS_ROCKETLAKE(dev_priv)) 4629 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 4630 else if (DISPLAY_VER(dev_priv) >= 12) 4631 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 4632 else if (IS_JSL_EHL(dev_priv)) 4633 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 4634 else if (DISPLAY_VER(dev_priv) == 11) 4635 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 4636 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 4637 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 4638 else 4639 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 4640 4641 if (DISPLAY_VER(dev_priv) >= 11) 4642 dig_port->saved_port_bits = 4643 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4644 & DDI_BUF_PORT_REVERSAL; 4645 else 4646 dig_port->saved_port_bits = 4647 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4648 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 4649 4650 if (intel_bios_is_lane_reversal_needed(dev_priv, port)) 4651 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL; 4652 4653 dig_port->dp.output_reg = INVALID_MMIO_REG; 4654 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 4655 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 4656 4657 if (intel_phy_is_tc(dev_priv, phy)) { 4658 bool is_legacy = 4659 !intel_bios_encoder_supports_typec_usb(devdata) && 4660 !intel_bios_encoder_supports_tbt(devdata); 4661 4662 intel_tc_port_init(dig_port, is_legacy); 4663 4664 encoder->update_prepare = intel_ddi_update_prepare; 4665 encoder->update_complete = intel_ddi_update_complete; 4666 } 4667 4668 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 4669 dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + 4670 port - PORT_A; 4671 4672 if (init_dp) { 4673 if (!intel_ddi_init_dp_connector(dig_port)) 4674 goto err; 4675 4676 dig_port->hpd_pulse = intel_dp_hpd_pulse; 4677 4678 if (dig_port->dp.mso_link_count) 4679 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); 4680 } 4681 4682 /* In theory we don't need the encoder->type check, but leave it just in 4683 * case we have some really bad VBTs... */ 4684 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 4685 if (!intel_ddi_init_hdmi_connector(dig_port)) 4686 goto err; 4687 } 4688 4689 if (DISPLAY_VER(dev_priv) >= 11) { 4690 if (intel_phy_is_tc(dev_priv, phy)) 4691 dig_port->connected = intel_tc_port_connected; 4692 else 4693 dig_port->connected = lpt_digital_port_connected; 4694 } else if (DISPLAY_VER(dev_priv) >= 8) { 4695 if (port == PORT_A || IS_GEMINILAKE(dev_priv) || 4696 IS_BROXTON(dev_priv)) 4697 dig_port->connected = bdw_digital_port_connected; 4698 else 4699 dig_port->connected = lpt_digital_port_connected; 4700 } else { 4701 if (port == PORT_A) 4702 dig_port->connected = hsw_digital_port_connected; 4703 else 4704 dig_port->connected = lpt_digital_port_connected; 4705 } 4706 4707 intel_infoframe_init(dig_port); 4708 4709 return; 4710 4711 err: 4712 drm_encoder_cleanup(&encoder->base); 4713 kfree(dig_port); 4714 } 4715