1 /* 2 * Copyright © 2006 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 */ 27 28 #include <drm/drm_dp_helper.h> 29 30 #include "display/intel_display.h" 31 #include "display/intel_display_types.h" 32 #include "display/intel_gmbus.h" 33 34 #include "i915_drv.h" 35 36 #define _INTEL_BIOS_PRIVATE 37 #include "intel_vbt_defs.h" 38 39 /** 40 * DOC: Video BIOS Table (VBT) 41 * 42 * The Video BIOS Table, or VBT, provides platform and board specific 43 * configuration information to the driver that is not discoverable or available 44 * through other means. The configuration is mostly related to display 45 * hardware. The VBT is available via the ACPI OpRegion or, on older systems, in 46 * the PCI ROM. 47 * 48 * The VBT consists of a VBT Header (defined as &struct vbt_header), a BDB 49 * Header (&struct bdb_header), and a number of BIOS Data Blocks (BDB) that 50 * contain the actual configuration information. The VBT Header, and thus the 51 * VBT, begins with "$VBT" signature. The VBT Header contains the offset of the 52 * BDB Header. The data blocks are concatenated after the BDB Header. The data 53 * blocks have a 1-byte Block ID, 2-byte Block Size, and Block Size bytes of 54 * data. (Block 53, the MIPI Sequence Block is an exception.) 55 * 56 * The driver parses the VBT during load. The relevant information is stored in 57 * driver private data for ease of use, and the actual VBT is not read after 58 * that. 59 */ 60 61 /* Wrapper for VBT child device config */ 62 struct intel_bios_encoder_data { 63 struct drm_i915_private *i915; 64 65 struct child_device_config child; 66 struct dsc_compression_parameters_entry *dsc; 67 struct list_head node; 68 }; 69 70 #define SLAVE_ADDR1 0x70 71 #define SLAVE_ADDR2 0x72 72 73 /* Get BDB block size given a pointer to Block ID. */ 74 static u32 _get_blocksize(const u8 *block_base) 75 { 76 /* The MIPI Sequence Block v3+ has a separate size field. */ 77 if (*block_base == BDB_MIPI_SEQUENCE && *(block_base + 3) >= 3) 78 return *((const u32 *)(block_base + 4)); 79 else 80 return *((const u16 *)(block_base + 1)); 81 } 82 83 /* Get BDB block size give a pointer to data after Block ID and Block Size. */ 84 static u32 get_blocksize(const void *block_data) 85 { 86 return _get_blocksize(block_data - 3); 87 } 88 89 static const void * 90 find_section(const void *_bdb, enum bdb_block_id section_id) 91 { 92 const struct bdb_header *bdb = _bdb; 93 const u8 *base = _bdb; 94 int index = 0; 95 u32 total, current_size; 96 enum bdb_block_id current_id; 97 98 /* skip to first section */ 99 index += bdb->header_size; 100 total = bdb->bdb_size; 101 102 /* walk the sections looking for section_id */ 103 while (index + 3 < total) { 104 current_id = *(base + index); 105 current_size = _get_blocksize(base + index); 106 index += 3; 107 108 if (index + current_size > total) 109 return NULL; 110 111 if (current_id == section_id) 112 return base + index; 113 114 index += current_size; 115 } 116 117 return NULL; 118 } 119 120 static void 121 fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode, 122 const struct lvds_dvo_timing *dvo_timing) 123 { 124 panel_fixed_mode->hdisplay = (dvo_timing->hactive_hi << 8) | 125 dvo_timing->hactive_lo; 126 panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay + 127 ((dvo_timing->hsync_off_hi << 8) | dvo_timing->hsync_off_lo); 128 panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start + 129 ((dvo_timing->hsync_pulse_width_hi << 8) | 130 dvo_timing->hsync_pulse_width_lo); 131 panel_fixed_mode->htotal = panel_fixed_mode->hdisplay + 132 ((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo); 133 134 panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) | 135 dvo_timing->vactive_lo; 136 panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay + 137 ((dvo_timing->vsync_off_hi << 4) | dvo_timing->vsync_off_lo); 138 panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start + 139 ((dvo_timing->vsync_pulse_width_hi << 4) | 140 dvo_timing->vsync_pulse_width_lo); 141 panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay + 142 ((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo); 143 panel_fixed_mode->clock = dvo_timing->clock * 10; 144 panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED; 145 146 if (dvo_timing->hsync_positive) 147 panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC; 148 else 149 panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC; 150 151 if (dvo_timing->vsync_positive) 152 panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC; 153 else 154 panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC; 155 156 panel_fixed_mode->width_mm = (dvo_timing->himage_hi << 8) | 157 dvo_timing->himage_lo; 158 panel_fixed_mode->height_mm = (dvo_timing->vimage_hi << 8) | 159 dvo_timing->vimage_lo; 160 161 /* Some VBTs have bogus h/vtotal values */ 162 if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal) 163 panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1; 164 if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal) 165 panel_fixed_mode->vtotal = panel_fixed_mode->vsync_end + 1; 166 167 drm_mode_set_name(panel_fixed_mode); 168 } 169 170 static const struct lvds_dvo_timing * 171 get_lvds_dvo_timing(const struct bdb_lvds_lfp_data *lvds_lfp_data, 172 const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs, 173 int index) 174 { 175 /* 176 * the size of fp_timing varies on the different platform. 177 * So calculate the DVO timing relative offset in LVDS data 178 * entry to get the DVO timing entry 179 */ 180 181 int lfp_data_size = 182 lvds_lfp_data_ptrs->ptr[1].dvo_timing_offset - 183 lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset; 184 int dvo_timing_offset = 185 lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset - 186 lvds_lfp_data_ptrs->ptr[0].fp_timing_offset; 187 char *entry = (char *)lvds_lfp_data->data + lfp_data_size * index; 188 189 return (struct lvds_dvo_timing *)(entry + dvo_timing_offset); 190 } 191 192 /* get lvds_fp_timing entry 193 * this function may return NULL if the corresponding entry is invalid 194 */ 195 static const struct lvds_fp_timing * 196 get_lvds_fp_timing(const struct bdb_header *bdb, 197 const struct bdb_lvds_lfp_data *data, 198 const struct bdb_lvds_lfp_data_ptrs *ptrs, 199 int index) 200 { 201 size_t data_ofs = (const u8 *)data - (const u8 *)bdb; 202 u16 data_size = ((const u16 *)data)[-1]; /* stored in header */ 203 size_t ofs; 204 205 if (index >= ARRAY_SIZE(ptrs->ptr)) 206 return NULL; 207 ofs = ptrs->ptr[index].fp_timing_offset; 208 if (ofs < data_ofs || 209 ofs + sizeof(struct lvds_fp_timing) > data_ofs + data_size) 210 return NULL; 211 return (const struct lvds_fp_timing *)((const u8 *)bdb + ofs); 212 } 213 214 /* Parse general panel options */ 215 static void 216 parse_panel_options(struct drm_i915_private *i915, 217 const struct bdb_header *bdb) 218 { 219 const struct bdb_lvds_options *lvds_options; 220 int panel_type; 221 int drrs_mode; 222 int ret; 223 224 lvds_options = find_section(bdb, BDB_LVDS_OPTIONS); 225 if (!lvds_options) 226 return; 227 228 i915->vbt.lvds_dither = lvds_options->pixel_dither; 229 230 ret = intel_opregion_get_panel_type(i915); 231 if (ret >= 0) { 232 drm_WARN_ON(&i915->drm, ret > 0xf); 233 panel_type = ret; 234 drm_dbg_kms(&i915->drm, "Panel type: %d (OpRegion)\n", 235 panel_type); 236 } else { 237 if (lvds_options->panel_type > 0xf) { 238 drm_dbg_kms(&i915->drm, 239 "Invalid VBT panel type 0x%x\n", 240 lvds_options->panel_type); 241 return; 242 } 243 panel_type = lvds_options->panel_type; 244 drm_dbg_kms(&i915->drm, "Panel type: %d (VBT)\n", 245 panel_type); 246 } 247 248 i915->vbt.panel_type = panel_type; 249 250 drrs_mode = (lvds_options->dps_panel_type_bits 251 >> (panel_type * 2)) & MODE_MASK; 252 /* 253 * VBT has static DRRS = 0 and seamless DRRS = 2. 254 * The below piece of code is required to adjust vbt.drrs_type 255 * to match the enum drrs_support_type. 256 */ 257 switch (drrs_mode) { 258 case 0: 259 i915->vbt.drrs_type = STATIC_DRRS_SUPPORT; 260 drm_dbg_kms(&i915->drm, "DRRS supported mode is static\n"); 261 break; 262 case 2: 263 i915->vbt.drrs_type = SEAMLESS_DRRS_SUPPORT; 264 drm_dbg_kms(&i915->drm, 265 "DRRS supported mode is seamless\n"); 266 break; 267 default: 268 i915->vbt.drrs_type = DRRS_NOT_SUPPORTED; 269 drm_dbg_kms(&i915->drm, 270 "DRRS not supported (VBT input)\n"); 271 break; 272 } 273 } 274 275 /* Try to find integrated panel timing data */ 276 static void 277 parse_lfp_panel_dtd(struct drm_i915_private *i915, 278 const struct bdb_header *bdb) 279 { 280 const struct bdb_lvds_lfp_data *lvds_lfp_data; 281 const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs; 282 const struct lvds_dvo_timing *panel_dvo_timing; 283 const struct lvds_fp_timing *fp_timing; 284 struct drm_display_mode *panel_fixed_mode; 285 int panel_type = i915->vbt.panel_type; 286 287 lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA); 288 if (!lvds_lfp_data) 289 return; 290 291 lvds_lfp_data_ptrs = find_section(bdb, BDB_LVDS_LFP_DATA_PTRS); 292 if (!lvds_lfp_data_ptrs) 293 return; 294 295 panel_dvo_timing = get_lvds_dvo_timing(lvds_lfp_data, 296 lvds_lfp_data_ptrs, 297 panel_type); 298 299 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL); 300 if (!panel_fixed_mode) 301 return; 302 303 fill_detail_timing_data(panel_fixed_mode, panel_dvo_timing); 304 305 i915->vbt.lfp_lvds_vbt_mode = panel_fixed_mode; 306 307 drm_dbg_kms(&i915->drm, 308 "Found panel mode in BIOS VBT legacy lfp table:\n"); 309 drm_mode_debug_printmodeline(panel_fixed_mode); 310 311 fp_timing = get_lvds_fp_timing(bdb, lvds_lfp_data, 312 lvds_lfp_data_ptrs, 313 panel_type); 314 if (fp_timing) { 315 /* check the resolution, just to be sure */ 316 if (fp_timing->x_res == panel_fixed_mode->hdisplay && 317 fp_timing->y_res == panel_fixed_mode->vdisplay) { 318 i915->vbt.bios_lvds_val = fp_timing->lvds_reg_val; 319 drm_dbg_kms(&i915->drm, 320 "VBT initial LVDS value %x\n", 321 i915->vbt.bios_lvds_val); 322 } 323 } 324 } 325 326 static void 327 parse_generic_dtd(struct drm_i915_private *i915, 328 const struct bdb_header *bdb) 329 { 330 const struct bdb_generic_dtd *generic_dtd; 331 const struct generic_dtd_entry *dtd; 332 struct drm_display_mode *panel_fixed_mode; 333 int num_dtd; 334 335 generic_dtd = find_section(bdb, BDB_GENERIC_DTD); 336 if (!generic_dtd) 337 return; 338 339 if (generic_dtd->gdtd_size < sizeof(struct generic_dtd_entry)) { 340 drm_err(&i915->drm, "GDTD size %u is too small.\n", 341 generic_dtd->gdtd_size); 342 return; 343 } else if (generic_dtd->gdtd_size != 344 sizeof(struct generic_dtd_entry)) { 345 drm_err(&i915->drm, "Unexpected GDTD size %u\n", 346 generic_dtd->gdtd_size); 347 /* DTD has unknown fields, but keep going */ 348 } 349 350 num_dtd = (get_blocksize(generic_dtd) - 351 sizeof(struct bdb_generic_dtd)) / generic_dtd->gdtd_size; 352 if (i915->vbt.panel_type >= num_dtd) { 353 drm_err(&i915->drm, 354 "Panel type %d not found in table of %d DTD's\n", 355 i915->vbt.panel_type, num_dtd); 356 return; 357 } 358 359 dtd = &generic_dtd->dtd[i915->vbt.panel_type]; 360 361 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL); 362 if (!panel_fixed_mode) 363 return; 364 365 panel_fixed_mode->hdisplay = dtd->hactive; 366 panel_fixed_mode->hsync_start = 367 panel_fixed_mode->hdisplay + dtd->hfront_porch; 368 panel_fixed_mode->hsync_end = 369 panel_fixed_mode->hsync_start + dtd->hsync; 370 panel_fixed_mode->htotal = 371 panel_fixed_mode->hdisplay + dtd->hblank; 372 373 panel_fixed_mode->vdisplay = dtd->vactive; 374 panel_fixed_mode->vsync_start = 375 panel_fixed_mode->vdisplay + dtd->vfront_porch; 376 panel_fixed_mode->vsync_end = 377 panel_fixed_mode->vsync_start + dtd->vsync; 378 panel_fixed_mode->vtotal = 379 panel_fixed_mode->vdisplay + dtd->vblank; 380 381 panel_fixed_mode->clock = dtd->pixel_clock; 382 panel_fixed_mode->width_mm = dtd->width_mm; 383 panel_fixed_mode->height_mm = dtd->height_mm; 384 385 panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED; 386 drm_mode_set_name(panel_fixed_mode); 387 388 if (dtd->hsync_positive_polarity) 389 panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC; 390 else 391 panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC; 392 393 if (dtd->vsync_positive_polarity) 394 panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC; 395 else 396 panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC; 397 398 drm_dbg_kms(&i915->drm, 399 "Found panel mode in BIOS VBT generic dtd table:\n"); 400 drm_mode_debug_printmodeline(panel_fixed_mode); 401 402 i915->vbt.lfp_lvds_vbt_mode = panel_fixed_mode; 403 } 404 405 static void 406 parse_panel_dtd(struct drm_i915_private *i915, 407 const struct bdb_header *bdb) 408 { 409 /* 410 * Older VBTs provided provided DTD information for internal displays 411 * through the "LFP panel DTD" block (42). As of VBT revision 229, 412 * that block is now deprecated and DTD information should be provided 413 * via a newer "generic DTD" block (58). Just to be safe, we'll 414 * try the new generic DTD block first on VBT >= 229, but still fall 415 * back to trying the old LFP block if that fails. 416 */ 417 if (bdb->version >= 229) 418 parse_generic_dtd(i915, bdb); 419 if (!i915->vbt.lfp_lvds_vbt_mode) 420 parse_lfp_panel_dtd(i915, bdb); 421 } 422 423 static void 424 parse_lfp_backlight(struct drm_i915_private *i915, 425 const struct bdb_header *bdb) 426 { 427 const struct bdb_lfp_backlight_data *backlight_data; 428 const struct lfp_backlight_data_entry *entry; 429 int panel_type = i915->vbt.panel_type; 430 u16 level; 431 432 backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT); 433 if (!backlight_data) 434 return; 435 436 if (backlight_data->entry_size != sizeof(backlight_data->data[0])) { 437 drm_dbg_kms(&i915->drm, 438 "Unsupported backlight data entry size %u\n", 439 backlight_data->entry_size); 440 return; 441 } 442 443 entry = &backlight_data->data[panel_type]; 444 445 i915->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM; 446 if (!i915->vbt.backlight.present) { 447 drm_dbg_kms(&i915->drm, 448 "PWM backlight not present in VBT (type %u)\n", 449 entry->type); 450 return; 451 } 452 453 i915->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI; 454 if (bdb->version >= 191) { 455 size_t exp_size; 456 457 if (bdb->version >= 236) 458 exp_size = sizeof(struct bdb_lfp_backlight_data); 459 else if (bdb->version >= 234) 460 exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_234; 461 else 462 exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_191; 463 464 if (get_blocksize(backlight_data) >= exp_size) { 465 const struct lfp_backlight_control_method *method; 466 467 method = &backlight_data->backlight_control[panel_type]; 468 i915->vbt.backlight.type = method->type; 469 i915->vbt.backlight.controller = method->controller; 470 } 471 } 472 473 i915->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz; 474 i915->vbt.backlight.active_low_pwm = entry->active_low_pwm; 475 476 if (bdb->version >= 234) { 477 u16 min_level; 478 bool scale; 479 480 level = backlight_data->brightness_level[panel_type].level; 481 min_level = backlight_data->brightness_min_level[panel_type].level; 482 483 if (bdb->version >= 236) 484 scale = backlight_data->brightness_precision_bits[panel_type] == 16; 485 else 486 scale = level > 255; 487 488 if (scale) 489 min_level = min_level / 255; 490 491 if (min_level > 255) { 492 drm_warn(&i915->drm, "Brightness min level > 255\n"); 493 level = 255; 494 } 495 i915->vbt.backlight.min_brightness = min_level; 496 } else { 497 level = backlight_data->level[panel_type]; 498 i915->vbt.backlight.min_brightness = entry->min_brightness; 499 } 500 501 drm_dbg_kms(&i915->drm, 502 "VBT backlight PWM modulation frequency %u Hz, " 503 "active %s, min brightness %u, level %u, controller %u\n", 504 i915->vbt.backlight.pwm_freq_hz, 505 i915->vbt.backlight.active_low_pwm ? "low" : "high", 506 i915->vbt.backlight.min_brightness, 507 level, 508 i915->vbt.backlight.controller); 509 } 510 511 /* Try to find sdvo panel data */ 512 static void 513 parse_sdvo_panel_data(struct drm_i915_private *i915, 514 const struct bdb_header *bdb) 515 { 516 const struct bdb_sdvo_panel_dtds *dtds; 517 struct drm_display_mode *panel_fixed_mode; 518 int index; 519 520 index = i915->params.vbt_sdvo_panel_type; 521 if (index == -2) { 522 drm_dbg_kms(&i915->drm, 523 "Ignore SDVO panel mode from BIOS VBT tables.\n"); 524 return; 525 } 526 527 if (index == -1) { 528 const struct bdb_sdvo_lvds_options *sdvo_lvds_options; 529 530 sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS); 531 if (!sdvo_lvds_options) 532 return; 533 534 index = sdvo_lvds_options->panel_type; 535 } 536 537 dtds = find_section(bdb, BDB_SDVO_PANEL_DTDS); 538 if (!dtds) 539 return; 540 541 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL); 542 if (!panel_fixed_mode) 543 return; 544 545 fill_detail_timing_data(panel_fixed_mode, &dtds->dtds[index]); 546 547 i915->vbt.sdvo_lvds_vbt_mode = panel_fixed_mode; 548 549 drm_dbg_kms(&i915->drm, 550 "Found SDVO panel mode in BIOS VBT tables:\n"); 551 drm_mode_debug_printmodeline(panel_fixed_mode); 552 } 553 554 static int intel_bios_ssc_frequency(struct drm_i915_private *i915, 555 bool alternate) 556 { 557 switch (DISPLAY_VER(i915)) { 558 case 2: 559 return alternate ? 66667 : 48000; 560 case 3: 561 case 4: 562 return alternate ? 100000 : 96000; 563 default: 564 return alternate ? 100000 : 120000; 565 } 566 } 567 568 static void 569 parse_general_features(struct drm_i915_private *i915, 570 const struct bdb_header *bdb) 571 { 572 const struct bdb_general_features *general; 573 574 general = find_section(bdb, BDB_GENERAL_FEATURES); 575 if (!general) 576 return; 577 578 i915->vbt.int_tv_support = general->int_tv_support; 579 /* int_crt_support can't be trusted on earlier platforms */ 580 if (bdb->version >= 155 && 581 (HAS_DDI(i915) || IS_VALLEYVIEW(i915))) 582 i915->vbt.int_crt_support = general->int_crt_support; 583 i915->vbt.lvds_use_ssc = general->enable_ssc; 584 i915->vbt.lvds_ssc_freq = 585 intel_bios_ssc_frequency(i915, general->ssc_freq); 586 i915->vbt.display_clock_mode = general->display_clock_mode; 587 i915->vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted; 588 if (bdb->version >= 181) { 589 i915->vbt.orientation = general->rotate_180 ? 590 DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP : 591 DRM_MODE_PANEL_ORIENTATION_NORMAL; 592 } else { 593 i915->vbt.orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN; 594 } 595 drm_dbg_kms(&i915->drm, 596 "BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n", 597 i915->vbt.int_tv_support, 598 i915->vbt.int_crt_support, 599 i915->vbt.lvds_use_ssc, 600 i915->vbt.lvds_ssc_freq, 601 i915->vbt.display_clock_mode, 602 i915->vbt.fdi_rx_polarity_inverted); 603 } 604 605 static const struct child_device_config * 606 child_device_ptr(const struct bdb_general_definitions *defs, int i) 607 { 608 return (const void *) &defs->devices[i * defs->child_dev_size]; 609 } 610 611 static void 612 parse_sdvo_device_mapping(struct drm_i915_private *i915) 613 { 614 struct sdvo_device_mapping *mapping; 615 const struct intel_bios_encoder_data *devdata; 616 const struct child_device_config *child; 617 int count = 0; 618 619 /* 620 * Only parse SDVO mappings on gens that could have SDVO. This isn't 621 * accurate and doesn't have to be, as long as it's not too strict. 622 */ 623 if (!IS_DISPLAY_VER(i915, 3, 7)) { 624 drm_dbg_kms(&i915->drm, "Skipping SDVO device mapping\n"); 625 return; 626 } 627 628 list_for_each_entry(devdata, &i915->vbt.display_devices, node) { 629 child = &devdata->child; 630 631 if (child->slave_addr != SLAVE_ADDR1 && 632 child->slave_addr != SLAVE_ADDR2) { 633 /* 634 * If the slave address is neither 0x70 nor 0x72, 635 * it is not a SDVO device. Skip it. 636 */ 637 continue; 638 } 639 if (child->dvo_port != DEVICE_PORT_DVOB && 640 child->dvo_port != DEVICE_PORT_DVOC) { 641 /* skip the incorrect SDVO port */ 642 drm_dbg_kms(&i915->drm, 643 "Incorrect SDVO port. Skip it\n"); 644 continue; 645 } 646 drm_dbg_kms(&i915->drm, 647 "the SDVO device with slave addr %2x is found on" 648 " %s port\n", 649 child->slave_addr, 650 (child->dvo_port == DEVICE_PORT_DVOB) ? 651 "SDVOB" : "SDVOC"); 652 mapping = &i915->vbt.sdvo_mappings[child->dvo_port - 1]; 653 if (!mapping->initialized) { 654 mapping->dvo_port = child->dvo_port; 655 mapping->slave_addr = child->slave_addr; 656 mapping->dvo_wiring = child->dvo_wiring; 657 mapping->ddc_pin = child->ddc_pin; 658 mapping->i2c_pin = child->i2c_pin; 659 mapping->initialized = 1; 660 drm_dbg_kms(&i915->drm, 661 "SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d\n", 662 mapping->dvo_port, mapping->slave_addr, 663 mapping->dvo_wiring, mapping->ddc_pin, 664 mapping->i2c_pin); 665 } else { 666 drm_dbg_kms(&i915->drm, 667 "Maybe one SDVO port is shared by " 668 "two SDVO device.\n"); 669 } 670 if (child->slave2_addr) { 671 /* Maybe this is a SDVO device with multiple inputs */ 672 /* And the mapping info is not added */ 673 drm_dbg_kms(&i915->drm, 674 "there exists the slave2_addr. Maybe this" 675 " is a SDVO device with multiple inputs.\n"); 676 } 677 count++; 678 } 679 680 if (!count) { 681 /* No SDVO device info is found */ 682 drm_dbg_kms(&i915->drm, 683 "No SDVO device info is found in VBT\n"); 684 } 685 } 686 687 static void 688 parse_driver_features(struct drm_i915_private *i915, 689 const struct bdb_header *bdb) 690 { 691 const struct bdb_driver_features *driver; 692 693 driver = find_section(bdb, BDB_DRIVER_FEATURES); 694 if (!driver) 695 return; 696 697 if (DISPLAY_VER(i915) >= 5) { 698 /* 699 * Note that we consider BDB_DRIVER_FEATURE_INT_SDVO_LVDS 700 * to mean "eDP". The VBT spec doesn't agree with that 701 * interpretation, but real world VBTs seem to. 702 */ 703 if (driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS) 704 i915->vbt.int_lvds_support = 0; 705 } else { 706 /* 707 * FIXME it's not clear which BDB version has the LVDS config 708 * bits defined. Revision history in the VBT spec says: 709 * "0.92 | Add two definitions for VBT value of LVDS Active 710 * Config (00b and 11b values defined) | 06/13/2005" 711 * but does not the specify the BDB version. 712 * 713 * So far version 134 (on i945gm) is the oldest VBT observed 714 * in the wild with the bits correctly populated. Version 715 * 108 (on i85x) does not have the bits correctly populated. 716 */ 717 if (bdb->version >= 134 && 718 driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS && 719 driver->lvds_config != BDB_DRIVER_FEATURE_INT_SDVO_LVDS) 720 i915->vbt.int_lvds_support = 0; 721 } 722 723 if (bdb->version < 228) { 724 drm_dbg_kms(&i915->drm, "DRRS State Enabled:%d\n", 725 driver->drrs_enabled); 726 /* 727 * If DRRS is not supported, drrs_type has to be set to 0. 728 * This is because, VBT is configured in such a way that 729 * static DRRS is 0 and DRRS not supported is represented by 730 * driver->drrs_enabled=false 731 */ 732 if (!driver->drrs_enabled) 733 i915->vbt.drrs_type = DRRS_NOT_SUPPORTED; 734 735 i915->vbt.psr.enable = driver->psr_enabled; 736 } 737 } 738 739 static void 740 parse_power_conservation_features(struct drm_i915_private *i915, 741 const struct bdb_header *bdb) 742 { 743 const struct bdb_lfp_power *power; 744 u8 panel_type = i915->vbt.panel_type; 745 746 if (bdb->version < 228) 747 return; 748 749 power = find_section(bdb, BDB_LFP_POWER); 750 if (!power) 751 return; 752 753 i915->vbt.psr.enable = power->psr & BIT(panel_type); 754 755 /* 756 * If DRRS is not supported, drrs_type has to be set to 0. 757 * This is because, VBT is configured in such a way that 758 * static DRRS is 0 and DRRS not supported is represented by 759 * power->drrs & BIT(panel_type)=false 760 */ 761 if (!(power->drrs & BIT(panel_type))) 762 i915->vbt.drrs_type = DRRS_NOT_SUPPORTED; 763 764 if (bdb->version >= 232) 765 i915->vbt.edp.hobl = power->hobl & BIT(panel_type); 766 } 767 768 static void 769 parse_edp(struct drm_i915_private *i915, const struct bdb_header *bdb) 770 { 771 const struct bdb_edp *edp; 772 const struct edp_power_seq *edp_pps; 773 const struct edp_fast_link_params *edp_link_params; 774 int panel_type = i915->vbt.panel_type; 775 776 edp = find_section(bdb, BDB_EDP); 777 if (!edp) 778 return; 779 780 switch ((edp->color_depth >> (panel_type * 2)) & 3) { 781 case EDP_18BPP: 782 i915->vbt.edp.bpp = 18; 783 break; 784 case EDP_24BPP: 785 i915->vbt.edp.bpp = 24; 786 break; 787 case EDP_30BPP: 788 i915->vbt.edp.bpp = 30; 789 break; 790 } 791 792 /* Get the eDP sequencing and link info */ 793 edp_pps = &edp->power_seqs[panel_type]; 794 edp_link_params = &edp->fast_link_params[panel_type]; 795 796 i915->vbt.edp.pps = *edp_pps; 797 798 switch (edp_link_params->rate) { 799 case EDP_RATE_1_62: 800 i915->vbt.edp.rate = DP_LINK_BW_1_62; 801 break; 802 case EDP_RATE_2_7: 803 i915->vbt.edp.rate = DP_LINK_BW_2_7; 804 break; 805 default: 806 drm_dbg_kms(&i915->drm, 807 "VBT has unknown eDP link rate value %u\n", 808 edp_link_params->rate); 809 break; 810 } 811 812 switch (edp_link_params->lanes) { 813 case EDP_LANE_1: 814 i915->vbt.edp.lanes = 1; 815 break; 816 case EDP_LANE_2: 817 i915->vbt.edp.lanes = 2; 818 break; 819 case EDP_LANE_4: 820 i915->vbt.edp.lanes = 4; 821 break; 822 default: 823 drm_dbg_kms(&i915->drm, 824 "VBT has unknown eDP lane count value %u\n", 825 edp_link_params->lanes); 826 break; 827 } 828 829 switch (edp_link_params->preemphasis) { 830 case EDP_PREEMPHASIS_NONE: 831 i915->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0; 832 break; 833 case EDP_PREEMPHASIS_3_5dB: 834 i915->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1; 835 break; 836 case EDP_PREEMPHASIS_6dB: 837 i915->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2; 838 break; 839 case EDP_PREEMPHASIS_9_5dB: 840 i915->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3; 841 break; 842 default: 843 drm_dbg_kms(&i915->drm, 844 "VBT has unknown eDP pre-emphasis value %u\n", 845 edp_link_params->preemphasis); 846 break; 847 } 848 849 switch (edp_link_params->vswing) { 850 case EDP_VSWING_0_4V: 851 i915->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 852 break; 853 case EDP_VSWING_0_6V: 854 i915->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1; 855 break; 856 case EDP_VSWING_0_8V: 857 i915->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 858 break; 859 case EDP_VSWING_1_2V: 860 i915->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 861 break; 862 default: 863 drm_dbg_kms(&i915->drm, 864 "VBT has unknown eDP voltage swing value %u\n", 865 edp_link_params->vswing); 866 break; 867 } 868 869 if (bdb->version >= 173) { 870 u8 vswing; 871 872 /* Don't read from VBT if module parameter has valid value*/ 873 if (i915->params.edp_vswing) { 874 i915->vbt.edp.low_vswing = 875 i915->params.edp_vswing == 1; 876 } else { 877 vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF; 878 i915->vbt.edp.low_vswing = vswing == 0; 879 } 880 } 881 } 882 883 static void 884 parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb) 885 { 886 const struct bdb_psr *psr; 887 const struct psr_table *psr_table; 888 int panel_type = i915->vbt.panel_type; 889 890 psr = find_section(bdb, BDB_PSR); 891 if (!psr) { 892 drm_dbg_kms(&i915->drm, "No PSR BDB found.\n"); 893 return; 894 } 895 896 psr_table = &psr->psr_table[panel_type]; 897 898 i915->vbt.psr.full_link = psr_table->full_link; 899 i915->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup; 900 901 /* Allowed VBT values goes from 0 to 15 */ 902 i915->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 : 903 psr_table->idle_frames > 15 ? 15 : psr_table->idle_frames; 904 905 switch (psr_table->lines_to_wait) { 906 case 0: 907 i915->vbt.psr.lines_to_wait = PSR_0_LINES_TO_WAIT; 908 break; 909 case 1: 910 i915->vbt.psr.lines_to_wait = PSR_1_LINE_TO_WAIT; 911 break; 912 case 2: 913 i915->vbt.psr.lines_to_wait = PSR_4_LINES_TO_WAIT; 914 break; 915 case 3: 916 i915->vbt.psr.lines_to_wait = PSR_8_LINES_TO_WAIT; 917 break; 918 default: 919 drm_dbg_kms(&i915->drm, 920 "VBT has unknown PSR lines to wait %u\n", 921 psr_table->lines_to_wait); 922 break; 923 } 924 925 /* 926 * New psr options 0=500us, 1=100us, 2=2500us, 3=0us 927 * Old decimal value is wake up time in multiples of 100 us. 928 */ 929 if (bdb->version >= 205 && 930 (DISPLAY_VER(i915) >= 9 && !IS_BROXTON(i915))) { 931 switch (psr_table->tp1_wakeup_time) { 932 case 0: 933 i915->vbt.psr.tp1_wakeup_time_us = 500; 934 break; 935 case 1: 936 i915->vbt.psr.tp1_wakeup_time_us = 100; 937 break; 938 case 3: 939 i915->vbt.psr.tp1_wakeup_time_us = 0; 940 break; 941 default: 942 drm_dbg_kms(&i915->drm, 943 "VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n", 944 psr_table->tp1_wakeup_time); 945 fallthrough; 946 case 2: 947 i915->vbt.psr.tp1_wakeup_time_us = 2500; 948 break; 949 } 950 951 switch (psr_table->tp2_tp3_wakeup_time) { 952 case 0: 953 i915->vbt.psr.tp2_tp3_wakeup_time_us = 500; 954 break; 955 case 1: 956 i915->vbt.psr.tp2_tp3_wakeup_time_us = 100; 957 break; 958 case 3: 959 i915->vbt.psr.tp2_tp3_wakeup_time_us = 0; 960 break; 961 default: 962 drm_dbg_kms(&i915->drm, 963 "VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n", 964 psr_table->tp2_tp3_wakeup_time); 965 fallthrough; 966 case 2: 967 i915->vbt.psr.tp2_tp3_wakeup_time_us = 2500; 968 break; 969 } 970 } else { 971 i915->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100; 972 i915->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100; 973 } 974 975 if (bdb->version >= 226) { 976 u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time; 977 978 wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3; 979 switch (wakeup_time) { 980 case 0: 981 wakeup_time = 500; 982 break; 983 case 1: 984 wakeup_time = 100; 985 break; 986 case 3: 987 wakeup_time = 50; 988 break; 989 default: 990 case 2: 991 wakeup_time = 2500; 992 break; 993 } 994 i915->vbt.psr.psr2_tp2_tp3_wakeup_time_us = wakeup_time; 995 } else { 996 /* Reusing PSR1 wakeup time for PSR2 in older VBTs */ 997 i915->vbt.psr.psr2_tp2_tp3_wakeup_time_us = i915->vbt.psr.tp2_tp3_wakeup_time_us; 998 } 999 } 1000 1001 static void parse_dsi_backlight_ports(struct drm_i915_private *i915, 1002 u16 version, enum port port) 1003 { 1004 if (!i915->vbt.dsi.config->dual_link || version < 197) { 1005 i915->vbt.dsi.bl_ports = BIT(port); 1006 if (i915->vbt.dsi.config->cabc_supported) 1007 i915->vbt.dsi.cabc_ports = BIT(port); 1008 1009 return; 1010 } 1011 1012 switch (i915->vbt.dsi.config->dl_dcs_backlight_ports) { 1013 case DL_DCS_PORT_A: 1014 i915->vbt.dsi.bl_ports = BIT(PORT_A); 1015 break; 1016 case DL_DCS_PORT_C: 1017 i915->vbt.dsi.bl_ports = BIT(PORT_C); 1018 break; 1019 default: 1020 case DL_DCS_PORT_A_AND_C: 1021 i915->vbt.dsi.bl_ports = BIT(PORT_A) | BIT(PORT_C); 1022 break; 1023 } 1024 1025 if (!i915->vbt.dsi.config->cabc_supported) 1026 return; 1027 1028 switch (i915->vbt.dsi.config->dl_dcs_cabc_ports) { 1029 case DL_DCS_PORT_A: 1030 i915->vbt.dsi.cabc_ports = BIT(PORT_A); 1031 break; 1032 case DL_DCS_PORT_C: 1033 i915->vbt.dsi.cabc_ports = BIT(PORT_C); 1034 break; 1035 default: 1036 case DL_DCS_PORT_A_AND_C: 1037 i915->vbt.dsi.cabc_ports = 1038 BIT(PORT_A) | BIT(PORT_C); 1039 break; 1040 } 1041 } 1042 1043 static void 1044 parse_mipi_config(struct drm_i915_private *i915, 1045 const struct bdb_header *bdb) 1046 { 1047 const struct bdb_mipi_config *start; 1048 const struct mipi_config *config; 1049 const struct mipi_pps_data *pps; 1050 int panel_type = i915->vbt.panel_type; 1051 enum port port; 1052 1053 /* parse MIPI blocks only if LFP type is MIPI */ 1054 if (!intel_bios_is_dsi_present(i915, &port)) 1055 return; 1056 1057 /* Initialize this to undefined indicating no generic MIPI support */ 1058 i915->vbt.dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID; 1059 1060 /* Block #40 is already parsed and panel_fixed_mode is 1061 * stored in i915->lfp_lvds_vbt_mode 1062 * resuse this when needed 1063 */ 1064 1065 /* Parse #52 for panel index used from panel_type already 1066 * parsed 1067 */ 1068 start = find_section(bdb, BDB_MIPI_CONFIG); 1069 if (!start) { 1070 drm_dbg_kms(&i915->drm, "No MIPI config BDB found"); 1071 return; 1072 } 1073 1074 drm_dbg(&i915->drm, "Found MIPI Config block, panel index = %d\n", 1075 panel_type); 1076 1077 /* 1078 * get hold of the correct configuration block and pps data as per 1079 * the panel_type as index 1080 */ 1081 config = &start->config[panel_type]; 1082 pps = &start->pps[panel_type]; 1083 1084 /* store as of now full data. Trim when we realise all is not needed */ 1085 i915->vbt.dsi.config = kmemdup(config, sizeof(struct mipi_config), GFP_KERNEL); 1086 if (!i915->vbt.dsi.config) 1087 return; 1088 1089 i915->vbt.dsi.pps = kmemdup(pps, sizeof(struct mipi_pps_data), GFP_KERNEL); 1090 if (!i915->vbt.dsi.pps) { 1091 kfree(i915->vbt.dsi.config); 1092 return; 1093 } 1094 1095 parse_dsi_backlight_ports(i915, bdb->version, port); 1096 1097 /* FIXME is the 90 vs. 270 correct? */ 1098 switch (config->rotation) { 1099 case ENABLE_ROTATION_0: 1100 /* 1101 * Most (all?) VBTs claim 0 degrees despite having 1102 * an upside down panel, thus we do not trust this. 1103 */ 1104 i915->vbt.dsi.orientation = 1105 DRM_MODE_PANEL_ORIENTATION_UNKNOWN; 1106 break; 1107 case ENABLE_ROTATION_90: 1108 i915->vbt.dsi.orientation = 1109 DRM_MODE_PANEL_ORIENTATION_RIGHT_UP; 1110 break; 1111 case ENABLE_ROTATION_180: 1112 i915->vbt.dsi.orientation = 1113 DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP; 1114 break; 1115 case ENABLE_ROTATION_270: 1116 i915->vbt.dsi.orientation = 1117 DRM_MODE_PANEL_ORIENTATION_LEFT_UP; 1118 break; 1119 } 1120 1121 /* We have mandatory mipi config blocks. Initialize as generic panel */ 1122 i915->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID; 1123 } 1124 1125 /* Find the sequence block and size for the given panel. */ 1126 static const u8 * 1127 find_panel_sequence_block(const struct bdb_mipi_sequence *sequence, 1128 u16 panel_id, u32 *seq_size) 1129 { 1130 u32 total = get_blocksize(sequence); 1131 const u8 *data = &sequence->data[0]; 1132 u8 current_id; 1133 u32 current_size; 1134 int header_size = sequence->version >= 3 ? 5 : 3; 1135 int index = 0; 1136 int i; 1137 1138 /* skip new block size */ 1139 if (sequence->version >= 3) 1140 data += 4; 1141 1142 for (i = 0; i < MAX_MIPI_CONFIGURATIONS && index < total; i++) { 1143 if (index + header_size > total) { 1144 DRM_ERROR("Invalid sequence block (header)\n"); 1145 return NULL; 1146 } 1147 1148 current_id = *(data + index); 1149 if (sequence->version >= 3) 1150 current_size = *((const u32 *)(data + index + 1)); 1151 else 1152 current_size = *((const u16 *)(data + index + 1)); 1153 1154 index += header_size; 1155 1156 if (index + current_size > total) { 1157 DRM_ERROR("Invalid sequence block\n"); 1158 return NULL; 1159 } 1160 1161 if (current_id == panel_id) { 1162 *seq_size = current_size; 1163 return data + index; 1164 } 1165 1166 index += current_size; 1167 } 1168 1169 DRM_ERROR("Sequence block detected but no valid configuration\n"); 1170 1171 return NULL; 1172 } 1173 1174 static int goto_next_sequence(const u8 *data, int index, int total) 1175 { 1176 u16 len; 1177 1178 /* Skip Sequence Byte. */ 1179 for (index = index + 1; index < total; index += len) { 1180 u8 operation_byte = *(data + index); 1181 index++; 1182 1183 switch (operation_byte) { 1184 case MIPI_SEQ_ELEM_END: 1185 return index; 1186 case MIPI_SEQ_ELEM_SEND_PKT: 1187 if (index + 4 > total) 1188 return 0; 1189 1190 len = *((const u16 *)(data + index + 2)) + 4; 1191 break; 1192 case MIPI_SEQ_ELEM_DELAY: 1193 len = 4; 1194 break; 1195 case MIPI_SEQ_ELEM_GPIO: 1196 len = 2; 1197 break; 1198 case MIPI_SEQ_ELEM_I2C: 1199 if (index + 7 > total) 1200 return 0; 1201 len = *(data + index + 6) + 7; 1202 break; 1203 default: 1204 DRM_ERROR("Unknown operation byte\n"); 1205 return 0; 1206 } 1207 } 1208 1209 return 0; 1210 } 1211 1212 static int goto_next_sequence_v3(const u8 *data, int index, int total) 1213 { 1214 int seq_end; 1215 u16 len; 1216 u32 size_of_sequence; 1217 1218 /* 1219 * Could skip sequence based on Size of Sequence alone, but also do some 1220 * checking on the structure. 1221 */ 1222 if (total < 5) { 1223 DRM_ERROR("Too small sequence size\n"); 1224 return 0; 1225 } 1226 1227 /* Skip Sequence Byte. */ 1228 index++; 1229 1230 /* 1231 * Size of Sequence. Excludes the Sequence Byte and the size itself, 1232 * includes MIPI_SEQ_ELEM_END byte, excludes the final MIPI_SEQ_END 1233 * byte. 1234 */ 1235 size_of_sequence = *((const u32 *)(data + index)); 1236 index += 4; 1237 1238 seq_end = index + size_of_sequence; 1239 if (seq_end > total) { 1240 DRM_ERROR("Invalid sequence size\n"); 1241 return 0; 1242 } 1243 1244 for (; index < total; index += len) { 1245 u8 operation_byte = *(data + index); 1246 index++; 1247 1248 if (operation_byte == MIPI_SEQ_ELEM_END) { 1249 if (index != seq_end) { 1250 DRM_ERROR("Invalid element structure\n"); 1251 return 0; 1252 } 1253 return index; 1254 } 1255 1256 len = *(data + index); 1257 index++; 1258 1259 /* 1260 * FIXME: Would be nice to check elements like for v1/v2 in 1261 * goto_next_sequence() above. 1262 */ 1263 switch (operation_byte) { 1264 case MIPI_SEQ_ELEM_SEND_PKT: 1265 case MIPI_SEQ_ELEM_DELAY: 1266 case MIPI_SEQ_ELEM_GPIO: 1267 case MIPI_SEQ_ELEM_I2C: 1268 case MIPI_SEQ_ELEM_SPI: 1269 case MIPI_SEQ_ELEM_PMIC: 1270 break; 1271 default: 1272 DRM_ERROR("Unknown operation byte %u\n", 1273 operation_byte); 1274 break; 1275 } 1276 } 1277 1278 return 0; 1279 } 1280 1281 /* 1282 * Get len of pre-fixed deassert fragment from a v1 init OTP sequence, 1283 * skip all delay + gpio operands and stop at the first DSI packet op. 1284 */ 1285 static int get_init_otp_deassert_fragment_len(struct drm_i915_private *i915) 1286 { 1287 const u8 *data = i915->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP]; 1288 int index, len; 1289 1290 if (drm_WARN_ON(&i915->drm, 1291 !data || i915->vbt.dsi.seq_version != 1)) 1292 return 0; 1293 1294 /* index = 1 to skip sequence byte */ 1295 for (index = 1; data[index] != MIPI_SEQ_ELEM_END; index += len) { 1296 switch (data[index]) { 1297 case MIPI_SEQ_ELEM_SEND_PKT: 1298 return index == 1 ? 0 : index; 1299 case MIPI_SEQ_ELEM_DELAY: 1300 len = 5; /* 1 byte for operand + uint32 */ 1301 break; 1302 case MIPI_SEQ_ELEM_GPIO: 1303 len = 3; /* 1 byte for op, 1 for gpio_nr, 1 for value */ 1304 break; 1305 default: 1306 return 0; 1307 } 1308 } 1309 1310 return 0; 1311 } 1312 1313 /* 1314 * Some v1 VBT MIPI sequences do the deassert in the init OTP sequence. 1315 * The deassert must be done before calling intel_dsi_device_ready, so for 1316 * these devices we split the init OTP sequence into a deassert sequence and 1317 * the actual init OTP part. 1318 */ 1319 static void fixup_mipi_sequences(struct drm_i915_private *i915) 1320 { 1321 u8 *init_otp; 1322 int len; 1323 1324 /* Limit this to VLV for now. */ 1325 if (!IS_VALLEYVIEW(i915)) 1326 return; 1327 1328 /* Limit this to v1 vid-mode sequences */ 1329 if (i915->vbt.dsi.config->is_cmd_mode || 1330 i915->vbt.dsi.seq_version != 1) 1331 return; 1332 1333 /* Only do this if there are otp and assert seqs and no deassert seq */ 1334 if (!i915->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] || 1335 !i915->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET] || 1336 i915->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET]) 1337 return; 1338 1339 /* The deassert-sequence ends at the first DSI packet */ 1340 len = get_init_otp_deassert_fragment_len(i915); 1341 if (!len) 1342 return; 1343 1344 drm_dbg_kms(&i915->drm, 1345 "Using init OTP fragment to deassert reset\n"); 1346 1347 /* Copy the fragment, update seq byte and terminate it */ 1348 init_otp = (u8 *)i915->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP]; 1349 i915->vbt.dsi.deassert_seq = kmemdup(init_otp, len + 1, GFP_KERNEL); 1350 if (!i915->vbt.dsi.deassert_seq) 1351 return; 1352 i915->vbt.dsi.deassert_seq[0] = MIPI_SEQ_DEASSERT_RESET; 1353 i915->vbt.dsi.deassert_seq[len] = MIPI_SEQ_ELEM_END; 1354 /* Use the copy for deassert */ 1355 i915->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET] = 1356 i915->vbt.dsi.deassert_seq; 1357 /* Replace the last byte of the fragment with init OTP seq byte */ 1358 init_otp[len - 1] = MIPI_SEQ_INIT_OTP; 1359 /* And make MIPI_MIPI_SEQ_INIT_OTP point to it */ 1360 i915->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] = init_otp + len - 1; 1361 } 1362 1363 static void 1364 parse_mipi_sequence(struct drm_i915_private *i915, 1365 const struct bdb_header *bdb) 1366 { 1367 int panel_type = i915->vbt.panel_type; 1368 const struct bdb_mipi_sequence *sequence; 1369 const u8 *seq_data; 1370 u32 seq_size; 1371 u8 *data; 1372 int index = 0; 1373 1374 /* Only our generic panel driver uses the sequence block. */ 1375 if (i915->vbt.dsi.panel_id != MIPI_DSI_GENERIC_PANEL_ID) 1376 return; 1377 1378 sequence = find_section(bdb, BDB_MIPI_SEQUENCE); 1379 if (!sequence) { 1380 drm_dbg_kms(&i915->drm, 1381 "No MIPI Sequence found, parsing complete\n"); 1382 return; 1383 } 1384 1385 /* Fail gracefully for forward incompatible sequence block. */ 1386 if (sequence->version >= 4) { 1387 drm_err(&i915->drm, 1388 "Unable to parse MIPI Sequence Block v%u\n", 1389 sequence->version); 1390 return; 1391 } 1392 1393 drm_dbg(&i915->drm, "Found MIPI sequence block v%u\n", 1394 sequence->version); 1395 1396 seq_data = find_panel_sequence_block(sequence, panel_type, &seq_size); 1397 if (!seq_data) 1398 return; 1399 1400 data = kmemdup(seq_data, seq_size, GFP_KERNEL); 1401 if (!data) 1402 return; 1403 1404 /* Parse the sequences, store pointers to each sequence. */ 1405 for (;;) { 1406 u8 seq_id = *(data + index); 1407 if (seq_id == MIPI_SEQ_END) 1408 break; 1409 1410 if (seq_id >= MIPI_SEQ_MAX) { 1411 drm_err(&i915->drm, "Unknown sequence %u\n", 1412 seq_id); 1413 goto err; 1414 } 1415 1416 /* Log about presence of sequences we won't run. */ 1417 if (seq_id == MIPI_SEQ_TEAR_ON || seq_id == MIPI_SEQ_TEAR_OFF) 1418 drm_dbg_kms(&i915->drm, 1419 "Unsupported sequence %u\n", seq_id); 1420 1421 i915->vbt.dsi.sequence[seq_id] = data + index; 1422 1423 if (sequence->version >= 3) 1424 index = goto_next_sequence_v3(data, index, seq_size); 1425 else 1426 index = goto_next_sequence(data, index, seq_size); 1427 if (!index) { 1428 drm_err(&i915->drm, "Invalid sequence %u\n", 1429 seq_id); 1430 goto err; 1431 } 1432 } 1433 1434 i915->vbt.dsi.data = data; 1435 i915->vbt.dsi.size = seq_size; 1436 i915->vbt.dsi.seq_version = sequence->version; 1437 1438 fixup_mipi_sequences(i915); 1439 1440 drm_dbg(&i915->drm, "MIPI related VBT parsing complete\n"); 1441 return; 1442 1443 err: 1444 kfree(data); 1445 memset(i915->vbt.dsi.sequence, 0, sizeof(i915->vbt.dsi.sequence)); 1446 } 1447 1448 static void 1449 parse_compression_parameters(struct drm_i915_private *i915, 1450 const struct bdb_header *bdb) 1451 { 1452 const struct bdb_compression_parameters *params; 1453 struct intel_bios_encoder_data *devdata; 1454 const struct child_device_config *child; 1455 u16 block_size; 1456 int index; 1457 1458 if (bdb->version < 198) 1459 return; 1460 1461 params = find_section(bdb, BDB_COMPRESSION_PARAMETERS); 1462 if (params) { 1463 /* Sanity checks */ 1464 if (params->entry_size != sizeof(params->data[0])) { 1465 drm_dbg_kms(&i915->drm, 1466 "VBT: unsupported compression param entry size\n"); 1467 return; 1468 } 1469 1470 block_size = get_blocksize(params); 1471 if (block_size < sizeof(*params)) { 1472 drm_dbg_kms(&i915->drm, 1473 "VBT: expected 16 compression param entries\n"); 1474 return; 1475 } 1476 } 1477 1478 list_for_each_entry(devdata, &i915->vbt.display_devices, node) { 1479 child = &devdata->child; 1480 1481 if (!child->compression_enable) 1482 continue; 1483 1484 if (!params) { 1485 drm_dbg_kms(&i915->drm, 1486 "VBT: compression params not available\n"); 1487 continue; 1488 } 1489 1490 if (child->compression_method_cps) { 1491 drm_dbg_kms(&i915->drm, 1492 "VBT: CPS compression not supported\n"); 1493 continue; 1494 } 1495 1496 index = child->compression_structure_index; 1497 1498 devdata->dsc = kmemdup(¶ms->data[index], 1499 sizeof(*devdata->dsc), GFP_KERNEL); 1500 } 1501 } 1502 1503 static u8 translate_iboost(u8 val) 1504 { 1505 static const u8 mapping[] = { 1, 3, 7 }; /* See VBT spec */ 1506 1507 if (val >= ARRAY_SIZE(mapping)) { 1508 DRM_DEBUG_KMS("Unsupported I_boost value found in VBT (%d), display may not work properly\n", val); 1509 return 0; 1510 } 1511 return mapping[val]; 1512 } 1513 1514 static enum port get_port_by_ddc_pin(struct drm_i915_private *i915, u8 ddc_pin) 1515 { 1516 const struct ddi_vbt_port_info *info; 1517 enum port port; 1518 1519 if (!ddc_pin) 1520 return PORT_NONE; 1521 1522 for_each_port(port) { 1523 info = &i915->vbt.ddi_port_info[port]; 1524 1525 if (info->devdata && ddc_pin == info->alternate_ddc_pin) 1526 return port; 1527 } 1528 1529 return PORT_NONE; 1530 } 1531 1532 static void sanitize_ddc_pin(struct drm_i915_private *i915, 1533 enum port port) 1534 { 1535 struct ddi_vbt_port_info *info = &i915->vbt.ddi_port_info[port]; 1536 struct child_device_config *child; 1537 enum port p; 1538 1539 p = get_port_by_ddc_pin(i915, info->alternate_ddc_pin); 1540 if (p == PORT_NONE) 1541 return; 1542 1543 drm_dbg_kms(&i915->drm, 1544 "port %c trying to use the same DDC pin (0x%x) as port %c, " 1545 "disabling port %c DVI/HDMI support\n", 1546 port_name(port), info->alternate_ddc_pin, 1547 port_name(p), port_name(p)); 1548 1549 /* 1550 * If we have multiple ports supposedly sharing the pin, then dvi/hdmi 1551 * couldn't exist on the shared port. Otherwise they share the same ddc 1552 * pin and system couldn't communicate with them separately. 1553 * 1554 * Give inverse child device order the priority, last one wins. Yes, 1555 * there are real machines (eg. Asrock B250M-HDV) where VBT has both 1556 * port A and port E with the same AUX ch and we must pick port E :( 1557 */ 1558 info = &i915->vbt.ddi_port_info[p]; 1559 child = &info->devdata->child; 1560 1561 child->device_type &= ~DEVICE_TYPE_TMDS_DVI_SIGNALING; 1562 child->device_type |= DEVICE_TYPE_NOT_HDMI_OUTPUT; 1563 1564 info->alternate_ddc_pin = 0; 1565 } 1566 1567 static enum port get_port_by_aux_ch(struct drm_i915_private *i915, u8 aux_ch) 1568 { 1569 const struct ddi_vbt_port_info *info; 1570 enum port port; 1571 1572 if (!aux_ch) 1573 return PORT_NONE; 1574 1575 for_each_port(port) { 1576 info = &i915->vbt.ddi_port_info[port]; 1577 1578 if (info->devdata && aux_ch == info->alternate_aux_channel) 1579 return port; 1580 } 1581 1582 return PORT_NONE; 1583 } 1584 1585 static void sanitize_aux_ch(struct drm_i915_private *i915, 1586 enum port port) 1587 { 1588 struct ddi_vbt_port_info *info = &i915->vbt.ddi_port_info[port]; 1589 struct child_device_config *child; 1590 enum port p; 1591 1592 p = get_port_by_aux_ch(i915, info->alternate_aux_channel); 1593 if (p == PORT_NONE) 1594 return; 1595 1596 drm_dbg_kms(&i915->drm, 1597 "port %c trying to use the same AUX CH (0x%x) as port %c, " 1598 "disabling port %c DP support\n", 1599 port_name(port), info->alternate_aux_channel, 1600 port_name(p), port_name(p)); 1601 1602 /* 1603 * If we have multiple ports supposedly sharing the aux channel, then DP 1604 * couldn't exist on the shared port. Otherwise they share the same aux 1605 * channel and system couldn't communicate with them separately. 1606 * 1607 * Give inverse child device order the priority, last one wins. Yes, 1608 * there are real machines (eg. Asrock B250M-HDV) where VBT has both 1609 * port A and port E with the same AUX ch and we must pick port E :( 1610 */ 1611 info = &i915->vbt.ddi_port_info[p]; 1612 child = &info->devdata->child; 1613 1614 child->device_type &= ~DEVICE_TYPE_DISPLAYPORT_OUTPUT; 1615 info->alternate_aux_channel = 0; 1616 } 1617 1618 static const u8 cnp_ddc_pin_map[] = { 1619 [0] = 0, /* N/A */ 1620 [DDC_BUS_DDI_B] = GMBUS_PIN_1_BXT, 1621 [DDC_BUS_DDI_C] = GMBUS_PIN_2_BXT, 1622 [DDC_BUS_DDI_D] = GMBUS_PIN_4_CNP, /* sic */ 1623 [DDC_BUS_DDI_F] = GMBUS_PIN_3_BXT, /* sic */ 1624 }; 1625 1626 static const u8 icp_ddc_pin_map[] = { 1627 [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT, 1628 [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT, 1629 [TGL_DDC_BUS_DDI_C] = GMBUS_PIN_3_BXT, 1630 [ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP, 1631 [ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP, 1632 [ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP, 1633 [ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP, 1634 [TGL_DDC_BUS_PORT_5] = GMBUS_PIN_13_TC5_TGP, 1635 [TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP, 1636 }; 1637 1638 static const u8 rkl_pch_tgp_ddc_pin_map[] = { 1639 [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT, 1640 [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT, 1641 [RKL_DDC_BUS_DDI_D] = GMBUS_PIN_9_TC1_ICP, 1642 [RKL_DDC_BUS_DDI_E] = GMBUS_PIN_10_TC2_ICP, 1643 }; 1644 1645 static const u8 adls_ddc_pin_map[] = { 1646 [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT, 1647 [ADLS_DDC_BUS_PORT_TC1] = GMBUS_PIN_9_TC1_ICP, 1648 [ADLS_DDC_BUS_PORT_TC2] = GMBUS_PIN_10_TC2_ICP, 1649 [ADLS_DDC_BUS_PORT_TC3] = GMBUS_PIN_11_TC3_ICP, 1650 [ADLS_DDC_BUS_PORT_TC4] = GMBUS_PIN_12_TC4_ICP, 1651 }; 1652 1653 static const u8 gen9bc_tgp_ddc_pin_map[] = { 1654 [DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT, 1655 [DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP, 1656 [DDC_BUS_DDI_D] = GMBUS_PIN_10_TC2_ICP, 1657 }; 1658 1659 static const u8 adlp_ddc_pin_map[] = { 1660 [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT, 1661 [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT, 1662 [ADLP_DDC_BUS_PORT_TC1] = GMBUS_PIN_9_TC1_ICP, 1663 [ADLP_DDC_BUS_PORT_TC2] = GMBUS_PIN_10_TC2_ICP, 1664 [ADLP_DDC_BUS_PORT_TC3] = GMBUS_PIN_11_TC3_ICP, 1665 [ADLP_DDC_BUS_PORT_TC4] = GMBUS_PIN_12_TC4_ICP, 1666 }; 1667 1668 static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin) 1669 { 1670 const u8 *ddc_pin_map; 1671 int n_entries; 1672 1673 if (IS_ALDERLAKE_P(i915)) { 1674 ddc_pin_map = adlp_ddc_pin_map; 1675 n_entries = ARRAY_SIZE(adlp_ddc_pin_map); 1676 } else if (IS_ALDERLAKE_S(i915)) { 1677 ddc_pin_map = adls_ddc_pin_map; 1678 n_entries = ARRAY_SIZE(adls_ddc_pin_map); 1679 } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) { 1680 return vbt_pin; 1681 } else if (IS_ROCKETLAKE(i915) && INTEL_PCH_TYPE(i915) == PCH_TGP) { 1682 ddc_pin_map = rkl_pch_tgp_ddc_pin_map; 1683 n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map); 1684 } else if (HAS_PCH_TGP(i915) && DISPLAY_VER(i915) == 9) { 1685 ddc_pin_map = gen9bc_tgp_ddc_pin_map; 1686 n_entries = ARRAY_SIZE(gen9bc_tgp_ddc_pin_map); 1687 } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) { 1688 ddc_pin_map = icp_ddc_pin_map; 1689 n_entries = ARRAY_SIZE(icp_ddc_pin_map); 1690 } else if (HAS_PCH_CNP(i915)) { 1691 ddc_pin_map = cnp_ddc_pin_map; 1692 n_entries = ARRAY_SIZE(cnp_ddc_pin_map); 1693 } else { 1694 /* Assuming direct map */ 1695 return vbt_pin; 1696 } 1697 1698 if (vbt_pin < n_entries && ddc_pin_map[vbt_pin] != 0) 1699 return ddc_pin_map[vbt_pin]; 1700 1701 drm_dbg_kms(&i915->drm, 1702 "Ignoring alternate pin: VBT claims DDC pin %d, which is not valid for this platform\n", 1703 vbt_pin); 1704 return 0; 1705 } 1706 1707 static u8 dvo_port_type(u8 dvo_port) 1708 { 1709 switch (dvo_port) { 1710 case DVO_PORT_HDMIA: 1711 case DVO_PORT_HDMIB: 1712 case DVO_PORT_HDMIC: 1713 case DVO_PORT_HDMID: 1714 case DVO_PORT_HDMIE: 1715 case DVO_PORT_HDMIF: 1716 case DVO_PORT_HDMIG: 1717 case DVO_PORT_HDMIH: 1718 case DVO_PORT_HDMII: 1719 return DVO_PORT_HDMIA; 1720 case DVO_PORT_DPA: 1721 case DVO_PORT_DPB: 1722 case DVO_PORT_DPC: 1723 case DVO_PORT_DPD: 1724 case DVO_PORT_DPE: 1725 case DVO_PORT_DPF: 1726 case DVO_PORT_DPG: 1727 case DVO_PORT_DPH: 1728 case DVO_PORT_DPI: 1729 return DVO_PORT_DPA; 1730 case DVO_PORT_MIPIA: 1731 case DVO_PORT_MIPIB: 1732 case DVO_PORT_MIPIC: 1733 case DVO_PORT_MIPID: 1734 return DVO_PORT_MIPIA; 1735 default: 1736 return dvo_port; 1737 } 1738 } 1739 1740 static enum port __dvo_port_to_port(int n_ports, int n_dvo, 1741 const int port_mapping[][3], u8 dvo_port) 1742 { 1743 enum port port; 1744 int i; 1745 1746 for (port = PORT_A; port < n_ports; port++) { 1747 for (i = 0; i < n_dvo; i++) { 1748 if (port_mapping[port][i] == -1) 1749 break; 1750 1751 if (dvo_port == port_mapping[port][i]) 1752 return port; 1753 } 1754 } 1755 1756 return PORT_NONE; 1757 } 1758 1759 static enum port dvo_port_to_port(struct drm_i915_private *i915, 1760 u8 dvo_port) 1761 { 1762 /* 1763 * Each DDI port can have more than one value on the "DVO Port" field, 1764 * so look for all the possible values for each port. 1765 */ 1766 static const int port_mapping[][3] = { 1767 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, 1768 [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, 1769 [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, 1770 [PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, 1771 [PORT_E] = { DVO_PORT_HDMIE, DVO_PORT_DPE, DVO_PORT_CRT }, 1772 [PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 }, 1773 [PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 }, 1774 [PORT_H] = { DVO_PORT_HDMIH, DVO_PORT_DPH, -1 }, 1775 [PORT_I] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 }, 1776 }; 1777 /* 1778 * RKL VBT uses PHY based mapping. Combo PHYs A,B,C,D 1779 * map to DDI A,B,TC1,TC2 respectively. 1780 */ 1781 static const int rkl_port_mapping[][3] = { 1782 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, 1783 [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, 1784 [PORT_C] = { -1 }, 1785 [PORT_TC1] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, 1786 [PORT_TC2] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, 1787 }; 1788 /* 1789 * Alderlake S ports used in the driver are PORT_A, PORT_D, PORT_E, 1790 * PORT_F and PORT_G, we need to map that to correct VBT sections. 1791 */ 1792 static const int adls_port_mapping[][3] = { 1793 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, 1794 [PORT_B] = { -1 }, 1795 [PORT_C] = { -1 }, 1796 [PORT_TC1] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, 1797 [PORT_TC2] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, 1798 [PORT_TC3] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, 1799 [PORT_TC4] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 }, 1800 }; 1801 static const int xelpd_port_mapping[][3] = { 1802 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, 1803 [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, 1804 [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, 1805 [PORT_D_XELPD] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, 1806 [PORT_E_XELPD] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 }, 1807 [PORT_TC1] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 }, 1808 [PORT_TC2] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 }, 1809 [PORT_TC3] = { DVO_PORT_HDMIH, DVO_PORT_DPH, -1 }, 1810 [PORT_TC4] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 }, 1811 }; 1812 1813 if (DISPLAY_VER(i915) == 13) 1814 return __dvo_port_to_port(ARRAY_SIZE(xelpd_port_mapping), 1815 ARRAY_SIZE(xelpd_port_mapping[0]), 1816 xelpd_port_mapping, 1817 dvo_port); 1818 else if (IS_ALDERLAKE_S(i915)) 1819 return __dvo_port_to_port(ARRAY_SIZE(adls_port_mapping), 1820 ARRAY_SIZE(adls_port_mapping[0]), 1821 adls_port_mapping, 1822 dvo_port); 1823 else if (IS_DG1(i915) || IS_ROCKETLAKE(i915)) 1824 return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping), 1825 ARRAY_SIZE(rkl_port_mapping[0]), 1826 rkl_port_mapping, 1827 dvo_port); 1828 else 1829 return __dvo_port_to_port(ARRAY_SIZE(port_mapping), 1830 ARRAY_SIZE(port_mapping[0]), 1831 port_mapping, 1832 dvo_port); 1833 } 1834 1835 static int parse_bdb_230_dp_max_link_rate(const int vbt_max_link_rate) 1836 { 1837 switch (vbt_max_link_rate) { 1838 default: 1839 case BDB_230_VBT_DP_MAX_LINK_RATE_DEF: 1840 return 0; 1841 case BDB_230_VBT_DP_MAX_LINK_RATE_UHBR20: 1842 return 2000000; 1843 case BDB_230_VBT_DP_MAX_LINK_RATE_UHBR13P5: 1844 return 1350000; 1845 case BDB_230_VBT_DP_MAX_LINK_RATE_UHBR10: 1846 return 1000000; 1847 case BDB_230_VBT_DP_MAX_LINK_RATE_HBR3: 1848 return 810000; 1849 case BDB_230_VBT_DP_MAX_LINK_RATE_HBR2: 1850 return 540000; 1851 case BDB_230_VBT_DP_MAX_LINK_RATE_HBR: 1852 return 270000; 1853 case BDB_230_VBT_DP_MAX_LINK_RATE_LBR: 1854 return 162000; 1855 } 1856 } 1857 1858 static int parse_bdb_216_dp_max_link_rate(const int vbt_max_link_rate) 1859 { 1860 switch (vbt_max_link_rate) { 1861 default: 1862 case BDB_216_VBT_DP_MAX_LINK_RATE_HBR3: 1863 return 810000; 1864 case BDB_216_VBT_DP_MAX_LINK_RATE_HBR2: 1865 return 540000; 1866 case BDB_216_VBT_DP_MAX_LINK_RATE_HBR: 1867 return 270000; 1868 case BDB_216_VBT_DP_MAX_LINK_RATE_LBR: 1869 return 162000; 1870 } 1871 } 1872 1873 static void sanitize_device_type(struct intel_bios_encoder_data *devdata, 1874 enum port port) 1875 { 1876 struct drm_i915_private *i915 = devdata->i915; 1877 bool is_hdmi; 1878 1879 if (port != PORT_A || DISPLAY_VER(i915) >= 12) 1880 return; 1881 1882 if (!(devdata->child.device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING)) 1883 return; 1884 1885 is_hdmi = !(devdata->child.device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT); 1886 1887 drm_dbg_kms(&i915->drm, "VBT claims port A supports DVI%s, ignoring\n", 1888 is_hdmi ? "/HDMI" : ""); 1889 1890 devdata->child.device_type &= ~DEVICE_TYPE_TMDS_DVI_SIGNALING; 1891 devdata->child.device_type |= DEVICE_TYPE_NOT_HDMI_OUTPUT; 1892 } 1893 1894 static bool 1895 intel_bios_encoder_supports_crt(const struct intel_bios_encoder_data *devdata) 1896 { 1897 return devdata->child.device_type & DEVICE_TYPE_ANALOG_OUTPUT; 1898 } 1899 1900 bool 1901 intel_bios_encoder_supports_dvi(const struct intel_bios_encoder_data *devdata) 1902 { 1903 return devdata->child.device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING; 1904 } 1905 1906 bool 1907 intel_bios_encoder_supports_hdmi(const struct intel_bios_encoder_data *devdata) 1908 { 1909 return intel_bios_encoder_supports_dvi(devdata) && 1910 (devdata->child.device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0; 1911 } 1912 1913 bool 1914 intel_bios_encoder_supports_dp(const struct intel_bios_encoder_data *devdata) 1915 { 1916 return devdata->child.device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT; 1917 } 1918 1919 static bool 1920 intel_bios_encoder_supports_edp(const struct intel_bios_encoder_data *devdata) 1921 { 1922 return intel_bios_encoder_supports_dp(devdata) && 1923 devdata->child.device_type & DEVICE_TYPE_INTERNAL_CONNECTOR; 1924 } 1925 1926 static bool is_port_valid(struct drm_i915_private *i915, enum port port) 1927 { 1928 /* 1929 * On some ICL SKUs port F is not present, but broken VBTs mark 1930 * the port as present. Only try to initialize port F for the 1931 * SKUs that may actually have it. 1932 */ 1933 if (port == PORT_F && IS_ICELAKE(i915)) 1934 return IS_ICL_WITH_PORT_F(i915); 1935 1936 return true; 1937 } 1938 1939 static void parse_ddi_port(struct drm_i915_private *i915, 1940 struct intel_bios_encoder_data *devdata) 1941 { 1942 const struct child_device_config *child = &devdata->child; 1943 struct ddi_vbt_port_info *info; 1944 bool is_dvi, is_hdmi, is_dp, is_edp, is_crt, supports_typec_usb, supports_tbt; 1945 int dp_boost_level, hdmi_boost_level; 1946 enum port port; 1947 1948 port = dvo_port_to_port(i915, child->dvo_port); 1949 if (port == PORT_NONE) 1950 return; 1951 1952 if (!is_port_valid(i915, port)) { 1953 drm_dbg_kms(&i915->drm, 1954 "VBT reports port %c as supported, but that can't be true: skipping\n", 1955 port_name(port)); 1956 return; 1957 } 1958 1959 info = &i915->vbt.ddi_port_info[port]; 1960 1961 if (info->devdata) { 1962 drm_dbg_kms(&i915->drm, 1963 "More than one child device for port %c in VBT, using the first.\n", 1964 port_name(port)); 1965 return; 1966 } 1967 1968 sanitize_device_type(devdata, port); 1969 1970 is_dvi = intel_bios_encoder_supports_dvi(devdata); 1971 is_dp = intel_bios_encoder_supports_dp(devdata); 1972 is_crt = intel_bios_encoder_supports_crt(devdata); 1973 is_hdmi = intel_bios_encoder_supports_hdmi(devdata); 1974 is_edp = intel_bios_encoder_supports_edp(devdata); 1975 1976 supports_typec_usb = intel_bios_encoder_supports_typec_usb(devdata); 1977 supports_tbt = intel_bios_encoder_supports_tbt(devdata); 1978 1979 drm_dbg_kms(&i915->drm, 1980 "Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d LSPCON:%d USB-Type-C:%d TBT:%d DSC:%d\n", 1981 port_name(port), is_crt, is_dvi, is_hdmi, is_dp, is_edp, 1982 HAS_LSPCON(i915) && child->lspcon, 1983 supports_typec_usb, supports_tbt, 1984 devdata->dsc != NULL); 1985 1986 if (is_dvi) { 1987 u8 ddc_pin; 1988 1989 ddc_pin = map_ddc_pin(i915, child->ddc_pin); 1990 if (intel_gmbus_is_valid_pin(i915, ddc_pin)) { 1991 info->alternate_ddc_pin = ddc_pin; 1992 sanitize_ddc_pin(i915, port); 1993 } else { 1994 drm_dbg_kms(&i915->drm, 1995 "Port %c has invalid DDC pin %d, " 1996 "sticking to defaults\n", 1997 port_name(port), ddc_pin); 1998 } 1999 } 2000 2001 if (is_dp) { 2002 info->alternate_aux_channel = child->aux_channel; 2003 2004 sanitize_aux_ch(i915, port); 2005 } 2006 2007 if (i915->vbt.version >= 158) { 2008 /* The VBT HDMI level shift values match the table we have. */ 2009 u8 hdmi_level_shift = child->hdmi_level_shifter_value; 2010 drm_dbg_kms(&i915->drm, 2011 "Port %c VBT HDMI level shift: %d\n", 2012 port_name(port), 2013 hdmi_level_shift); 2014 info->hdmi_level_shift = hdmi_level_shift; 2015 info->hdmi_level_shift_set = true; 2016 } 2017 2018 if (i915->vbt.version >= 204) { 2019 int max_tmds_clock; 2020 2021 switch (child->hdmi_max_data_rate) { 2022 default: 2023 MISSING_CASE(child->hdmi_max_data_rate); 2024 fallthrough; 2025 case HDMI_MAX_DATA_RATE_PLATFORM: 2026 max_tmds_clock = 0; 2027 break; 2028 case HDMI_MAX_DATA_RATE_297: 2029 max_tmds_clock = 297000; 2030 break; 2031 case HDMI_MAX_DATA_RATE_165: 2032 max_tmds_clock = 165000; 2033 break; 2034 } 2035 2036 if (max_tmds_clock) 2037 drm_dbg_kms(&i915->drm, 2038 "Port %c VBT HDMI max TMDS clock: %d kHz\n", 2039 port_name(port), max_tmds_clock); 2040 info->max_tmds_clock = max_tmds_clock; 2041 } 2042 2043 /* I_boost config for SKL and above */ 2044 dp_boost_level = intel_bios_encoder_dp_boost_level(devdata); 2045 if (dp_boost_level) 2046 drm_dbg_kms(&i915->drm, 2047 "Port %c VBT (e)DP boost level: %d\n", 2048 port_name(port), dp_boost_level); 2049 2050 hdmi_boost_level = intel_bios_encoder_hdmi_boost_level(devdata); 2051 if (hdmi_boost_level) 2052 drm_dbg_kms(&i915->drm, 2053 "Port %c VBT HDMI boost level: %d\n", 2054 port_name(port), hdmi_boost_level); 2055 2056 /* DP max link rate for GLK+ */ 2057 if (i915->vbt.version >= 216) { 2058 if (i915->vbt.version >= 230) 2059 info->dp_max_link_rate = parse_bdb_230_dp_max_link_rate(child->dp_max_link_rate); 2060 else 2061 info->dp_max_link_rate = parse_bdb_216_dp_max_link_rate(child->dp_max_link_rate); 2062 2063 drm_dbg_kms(&i915->drm, 2064 "Port %c VBT DP max link rate: %d\n", 2065 port_name(port), info->dp_max_link_rate); 2066 } 2067 2068 info->devdata = devdata; 2069 } 2070 2071 static void parse_ddi_ports(struct drm_i915_private *i915) 2072 { 2073 struct intel_bios_encoder_data *devdata; 2074 2075 if (!HAS_DDI(i915) && !IS_CHERRYVIEW(i915)) 2076 return; 2077 2078 if (i915->vbt.version < 155) 2079 return; 2080 2081 list_for_each_entry(devdata, &i915->vbt.display_devices, node) 2082 parse_ddi_port(i915, devdata); 2083 } 2084 2085 static void 2086 parse_general_definitions(struct drm_i915_private *i915, 2087 const struct bdb_header *bdb) 2088 { 2089 const struct bdb_general_definitions *defs; 2090 struct intel_bios_encoder_data *devdata; 2091 const struct child_device_config *child; 2092 int i, child_device_num; 2093 u8 expected_size; 2094 u16 block_size; 2095 int bus_pin; 2096 2097 defs = find_section(bdb, BDB_GENERAL_DEFINITIONS); 2098 if (!defs) { 2099 drm_dbg_kms(&i915->drm, 2100 "No general definition block is found, no devices defined.\n"); 2101 return; 2102 } 2103 2104 block_size = get_blocksize(defs); 2105 if (block_size < sizeof(*defs)) { 2106 drm_dbg_kms(&i915->drm, 2107 "General definitions block too small (%u)\n", 2108 block_size); 2109 return; 2110 } 2111 2112 bus_pin = defs->crt_ddc_gmbus_pin; 2113 drm_dbg_kms(&i915->drm, "crt_ddc_bus_pin: %d\n", bus_pin); 2114 if (intel_gmbus_is_valid_pin(i915, bus_pin)) 2115 i915->vbt.crt_ddc_pin = bus_pin; 2116 2117 if (bdb->version < 106) { 2118 expected_size = 22; 2119 } else if (bdb->version < 111) { 2120 expected_size = 27; 2121 } else if (bdb->version < 195) { 2122 expected_size = LEGACY_CHILD_DEVICE_CONFIG_SIZE; 2123 } else if (bdb->version == 195) { 2124 expected_size = 37; 2125 } else if (bdb->version <= 215) { 2126 expected_size = 38; 2127 } else if (bdb->version <= 237) { 2128 expected_size = 39; 2129 } else { 2130 expected_size = sizeof(*child); 2131 BUILD_BUG_ON(sizeof(*child) < 39); 2132 drm_dbg(&i915->drm, 2133 "Expected child device config size for VBT version %u not known; assuming %u\n", 2134 bdb->version, expected_size); 2135 } 2136 2137 /* Flag an error for unexpected size, but continue anyway. */ 2138 if (defs->child_dev_size != expected_size) 2139 drm_err(&i915->drm, 2140 "Unexpected child device config size %u (expected %u for VBT version %u)\n", 2141 defs->child_dev_size, expected_size, bdb->version); 2142 2143 /* The legacy sized child device config is the minimum we need. */ 2144 if (defs->child_dev_size < LEGACY_CHILD_DEVICE_CONFIG_SIZE) { 2145 drm_dbg_kms(&i915->drm, 2146 "Child device config size %u is too small.\n", 2147 defs->child_dev_size); 2148 return; 2149 } 2150 2151 /* get the number of child device */ 2152 child_device_num = (block_size - sizeof(*defs)) / defs->child_dev_size; 2153 2154 for (i = 0; i < child_device_num; i++) { 2155 child = child_device_ptr(defs, i); 2156 if (!child->device_type) 2157 continue; 2158 2159 drm_dbg_kms(&i915->drm, 2160 "Found VBT child device with type 0x%x\n", 2161 child->device_type); 2162 2163 devdata = kzalloc(sizeof(*devdata), GFP_KERNEL); 2164 if (!devdata) 2165 break; 2166 2167 devdata->i915 = i915; 2168 2169 /* 2170 * Copy as much as we know (sizeof) and is available 2171 * (child_dev_size) of the child device config. Accessing the 2172 * data must depend on VBT version. 2173 */ 2174 memcpy(&devdata->child, child, 2175 min_t(size_t, defs->child_dev_size, sizeof(*child))); 2176 2177 list_add_tail(&devdata->node, &i915->vbt.display_devices); 2178 } 2179 2180 if (list_empty(&i915->vbt.display_devices)) 2181 drm_dbg_kms(&i915->drm, 2182 "no child dev is parsed from VBT\n"); 2183 } 2184 2185 /* Common defaults which may be overridden by VBT. */ 2186 static void 2187 init_vbt_defaults(struct drm_i915_private *i915) 2188 { 2189 i915->vbt.crt_ddc_pin = GMBUS_PIN_VGADDC; 2190 2191 /* Default to having backlight */ 2192 i915->vbt.backlight.present = true; 2193 2194 /* LFP panel data */ 2195 i915->vbt.lvds_dither = 1; 2196 2197 /* SDVO panel data */ 2198 i915->vbt.sdvo_lvds_vbt_mode = NULL; 2199 2200 /* general features */ 2201 i915->vbt.int_tv_support = 1; 2202 i915->vbt.int_crt_support = 1; 2203 2204 /* driver features */ 2205 i915->vbt.int_lvds_support = 1; 2206 2207 /* Default to using SSC */ 2208 i915->vbt.lvds_use_ssc = 1; 2209 /* 2210 * Core/SandyBridge/IvyBridge use alternative (120MHz) reference 2211 * clock for LVDS. 2212 */ 2213 i915->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(i915, 2214 !HAS_PCH_SPLIT(i915)); 2215 drm_dbg_kms(&i915->drm, "Set default to SSC at %d kHz\n", 2216 i915->vbt.lvds_ssc_freq); 2217 } 2218 2219 /* Defaults to initialize only if there is no VBT. */ 2220 static void 2221 init_vbt_missing_defaults(struct drm_i915_private *i915) 2222 { 2223 enum port port; 2224 int ports = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | 2225 BIT(PORT_D) | BIT(PORT_E) | BIT(PORT_F); 2226 2227 if (!HAS_DDI(i915) && !IS_CHERRYVIEW(i915)) 2228 return; 2229 2230 for_each_port_masked(port, ports) { 2231 struct intel_bios_encoder_data *devdata; 2232 struct child_device_config *child; 2233 enum phy phy = intel_port_to_phy(i915, port); 2234 2235 /* 2236 * VBT has the TypeC mode (native,TBT/USB) and we don't want 2237 * to detect it. 2238 */ 2239 if (intel_phy_is_tc(i915, phy)) 2240 continue; 2241 2242 /* Create fake child device config */ 2243 devdata = kzalloc(sizeof(*devdata), GFP_KERNEL); 2244 if (!devdata) 2245 break; 2246 2247 devdata->i915 = i915; 2248 child = &devdata->child; 2249 2250 if (port == PORT_F) 2251 child->dvo_port = DVO_PORT_HDMIF; 2252 else if (port == PORT_E) 2253 child->dvo_port = DVO_PORT_HDMIE; 2254 else 2255 child->dvo_port = DVO_PORT_HDMIA + port; 2256 2257 if (port != PORT_A && port != PORT_E) 2258 child->device_type |= DEVICE_TYPE_TMDS_DVI_SIGNALING; 2259 2260 if (port != PORT_E) 2261 child->device_type |= DEVICE_TYPE_DISPLAYPORT_OUTPUT; 2262 2263 if (port == PORT_A) 2264 child->device_type |= DEVICE_TYPE_INTERNAL_CONNECTOR; 2265 2266 list_add_tail(&devdata->node, &i915->vbt.display_devices); 2267 2268 drm_dbg_kms(&i915->drm, 2269 "Generating default VBT child device with type 0x04%x on port %c\n", 2270 child->device_type, port_name(port)); 2271 } 2272 2273 /* Bypass some minimum baseline VBT version checks */ 2274 i915->vbt.version = 155; 2275 } 2276 2277 static const struct bdb_header *get_bdb_header(const struct vbt_header *vbt) 2278 { 2279 const void *_vbt = vbt; 2280 2281 return _vbt + vbt->bdb_offset; 2282 } 2283 2284 #include <dev/isa/isareg.h> 2285 #include <dev/isa/isavar.h> 2286 2287 #define VGA_BIOS_ADDR 0xc0000 2288 #define VGA_BIOS_LEN 0x10000 2289 2290 /** 2291 * intel_bios_is_valid_vbt - does the given buffer contain a valid VBT 2292 * @buf: pointer to a buffer to validate 2293 * @size: size of the buffer 2294 * 2295 * Returns true on valid VBT. 2296 */ 2297 bool intel_bios_is_valid_vbt(const void *buf, size_t size) 2298 { 2299 const struct vbt_header *vbt = buf; 2300 const struct bdb_header *bdb; 2301 2302 if (!vbt) 2303 return false; 2304 2305 if (sizeof(struct vbt_header) > size) { 2306 DRM_DEBUG_DRIVER("VBT header incomplete\n"); 2307 return false; 2308 } 2309 2310 if (memcmp(vbt->signature, "$VBT", 4)) { 2311 DRM_DEBUG_DRIVER("VBT invalid signature\n"); 2312 return false; 2313 } 2314 2315 if (vbt->vbt_size > size) { 2316 DRM_DEBUG_DRIVER("VBT incomplete (vbt_size overflows)\n"); 2317 return false; 2318 } 2319 2320 size = vbt->vbt_size; 2321 2322 if (range_overflows_t(size_t, 2323 vbt->bdb_offset, 2324 sizeof(struct bdb_header), 2325 size)) { 2326 DRM_DEBUG_DRIVER("BDB header incomplete\n"); 2327 return false; 2328 } 2329 2330 bdb = get_bdb_header(vbt); 2331 if (range_overflows_t(size_t, vbt->bdb_offset, bdb->bdb_size, size)) { 2332 DRM_DEBUG_DRIVER("BDB incomplete\n"); 2333 return false; 2334 } 2335 2336 return vbt; 2337 } 2338 2339 static struct vbt_header *oprom_get_vbt(struct drm_i915_private *i915) 2340 { 2341 #ifdef __linux__ 2342 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 2343 #endif 2344 void __iomem *p = NULL, *oprom; 2345 struct vbt_header *vbt; 2346 u16 vbt_size; 2347 size_t i, size; 2348 2349 #ifdef __linux__ 2350 oprom = pci_map_rom(pdev, &size); 2351 if (!oprom) 2352 return NULL; 2353 #else 2354 oprom = (u8 *)ISA_HOLE_VADDR(VGA_BIOS_ADDR); 2355 size = VGA_BIOS_LEN; 2356 #endif 2357 2358 /* Scour memory looking for the VBT signature. */ 2359 for (i = 0; i + 4 < size; i += 4) { 2360 if (ioread32(oprom + i) != *((const u32 *)"$VBT")) 2361 continue; 2362 2363 p = oprom + i; 2364 size -= i; 2365 break; 2366 } 2367 2368 if (!p) 2369 goto err_unmap_oprom; 2370 2371 if (sizeof(struct vbt_header) > size) { 2372 drm_dbg(&i915->drm, "VBT header incomplete\n"); 2373 goto err_unmap_oprom; 2374 } 2375 2376 vbt_size = ioread16(p + offsetof(struct vbt_header, vbt_size)); 2377 if (vbt_size > size) { 2378 drm_dbg(&i915->drm, 2379 "VBT incomplete (vbt_size overflows)\n"); 2380 goto err_unmap_oprom; 2381 } 2382 2383 /* The rest will be validated by intel_bios_is_valid_vbt() */ 2384 vbt = kmalloc(vbt_size, GFP_KERNEL); 2385 if (!vbt) 2386 goto err_unmap_oprom; 2387 2388 memcpy_fromio(vbt, p, vbt_size); 2389 2390 if (!intel_bios_is_valid_vbt(vbt, vbt_size)) 2391 goto err_free_vbt; 2392 2393 #ifdef __linux__ 2394 pci_unmap_rom(pdev, oprom); 2395 #endif 2396 2397 return vbt; 2398 2399 err_free_vbt: 2400 kfree(vbt); 2401 err_unmap_oprom: 2402 #ifdef __linux__ 2403 pci_unmap_rom(pdev, oprom); 2404 #endif 2405 2406 return NULL; 2407 } 2408 2409 /** 2410 * intel_bios_init - find VBT and initialize settings from the BIOS 2411 * @i915: i915 device instance 2412 * 2413 * Parse and initialize settings from the Video BIOS Tables (VBT). If the VBT 2414 * was not found in ACPI OpRegion, try to find it in PCI ROM first. Also 2415 * initialize some defaults if the VBT is not present at all. 2416 */ 2417 void intel_bios_init(struct drm_i915_private *i915) 2418 { 2419 const struct vbt_header *vbt = i915->opregion.vbt; 2420 struct vbt_header *oprom_vbt = NULL; 2421 const struct bdb_header *bdb; 2422 2423 INIT_LIST_HEAD(&i915->vbt.display_devices); 2424 2425 if (!HAS_DISPLAY(i915)) { 2426 drm_dbg_kms(&i915->drm, 2427 "Skipping VBT init due to disabled display.\n"); 2428 return; 2429 } 2430 2431 init_vbt_defaults(i915); 2432 2433 /* If the OpRegion does not have VBT, look in PCI ROM. */ 2434 if (!vbt) { 2435 oprom_vbt = oprom_get_vbt(i915); 2436 if (!oprom_vbt) 2437 goto out; 2438 2439 vbt = oprom_vbt; 2440 2441 drm_dbg_kms(&i915->drm, "Found valid VBT in PCI ROM\n"); 2442 } 2443 2444 bdb = get_bdb_header(vbt); 2445 i915->vbt.version = bdb->version; 2446 2447 drm_dbg_kms(&i915->drm, 2448 "VBT signature \"%.*s\", BDB version %d\n", 2449 (int)sizeof(vbt->signature), vbt->signature, bdb->version); 2450 2451 /* Grab useful general definitions */ 2452 parse_general_features(i915, bdb); 2453 parse_general_definitions(i915, bdb); 2454 parse_panel_options(i915, bdb); 2455 parse_panel_dtd(i915, bdb); 2456 parse_lfp_backlight(i915, bdb); 2457 parse_sdvo_panel_data(i915, bdb); 2458 parse_driver_features(i915, bdb); 2459 parse_power_conservation_features(i915, bdb); 2460 parse_edp(i915, bdb); 2461 parse_psr(i915, bdb); 2462 parse_mipi_config(i915, bdb); 2463 parse_mipi_sequence(i915, bdb); 2464 2465 /* Depends on child device list */ 2466 parse_compression_parameters(i915, bdb); 2467 2468 out: 2469 if (!vbt) { 2470 drm_info(&i915->drm, 2471 "Failed to find VBIOS tables (VBT)\n"); 2472 init_vbt_missing_defaults(i915); 2473 } 2474 2475 /* Further processing on pre-parsed or generated child device data */ 2476 parse_sdvo_device_mapping(i915); 2477 parse_ddi_ports(i915); 2478 2479 kfree(oprom_vbt); 2480 } 2481 2482 /** 2483 * intel_bios_driver_remove - Free any resources allocated by intel_bios_init() 2484 * @i915: i915 device instance 2485 */ 2486 void intel_bios_driver_remove(struct drm_i915_private *i915) 2487 { 2488 struct intel_bios_encoder_data *devdata, *n; 2489 2490 list_for_each_entry_safe(devdata, n, &i915->vbt.display_devices, node) { 2491 list_del(&devdata->node); 2492 kfree(devdata->dsc); 2493 kfree(devdata); 2494 } 2495 2496 kfree(i915->vbt.sdvo_lvds_vbt_mode); 2497 i915->vbt.sdvo_lvds_vbt_mode = NULL; 2498 kfree(i915->vbt.lfp_lvds_vbt_mode); 2499 i915->vbt.lfp_lvds_vbt_mode = NULL; 2500 kfree(i915->vbt.dsi.data); 2501 i915->vbt.dsi.data = NULL; 2502 kfree(i915->vbt.dsi.pps); 2503 i915->vbt.dsi.pps = NULL; 2504 kfree(i915->vbt.dsi.config); 2505 i915->vbt.dsi.config = NULL; 2506 kfree(i915->vbt.dsi.deassert_seq); 2507 i915->vbt.dsi.deassert_seq = NULL; 2508 } 2509 2510 /** 2511 * intel_bios_is_tv_present - is integrated TV present in VBT 2512 * @i915: i915 device instance 2513 * 2514 * Return true if TV is present. If no child devices were parsed from VBT, 2515 * assume TV is present. 2516 */ 2517 bool intel_bios_is_tv_present(struct drm_i915_private *i915) 2518 { 2519 const struct intel_bios_encoder_data *devdata; 2520 const struct child_device_config *child; 2521 2522 if (!i915->vbt.int_tv_support) 2523 return false; 2524 2525 if (list_empty(&i915->vbt.display_devices)) 2526 return true; 2527 2528 list_for_each_entry(devdata, &i915->vbt.display_devices, node) { 2529 child = &devdata->child; 2530 2531 /* 2532 * If the device type is not TV, continue. 2533 */ 2534 switch (child->device_type) { 2535 case DEVICE_TYPE_INT_TV: 2536 case DEVICE_TYPE_TV: 2537 case DEVICE_TYPE_TV_SVIDEO_COMPOSITE: 2538 break; 2539 default: 2540 continue; 2541 } 2542 /* Only when the addin_offset is non-zero, it is regarded 2543 * as present. 2544 */ 2545 if (child->addin_offset) 2546 return true; 2547 } 2548 2549 return false; 2550 } 2551 2552 /** 2553 * intel_bios_is_lvds_present - is LVDS present in VBT 2554 * @i915: i915 device instance 2555 * @i2c_pin: i2c pin for LVDS if present 2556 * 2557 * Return true if LVDS is present. If no child devices were parsed from VBT, 2558 * assume LVDS is present. 2559 */ 2560 bool intel_bios_is_lvds_present(struct drm_i915_private *i915, u8 *i2c_pin) 2561 { 2562 const struct intel_bios_encoder_data *devdata; 2563 const struct child_device_config *child; 2564 2565 if (list_empty(&i915->vbt.display_devices)) 2566 return true; 2567 2568 list_for_each_entry(devdata, &i915->vbt.display_devices, node) { 2569 child = &devdata->child; 2570 2571 /* If the device type is not LFP, continue. 2572 * We have to check both the new identifiers as well as the 2573 * old for compatibility with some BIOSes. 2574 */ 2575 if (child->device_type != DEVICE_TYPE_INT_LFP && 2576 child->device_type != DEVICE_TYPE_LFP) 2577 continue; 2578 2579 if (intel_gmbus_is_valid_pin(i915, child->i2c_pin)) 2580 *i2c_pin = child->i2c_pin; 2581 2582 /* However, we cannot trust the BIOS writers to populate 2583 * the VBT correctly. Since LVDS requires additional 2584 * information from AIM blocks, a non-zero addin offset is 2585 * a good indicator that the LVDS is actually present. 2586 */ 2587 if (child->addin_offset) 2588 return true; 2589 2590 /* But even then some BIOS writers perform some black magic 2591 * and instantiate the device without reference to any 2592 * additional data. Trust that if the VBT was written into 2593 * the OpRegion then they have validated the LVDS's existence. 2594 */ 2595 if (i915->opregion.vbt) 2596 return true; 2597 } 2598 2599 return false; 2600 } 2601 2602 /** 2603 * intel_bios_is_port_present - is the specified digital port present 2604 * @i915: i915 device instance 2605 * @port: port to check 2606 * 2607 * Return true if the device in %port is present. 2608 */ 2609 bool intel_bios_is_port_present(struct drm_i915_private *i915, enum port port) 2610 { 2611 const struct intel_bios_encoder_data *devdata; 2612 const struct child_device_config *child; 2613 static const struct { 2614 u16 dp, hdmi; 2615 } port_mapping[] = { 2616 [PORT_B] = { DVO_PORT_DPB, DVO_PORT_HDMIB, }, 2617 [PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, }, 2618 [PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, }, 2619 [PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, }, 2620 [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, }, 2621 }; 2622 2623 if (HAS_DDI(i915)) { 2624 const struct ddi_vbt_port_info *port_info = 2625 &i915->vbt.ddi_port_info[port]; 2626 2627 return port_info->devdata; 2628 } 2629 2630 /* FIXME maybe deal with port A as well? */ 2631 if (drm_WARN_ON(&i915->drm, 2632 port == PORT_A) || port >= ARRAY_SIZE(port_mapping)) 2633 return false; 2634 2635 list_for_each_entry(devdata, &i915->vbt.display_devices, node) { 2636 child = &devdata->child; 2637 2638 if ((child->dvo_port == port_mapping[port].dp || 2639 child->dvo_port == port_mapping[port].hdmi) && 2640 (child->device_type & (DEVICE_TYPE_TMDS_DVI_SIGNALING | 2641 DEVICE_TYPE_DISPLAYPORT_OUTPUT))) 2642 return true; 2643 } 2644 2645 return false; 2646 } 2647 2648 /** 2649 * intel_bios_is_port_edp - is the device in given port eDP 2650 * @i915: i915 device instance 2651 * @port: port to check 2652 * 2653 * Return true if the device in %port is eDP. 2654 */ 2655 bool intel_bios_is_port_edp(struct drm_i915_private *i915, enum port port) 2656 { 2657 const struct intel_bios_encoder_data *devdata; 2658 const struct child_device_config *child; 2659 static const short port_mapping[] = { 2660 [PORT_B] = DVO_PORT_DPB, 2661 [PORT_C] = DVO_PORT_DPC, 2662 [PORT_D] = DVO_PORT_DPD, 2663 [PORT_E] = DVO_PORT_DPE, 2664 [PORT_F] = DVO_PORT_DPF, 2665 }; 2666 2667 /* 2668 * XXX on T14 Gen 3 resume 2669 * [drm] AUX A/DDI A/PHY A: timeout (status 0x7d4003ff) 2670 * [drm] AUX A/DDI A/PHY A: Too many retries, giving up. First error: -60 2671 * intel_edp_init_source_oui *ERROR* [drm] *ERROR* Failed to write source OUI 2672 * intel_dp_link_training_clock_recovery *ERROR* [drm] *ERROR* failed to enable link training 2673 * https://gitlab.freedesktop.org/drm/intel/-/issues/5531 2674 */ 2675 if (IS_ALDERLAKE_P(i915) && port == PORT_B) 2676 return false; 2677 2678 if (HAS_DDI(i915)) { 2679 const struct intel_bios_encoder_data *devdata; 2680 2681 devdata = intel_bios_encoder_data_lookup(i915, port); 2682 2683 return devdata && intel_bios_encoder_supports_edp(devdata); 2684 } 2685 2686 list_for_each_entry(devdata, &i915->vbt.display_devices, node) { 2687 child = &devdata->child; 2688 2689 if (child->dvo_port == port_mapping[port] && 2690 (child->device_type & DEVICE_TYPE_eDP_BITS) == 2691 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) 2692 return true; 2693 } 2694 2695 return false; 2696 } 2697 2698 static bool child_dev_is_dp_dual_mode(const struct child_device_config *child) 2699 { 2700 if ((child->device_type & DEVICE_TYPE_DP_DUAL_MODE_BITS) != 2701 (DEVICE_TYPE_DP_DUAL_MODE & DEVICE_TYPE_DP_DUAL_MODE_BITS)) 2702 return false; 2703 2704 if (dvo_port_type(child->dvo_port) == DVO_PORT_DPA) 2705 return true; 2706 2707 /* Only accept a HDMI dvo_port as DP++ if it has an AUX channel */ 2708 if (dvo_port_type(child->dvo_port) == DVO_PORT_HDMIA && 2709 child->aux_channel != 0) 2710 return true; 2711 2712 return false; 2713 } 2714 2715 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *i915, 2716 enum port port) 2717 { 2718 static const struct { 2719 u16 dp, hdmi; 2720 } port_mapping[] = { 2721 /* 2722 * Buggy VBTs may declare DP ports as having 2723 * HDMI type dvo_port :( So let's check both. 2724 */ 2725 [PORT_B] = { DVO_PORT_DPB, DVO_PORT_HDMIB, }, 2726 [PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, }, 2727 [PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, }, 2728 [PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, }, 2729 [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, }, 2730 }; 2731 const struct intel_bios_encoder_data *devdata; 2732 2733 if (HAS_DDI(i915)) { 2734 const struct intel_bios_encoder_data *devdata; 2735 2736 devdata = intel_bios_encoder_data_lookup(i915, port); 2737 2738 return devdata && child_dev_is_dp_dual_mode(&devdata->child); 2739 } 2740 2741 if (port == PORT_A || port >= ARRAY_SIZE(port_mapping)) 2742 return false; 2743 2744 list_for_each_entry(devdata, &i915->vbt.display_devices, node) { 2745 if ((devdata->child.dvo_port == port_mapping[port].dp || 2746 devdata->child.dvo_port == port_mapping[port].hdmi) && 2747 child_dev_is_dp_dual_mode(&devdata->child)) 2748 return true; 2749 } 2750 2751 return false; 2752 } 2753 2754 /** 2755 * intel_bios_is_dsi_present - is DSI present in VBT 2756 * @i915: i915 device instance 2757 * @port: port for DSI if present 2758 * 2759 * Return true if DSI is present, and return the port in %port. 2760 */ 2761 bool intel_bios_is_dsi_present(struct drm_i915_private *i915, 2762 enum port *port) 2763 { 2764 const struct intel_bios_encoder_data *devdata; 2765 const struct child_device_config *child; 2766 u8 dvo_port; 2767 2768 list_for_each_entry(devdata, &i915->vbt.display_devices, node) { 2769 child = &devdata->child; 2770 2771 if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT)) 2772 continue; 2773 2774 dvo_port = child->dvo_port; 2775 2776 if (dvo_port == DVO_PORT_MIPIA || 2777 (dvo_port == DVO_PORT_MIPIB && DISPLAY_VER(i915) >= 11) || 2778 (dvo_port == DVO_PORT_MIPIC && DISPLAY_VER(i915) < 11)) { 2779 if (port) 2780 *port = dvo_port - DVO_PORT_MIPIA; 2781 return true; 2782 } else if (dvo_port == DVO_PORT_MIPIB || 2783 dvo_port == DVO_PORT_MIPIC || 2784 dvo_port == DVO_PORT_MIPID) { 2785 drm_dbg_kms(&i915->drm, 2786 "VBT has unsupported DSI port %c\n", 2787 port_name(dvo_port - DVO_PORT_MIPIA)); 2788 } 2789 } 2790 2791 return false; 2792 } 2793 2794 static void fill_dsc(struct intel_crtc_state *crtc_state, 2795 struct dsc_compression_parameters_entry *dsc, 2796 int dsc_max_bpc) 2797 { 2798 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 2799 int bpc = 8; 2800 2801 vdsc_cfg->dsc_version_major = dsc->version_major; 2802 vdsc_cfg->dsc_version_minor = dsc->version_minor; 2803 2804 if (dsc->support_12bpc && dsc_max_bpc >= 12) 2805 bpc = 12; 2806 else if (dsc->support_10bpc && dsc_max_bpc >= 10) 2807 bpc = 10; 2808 else if (dsc->support_8bpc && dsc_max_bpc >= 8) 2809 bpc = 8; 2810 else 2811 DRM_DEBUG_KMS("VBT: Unsupported BPC %d for DCS\n", 2812 dsc_max_bpc); 2813 2814 crtc_state->pipe_bpp = bpc * 3; 2815 2816 crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp, 2817 VBT_DSC_MAX_BPP(dsc->max_bpp)); 2818 2819 /* 2820 * FIXME: This is ugly, and slice count should take DSC engine 2821 * throughput etc. into account. 2822 * 2823 * Also, per spec DSI supports 1, 2, 3 or 4 horizontal slices. 2824 */ 2825 if (dsc->slices_per_line & BIT(2)) { 2826 crtc_state->dsc.slice_count = 4; 2827 } else if (dsc->slices_per_line & BIT(1)) { 2828 crtc_state->dsc.slice_count = 2; 2829 } else { 2830 /* FIXME */ 2831 if (!(dsc->slices_per_line & BIT(0))) 2832 DRM_DEBUG_KMS("VBT: Unsupported DSC slice count for DSI\n"); 2833 2834 crtc_state->dsc.slice_count = 1; 2835 } 2836 2837 if (crtc_state->hw.adjusted_mode.crtc_hdisplay % 2838 crtc_state->dsc.slice_count != 0) 2839 DRM_DEBUG_KMS("VBT: DSC hdisplay %d not divisible by slice count %d\n", 2840 crtc_state->hw.adjusted_mode.crtc_hdisplay, 2841 crtc_state->dsc.slice_count); 2842 2843 /* 2844 * The VBT rc_buffer_block_size and rc_buffer_size definitions 2845 * correspond to DP 1.4 DPCD offsets 0x62 and 0x63. 2846 */ 2847 vdsc_cfg->rc_model_size = drm_dsc_dp_rc_buffer_size(dsc->rc_buffer_block_size, 2848 dsc->rc_buffer_size); 2849 2850 /* FIXME: DSI spec says bpc + 1 for this one */ 2851 vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth); 2852 2853 vdsc_cfg->block_pred_enable = dsc->block_prediction_enable; 2854 2855 vdsc_cfg->slice_height = dsc->slice_height; 2856 } 2857 2858 /* FIXME: initially DSI specific */ 2859 bool intel_bios_get_dsc_params(struct intel_encoder *encoder, 2860 struct intel_crtc_state *crtc_state, 2861 int dsc_max_bpc) 2862 { 2863 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2864 const struct intel_bios_encoder_data *devdata; 2865 const struct child_device_config *child; 2866 2867 list_for_each_entry(devdata, &i915->vbt.display_devices, node) { 2868 child = &devdata->child; 2869 2870 if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT)) 2871 continue; 2872 2873 if (child->dvo_port - DVO_PORT_MIPIA == encoder->port) { 2874 if (!devdata->dsc) 2875 return false; 2876 2877 if (crtc_state) 2878 fill_dsc(crtc_state, devdata->dsc, dsc_max_bpc); 2879 2880 return true; 2881 } 2882 } 2883 2884 return false; 2885 } 2886 2887 /** 2888 * intel_bios_is_port_hpd_inverted - is HPD inverted for %port 2889 * @i915: i915 device instance 2890 * @port: port to check 2891 * 2892 * Return true if HPD should be inverted for %port. 2893 */ 2894 bool 2895 intel_bios_is_port_hpd_inverted(const struct drm_i915_private *i915, 2896 enum port port) 2897 { 2898 const struct intel_bios_encoder_data *devdata = 2899 i915->vbt.ddi_port_info[port].devdata; 2900 2901 if (drm_WARN_ON_ONCE(&i915->drm, 2902 !IS_GEMINILAKE(i915) && !IS_BROXTON(i915))) 2903 return false; 2904 2905 return devdata && devdata->child.hpd_invert; 2906 } 2907 2908 /** 2909 * intel_bios_is_lspcon_present - if LSPCON is attached on %port 2910 * @i915: i915 device instance 2911 * @port: port to check 2912 * 2913 * Return true if LSPCON is present on this port 2914 */ 2915 bool 2916 intel_bios_is_lspcon_present(const struct drm_i915_private *i915, 2917 enum port port) 2918 { 2919 const struct intel_bios_encoder_data *devdata = 2920 i915->vbt.ddi_port_info[port].devdata; 2921 2922 return HAS_LSPCON(i915) && devdata && devdata->child.lspcon; 2923 } 2924 2925 /** 2926 * intel_bios_is_lane_reversal_needed - if lane reversal needed on port 2927 * @i915: i915 device instance 2928 * @port: port to check 2929 * 2930 * Return true if port requires lane reversal 2931 */ 2932 bool 2933 intel_bios_is_lane_reversal_needed(const struct drm_i915_private *i915, 2934 enum port port) 2935 { 2936 const struct intel_bios_encoder_data *devdata = 2937 i915->vbt.ddi_port_info[port].devdata; 2938 2939 return devdata && devdata->child.lane_reversal; 2940 } 2941 2942 enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *i915, 2943 enum port port) 2944 { 2945 const struct ddi_vbt_port_info *info = 2946 &i915->vbt.ddi_port_info[port]; 2947 enum aux_ch aux_ch; 2948 2949 if (!info->alternate_aux_channel) { 2950 aux_ch = (enum aux_ch)port; 2951 2952 drm_dbg_kms(&i915->drm, 2953 "using AUX %c for port %c (platform default)\n", 2954 aux_ch_name(aux_ch), port_name(port)); 2955 return aux_ch; 2956 } 2957 2958 /* 2959 * RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D 2960 * map to DDI A,B,TC1,TC2 respectively. 2961 * 2962 * ADL-S VBT uses PHY based mapping. Combo PHYs A,B,C,D,E 2963 * map to DDI A,TC1,TC2,TC3,TC4 respectively. 2964 */ 2965 switch (info->alternate_aux_channel) { 2966 case DP_AUX_A: 2967 aux_ch = AUX_CH_A; 2968 break; 2969 case DP_AUX_B: 2970 if (IS_ALDERLAKE_S(i915)) 2971 aux_ch = AUX_CH_USBC1; 2972 else 2973 aux_ch = AUX_CH_B; 2974 break; 2975 case DP_AUX_C: 2976 if (IS_ALDERLAKE_S(i915)) 2977 aux_ch = AUX_CH_USBC2; 2978 else if (IS_DG1(i915) || IS_ROCKETLAKE(i915)) 2979 aux_ch = AUX_CH_USBC1; 2980 else 2981 aux_ch = AUX_CH_C; 2982 break; 2983 case DP_AUX_D: 2984 if (DISPLAY_VER(i915) == 13) 2985 aux_ch = AUX_CH_D_XELPD; 2986 else if (IS_ALDERLAKE_S(i915)) 2987 aux_ch = AUX_CH_USBC3; 2988 else if (IS_DG1(i915) || IS_ROCKETLAKE(i915)) 2989 aux_ch = AUX_CH_USBC2; 2990 else 2991 aux_ch = AUX_CH_D; 2992 break; 2993 case DP_AUX_E: 2994 if (DISPLAY_VER(i915) == 13) 2995 aux_ch = AUX_CH_E_XELPD; 2996 else if (IS_ALDERLAKE_S(i915)) 2997 aux_ch = AUX_CH_USBC4; 2998 else 2999 aux_ch = AUX_CH_E; 3000 break; 3001 case DP_AUX_F: 3002 if (DISPLAY_VER(i915) == 13) 3003 aux_ch = AUX_CH_USBC1; 3004 else 3005 aux_ch = AUX_CH_F; 3006 break; 3007 case DP_AUX_G: 3008 if (DISPLAY_VER(i915) == 13) 3009 aux_ch = AUX_CH_USBC2; 3010 else 3011 aux_ch = AUX_CH_G; 3012 break; 3013 case DP_AUX_H: 3014 if (DISPLAY_VER(i915) == 13) 3015 aux_ch = AUX_CH_USBC3; 3016 else 3017 aux_ch = AUX_CH_H; 3018 break; 3019 case DP_AUX_I: 3020 if (DISPLAY_VER(i915) == 13) 3021 aux_ch = AUX_CH_USBC4; 3022 else 3023 aux_ch = AUX_CH_I; 3024 break; 3025 default: 3026 MISSING_CASE(info->alternate_aux_channel); 3027 aux_ch = AUX_CH_A; 3028 break; 3029 } 3030 3031 drm_dbg_kms(&i915->drm, "using AUX %c for port %c (VBT)\n", 3032 aux_ch_name(aux_ch), port_name(port)); 3033 3034 return aux_ch; 3035 } 3036 3037 int intel_bios_max_tmds_clock(struct intel_encoder *encoder) 3038 { 3039 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3040 3041 return i915->vbt.ddi_port_info[encoder->port].max_tmds_clock; 3042 } 3043 3044 int intel_bios_hdmi_level_shift(struct intel_encoder *encoder) 3045 { 3046 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3047 const struct ddi_vbt_port_info *info = 3048 &i915->vbt.ddi_port_info[encoder->port]; 3049 3050 return info->hdmi_level_shift_set ? info->hdmi_level_shift : -1; 3051 } 3052 3053 int intel_bios_encoder_dp_boost_level(const struct intel_bios_encoder_data *devdata) 3054 { 3055 if (!devdata || devdata->i915->vbt.version < 196 || !devdata->child.iboost) 3056 return 0; 3057 3058 return translate_iboost(devdata->child.dp_iboost_level); 3059 } 3060 3061 int intel_bios_encoder_hdmi_boost_level(const struct intel_bios_encoder_data *devdata) 3062 { 3063 if (!devdata || devdata->i915->vbt.version < 196 || !devdata->child.iboost) 3064 return 0; 3065 3066 return translate_iboost(devdata->child.hdmi_iboost_level); 3067 } 3068 3069 int intel_bios_dp_max_link_rate(struct intel_encoder *encoder) 3070 { 3071 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3072 3073 return i915->vbt.ddi_port_info[encoder->port].dp_max_link_rate; 3074 } 3075 3076 int intel_bios_alternate_ddc_pin(struct intel_encoder *encoder) 3077 { 3078 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3079 3080 return i915->vbt.ddi_port_info[encoder->port].alternate_ddc_pin; 3081 } 3082 3083 bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata) 3084 { 3085 return devdata->i915->vbt.version >= 195 && devdata->child.dp_usb_type_c; 3086 } 3087 3088 bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata) 3089 { 3090 return devdata->i915->vbt.version >= 209 && devdata->child.tbt; 3091 } 3092 3093 const struct intel_bios_encoder_data * 3094 intel_bios_encoder_data_lookup(struct drm_i915_private *i915, enum port port) 3095 { 3096 return i915->vbt.ddi_port_info[port].devdata; 3097 } 3098