1 /* 2 * Copyright © 2018 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Madhav Chauhan <madhav.chauhan@intel.com> 25 * Jani Nikula <jani.nikula@intel.com> 26 */ 27 28 #include <drm/display/drm_dsc_helper.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_mipi_dsi.h> 31 32 #include "icl_dsi.h" 33 #include "icl_dsi_regs.h" 34 #include "intel_atomic.h" 35 #include "intel_backlight.h" 36 #include "intel_backlight_regs.h" 37 #include "intel_combo_phy.h" 38 #include "intel_combo_phy_regs.h" 39 #include "intel_connector.h" 40 #include "intel_crtc.h" 41 #include "intel_ddi.h" 42 #include "intel_de.h" 43 #include "intel_dsi.h" 44 #include "intel_dsi_vbt.h" 45 #include "intel_panel.h" 46 #include "intel_vdsc.h" 47 #include "skl_scaler.h" 48 #include "skl_universal_plane.h" 49 50 static int header_credits_available(struct drm_i915_private *dev_priv, 51 enum transcoder dsi_trans) 52 { 53 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) 54 >> FREE_HEADER_CREDIT_SHIFT; 55 } 56 57 static int payload_credits_available(struct drm_i915_private *dev_priv, 58 enum transcoder dsi_trans) 59 { 60 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) 61 >> FREE_PLOAD_CREDIT_SHIFT; 62 } 63 64 static bool wait_for_header_credits(struct drm_i915_private *dev_priv, 65 enum transcoder dsi_trans, int hdr_credit) 66 { 67 if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >= 68 hdr_credit, 100)) { 69 drm_err(&dev_priv->drm, "DSI header credits not released\n"); 70 return false; 71 } 72 73 return true; 74 } 75 76 static bool wait_for_payload_credits(struct drm_i915_private *dev_priv, 77 enum transcoder dsi_trans, int payld_credit) 78 { 79 if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >= 80 payld_credit, 100)) { 81 drm_err(&dev_priv->drm, "DSI payload credits not released\n"); 82 return false; 83 } 84 85 return true; 86 } 87 88 static enum transcoder dsi_port_to_transcoder(enum port port) 89 { 90 if (port == PORT_A) 91 return TRANSCODER_DSI_0; 92 else 93 return TRANSCODER_DSI_1; 94 } 95 96 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) 97 { 98 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 99 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 100 struct mipi_dsi_device *dsi; 101 enum port port; 102 enum transcoder dsi_trans; 103 int ret; 104 105 /* wait for header/payload credits to be released */ 106 for_each_dsi_port(port, intel_dsi->ports) { 107 dsi_trans = dsi_port_to_transcoder(port); 108 wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT); 109 wait_for_payload_credits(dev_priv, dsi_trans, MAX_PLOAD_CREDIT); 110 } 111 112 /* send nop DCS command */ 113 for_each_dsi_port(port, intel_dsi->ports) { 114 dsi = intel_dsi->dsi_hosts[port]->device; 115 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 116 dsi->channel = 0; 117 ret = mipi_dsi_dcs_nop(dsi); 118 if (ret < 0) 119 drm_err(&dev_priv->drm, 120 "error sending DCS NOP command\n"); 121 } 122 123 /* wait for header credits to be released */ 124 for_each_dsi_port(port, intel_dsi->ports) { 125 dsi_trans = dsi_port_to_transcoder(port); 126 wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT); 127 } 128 129 /* wait for LP TX in progress bit to be cleared */ 130 for_each_dsi_port(port, intel_dsi->ports) { 131 dsi_trans = dsi_port_to_transcoder(port); 132 if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & 133 LPTX_IN_PROGRESS), 20)) 134 drm_err(&dev_priv->drm, "LPTX bit not cleared\n"); 135 } 136 } 137 138 static int dsi_send_pkt_payld(struct intel_dsi_host *host, 139 const struct mipi_dsi_packet *packet) 140 { 141 struct intel_dsi *intel_dsi = host->intel_dsi; 142 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 143 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 144 const u8 *data = packet->payload; 145 u32 len = packet->payload_length; 146 int i, j; 147 148 /* payload queue can accept *256 bytes*, check limit */ 149 if (len > MAX_PLOAD_CREDIT * 4) { 150 drm_err(&i915->drm, "payload size exceeds max queue limit\n"); 151 return -EINVAL; 152 } 153 154 for (i = 0; i < len; i += 4) { 155 u32 tmp = 0; 156 157 if (!wait_for_payload_credits(i915, dsi_trans, 1)) 158 return -EBUSY; 159 160 for (j = 0; j < min_t(u32, len - i, 4); j++) 161 tmp |= *data++ << 8 * j; 162 163 intel_de_write(i915, DSI_CMD_TXPYLD(dsi_trans), tmp); 164 } 165 166 return 0; 167 } 168 169 static int dsi_send_pkt_hdr(struct intel_dsi_host *host, 170 const struct mipi_dsi_packet *packet, 171 bool enable_lpdt) 172 { 173 struct intel_dsi *intel_dsi = host->intel_dsi; 174 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 175 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 176 u32 tmp; 177 178 if (!wait_for_header_credits(dev_priv, dsi_trans, 1)) 179 return -EBUSY; 180 181 tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans)); 182 183 if (packet->payload) 184 tmp |= PAYLOAD_PRESENT; 185 else 186 tmp &= ~PAYLOAD_PRESENT; 187 188 tmp &= ~VBLANK_FENCE; 189 190 if (enable_lpdt) 191 tmp |= LP_DATA_TRANSFER; 192 else 193 tmp &= ~LP_DATA_TRANSFER; 194 195 tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK); 196 tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT); 197 tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT); 198 tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT); 199 tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT); 200 intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp); 201 202 return 0; 203 } 204 205 void icl_dsi_frame_update(struct intel_crtc_state *crtc_state) 206 { 207 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 208 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 209 u32 tmp, mode_flags; 210 enum port port; 211 212 mode_flags = crtc_state->mode_flags; 213 214 /* 215 * case 1 also covers dual link 216 * In case of dual link, frame update should be set on 217 * DSI_0 218 */ 219 if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0) 220 port = PORT_A; 221 else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1) 222 port = PORT_B; 223 else 224 return; 225 226 tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port)); 227 tmp |= DSI_FRAME_UPDATE_REQUEST; 228 intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp); 229 } 230 231 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) 232 { 233 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 234 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 235 enum phy phy; 236 u32 tmp; 237 int lane; 238 239 for_each_dsi_phy(phy, intel_dsi->phys) { 240 /* 241 * Program voltage swing and pre-emphasis level values as per 242 * table in BSPEC under DDI buffer programing 243 */ 244 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 245 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); 246 tmp |= SCALING_MODE_SEL(0x2); 247 tmp |= TAP2_DISABLE | TAP3_DISABLE; 248 tmp |= RTERM_SELECT(0x6); 249 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 250 251 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 252 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); 253 tmp |= SCALING_MODE_SEL(0x2); 254 tmp |= TAP2_DISABLE | TAP3_DISABLE; 255 tmp |= RTERM_SELECT(0x6); 256 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 257 258 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy)); 259 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 260 RCOMP_SCALAR_MASK); 261 tmp |= SWING_SEL_UPPER(0x2); 262 tmp |= SWING_SEL_LOWER(0x2); 263 tmp |= RCOMP_SCALAR(0x98); 264 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); 265 266 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy)); 267 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 268 RCOMP_SCALAR_MASK); 269 tmp |= SWING_SEL_UPPER(0x2); 270 tmp |= SWING_SEL_LOWER(0x2); 271 tmp |= RCOMP_SCALAR(0x98); 272 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp); 273 274 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy)); 275 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 276 CURSOR_COEFF_MASK); 277 tmp |= POST_CURSOR_1(0x0); 278 tmp |= POST_CURSOR_2(0x0); 279 tmp |= CURSOR_COEFF(0x3f); 280 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp); 281 282 for (lane = 0; lane <= 3; lane++) { 283 /* Bspec: must not use GRP register for write */ 284 tmp = intel_de_read(dev_priv, 285 ICL_PORT_TX_DW4_LN(lane, phy)); 286 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 287 CURSOR_COEFF_MASK); 288 tmp |= POST_CURSOR_1(0x0); 289 tmp |= POST_CURSOR_2(0x0); 290 tmp |= CURSOR_COEFF(0x3f); 291 intel_de_write(dev_priv, 292 ICL_PORT_TX_DW4_LN(lane, phy), tmp); 293 } 294 } 295 } 296 297 static void configure_dual_link_mode(struct intel_encoder *encoder, 298 const struct intel_crtc_state *pipe_config) 299 { 300 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 301 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 302 i915_reg_t dss_ctl1_reg, dss_ctl2_reg; 303 u32 dss_ctl1; 304 305 /* FIXME: Move all DSS handling to intel_vdsc.c */ 306 if (DISPLAY_VER(dev_priv) >= 12) { 307 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 308 309 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe); 310 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe); 311 } else { 312 dss_ctl1_reg = DSS_CTL1; 313 dss_ctl2_reg = DSS_CTL2; 314 } 315 316 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg); 317 dss_ctl1 |= SPLITTER_ENABLE; 318 dss_ctl1 &= ~OVERLAP_PIXELS_MASK; 319 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); 320 321 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 322 const struct drm_display_mode *adjusted_mode = 323 &pipe_config->hw.adjusted_mode; 324 u32 dss_ctl2; 325 u16 hactive = adjusted_mode->crtc_hdisplay; 326 u16 dl_buffer_depth; 327 328 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE; 329 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; 330 331 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH) 332 drm_err(&dev_priv->drm, 333 "DL buffer depth exceed max value\n"); 334 335 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; 336 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 337 dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg); 338 dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK; 339 dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 340 intel_de_write(dev_priv, dss_ctl2_reg, dss_ctl2); 341 } else { 342 /* Interleave */ 343 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE; 344 } 345 346 intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1); 347 } 348 349 /* aka DSI 8X clock */ 350 static int afe_clk(struct intel_encoder *encoder, 351 const struct intel_crtc_state *crtc_state) 352 { 353 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 354 int bpp; 355 356 if (crtc_state->dsc.compression_enable) 357 bpp = crtc_state->dsc.compressed_bpp; 358 else 359 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 360 361 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count); 362 } 363 364 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder, 365 const struct intel_crtc_state *crtc_state) 366 { 367 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 368 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 369 enum port port; 370 int afe_clk_khz; 371 int theo_word_clk, act_word_clk; 372 u32 esc_clk_div_m, esc_clk_div_m_phy; 373 374 afe_clk_khz = afe_clk(encoder, crtc_state); 375 376 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { 377 theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK); 378 act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2); 379 esc_clk_div_m = act_word_clk * 8; 380 esc_clk_div_m_phy = (act_word_clk - 1) / 2; 381 } else { 382 esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK); 383 } 384 385 for_each_dsi_port(port, intel_dsi->ports) { 386 intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port), 387 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 388 intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port)); 389 } 390 391 for_each_dsi_port(port, intel_dsi->ports) { 392 intel_de_write(dev_priv, ICL_DPHY_ESC_CLK_DIV(port), 393 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 394 intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port)); 395 } 396 397 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { 398 for_each_dsi_port(port, intel_dsi->ports) { 399 intel_de_write(dev_priv, ADL_MIPIO_DW(port, 8), 400 esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY); 401 intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8)); 402 } 403 } 404 } 405 406 static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv, 407 struct intel_dsi *intel_dsi) 408 { 409 enum port port; 410 411 for_each_dsi_port(port, intel_dsi->ports) { 412 drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]); 413 intel_dsi->io_wakeref[port] = 414 intel_display_power_get(dev_priv, 415 port == PORT_A ? 416 POWER_DOMAIN_PORT_DDI_IO_A : 417 POWER_DOMAIN_PORT_DDI_IO_B); 418 } 419 } 420 421 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder) 422 { 423 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 424 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 425 enum port port; 426 u32 tmp; 427 428 for_each_dsi_port(port, intel_dsi->ports) { 429 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port)); 430 tmp |= COMBO_PHY_MODE_DSI; 431 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp); 432 } 433 434 get_dsi_io_power_domains(dev_priv, intel_dsi); 435 } 436 437 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder) 438 { 439 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 440 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 441 enum phy phy; 442 443 for_each_dsi_phy(phy, intel_dsi->phys) 444 intel_combo_phy_power_up_lanes(dev_priv, phy, true, 445 intel_dsi->lane_count, false); 446 } 447 448 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) 449 { 450 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 451 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 452 enum phy phy; 453 u32 tmp; 454 int lane; 455 456 /* Step 4b(i) set loadgen select for transmit and aux lanes */ 457 for_each_dsi_phy(phy, intel_dsi->phys) { 458 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy)); 459 tmp &= ~LOADGEN_SELECT; 460 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp); 461 for (lane = 0; lane <= 3; lane++) { 462 tmp = intel_de_read(dev_priv, 463 ICL_PORT_TX_DW4_LN(lane, phy)); 464 tmp &= ~LOADGEN_SELECT; 465 if (lane != 2) 466 tmp |= LOADGEN_SELECT; 467 intel_de_write(dev_priv, 468 ICL_PORT_TX_DW4_LN(lane, phy), tmp); 469 } 470 } 471 472 /* Step 4b(ii) set latency optimization for transmit and aux lanes */ 473 for_each_dsi_phy(phy, intel_dsi->phys) { 474 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy)); 475 tmp &= ~FRC_LATENCY_OPTIM_MASK; 476 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 477 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp); 478 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy)); 479 tmp &= ~FRC_LATENCY_OPTIM_MASK; 480 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 481 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); 482 483 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */ 484 if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) { 485 tmp = intel_de_read(dev_priv, 486 ICL_PORT_PCS_DW1_AUX(phy)); 487 tmp &= ~LATENCY_OPTIM_MASK; 488 tmp |= LATENCY_OPTIM_VAL(0); 489 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), 490 tmp); 491 492 tmp = intel_de_read(dev_priv, 493 ICL_PORT_PCS_DW1_LN(0, phy)); 494 tmp &= ~LATENCY_OPTIM_MASK; 495 tmp |= LATENCY_OPTIM_VAL(0x1); 496 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), 497 tmp); 498 } 499 } 500 501 } 502 503 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) 504 { 505 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 506 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 507 u32 tmp; 508 enum phy phy; 509 510 /* clear common keeper enable bit */ 511 for_each_dsi_phy(phy, intel_dsi->phys) { 512 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 513 tmp &= ~COMMON_KEEPER_EN; 514 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp); 515 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_AUX(phy)); 516 tmp &= ~COMMON_KEEPER_EN; 517 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), tmp); 518 } 519 520 /* 521 * Set SUS Clock Config bitfield to 11b 522 * Note: loadgen select program is done 523 * as part of lane phy sequence configuration 524 */ 525 for_each_dsi_phy(phy, intel_dsi->phys) { 526 tmp = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); 527 tmp |= SUS_CLOCK_CONFIG; 528 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), tmp); 529 } 530 531 /* Clear training enable to change swing values */ 532 for_each_dsi_phy(phy, intel_dsi->phys) { 533 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 534 tmp &= ~TX_TRAINING_EN; 535 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 536 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 537 tmp &= ~TX_TRAINING_EN; 538 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 539 } 540 541 /* Program swing and de-emphasis */ 542 dsi_program_swing_and_deemphasis(encoder); 543 544 /* Set training enable to trigger update */ 545 for_each_dsi_phy(phy, intel_dsi->phys) { 546 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 547 tmp |= TX_TRAINING_EN; 548 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 549 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 550 tmp |= TX_TRAINING_EN; 551 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 552 } 553 } 554 555 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder) 556 { 557 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 558 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 559 u32 tmp; 560 enum port port; 561 562 for_each_dsi_port(port, intel_dsi->ports) { 563 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 564 tmp |= DDI_BUF_CTL_ENABLE; 565 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp); 566 567 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 568 DDI_BUF_IS_IDLE), 569 500)) 570 drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", 571 port_name(port)); 572 } 573 } 574 575 static void 576 gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, 577 const struct intel_crtc_state *crtc_state) 578 { 579 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 580 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 581 u32 tmp; 582 enum port port; 583 enum phy phy; 584 585 /* Program T-INIT master registers */ 586 for_each_dsi_port(port, intel_dsi->ports) { 587 tmp = intel_de_read(dev_priv, ICL_DSI_T_INIT_MASTER(port)); 588 tmp &= ~DSI_T_INIT_MASTER_MASK; 589 tmp |= intel_dsi->init_count; 590 intel_de_write(dev_priv, ICL_DSI_T_INIT_MASTER(port), tmp); 591 } 592 593 /* Program DPHY clock lanes timings */ 594 for_each_dsi_port(port, intel_dsi->ports) { 595 intel_de_write(dev_priv, DPHY_CLK_TIMING_PARAM(port), 596 intel_dsi->dphy_reg); 597 598 /* shadow register inside display core */ 599 intel_de_write(dev_priv, DSI_CLK_TIMING_PARAM(port), 600 intel_dsi->dphy_reg); 601 } 602 603 /* Program DPHY data lanes timings */ 604 for_each_dsi_port(port, intel_dsi->ports) { 605 intel_de_write(dev_priv, DPHY_DATA_TIMING_PARAM(port), 606 intel_dsi->dphy_data_lane_reg); 607 608 /* shadow register inside display core */ 609 intel_de_write(dev_priv, DSI_DATA_TIMING_PARAM(port), 610 intel_dsi->dphy_data_lane_reg); 611 } 612 613 /* 614 * If DSI link operating at or below an 800 MHz, 615 * TA_SURE should be override and programmed to 616 * a value '0' inside TA_PARAM_REGISTERS otherwise 617 * leave all fields at HW default values. 618 */ 619 if (DISPLAY_VER(dev_priv) == 11) { 620 if (afe_clk(encoder, crtc_state) <= 800000) { 621 for_each_dsi_port(port, intel_dsi->ports) { 622 tmp = intel_de_read(dev_priv, 623 DPHY_TA_TIMING_PARAM(port)); 624 tmp &= ~TA_SURE_MASK; 625 tmp |= TA_SURE_OVERRIDE | TA_SURE(0); 626 intel_de_write(dev_priv, 627 DPHY_TA_TIMING_PARAM(port), 628 tmp); 629 630 /* shadow register inside display core */ 631 tmp = intel_de_read(dev_priv, 632 DSI_TA_TIMING_PARAM(port)); 633 tmp &= ~TA_SURE_MASK; 634 tmp |= TA_SURE_OVERRIDE | TA_SURE(0); 635 intel_de_write(dev_priv, 636 DSI_TA_TIMING_PARAM(port), tmp); 637 } 638 } 639 } 640 641 if (IS_JSL_EHL(dev_priv)) { 642 for_each_dsi_phy(phy, intel_dsi->phys) { 643 tmp = intel_de_read(dev_priv, ICL_DPHY_CHKN(phy)); 644 tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP; 645 intel_de_write(dev_priv, ICL_DPHY_CHKN(phy), tmp); 646 } 647 } 648 } 649 650 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) 651 { 652 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 653 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 654 u32 tmp; 655 enum phy phy; 656 657 mutex_lock(&dev_priv->display.dpll.lock); 658 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 659 for_each_dsi_phy(phy, intel_dsi->phys) 660 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 661 662 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); 663 mutex_unlock(&dev_priv->display.dpll.lock); 664 } 665 666 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) 667 { 668 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 669 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 670 u32 tmp; 671 enum phy phy; 672 673 mutex_lock(&dev_priv->display.dpll.lock); 674 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 675 for_each_dsi_phy(phy, intel_dsi->phys) 676 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 677 678 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); 679 mutex_unlock(&dev_priv->display.dpll.lock); 680 } 681 682 static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder) 683 { 684 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 685 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 686 bool clock_enabled = false; 687 enum phy phy; 688 u32 tmp; 689 690 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 691 692 for_each_dsi_phy(phy, intel_dsi->phys) { 693 if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy))) 694 clock_enabled = true; 695 } 696 697 return clock_enabled; 698 } 699 700 static void gen11_dsi_map_pll(struct intel_encoder *encoder, 701 const struct intel_crtc_state *crtc_state) 702 { 703 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 704 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 705 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 706 enum phy phy; 707 u32 val; 708 709 mutex_lock(&dev_priv->display.dpll.lock); 710 711 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 712 for_each_dsi_phy(phy, intel_dsi->phys) { 713 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 714 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 715 } 716 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 717 718 for_each_dsi_phy(phy, intel_dsi->phys) { 719 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 720 } 721 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 722 723 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); 724 725 mutex_unlock(&dev_priv->display.dpll.lock); 726 } 727 728 static void 729 gen11_dsi_configure_transcoder(struct intel_encoder *encoder, 730 const struct intel_crtc_state *pipe_config) 731 { 732 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 733 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 734 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 735 enum pipe pipe = crtc->pipe; 736 u32 tmp; 737 enum port port; 738 enum transcoder dsi_trans; 739 740 for_each_dsi_port(port, intel_dsi->ports) { 741 dsi_trans = dsi_port_to_transcoder(port); 742 tmp = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)); 743 744 if (intel_dsi->eotp_pkt) 745 tmp &= ~EOTP_DISABLED; 746 else 747 tmp |= EOTP_DISABLED; 748 749 /* enable link calibration if freq > 1.5Gbps */ 750 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) { 751 tmp &= ~LINK_CALIBRATION_MASK; 752 tmp |= CALIBRATION_ENABLED_INITIAL_ONLY; 753 } 754 755 /* configure continuous clock */ 756 tmp &= ~CONTINUOUS_CLK_MASK; 757 if (intel_dsi->clock_stop) 758 tmp |= CLK_ENTER_LP_AFTER_DATA; 759 else 760 tmp |= CLK_HS_CONTINUOUS; 761 762 /* configure buffer threshold limit to minimum */ 763 tmp &= ~PIX_BUF_THRESHOLD_MASK; 764 tmp |= PIX_BUF_THRESHOLD_1_4; 765 766 /* set virtual channel to '0' */ 767 tmp &= ~PIX_VIRT_CHAN_MASK; 768 tmp |= PIX_VIRT_CHAN(0); 769 770 /* program BGR transmission */ 771 if (intel_dsi->bgr_enabled) 772 tmp |= BGR_TRANSMISSION; 773 774 /* select pixel format */ 775 tmp &= ~PIX_FMT_MASK; 776 if (pipe_config->dsc.compression_enable) { 777 tmp |= PIX_FMT_COMPRESSED; 778 } else { 779 switch (intel_dsi->pixel_format) { 780 default: 781 MISSING_CASE(intel_dsi->pixel_format); 782 fallthrough; 783 case MIPI_DSI_FMT_RGB565: 784 tmp |= PIX_FMT_RGB565; 785 break; 786 case MIPI_DSI_FMT_RGB666_PACKED: 787 tmp |= PIX_FMT_RGB666_PACKED; 788 break; 789 case MIPI_DSI_FMT_RGB666: 790 tmp |= PIX_FMT_RGB666_LOOSE; 791 break; 792 case MIPI_DSI_FMT_RGB888: 793 tmp |= PIX_FMT_RGB888; 794 break; 795 } 796 } 797 798 if (DISPLAY_VER(dev_priv) >= 12) { 799 if (is_vid_mode(intel_dsi)) 800 tmp |= BLANKING_PACKET_ENABLE; 801 } 802 803 /* program DSI operation mode */ 804 if (is_vid_mode(intel_dsi)) { 805 tmp &= ~OP_MODE_MASK; 806 switch (intel_dsi->video_mode) { 807 default: 808 MISSING_CASE(intel_dsi->video_mode); 809 fallthrough; 810 case NON_BURST_SYNC_EVENTS: 811 tmp |= VIDEO_MODE_SYNC_EVENT; 812 break; 813 case NON_BURST_SYNC_PULSE: 814 tmp |= VIDEO_MODE_SYNC_PULSE; 815 break; 816 } 817 } else { 818 /* 819 * FIXME: Retrieve this info from VBT. 820 * As per the spec when dsi transcoder is operating 821 * in TE GATE mode, TE comes from GPIO 822 * which is UTIL PIN for DSI 0. 823 * Also this GPIO would not be used for other 824 * purposes is an assumption. 825 */ 826 tmp &= ~OP_MODE_MASK; 827 tmp |= CMD_MODE_TE_GATE; 828 tmp |= TE_SOURCE_GPIO; 829 } 830 831 intel_de_write(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans), tmp); 832 } 833 834 /* enable port sync mode if dual link */ 835 if (intel_dsi->dual_link) { 836 for_each_dsi_port(port, intel_dsi->ports) { 837 dsi_trans = dsi_port_to_transcoder(port); 838 tmp = intel_de_read(dev_priv, 839 TRANS_DDI_FUNC_CTL2(dsi_trans)); 840 tmp |= PORT_SYNC_MODE_ENABLE; 841 intel_de_write(dev_priv, 842 TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); 843 } 844 845 /* configure stream splitting */ 846 configure_dual_link_mode(encoder, pipe_config); 847 } 848 849 for_each_dsi_port(port, intel_dsi->ports) { 850 dsi_trans = dsi_port_to_transcoder(port); 851 852 /* select data lane width */ 853 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 854 tmp &= ~DDI_PORT_WIDTH_MASK; 855 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count); 856 857 /* select input pipe */ 858 tmp &= ~TRANS_DDI_EDP_INPUT_MASK; 859 switch (pipe) { 860 default: 861 MISSING_CASE(pipe); 862 fallthrough; 863 case PIPE_A: 864 tmp |= TRANS_DDI_EDP_INPUT_A_ON; 865 break; 866 case PIPE_B: 867 tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 868 break; 869 case PIPE_C: 870 tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 871 break; 872 case PIPE_D: 873 tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF; 874 break; 875 } 876 877 /* enable DDI buffer */ 878 tmp |= TRANS_DDI_FUNC_ENABLE; 879 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp); 880 } 881 882 /* wait for link ready */ 883 for_each_dsi_port(port, intel_dsi->ports) { 884 dsi_trans = dsi_port_to_transcoder(port); 885 if (wait_for_us((intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)) & 886 LINK_READY), 2500)) 887 drm_err(&dev_priv->drm, "DSI link not ready\n"); 888 } 889 } 890 891 static void 892 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 893 const struct intel_crtc_state *crtc_state) 894 { 895 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 896 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 897 const struct drm_display_mode *adjusted_mode = 898 &crtc_state->hw.adjusted_mode; 899 enum port port; 900 enum transcoder dsi_trans; 901 /* horizontal timings */ 902 u16 htotal, hactive, hsync_start, hsync_end, hsync_size; 903 u16 hback_porch; 904 /* vertical timings */ 905 u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift; 906 int mul = 1, div = 1; 907 908 /* 909 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account 910 * for slower link speed if DSC is enabled. 911 * 912 * The compression frequency ratio is the ratio between compressed and 913 * non-compressed link speeds, and simplifies down to the ratio between 914 * compressed and non-compressed bpp. 915 */ 916 if (crtc_state->dsc.compression_enable) { 917 mul = crtc_state->dsc.compressed_bpp; 918 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 919 } 920 921 hactive = adjusted_mode->crtc_hdisplay; 922 923 if (is_vid_mode(intel_dsi)) 924 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 925 else 926 htotal = DIV_ROUND_UP((hactive + 160) * mul, div); 927 928 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 929 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 930 hsync_size = hsync_end - hsync_start; 931 hback_porch = (adjusted_mode->crtc_htotal - 932 adjusted_mode->crtc_hsync_end); 933 vactive = adjusted_mode->crtc_vdisplay; 934 935 if (is_vid_mode(intel_dsi)) { 936 vtotal = adjusted_mode->crtc_vtotal; 937 } else { 938 int bpp, line_time_us, byte_clk_period_ns; 939 940 if (crtc_state->dsc.compression_enable) 941 bpp = crtc_state->dsc.compressed_bpp; 942 else 943 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 944 945 byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state); 946 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count); 947 vtotal = vactive + DIV_ROUND_UP(400, line_time_us); 948 } 949 vsync_start = adjusted_mode->crtc_vsync_start; 950 vsync_end = adjusted_mode->crtc_vsync_end; 951 vsync_shift = hsync_start - htotal / 2; 952 953 if (intel_dsi->dual_link) { 954 hactive /= 2; 955 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 956 hactive += intel_dsi->pixel_overlap; 957 htotal /= 2; 958 } 959 960 /* minimum hactive as per bspec: 256 pixels */ 961 if (adjusted_mode->crtc_hdisplay < 256) 962 drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n"); 963 964 /* if RGB666 format, then hactive must be multiple of 4 pixels */ 965 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) 966 drm_err(&dev_priv->drm, 967 "hactive pixels are not multiple of 4\n"); 968 969 /* program TRANS_HTOTAL register */ 970 for_each_dsi_port(port, intel_dsi->ports) { 971 dsi_trans = dsi_port_to_transcoder(port); 972 intel_de_write(dev_priv, HTOTAL(dsi_trans), 973 (hactive - 1) | ((htotal - 1) << 16)); 974 } 975 976 /* TRANS_HSYNC register to be programmed only for video mode */ 977 if (is_vid_mode(intel_dsi)) { 978 if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) { 979 /* BSPEC: hsync size should be atleast 16 pixels */ 980 if (hsync_size < 16) 981 drm_err(&dev_priv->drm, 982 "hsync size < 16 pixels\n"); 983 } 984 985 if (hback_porch < 16) 986 drm_err(&dev_priv->drm, "hback porch < 16 pixels\n"); 987 988 if (intel_dsi->dual_link) { 989 hsync_start /= 2; 990 hsync_end /= 2; 991 } 992 993 for_each_dsi_port(port, intel_dsi->ports) { 994 dsi_trans = dsi_port_to_transcoder(port); 995 intel_de_write(dev_priv, HSYNC(dsi_trans), 996 (hsync_start - 1) | ((hsync_end - 1) << 16)); 997 } 998 } 999 1000 /* program TRANS_VTOTAL register */ 1001 for_each_dsi_port(port, intel_dsi->ports) { 1002 dsi_trans = dsi_port_to_transcoder(port); 1003 /* 1004 * FIXME: Programing this by assuming progressive mode, since 1005 * non-interlaced info from VBT is not saved inside 1006 * struct drm_display_mode. 1007 * For interlace mode: program required pixel minus 2 1008 */ 1009 intel_de_write(dev_priv, VTOTAL(dsi_trans), 1010 (vactive - 1) | ((vtotal - 1) << 16)); 1011 } 1012 1013 if (vsync_end < vsync_start || vsync_end > vtotal) 1014 drm_err(&dev_priv->drm, "Invalid vsync_end value\n"); 1015 1016 if (vsync_start < vactive) 1017 drm_err(&dev_priv->drm, "vsync_start less than vactive\n"); 1018 1019 /* program TRANS_VSYNC register for video mode only */ 1020 if (is_vid_mode(intel_dsi)) { 1021 for_each_dsi_port(port, intel_dsi->ports) { 1022 dsi_trans = dsi_port_to_transcoder(port); 1023 intel_de_write(dev_priv, VSYNC(dsi_trans), 1024 (vsync_start - 1) | ((vsync_end - 1) << 16)); 1025 } 1026 } 1027 1028 /* 1029 * FIXME: It has to be programmed only for video modes and interlaced 1030 * modes. Put the check condition here once interlaced 1031 * info available as described above. 1032 * program TRANS_VSYNCSHIFT register 1033 */ 1034 if (is_vid_mode(intel_dsi)) { 1035 for_each_dsi_port(port, intel_dsi->ports) { 1036 dsi_trans = dsi_port_to_transcoder(port); 1037 intel_de_write(dev_priv, VSYNCSHIFT(dsi_trans), 1038 vsync_shift); 1039 } 1040 } 1041 1042 /* program TRANS_VBLANK register, should be same as vtotal programmed */ 1043 if (DISPLAY_VER(dev_priv) >= 12) { 1044 for_each_dsi_port(port, intel_dsi->ports) { 1045 dsi_trans = dsi_port_to_transcoder(port); 1046 intel_de_write(dev_priv, VBLANK(dsi_trans), 1047 (vactive - 1) | ((vtotal - 1) << 16)); 1048 } 1049 } 1050 } 1051 1052 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) 1053 { 1054 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1055 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1056 enum port port; 1057 enum transcoder dsi_trans; 1058 u32 tmp; 1059 1060 for_each_dsi_port(port, intel_dsi->ports) { 1061 dsi_trans = dsi_port_to_transcoder(port); 1062 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1063 tmp |= PIPECONF_ENABLE; 1064 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); 1065 1066 /* wait for transcoder to be enabled */ 1067 if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans), 1068 PIPECONF_STATE_ENABLE, 10)) 1069 drm_err(&dev_priv->drm, 1070 "DSI transcoder not enabled\n"); 1071 } 1072 } 1073 1074 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder, 1075 const struct intel_crtc_state *crtc_state) 1076 { 1077 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1078 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1079 enum port port; 1080 enum transcoder dsi_trans; 1081 u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul; 1082 1083 /* 1084 * escape clock count calculation: 1085 * BYTE_CLK_COUNT = TIME_NS/(8 * UI) 1086 * UI (nsec) = (10^6)/Bitrate 1087 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate 1088 * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS 1089 */ 1090 divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000; 1091 mul = 8 * 1000000; 1092 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul, 1093 divisor); 1094 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor); 1095 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor); 1096 1097 for_each_dsi_port(port, intel_dsi->ports) { 1098 dsi_trans = dsi_port_to_transcoder(port); 1099 1100 /* program hst_tx_timeout */ 1101 tmp = intel_de_read(dev_priv, DSI_HSTX_TO(dsi_trans)); 1102 tmp &= ~HSTX_TIMEOUT_VALUE_MASK; 1103 tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout); 1104 intel_de_write(dev_priv, DSI_HSTX_TO(dsi_trans), tmp); 1105 1106 /* FIXME: DSI_CALIB_TO */ 1107 1108 /* program lp_rx_host timeout */ 1109 tmp = intel_de_read(dev_priv, DSI_LPRX_HOST_TO(dsi_trans)); 1110 tmp &= ~LPRX_TIMEOUT_VALUE_MASK; 1111 tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout); 1112 intel_de_write(dev_priv, DSI_LPRX_HOST_TO(dsi_trans), tmp); 1113 1114 /* FIXME: DSI_PWAIT_TO */ 1115 1116 /* program turn around timeout */ 1117 tmp = intel_de_read(dev_priv, DSI_TA_TO(dsi_trans)); 1118 tmp &= ~TA_TIMEOUT_VALUE_MASK; 1119 tmp |= TA_TIMEOUT_VALUE(ta_timeout); 1120 intel_de_write(dev_priv, DSI_TA_TO(dsi_trans), tmp); 1121 } 1122 } 1123 1124 static void gen11_dsi_config_util_pin(struct intel_encoder *encoder, 1125 bool enable) 1126 { 1127 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1128 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1129 u32 tmp; 1130 1131 /* 1132 * used as TE i/p for DSI0, 1133 * for dual link/DSI1 TE is from slave DSI1 1134 * through GPIO. 1135 */ 1136 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) 1137 return; 1138 1139 tmp = intel_de_read(dev_priv, UTIL_PIN_CTL); 1140 1141 if (enable) { 1142 tmp |= UTIL_PIN_DIRECTION_INPUT; 1143 tmp |= UTIL_PIN_ENABLE; 1144 } else { 1145 tmp &= ~UTIL_PIN_ENABLE; 1146 } 1147 intel_de_write(dev_priv, UTIL_PIN_CTL, tmp); 1148 } 1149 1150 static void 1151 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, 1152 const struct intel_crtc_state *crtc_state) 1153 { 1154 /* step 4a: power up all lanes of the DDI used by DSI */ 1155 gen11_dsi_power_up_lanes(encoder); 1156 1157 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */ 1158 gen11_dsi_config_phy_lanes_sequence(encoder); 1159 1160 /* step 4c: configure voltage swing and skew */ 1161 gen11_dsi_voltage_swing_program_seq(encoder); 1162 1163 /* enable DDI buffer */ 1164 gen11_dsi_enable_ddi_buffer(encoder); 1165 1166 /* setup D-PHY timings */ 1167 gen11_dsi_setup_dphy_timings(encoder, crtc_state); 1168 1169 /* Since transcoder is configured to take events from GPIO */ 1170 gen11_dsi_config_util_pin(encoder, true); 1171 1172 /* step 4h: setup DSI protocol timeouts */ 1173 gen11_dsi_setup_timeouts(encoder, crtc_state); 1174 1175 /* Step (4h, 4i, 4j, 4k): Configure transcoder */ 1176 gen11_dsi_configure_transcoder(encoder, crtc_state); 1177 1178 /* Step 4l: Gate DDI clocks */ 1179 gen11_dsi_gate_clocks(encoder); 1180 } 1181 1182 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) 1183 { 1184 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1185 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1186 struct mipi_dsi_device *dsi; 1187 enum port port; 1188 enum transcoder dsi_trans; 1189 u32 tmp; 1190 int ret; 1191 1192 /* set maximum return packet size */ 1193 for_each_dsi_port(port, intel_dsi->ports) { 1194 dsi_trans = dsi_port_to_transcoder(port); 1195 1196 /* 1197 * FIXME: This uses the number of DW's currently in the payload 1198 * receive queue. This is probably not what we want here. 1199 */ 1200 tmp = intel_de_read(dev_priv, DSI_CMD_RXCTL(dsi_trans)); 1201 tmp &= NUMBER_RX_PLOAD_DW_MASK; 1202 /* multiply "Number Rx Payload DW" by 4 to get max value */ 1203 tmp = tmp * 4; 1204 dsi = intel_dsi->dsi_hosts[port]->device; 1205 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp); 1206 if (ret < 0) 1207 drm_err(&dev_priv->drm, 1208 "error setting max return pkt size%d\n", tmp); 1209 } 1210 1211 /* panel power on related mipi dsi vbt sequences */ 1212 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 1213 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); 1214 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 1215 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 1216 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 1217 1218 /* ensure all panel commands dispatched before enabling transcoder */ 1219 wait_for_cmds_dispatched_to_panel(encoder); 1220 } 1221 1222 static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state, 1223 struct intel_encoder *encoder, 1224 const struct intel_crtc_state *crtc_state, 1225 const struct drm_connector_state *conn_state) 1226 { 1227 /* step2: enable IO power */ 1228 gen11_dsi_enable_io_power(encoder); 1229 1230 /* step3: enable DSI PLL */ 1231 gen11_dsi_program_esc_clk_div(encoder, crtc_state); 1232 } 1233 1234 static void gen11_dsi_pre_enable(struct intel_atomic_state *state, 1235 struct intel_encoder *encoder, 1236 const struct intel_crtc_state *pipe_config, 1237 const struct drm_connector_state *conn_state) 1238 { 1239 /* step3b */ 1240 gen11_dsi_map_pll(encoder, pipe_config); 1241 1242 /* step4: enable DSI port and DPHY */ 1243 gen11_dsi_enable_port_and_phy(encoder, pipe_config); 1244 1245 /* step5: program and powerup panel */ 1246 gen11_dsi_powerup_panel(encoder); 1247 1248 intel_dsc_dsi_pps_write(encoder, pipe_config); 1249 1250 /* step6c: configure transcoder timings */ 1251 gen11_dsi_set_transcoder_timings(encoder, pipe_config); 1252 } 1253 1254 /* 1255 * Wa_1409054076:icl,jsl,ehl 1256 * When pipe A is disabled and MIPI DSI is enabled on pipe B, 1257 * the AMT KVMR feature will incorrectly see pipe A as enabled. 1258 * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave 1259 * it set while DSI is enabled on pipe B 1260 */ 1261 static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder, 1262 enum pipe pipe, bool enable) 1263 { 1264 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1265 1266 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B) 1267 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 1268 IGNORE_KVMR_PIPE_A, 1269 enable ? IGNORE_KVMR_PIPE_A : 0); 1270 } 1271 1272 /* 1273 * Wa_16012360555:adl-p 1274 * SW will have to program the "LP to HS Wakeup Guardband" 1275 * to account for the repeaters on the HS Request/Ready 1276 * PPI signaling between the Display engine and the DPHY. 1277 */ 1278 static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder) 1279 { 1280 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1281 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1282 enum port port; 1283 1284 if (DISPLAY_VER(i915) == 13) { 1285 for_each_dsi_port(port, intel_dsi->ports) 1286 intel_de_rmw(i915, TGL_DSI_CHKN_REG(port), 1287 TGL_DSI_CHKN_LSHS_GB_MASK, 1288 TGL_DSI_CHKN_LSHS_GB(4)); 1289 } 1290 } 1291 1292 static void gen11_dsi_enable(struct intel_atomic_state *state, 1293 struct intel_encoder *encoder, 1294 const struct intel_crtc_state *crtc_state, 1295 const struct drm_connector_state *conn_state) 1296 { 1297 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1298 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 1299 1300 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 1301 1302 /* Wa_1409054076:icl,jsl,ehl */ 1303 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true); 1304 1305 /* Wa_16012360555:adl-p */ 1306 adlp_set_lp_hs_wakeup_gb(encoder); 1307 1308 /* step6d: enable dsi transcoder */ 1309 gen11_dsi_enable_transcoder(encoder); 1310 1311 /* step7: enable backlight */ 1312 intel_backlight_enable(crtc_state, conn_state); 1313 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 1314 1315 intel_crtc_vblank_on(crtc_state); 1316 } 1317 1318 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) 1319 { 1320 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1321 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1322 enum port port; 1323 enum transcoder dsi_trans; 1324 u32 tmp; 1325 1326 for_each_dsi_port(port, intel_dsi->ports) { 1327 dsi_trans = dsi_port_to_transcoder(port); 1328 1329 /* disable transcoder */ 1330 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1331 tmp &= ~PIPECONF_ENABLE; 1332 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); 1333 1334 /* wait for transcoder to be disabled */ 1335 if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans), 1336 PIPECONF_STATE_ENABLE, 50)) 1337 drm_err(&dev_priv->drm, 1338 "DSI trancoder not disabled\n"); 1339 } 1340 } 1341 1342 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder) 1343 { 1344 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1345 1346 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 1347 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 1348 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 1349 1350 /* ensure cmds dispatched to panel */ 1351 wait_for_cmds_dispatched_to_panel(encoder); 1352 } 1353 1354 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) 1355 { 1356 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1357 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1358 enum port port; 1359 enum transcoder dsi_trans; 1360 u32 tmp; 1361 1362 /* disable periodic update mode */ 1363 if (is_cmd_mode(intel_dsi)) { 1364 for_each_dsi_port(port, intel_dsi->ports) { 1365 tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port)); 1366 tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE; 1367 intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp); 1368 } 1369 } 1370 1371 /* put dsi link in ULPS */ 1372 for_each_dsi_port(port, intel_dsi->ports) { 1373 dsi_trans = dsi_port_to_transcoder(port); 1374 tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)); 1375 tmp |= LINK_ENTER_ULPS; 1376 tmp &= ~LINK_ULPS_TYPE_LP11; 1377 intel_de_write(dev_priv, DSI_LP_MSG(dsi_trans), tmp); 1378 1379 if (wait_for_us((intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & 1380 LINK_IN_ULPS), 1381 10)) 1382 drm_err(&dev_priv->drm, "DSI link not in ULPS\n"); 1383 } 1384 1385 /* disable ddi function */ 1386 for_each_dsi_port(port, intel_dsi->ports) { 1387 dsi_trans = dsi_port_to_transcoder(port); 1388 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 1389 tmp &= ~TRANS_DDI_FUNC_ENABLE; 1390 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp); 1391 } 1392 1393 /* disable port sync mode if dual link */ 1394 if (intel_dsi->dual_link) { 1395 for_each_dsi_port(port, intel_dsi->ports) { 1396 dsi_trans = dsi_port_to_transcoder(port); 1397 tmp = intel_de_read(dev_priv, 1398 TRANS_DDI_FUNC_CTL2(dsi_trans)); 1399 tmp &= ~PORT_SYNC_MODE_ENABLE; 1400 intel_de_write(dev_priv, 1401 TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); 1402 } 1403 } 1404 } 1405 1406 static void gen11_dsi_disable_port(struct intel_encoder *encoder) 1407 { 1408 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1409 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1410 u32 tmp; 1411 enum port port; 1412 1413 gen11_dsi_ungate_clocks(encoder); 1414 for_each_dsi_port(port, intel_dsi->ports) { 1415 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 1416 tmp &= ~DDI_BUF_CTL_ENABLE; 1417 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp); 1418 1419 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 1420 DDI_BUF_IS_IDLE), 1421 8)) 1422 drm_err(&dev_priv->drm, 1423 "DDI port:%c buffer not idle\n", 1424 port_name(port)); 1425 } 1426 gen11_dsi_gate_clocks(encoder); 1427 } 1428 1429 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) 1430 { 1431 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1432 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1433 enum port port; 1434 u32 tmp; 1435 1436 for_each_dsi_port(port, intel_dsi->ports) { 1437 intel_wakeref_t wakeref; 1438 1439 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); 1440 intel_display_power_put(dev_priv, 1441 port == PORT_A ? 1442 POWER_DOMAIN_PORT_DDI_IO_A : 1443 POWER_DOMAIN_PORT_DDI_IO_B, 1444 wakeref); 1445 } 1446 1447 /* set mode to DDI */ 1448 for_each_dsi_port(port, intel_dsi->ports) { 1449 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port)); 1450 tmp &= ~COMBO_PHY_MODE_DSI; 1451 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp); 1452 } 1453 } 1454 1455 static void gen11_dsi_disable(struct intel_atomic_state *state, 1456 struct intel_encoder *encoder, 1457 const struct intel_crtc_state *old_crtc_state, 1458 const struct drm_connector_state *old_conn_state) 1459 { 1460 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1461 struct intel_crtc *crtc = to_intel_crtc(old_conn_state->crtc); 1462 1463 /* step1: turn off backlight */ 1464 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 1465 intel_backlight_disable(old_conn_state); 1466 1467 /* step2d,e: disable transcoder and wait */ 1468 gen11_dsi_disable_transcoder(encoder); 1469 1470 /* Wa_1409054076:icl,jsl,ehl */ 1471 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false); 1472 1473 /* step2f,g: powerdown panel */ 1474 gen11_dsi_powerdown_panel(encoder); 1475 1476 /* step2h,i,j: deconfig trancoder */ 1477 gen11_dsi_deconfigure_trancoder(encoder); 1478 1479 /* step3: disable port */ 1480 gen11_dsi_disable_port(encoder); 1481 1482 gen11_dsi_config_util_pin(encoder, false); 1483 1484 /* step4: disable IO power */ 1485 gen11_dsi_disable_io_power(encoder); 1486 } 1487 1488 static void gen11_dsi_post_disable(struct intel_atomic_state *state, 1489 struct intel_encoder *encoder, 1490 const struct intel_crtc_state *old_crtc_state, 1491 const struct drm_connector_state *old_conn_state) 1492 { 1493 intel_crtc_vblank_off(old_crtc_state); 1494 1495 intel_dsc_disable(old_crtc_state); 1496 1497 skl_scaler_disable(old_crtc_state); 1498 } 1499 1500 static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector, 1501 struct drm_display_mode *mode) 1502 { 1503 /* FIXME: DSC? */ 1504 return intel_dsi_mode_valid(connector, mode); 1505 } 1506 1507 static void gen11_dsi_get_timings(struct intel_encoder *encoder, 1508 struct intel_crtc_state *pipe_config) 1509 { 1510 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1511 struct drm_display_mode *adjusted_mode = 1512 &pipe_config->hw.adjusted_mode; 1513 1514 if (pipe_config->dsc.compressed_bpp) { 1515 int div = pipe_config->dsc.compressed_bpp; 1516 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1517 1518 adjusted_mode->crtc_htotal = 1519 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 1520 adjusted_mode->crtc_hsync_start = 1521 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 1522 adjusted_mode->crtc_hsync_end = 1523 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 1524 } 1525 1526 if (intel_dsi->dual_link) { 1527 adjusted_mode->crtc_hdisplay *= 2; 1528 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1529 adjusted_mode->crtc_hdisplay -= 1530 intel_dsi->pixel_overlap; 1531 adjusted_mode->crtc_htotal *= 2; 1532 } 1533 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1534 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1535 1536 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { 1537 if (intel_dsi->dual_link) { 1538 adjusted_mode->crtc_hsync_start *= 2; 1539 adjusted_mode->crtc_hsync_end *= 2; 1540 } 1541 } 1542 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1543 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1544 } 1545 1546 static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi) 1547 { 1548 struct drm_device *dev = intel_dsi->base.base.dev; 1549 struct drm_i915_private *dev_priv = to_i915(dev); 1550 enum transcoder dsi_trans; 1551 u32 val; 1552 1553 if (intel_dsi->ports == BIT(PORT_B)) 1554 dsi_trans = TRANSCODER_DSI_1; 1555 else 1556 dsi_trans = TRANSCODER_DSI_0; 1557 1558 val = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)); 1559 return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE); 1560 } 1561 1562 static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi, 1563 struct intel_crtc_state *pipe_config) 1564 { 1565 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) 1566 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 | 1567 I915_MODE_FLAG_DSI_USE_TE0; 1568 else if (intel_dsi->ports == BIT(PORT_B)) 1569 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1; 1570 else 1571 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0; 1572 } 1573 1574 static void gen11_dsi_get_config(struct intel_encoder *encoder, 1575 struct intel_crtc_state *pipe_config) 1576 { 1577 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1578 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1579 1580 intel_ddi_get_clock(encoder, pipe_config, icl_ddi_combo_get_pll(encoder)); 1581 1582 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; 1583 if (intel_dsi->dual_link) 1584 pipe_config->hw.adjusted_mode.crtc_clock *= 2; 1585 1586 gen11_dsi_get_timings(encoder, pipe_config); 1587 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1588 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); 1589 1590 /* Get the details on which TE should be enabled */ 1591 if (is_cmd_mode(intel_dsi)) 1592 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1593 1594 if (gen11_dsi_is_periodic_cmd_mode(intel_dsi)) 1595 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE; 1596 } 1597 1598 static void gen11_dsi_sync_state(struct intel_encoder *encoder, 1599 const struct intel_crtc_state *crtc_state) 1600 { 1601 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1602 struct intel_crtc *intel_crtc; 1603 enum pipe pipe; 1604 1605 if (!crtc_state) 1606 return; 1607 1608 intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1609 pipe = intel_crtc->pipe; 1610 1611 /* wa verify 1409054076:icl,jsl,ehl */ 1612 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B && 1613 !(intel_de_read(dev_priv, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A)) 1614 drm_dbg_kms(&dev_priv->drm, 1615 "[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n", 1616 encoder->base.base.id, 1617 encoder->base.name); 1618 } 1619 1620 static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, 1621 struct intel_crtc_state *crtc_state) 1622 { 1623 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1624 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1625 int dsc_max_bpc = DISPLAY_VER(dev_priv) >= 12 ? 12 : 10; 1626 bool use_dsc; 1627 int ret; 1628 1629 use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc); 1630 if (!use_dsc) 1631 return 0; 1632 1633 if (crtc_state->pipe_bpp < 8 * 3) 1634 return -EINVAL; 1635 1636 /* FIXME: split only when necessary */ 1637 if (crtc_state->dsc.slice_count > 1) 1638 crtc_state->dsc.dsc_split = true; 1639 1640 vdsc_cfg->convert_rgb = true; 1641 1642 /* FIXME: initialize from VBT */ 1643 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 1644 1645 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1646 1647 ret = intel_dsc_compute_params(crtc_state); 1648 if (ret) 1649 return ret; 1650 1651 /* DSI specific sanity checks on the common code */ 1652 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable); 1653 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422); 1654 drm_WARN_ON(&dev_priv->drm, 1655 vdsc_cfg->pic_width % vdsc_cfg->slice_width); 1656 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8); 1657 drm_WARN_ON(&dev_priv->drm, 1658 vdsc_cfg->pic_height % vdsc_cfg->slice_height); 1659 1660 ret = drm_dsc_compute_rc_parameters(vdsc_cfg); 1661 if (ret) 1662 return ret; 1663 1664 crtc_state->dsc.compression_enable = true; 1665 1666 return 0; 1667 } 1668 1669 static int gen11_dsi_compute_config(struct intel_encoder *encoder, 1670 struct intel_crtc_state *pipe_config, 1671 struct drm_connector_state *conn_state) 1672 { 1673 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1674 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, 1675 base); 1676 struct intel_connector *intel_connector = intel_dsi->attached_connector; 1677 struct drm_display_mode *adjusted_mode = 1678 &pipe_config->hw.adjusted_mode; 1679 int ret; 1680 1681 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1682 1683 ret = intel_panel_compute_config(intel_connector, adjusted_mode); 1684 if (ret) 1685 return ret; 1686 1687 ret = intel_panel_fitting(pipe_config, conn_state); 1688 if (ret) 1689 return ret; 1690 1691 adjusted_mode->flags = 0; 1692 1693 /* Dual link goes to trancoder DSI'0' */ 1694 if (intel_dsi->ports == BIT(PORT_B)) 1695 pipe_config->cpu_transcoder = TRANSCODER_DSI_1; 1696 else 1697 pipe_config->cpu_transcoder = TRANSCODER_DSI_0; 1698 1699 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 1700 pipe_config->pipe_bpp = 24; 1701 else 1702 pipe_config->pipe_bpp = 18; 1703 1704 pipe_config->clock_set = true; 1705 1706 if (gen11_dsi_dsc_compute_config(encoder, pipe_config)) 1707 drm_dbg_kms(&i915->drm, "Attempting to use DSC failed\n"); 1708 1709 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5; 1710 1711 /* 1712 * In case of TE GATE cmd mode, we 1713 * receive TE from the slave if 1714 * dual link is enabled 1715 */ 1716 if (is_cmd_mode(intel_dsi)) 1717 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1718 1719 return 0; 1720 } 1721 1722 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder, 1723 struct intel_crtc_state *crtc_state) 1724 { 1725 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1726 1727 get_dsi_io_power_domains(i915, 1728 enc_to_intel_dsi(encoder)); 1729 } 1730 1731 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, 1732 enum pipe *pipe) 1733 { 1734 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1735 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1736 enum transcoder dsi_trans; 1737 intel_wakeref_t wakeref; 1738 enum port port; 1739 bool ret = false; 1740 u32 tmp; 1741 1742 wakeref = intel_display_power_get_if_enabled(dev_priv, 1743 encoder->power_domain); 1744 if (!wakeref) 1745 return false; 1746 1747 for_each_dsi_port(port, intel_dsi->ports) { 1748 dsi_trans = dsi_port_to_transcoder(port); 1749 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 1750 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1751 case TRANS_DDI_EDP_INPUT_A_ON: 1752 *pipe = PIPE_A; 1753 break; 1754 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1755 *pipe = PIPE_B; 1756 break; 1757 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1758 *pipe = PIPE_C; 1759 break; 1760 case TRANS_DDI_EDP_INPUT_D_ONOFF: 1761 *pipe = PIPE_D; 1762 break; 1763 default: 1764 drm_err(&dev_priv->drm, "Invalid PIPE input\n"); 1765 goto out; 1766 } 1767 1768 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1769 ret = tmp & PIPECONF_ENABLE; 1770 } 1771 out: 1772 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1773 return ret; 1774 } 1775 1776 static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder, 1777 struct intel_crtc_state *crtc_state) 1778 { 1779 if (crtc_state->dsc.compression_enable) { 1780 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n"); 1781 crtc_state->uapi.mode_changed = true; 1782 1783 return false; 1784 } 1785 1786 return true; 1787 } 1788 1789 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder) 1790 { 1791 intel_encoder_destroy(encoder); 1792 } 1793 1794 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = { 1795 .destroy = gen11_dsi_encoder_destroy, 1796 }; 1797 1798 static const struct drm_connector_funcs gen11_dsi_connector_funcs = { 1799 .detect = intel_panel_detect, 1800 .late_register = intel_connector_register, 1801 .early_unregister = intel_connector_unregister, 1802 .destroy = intel_connector_destroy, 1803 .fill_modes = drm_helper_probe_single_connector_modes, 1804 .atomic_get_property = intel_digital_connector_atomic_get_property, 1805 .atomic_set_property = intel_digital_connector_atomic_set_property, 1806 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1807 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1808 }; 1809 1810 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = { 1811 .get_modes = intel_dsi_get_modes, 1812 .mode_valid = gen11_dsi_mode_valid, 1813 .atomic_check = intel_digital_connector_atomic_check, 1814 }; 1815 1816 static int gen11_dsi_host_attach(struct mipi_dsi_host *host, 1817 struct mipi_dsi_device *dsi) 1818 { 1819 return 0; 1820 } 1821 1822 static int gen11_dsi_host_detach(struct mipi_dsi_host *host, 1823 struct mipi_dsi_device *dsi) 1824 { 1825 return 0; 1826 } 1827 1828 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host, 1829 const struct mipi_dsi_msg *msg) 1830 { 1831 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 1832 struct mipi_dsi_packet dsi_pkt; 1833 ssize_t ret; 1834 bool enable_lpdt = false; 1835 1836 ret = mipi_dsi_create_packet(&dsi_pkt, msg); 1837 if (ret < 0) 1838 return ret; 1839 1840 if (msg->flags & MIPI_DSI_MSG_USE_LPM) 1841 enable_lpdt = true; 1842 1843 /* only long packet contains payload */ 1844 if (mipi_dsi_packet_format_is_long(msg->type)) { 1845 ret = dsi_send_pkt_payld(intel_dsi_host, &dsi_pkt); 1846 if (ret < 0) 1847 return ret; 1848 } 1849 1850 /* send packet header */ 1851 ret = dsi_send_pkt_hdr(intel_dsi_host, &dsi_pkt, enable_lpdt); 1852 if (ret < 0) 1853 return ret; 1854 1855 //TODO: add payload receive code if needed 1856 1857 ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length; 1858 1859 return ret; 1860 } 1861 1862 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = { 1863 .attach = gen11_dsi_host_attach, 1864 .detach = gen11_dsi_host_detach, 1865 .transfer = gen11_dsi_host_transfer, 1866 }; 1867 1868 #define ICL_PREPARE_CNT_MAX 0x7 1869 #define ICL_CLK_ZERO_CNT_MAX 0xf 1870 #define ICL_TRAIL_CNT_MAX 0x7 1871 #define ICL_TCLK_PRE_CNT_MAX 0x3 1872 #define ICL_TCLK_POST_CNT_MAX 0x7 1873 #define ICL_HS_ZERO_CNT_MAX 0xf 1874 #define ICL_EXIT_ZERO_CNT_MAX 0x7 1875 1876 static void icl_dphy_param_init(struct intel_dsi *intel_dsi) 1877 { 1878 struct drm_device *dev = intel_dsi->base.base.dev; 1879 struct drm_i915_private *dev_priv = to_i915(dev); 1880 struct intel_connector *connector = intel_dsi->attached_connector; 1881 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 1882 u32 tlpx_ns; 1883 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1884 u32 ths_prepare_ns, tclk_trail_ns; 1885 u32 hs_zero_cnt; 1886 u32 tclk_pre_cnt, tclk_post_cnt; 1887 1888 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1889 1890 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1891 ths_prepare_ns = max(mipi_config->ths_prepare, 1892 mipi_config->tclk_prepare); 1893 1894 /* 1895 * prepare cnt in escape clocks 1896 * this field represents a hexadecimal value with a precision 1897 * of 1.2 – i.e. the most significant bit is the integer 1898 * and the least significant 2 bits are fraction bits. 1899 * so, the field can represent a range of 0.25 to 1.75 1900 */ 1901 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns); 1902 if (prepare_cnt > ICL_PREPARE_CNT_MAX) { 1903 drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n", 1904 prepare_cnt); 1905 prepare_cnt = ICL_PREPARE_CNT_MAX; 1906 } 1907 1908 /* clk zero count in escape clocks */ 1909 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero - 1910 ths_prepare_ns, tlpx_ns); 1911 if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) { 1912 drm_dbg_kms(&dev_priv->drm, 1913 "clk_zero_cnt out of range (%d)\n", clk_zero_cnt); 1914 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX; 1915 } 1916 1917 /* trail cnt in escape clocks*/ 1918 trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns); 1919 if (trail_cnt > ICL_TRAIL_CNT_MAX) { 1920 drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n", 1921 trail_cnt); 1922 trail_cnt = ICL_TRAIL_CNT_MAX; 1923 } 1924 1925 /* tclk pre count in escape clocks */ 1926 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); 1927 if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) { 1928 drm_dbg_kms(&dev_priv->drm, 1929 "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt); 1930 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX; 1931 } 1932 1933 /* tclk post count in escape clocks */ 1934 tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns); 1935 if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) { 1936 drm_dbg_kms(&dev_priv->drm, 1937 "tclk_post_cnt out of range (%d)\n", 1938 tclk_post_cnt); 1939 tclk_post_cnt = ICL_TCLK_POST_CNT_MAX; 1940 } 1941 1942 /* hs zero cnt in escape clocks */ 1943 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - 1944 ths_prepare_ns, tlpx_ns); 1945 if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) { 1946 drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n", 1947 hs_zero_cnt); 1948 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX; 1949 } 1950 1951 /* hs exit zero cnt in escape clocks */ 1952 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns); 1953 if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) { 1954 drm_dbg_kms(&dev_priv->drm, 1955 "exit_zero_cnt out of range (%d)\n", 1956 exit_zero_cnt); 1957 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX; 1958 } 1959 1960 /* clock lane dphy timings */ 1961 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE | 1962 CLK_PREPARE(prepare_cnt) | 1963 CLK_ZERO_OVERRIDE | 1964 CLK_ZERO(clk_zero_cnt) | 1965 CLK_PRE_OVERRIDE | 1966 CLK_PRE(tclk_pre_cnt) | 1967 CLK_POST_OVERRIDE | 1968 CLK_POST(tclk_post_cnt) | 1969 CLK_TRAIL_OVERRIDE | 1970 CLK_TRAIL(trail_cnt)); 1971 1972 /* data lanes dphy timings */ 1973 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | 1974 HS_PREPARE(prepare_cnt) | 1975 HS_ZERO_OVERRIDE | 1976 HS_ZERO(hs_zero_cnt) | 1977 HS_TRAIL_OVERRIDE | 1978 HS_TRAIL(trail_cnt) | 1979 HS_EXIT_OVERRIDE | 1980 HS_EXIT(exit_zero_cnt)); 1981 1982 intel_dsi_log_params(intel_dsi); 1983 } 1984 1985 static void icl_dsi_add_properties(struct intel_connector *connector) 1986 { 1987 const struct drm_display_mode *fixed_mode = 1988 intel_panel_preferred_fixed_mode(connector); 1989 u32 allowed_scalers; 1990 1991 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | 1992 BIT(DRM_MODE_SCALE_FULLSCREEN) | 1993 BIT(DRM_MODE_SCALE_CENTER); 1994 1995 drm_connector_attach_scaling_mode_property(&connector->base, 1996 allowed_scalers); 1997 1998 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; 1999 2000 drm_connector_set_panel_orientation_with_quirk(&connector->base, 2001 intel_dsi_get_panel_orientation(connector), 2002 fixed_mode->hdisplay, 2003 fixed_mode->vdisplay); 2004 } 2005 2006 void icl_dsi_init(struct drm_i915_private *dev_priv) 2007 { 2008 struct drm_device *dev = &dev_priv->drm; 2009 struct intel_dsi *intel_dsi; 2010 struct intel_encoder *encoder; 2011 struct intel_connector *intel_connector; 2012 struct drm_connector *connector; 2013 enum port port; 2014 2015 if (!intel_bios_is_dsi_present(dev_priv, &port)) 2016 return; 2017 2018 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 2019 if (!intel_dsi) 2020 return; 2021 2022 intel_connector = intel_connector_alloc(); 2023 if (!intel_connector) { 2024 kfree(intel_dsi); 2025 return; 2026 } 2027 2028 encoder = &intel_dsi->base; 2029 intel_dsi->attached_connector = intel_connector; 2030 connector = &intel_connector->base; 2031 2032 /* register DSI encoder with DRM subsystem */ 2033 drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs, 2034 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port)); 2035 2036 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable; 2037 encoder->pre_enable = gen11_dsi_pre_enable; 2038 encoder->enable = gen11_dsi_enable; 2039 encoder->disable = gen11_dsi_disable; 2040 encoder->post_disable = gen11_dsi_post_disable; 2041 encoder->port = port; 2042 encoder->get_config = gen11_dsi_get_config; 2043 encoder->sync_state = gen11_dsi_sync_state; 2044 encoder->update_pipe = intel_backlight_update; 2045 encoder->compute_config = gen11_dsi_compute_config; 2046 encoder->get_hw_state = gen11_dsi_get_hw_state; 2047 encoder->initial_fastset_check = gen11_dsi_initial_fastset_check; 2048 encoder->type = INTEL_OUTPUT_DSI; 2049 encoder->cloneable = 0; 2050 encoder->pipe_mask = ~0; 2051 encoder->power_domain = POWER_DOMAIN_PORT_DSI; 2052 encoder->get_power_domains = gen11_dsi_get_power_domains; 2053 encoder->disable_clock = gen11_dsi_gate_clocks; 2054 encoder->is_clock_enabled = gen11_dsi_is_clock_enabled; 2055 2056 /* register DSI connector with DRM subsystem */ 2057 drm_connector_init(dev, connector, &gen11_dsi_connector_funcs, 2058 DRM_MODE_CONNECTOR_DSI); 2059 drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs); 2060 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 2061 connector->interlace_allowed = false; 2062 connector->doublescan_allowed = false; 2063 intel_connector->get_hw_state = intel_connector_get_hw_state; 2064 2065 /* attach connector to encoder */ 2066 intel_connector_attach_encoder(intel_connector, encoder); 2067 2068 encoder->devdata = intel_bios_encoder_data_lookup(dev_priv, port); 2069 intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata, NULL); 2070 2071 mutex_lock(&dev->mode_config.mutex); 2072 intel_panel_add_vbt_lfp_fixed_mode(intel_connector); 2073 mutex_unlock(&dev->mode_config.mutex); 2074 2075 if (!intel_panel_preferred_fixed_mode(intel_connector)) { 2076 drm_err(&dev_priv->drm, "DSI fixed mode info missing\n"); 2077 goto err; 2078 } 2079 2080 intel_panel_init(intel_connector); 2081 2082 intel_backlight_setup(intel_connector, INVALID_PIPE); 2083 2084 if (intel_connector->panel.vbt.dsi.config->dual_link) 2085 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); 2086 else 2087 intel_dsi->ports = BIT(port); 2088 2089 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) 2090 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; 2091 2092 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) 2093 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; 2094 2095 for_each_dsi_port(port, intel_dsi->ports) { 2096 struct intel_dsi_host *host; 2097 2098 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port); 2099 if (!host) 2100 goto err; 2101 2102 intel_dsi->dsi_hosts[port] = host; 2103 } 2104 2105 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 2106 drm_dbg_kms(&dev_priv->drm, "no device found\n"); 2107 goto err; 2108 } 2109 2110 icl_dphy_param_init(intel_dsi); 2111 2112 icl_dsi_add_properties(intel_connector); 2113 return; 2114 2115 err: 2116 drm_connector_cleanup(connector); 2117 drm_encoder_cleanup(&encoder->base); 2118 kfree(intel_dsi); 2119 kfree(intel_connector); 2120 } 2121