1 /* 2 * Copyright © 2018 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Madhav Chauhan <madhav.chauhan@intel.com> 25 * Jani Nikula <jani.nikula@intel.com> 26 */ 27 28 #include <drm/drm_atomic_helper.h> 29 #include <drm/drm_mipi_dsi.h> 30 31 #include "intel_atomic.h" 32 #include "intel_combo_phy.h" 33 #include "intel_connector.h" 34 #include "intel_crtc.h" 35 #include "intel_ddi.h" 36 #include "intel_de.h" 37 #include "intel_dsi.h" 38 #include "intel_panel.h" 39 #include "intel_vdsc.h" 40 #include "skl_scaler.h" 41 #include "skl_universal_plane.h" 42 43 static int header_credits_available(struct drm_i915_private *dev_priv, 44 enum transcoder dsi_trans) 45 { 46 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) 47 >> FREE_HEADER_CREDIT_SHIFT; 48 } 49 50 static int payload_credits_available(struct drm_i915_private *dev_priv, 51 enum transcoder dsi_trans) 52 { 53 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) 54 >> FREE_PLOAD_CREDIT_SHIFT; 55 } 56 57 static void wait_for_header_credits(struct drm_i915_private *dev_priv, 58 enum transcoder dsi_trans) 59 { 60 if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >= 61 MAX_HEADER_CREDIT, 100)) 62 drm_err(&dev_priv->drm, "DSI header credits not released\n"); 63 } 64 65 static void wait_for_payload_credits(struct drm_i915_private *dev_priv, 66 enum transcoder dsi_trans) 67 { 68 if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >= 69 MAX_PLOAD_CREDIT, 100)) 70 drm_err(&dev_priv->drm, "DSI payload credits not released\n"); 71 } 72 73 static enum transcoder dsi_port_to_transcoder(enum port port) 74 { 75 if (port == PORT_A) 76 return TRANSCODER_DSI_0; 77 else 78 return TRANSCODER_DSI_1; 79 } 80 81 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) 82 { 83 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 84 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 85 struct mipi_dsi_device *dsi; 86 enum port port; 87 enum transcoder dsi_trans; 88 int ret; 89 90 /* wait for header/payload credits to be released */ 91 for_each_dsi_port(port, intel_dsi->ports) { 92 dsi_trans = dsi_port_to_transcoder(port); 93 wait_for_header_credits(dev_priv, dsi_trans); 94 wait_for_payload_credits(dev_priv, dsi_trans); 95 } 96 97 /* send nop DCS command */ 98 for_each_dsi_port(port, intel_dsi->ports) { 99 dsi = intel_dsi->dsi_hosts[port]->device; 100 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 101 dsi->channel = 0; 102 ret = mipi_dsi_dcs_nop(dsi); 103 if (ret < 0) 104 drm_err(&dev_priv->drm, 105 "error sending DCS NOP command\n"); 106 } 107 108 /* wait for header credits to be released */ 109 for_each_dsi_port(port, intel_dsi->ports) { 110 dsi_trans = dsi_port_to_transcoder(port); 111 wait_for_header_credits(dev_priv, dsi_trans); 112 } 113 114 /* wait for LP TX in progress bit to be cleared */ 115 for_each_dsi_port(port, intel_dsi->ports) { 116 dsi_trans = dsi_port_to_transcoder(port); 117 if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & 118 LPTX_IN_PROGRESS), 20)) 119 drm_err(&dev_priv->drm, "LPTX bit not cleared\n"); 120 } 121 } 122 123 static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data, 124 u32 len) 125 { 126 struct intel_dsi *intel_dsi = host->intel_dsi; 127 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 128 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 129 int free_credits; 130 int i, j; 131 132 for (i = 0; i < len; i += 4) { 133 u32 tmp = 0; 134 135 free_credits = payload_credits_available(dev_priv, dsi_trans); 136 if (free_credits < 1) { 137 drm_err(&dev_priv->drm, 138 "Payload credit not available\n"); 139 return false; 140 } 141 142 for (j = 0; j < min_t(u32, len - i, 4); j++) 143 tmp |= *data++ << 8 * j; 144 145 intel_de_write(dev_priv, DSI_CMD_TXPYLD(dsi_trans), tmp); 146 } 147 148 return true; 149 } 150 151 static int dsi_send_pkt_hdr(struct intel_dsi_host *host, 152 struct mipi_dsi_packet pkt, bool enable_lpdt) 153 { 154 struct intel_dsi *intel_dsi = host->intel_dsi; 155 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 156 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 157 u32 tmp; 158 int free_credits; 159 160 /* check if header credit available */ 161 free_credits = header_credits_available(dev_priv, dsi_trans); 162 if (free_credits < 1) { 163 drm_err(&dev_priv->drm, 164 "send pkt header failed, not enough hdr credits\n"); 165 return -1; 166 } 167 168 tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans)); 169 170 if (pkt.payload) 171 tmp |= PAYLOAD_PRESENT; 172 else 173 tmp &= ~PAYLOAD_PRESENT; 174 175 tmp &= ~VBLANK_FENCE; 176 177 if (enable_lpdt) 178 tmp |= LP_DATA_TRANSFER; 179 180 tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK); 181 tmp |= ((pkt.header[0] & VC_MASK) << VC_SHIFT); 182 tmp |= ((pkt.header[0] & DT_MASK) << DT_SHIFT); 183 tmp |= (pkt.header[1] << PARAM_WC_LOWER_SHIFT); 184 tmp |= (pkt.header[2] << PARAM_WC_UPPER_SHIFT); 185 intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp); 186 187 return 0; 188 } 189 190 static int dsi_send_pkt_payld(struct intel_dsi_host *host, 191 struct mipi_dsi_packet pkt) 192 { 193 struct intel_dsi *intel_dsi = host->intel_dsi; 194 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 195 196 /* payload queue can accept *256 bytes*, check limit */ 197 if (pkt.payload_length > MAX_PLOAD_CREDIT * 4) { 198 drm_err(&i915->drm, "payload size exceeds max queue limit\n"); 199 return -1; 200 } 201 202 /* load data into command payload queue */ 203 if (!add_payld_to_queue(host, pkt.payload, 204 pkt.payload_length)) { 205 drm_err(&i915->drm, "adding payload to queue failed\n"); 206 return -1; 207 } 208 209 return 0; 210 } 211 212 void icl_dsi_frame_update(struct intel_crtc_state *crtc_state) 213 { 214 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 215 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 216 u32 tmp, mode_flags; 217 enum port port; 218 219 mode_flags = crtc_state->mode_flags; 220 221 /* 222 * case 1 also covers dual link 223 * In case of dual link, frame update should be set on 224 * DSI_0 225 */ 226 if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0) 227 port = PORT_A; 228 else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1) 229 port = PORT_B; 230 else 231 return; 232 233 tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port)); 234 tmp |= DSI_FRAME_UPDATE_REQUEST; 235 intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp); 236 } 237 238 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) 239 { 240 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 241 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 242 enum phy phy; 243 u32 tmp; 244 int lane; 245 246 for_each_dsi_phy(phy, intel_dsi->phys) { 247 /* 248 * Program voltage swing and pre-emphasis level values as per 249 * table in BSPEC under DDI buffer programing 250 */ 251 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 252 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); 253 tmp |= SCALING_MODE_SEL(0x2); 254 tmp |= TAP2_DISABLE | TAP3_DISABLE; 255 tmp |= RTERM_SELECT(0x6); 256 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 257 258 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 259 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); 260 tmp |= SCALING_MODE_SEL(0x2); 261 tmp |= TAP2_DISABLE | TAP3_DISABLE; 262 tmp |= RTERM_SELECT(0x6); 263 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 264 265 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); 266 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 267 RCOMP_SCALAR_MASK); 268 tmp |= SWING_SEL_UPPER(0x2); 269 tmp |= SWING_SEL_LOWER(0x2); 270 tmp |= RCOMP_SCALAR(0x98); 271 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); 272 273 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy)); 274 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 275 RCOMP_SCALAR_MASK); 276 tmp |= SWING_SEL_UPPER(0x2); 277 tmp |= SWING_SEL_LOWER(0x2); 278 tmp |= RCOMP_SCALAR(0x98); 279 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp); 280 281 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy)); 282 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 283 CURSOR_COEFF_MASK); 284 tmp |= POST_CURSOR_1(0x0); 285 tmp |= POST_CURSOR_2(0x0); 286 tmp |= CURSOR_COEFF(0x3f); 287 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp); 288 289 for (lane = 0; lane <= 3; lane++) { 290 /* Bspec: must not use GRP register for write */ 291 tmp = intel_de_read(dev_priv, 292 ICL_PORT_TX_DW4_LN(lane, phy)); 293 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 294 CURSOR_COEFF_MASK); 295 tmp |= POST_CURSOR_1(0x0); 296 tmp |= POST_CURSOR_2(0x0); 297 tmp |= CURSOR_COEFF(0x3f); 298 intel_de_write(dev_priv, 299 ICL_PORT_TX_DW4_LN(lane, phy), tmp); 300 } 301 } 302 } 303 304 static void configure_dual_link_mode(struct intel_encoder *encoder, 305 const struct intel_crtc_state *pipe_config) 306 { 307 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 308 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 309 u32 dss_ctl1; 310 311 dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1); 312 dss_ctl1 |= SPLITTER_ENABLE; 313 dss_ctl1 &= ~OVERLAP_PIXELS_MASK; 314 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); 315 316 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 317 const struct drm_display_mode *adjusted_mode = 318 &pipe_config->hw.adjusted_mode; 319 u32 dss_ctl2; 320 u16 hactive = adjusted_mode->crtc_hdisplay; 321 u16 dl_buffer_depth; 322 323 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE; 324 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; 325 326 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH) 327 drm_err(&dev_priv->drm, 328 "DL buffer depth exceed max value\n"); 329 330 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; 331 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 332 dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2); 333 dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK; 334 dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 335 intel_de_write(dev_priv, DSS_CTL2, dss_ctl2); 336 } else { 337 /* Interleave */ 338 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE; 339 } 340 341 intel_de_write(dev_priv, DSS_CTL1, dss_ctl1); 342 } 343 344 /* aka DSI 8X clock */ 345 static int afe_clk(struct intel_encoder *encoder, 346 const struct intel_crtc_state *crtc_state) 347 { 348 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 349 int bpp; 350 351 if (crtc_state->dsc.compression_enable) 352 bpp = crtc_state->dsc.compressed_bpp; 353 else 354 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 355 356 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count); 357 } 358 359 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder, 360 const struct intel_crtc_state *crtc_state) 361 { 362 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 363 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 364 enum port port; 365 int afe_clk_khz; 366 int theo_word_clk, act_word_clk; 367 u32 esc_clk_div_m, esc_clk_div_m_phy; 368 369 afe_clk_khz = afe_clk(encoder, crtc_state); 370 371 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { 372 theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK); 373 act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2); 374 esc_clk_div_m = act_word_clk * 8; 375 esc_clk_div_m_phy = (act_word_clk - 1) / 2; 376 } else { 377 esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK); 378 } 379 380 for_each_dsi_port(port, intel_dsi->ports) { 381 intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port), 382 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 383 intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port)); 384 } 385 386 for_each_dsi_port(port, intel_dsi->ports) { 387 intel_de_write(dev_priv, ICL_DPHY_ESC_CLK_DIV(port), 388 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 389 intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port)); 390 } 391 392 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { 393 for_each_dsi_port(port, intel_dsi->ports) { 394 intel_de_write(dev_priv, ADL_MIPIO_DW(port, 8), 395 esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY); 396 intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8)); 397 } 398 } 399 } 400 401 static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv, 402 struct intel_dsi *intel_dsi) 403 { 404 enum port port; 405 406 for_each_dsi_port(port, intel_dsi->ports) { 407 drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]); 408 intel_dsi->io_wakeref[port] = 409 intel_display_power_get(dev_priv, 410 port == PORT_A ? 411 POWER_DOMAIN_PORT_DDI_A_IO : 412 POWER_DOMAIN_PORT_DDI_B_IO); 413 } 414 } 415 416 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder) 417 { 418 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 419 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 420 enum port port; 421 u32 tmp; 422 423 for_each_dsi_port(port, intel_dsi->ports) { 424 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port)); 425 tmp |= COMBO_PHY_MODE_DSI; 426 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp); 427 } 428 429 get_dsi_io_power_domains(dev_priv, intel_dsi); 430 } 431 432 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder) 433 { 434 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 435 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 436 enum phy phy; 437 438 for_each_dsi_phy(phy, intel_dsi->phys) 439 intel_combo_phy_power_up_lanes(dev_priv, phy, true, 440 intel_dsi->lane_count, false); 441 } 442 443 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) 444 { 445 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 446 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 447 enum phy phy; 448 u32 tmp; 449 int lane; 450 451 /* Step 4b(i) set loadgen select for transmit and aux lanes */ 452 for_each_dsi_phy(phy, intel_dsi->phys) { 453 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy)); 454 tmp &= ~LOADGEN_SELECT; 455 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp); 456 for (lane = 0; lane <= 3; lane++) { 457 tmp = intel_de_read(dev_priv, 458 ICL_PORT_TX_DW4_LN(lane, phy)); 459 tmp &= ~LOADGEN_SELECT; 460 if (lane != 2) 461 tmp |= LOADGEN_SELECT; 462 intel_de_write(dev_priv, 463 ICL_PORT_TX_DW4_LN(lane, phy), tmp); 464 } 465 } 466 467 /* Step 4b(ii) set latency optimization for transmit and aux lanes */ 468 for_each_dsi_phy(phy, intel_dsi->phys) { 469 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy)); 470 tmp &= ~FRC_LATENCY_OPTIM_MASK; 471 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 472 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp); 473 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); 474 tmp &= ~FRC_LATENCY_OPTIM_MASK; 475 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 476 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); 477 478 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */ 479 if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) { 480 tmp = intel_de_read(dev_priv, 481 ICL_PORT_PCS_DW1_AUX(phy)); 482 tmp &= ~LATENCY_OPTIM_MASK; 483 tmp |= LATENCY_OPTIM_VAL(0); 484 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), 485 tmp); 486 487 tmp = intel_de_read(dev_priv, 488 ICL_PORT_PCS_DW1_LN0(phy)); 489 tmp &= ~LATENCY_OPTIM_MASK; 490 tmp |= LATENCY_OPTIM_VAL(0x1); 491 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), 492 tmp); 493 } 494 } 495 496 } 497 498 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) 499 { 500 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 501 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 502 u32 tmp; 503 enum phy phy; 504 505 /* clear common keeper enable bit */ 506 for_each_dsi_phy(phy, intel_dsi->phys) { 507 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy)); 508 tmp &= ~COMMON_KEEPER_EN; 509 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp); 510 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_AUX(phy)); 511 tmp &= ~COMMON_KEEPER_EN; 512 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), tmp); 513 } 514 515 /* 516 * Set SUS Clock Config bitfield to 11b 517 * Note: loadgen select program is done 518 * as part of lane phy sequence configuration 519 */ 520 for_each_dsi_phy(phy, intel_dsi->phys) { 521 tmp = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); 522 tmp |= SUS_CLOCK_CONFIG; 523 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), tmp); 524 } 525 526 /* Clear training enable to change swing values */ 527 for_each_dsi_phy(phy, intel_dsi->phys) { 528 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 529 tmp &= ~TX_TRAINING_EN; 530 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 531 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 532 tmp &= ~TX_TRAINING_EN; 533 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 534 } 535 536 /* Program swing and de-emphasis */ 537 dsi_program_swing_and_deemphasis(encoder); 538 539 /* Set training enable to trigger update */ 540 for_each_dsi_phy(phy, intel_dsi->phys) { 541 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 542 tmp |= TX_TRAINING_EN; 543 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 544 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 545 tmp |= TX_TRAINING_EN; 546 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 547 } 548 } 549 550 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder) 551 { 552 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 553 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 554 u32 tmp; 555 enum port port; 556 557 for_each_dsi_port(port, intel_dsi->ports) { 558 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 559 tmp |= DDI_BUF_CTL_ENABLE; 560 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp); 561 562 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 563 DDI_BUF_IS_IDLE), 564 500)) 565 drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", 566 port_name(port)); 567 } 568 } 569 570 static void 571 gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, 572 const struct intel_crtc_state *crtc_state) 573 { 574 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 575 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 576 u32 tmp; 577 enum port port; 578 enum phy phy; 579 580 /* Program T-INIT master registers */ 581 for_each_dsi_port(port, intel_dsi->ports) { 582 tmp = intel_de_read(dev_priv, ICL_DSI_T_INIT_MASTER(port)); 583 tmp &= ~MASTER_INIT_TIMER_MASK; 584 tmp |= intel_dsi->init_count; 585 intel_de_write(dev_priv, ICL_DSI_T_INIT_MASTER(port), tmp); 586 } 587 588 /* Program DPHY clock lanes timings */ 589 for_each_dsi_port(port, intel_dsi->ports) { 590 intel_de_write(dev_priv, DPHY_CLK_TIMING_PARAM(port), 591 intel_dsi->dphy_reg); 592 593 /* shadow register inside display core */ 594 intel_de_write(dev_priv, DSI_CLK_TIMING_PARAM(port), 595 intel_dsi->dphy_reg); 596 } 597 598 /* Program DPHY data lanes timings */ 599 for_each_dsi_port(port, intel_dsi->ports) { 600 intel_de_write(dev_priv, DPHY_DATA_TIMING_PARAM(port), 601 intel_dsi->dphy_data_lane_reg); 602 603 /* shadow register inside display core */ 604 intel_de_write(dev_priv, DSI_DATA_TIMING_PARAM(port), 605 intel_dsi->dphy_data_lane_reg); 606 } 607 608 /* 609 * If DSI link operating at or below an 800 MHz, 610 * TA_SURE should be override and programmed to 611 * a value '0' inside TA_PARAM_REGISTERS otherwise 612 * leave all fields at HW default values. 613 */ 614 if (DISPLAY_VER(dev_priv) == 11) { 615 if (afe_clk(encoder, crtc_state) <= 800000) { 616 for_each_dsi_port(port, intel_dsi->ports) { 617 tmp = intel_de_read(dev_priv, 618 DPHY_TA_TIMING_PARAM(port)); 619 tmp &= ~TA_SURE_MASK; 620 tmp |= TA_SURE_OVERRIDE | TA_SURE(0); 621 intel_de_write(dev_priv, 622 DPHY_TA_TIMING_PARAM(port), 623 tmp); 624 625 /* shadow register inside display core */ 626 tmp = intel_de_read(dev_priv, 627 DSI_TA_TIMING_PARAM(port)); 628 tmp &= ~TA_SURE_MASK; 629 tmp |= TA_SURE_OVERRIDE | TA_SURE(0); 630 intel_de_write(dev_priv, 631 DSI_TA_TIMING_PARAM(port), tmp); 632 } 633 } 634 } 635 636 if (IS_JSL_EHL(dev_priv)) { 637 for_each_dsi_phy(phy, intel_dsi->phys) { 638 tmp = intel_de_read(dev_priv, ICL_DPHY_CHKN(phy)); 639 tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP; 640 intel_de_write(dev_priv, ICL_DPHY_CHKN(phy), tmp); 641 } 642 } 643 } 644 645 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) 646 { 647 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 648 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 649 u32 tmp; 650 enum phy phy; 651 652 mutex_lock(&dev_priv->dpll.lock); 653 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 654 for_each_dsi_phy(phy, intel_dsi->phys) 655 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 656 657 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); 658 mutex_unlock(&dev_priv->dpll.lock); 659 } 660 661 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) 662 { 663 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 664 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 665 u32 tmp; 666 enum phy phy; 667 668 mutex_lock(&dev_priv->dpll.lock); 669 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 670 for_each_dsi_phy(phy, intel_dsi->phys) 671 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 672 673 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); 674 mutex_unlock(&dev_priv->dpll.lock); 675 } 676 677 static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder) 678 { 679 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 680 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 681 bool clock_enabled = false; 682 enum phy phy; 683 u32 tmp; 684 685 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 686 687 for_each_dsi_phy(phy, intel_dsi->phys) { 688 if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy))) 689 clock_enabled = true; 690 } 691 692 return clock_enabled; 693 } 694 695 static void gen11_dsi_map_pll(struct intel_encoder *encoder, 696 const struct intel_crtc_state *crtc_state) 697 { 698 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 699 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 700 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 701 enum phy phy; 702 u32 val; 703 704 mutex_lock(&dev_priv->dpll.lock); 705 706 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 707 for_each_dsi_phy(phy, intel_dsi->phys) { 708 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 709 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 710 } 711 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 712 713 for_each_dsi_phy(phy, intel_dsi->phys) { 714 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 715 } 716 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 717 718 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); 719 720 mutex_unlock(&dev_priv->dpll.lock); 721 } 722 723 static void 724 gen11_dsi_configure_transcoder(struct intel_encoder *encoder, 725 const struct intel_crtc_state *pipe_config) 726 { 727 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 728 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 729 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 730 enum pipe pipe = crtc->pipe; 731 u32 tmp; 732 enum port port; 733 enum transcoder dsi_trans; 734 735 for_each_dsi_port(port, intel_dsi->ports) { 736 dsi_trans = dsi_port_to_transcoder(port); 737 tmp = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)); 738 739 if (intel_dsi->eotp_pkt) 740 tmp &= ~EOTP_DISABLED; 741 else 742 tmp |= EOTP_DISABLED; 743 744 /* enable link calibration if freq > 1.5Gbps */ 745 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) { 746 tmp &= ~LINK_CALIBRATION_MASK; 747 tmp |= CALIBRATION_ENABLED_INITIAL_ONLY; 748 } 749 750 /* configure continuous clock */ 751 tmp &= ~CONTINUOUS_CLK_MASK; 752 if (intel_dsi->clock_stop) 753 tmp |= CLK_ENTER_LP_AFTER_DATA; 754 else 755 tmp |= CLK_HS_CONTINUOUS; 756 757 /* configure buffer threshold limit to minimum */ 758 tmp &= ~PIX_BUF_THRESHOLD_MASK; 759 tmp |= PIX_BUF_THRESHOLD_1_4; 760 761 /* set virtual channel to '0' */ 762 tmp &= ~PIX_VIRT_CHAN_MASK; 763 tmp |= PIX_VIRT_CHAN(0); 764 765 /* program BGR transmission */ 766 if (intel_dsi->bgr_enabled) 767 tmp |= BGR_TRANSMISSION; 768 769 /* select pixel format */ 770 tmp &= ~PIX_FMT_MASK; 771 if (pipe_config->dsc.compression_enable) { 772 tmp |= PIX_FMT_COMPRESSED; 773 } else { 774 switch (intel_dsi->pixel_format) { 775 default: 776 MISSING_CASE(intel_dsi->pixel_format); 777 fallthrough; 778 case MIPI_DSI_FMT_RGB565: 779 tmp |= PIX_FMT_RGB565; 780 break; 781 case MIPI_DSI_FMT_RGB666_PACKED: 782 tmp |= PIX_FMT_RGB666_PACKED; 783 break; 784 case MIPI_DSI_FMT_RGB666: 785 tmp |= PIX_FMT_RGB666_LOOSE; 786 break; 787 case MIPI_DSI_FMT_RGB888: 788 tmp |= PIX_FMT_RGB888; 789 break; 790 } 791 } 792 793 if (DISPLAY_VER(dev_priv) >= 12) { 794 if (is_vid_mode(intel_dsi)) 795 tmp |= BLANKING_PACKET_ENABLE; 796 } 797 798 /* program DSI operation mode */ 799 if (is_vid_mode(intel_dsi)) { 800 tmp &= ~OP_MODE_MASK; 801 switch (intel_dsi->video_mode_format) { 802 default: 803 MISSING_CASE(intel_dsi->video_mode_format); 804 fallthrough; 805 case VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS: 806 tmp |= VIDEO_MODE_SYNC_EVENT; 807 break; 808 case VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE: 809 tmp |= VIDEO_MODE_SYNC_PULSE; 810 break; 811 } 812 } else { 813 /* 814 * FIXME: Retrieve this info from VBT. 815 * As per the spec when dsi transcoder is operating 816 * in TE GATE mode, TE comes from GPIO 817 * which is UTIL PIN for DSI 0. 818 * Also this GPIO would not be used for other 819 * purposes is an assumption. 820 */ 821 tmp &= ~OP_MODE_MASK; 822 tmp |= CMD_MODE_TE_GATE; 823 tmp |= TE_SOURCE_GPIO; 824 } 825 826 intel_de_write(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans), tmp); 827 } 828 829 /* enable port sync mode if dual link */ 830 if (intel_dsi->dual_link) { 831 for_each_dsi_port(port, intel_dsi->ports) { 832 dsi_trans = dsi_port_to_transcoder(port); 833 tmp = intel_de_read(dev_priv, 834 TRANS_DDI_FUNC_CTL2(dsi_trans)); 835 tmp |= PORT_SYNC_MODE_ENABLE; 836 intel_de_write(dev_priv, 837 TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); 838 } 839 840 /* configure stream splitting */ 841 configure_dual_link_mode(encoder, pipe_config); 842 } 843 844 for_each_dsi_port(port, intel_dsi->ports) { 845 dsi_trans = dsi_port_to_transcoder(port); 846 847 /* select data lane width */ 848 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 849 tmp &= ~DDI_PORT_WIDTH_MASK; 850 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count); 851 852 /* select input pipe */ 853 tmp &= ~TRANS_DDI_EDP_INPUT_MASK; 854 switch (pipe) { 855 default: 856 MISSING_CASE(pipe); 857 fallthrough; 858 case PIPE_A: 859 tmp |= TRANS_DDI_EDP_INPUT_A_ON; 860 break; 861 case PIPE_B: 862 tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 863 break; 864 case PIPE_C: 865 tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 866 break; 867 case PIPE_D: 868 tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF; 869 break; 870 } 871 872 /* enable DDI buffer */ 873 tmp |= TRANS_DDI_FUNC_ENABLE; 874 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp); 875 } 876 877 /* wait for link ready */ 878 for_each_dsi_port(port, intel_dsi->ports) { 879 dsi_trans = dsi_port_to_transcoder(port); 880 if (wait_for_us((intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)) & 881 LINK_READY), 2500)) 882 drm_err(&dev_priv->drm, "DSI link not ready\n"); 883 } 884 } 885 886 static void 887 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 888 const struct intel_crtc_state *crtc_state) 889 { 890 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 891 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 892 const struct drm_display_mode *adjusted_mode = 893 &crtc_state->hw.adjusted_mode; 894 enum port port; 895 enum transcoder dsi_trans; 896 /* horizontal timings */ 897 u16 htotal, hactive, hsync_start, hsync_end, hsync_size; 898 u16 hback_porch; 899 /* vertical timings */ 900 u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift; 901 int mul = 1, div = 1; 902 903 /* 904 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account 905 * for slower link speed if DSC is enabled. 906 * 907 * The compression frequency ratio is the ratio between compressed and 908 * non-compressed link speeds, and simplifies down to the ratio between 909 * compressed and non-compressed bpp. 910 */ 911 if (crtc_state->dsc.compression_enable) { 912 mul = crtc_state->dsc.compressed_bpp; 913 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 914 } 915 916 hactive = adjusted_mode->crtc_hdisplay; 917 918 if (is_vid_mode(intel_dsi)) 919 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 920 else 921 htotal = DIV_ROUND_UP((hactive + 160) * mul, div); 922 923 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 924 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 925 hsync_size = hsync_end - hsync_start; 926 hback_porch = (adjusted_mode->crtc_htotal - 927 adjusted_mode->crtc_hsync_end); 928 vactive = adjusted_mode->crtc_vdisplay; 929 930 if (is_vid_mode(intel_dsi)) { 931 vtotal = adjusted_mode->crtc_vtotal; 932 } else { 933 int bpp, line_time_us, byte_clk_period_ns; 934 935 if (crtc_state->dsc.compression_enable) 936 bpp = crtc_state->dsc.compressed_bpp; 937 else 938 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 939 940 byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state); 941 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count); 942 vtotal = vactive + DIV_ROUND_UP(400, line_time_us); 943 } 944 vsync_start = adjusted_mode->crtc_vsync_start; 945 vsync_end = adjusted_mode->crtc_vsync_end; 946 vsync_shift = hsync_start - htotal / 2; 947 948 if (intel_dsi->dual_link) { 949 hactive /= 2; 950 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 951 hactive += intel_dsi->pixel_overlap; 952 htotal /= 2; 953 } 954 955 /* minimum hactive as per bspec: 256 pixels */ 956 if (adjusted_mode->crtc_hdisplay < 256) 957 drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n"); 958 959 /* if RGB666 format, then hactive must be multiple of 4 pixels */ 960 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) 961 drm_err(&dev_priv->drm, 962 "hactive pixels are not multiple of 4\n"); 963 964 /* program TRANS_HTOTAL register */ 965 for_each_dsi_port(port, intel_dsi->ports) { 966 dsi_trans = dsi_port_to_transcoder(port); 967 intel_de_write(dev_priv, HTOTAL(dsi_trans), 968 (hactive - 1) | ((htotal - 1) << 16)); 969 } 970 971 /* TRANS_HSYNC register to be programmed only for video mode */ 972 if (is_vid_mode(intel_dsi)) { 973 if (intel_dsi->video_mode_format == 974 VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) { 975 /* BSPEC: hsync size should be atleast 16 pixels */ 976 if (hsync_size < 16) 977 drm_err(&dev_priv->drm, 978 "hsync size < 16 pixels\n"); 979 } 980 981 if (hback_porch < 16) 982 drm_err(&dev_priv->drm, "hback porch < 16 pixels\n"); 983 984 if (intel_dsi->dual_link) { 985 hsync_start /= 2; 986 hsync_end /= 2; 987 } 988 989 for_each_dsi_port(port, intel_dsi->ports) { 990 dsi_trans = dsi_port_to_transcoder(port); 991 intel_de_write(dev_priv, HSYNC(dsi_trans), 992 (hsync_start - 1) | ((hsync_end - 1) << 16)); 993 } 994 } 995 996 /* program TRANS_VTOTAL register */ 997 for_each_dsi_port(port, intel_dsi->ports) { 998 dsi_trans = dsi_port_to_transcoder(port); 999 /* 1000 * FIXME: Programing this by assuming progressive mode, since 1001 * non-interlaced info from VBT is not saved inside 1002 * struct drm_display_mode. 1003 * For interlace mode: program required pixel minus 2 1004 */ 1005 intel_de_write(dev_priv, VTOTAL(dsi_trans), 1006 (vactive - 1) | ((vtotal - 1) << 16)); 1007 } 1008 1009 if (vsync_end < vsync_start || vsync_end > vtotal) 1010 drm_err(&dev_priv->drm, "Invalid vsync_end value\n"); 1011 1012 if (vsync_start < vactive) 1013 drm_err(&dev_priv->drm, "vsync_start less than vactive\n"); 1014 1015 /* program TRANS_VSYNC register for video mode only */ 1016 if (is_vid_mode(intel_dsi)) { 1017 for_each_dsi_port(port, intel_dsi->ports) { 1018 dsi_trans = dsi_port_to_transcoder(port); 1019 intel_de_write(dev_priv, VSYNC(dsi_trans), 1020 (vsync_start - 1) | ((vsync_end - 1) << 16)); 1021 } 1022 } 1023 1024 /* 1025 * FIXME: It has to be programmed only for video modes and interlaced 1026 * modes. Put the check condition here once interlaced 1027 * info available as described above. 1028 * program TRANS_VSYNCSHIFT register 1029 */ 1030 if (is_vid_mode(intel_dsi)) { 1031 for_each_dsi_port(port, intel_dsi->ports) { 1032 dsi_trans = dsi_port_to_transcoder(port); 1033 intel_de_write(dev_priv, VSYNCSHIFT(dsi_trans), 1034 vsync_shift); 1035 } 1036 } 1037 1038 /* program TRANS_VBLANK register, should be same as vtotal programmed */ 1039 if (DISPLAY_VER(dev_priv) >= 12) { 1040 for_each_dsi_port(port, intel_dsi->ports) { 1041 dsi_trans = dsi_port_to_transcoder(port); 1042 intel_de_write(dev_priv, VBLANK(dsi_trans), 1043 (vactive - 1) | ((vtotal - 1) << 16)); 1044 } 1045 } 1046 } 1047 1048 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) 1049 { 1050 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1051 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1052 enum port port; 1053 enum transcoder dsi_trans; 1054 u32 tmp; 1055 1056 for_each_dsi_port(port, intel_dsi->ports) { 1057 dsi_trans = dsi_port_to_transcoder(port); 1058 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1059 tmp |= PIPECONF_ENABLE; 1060 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); 1061 1062 /* wait for transcoder to be enabled */ 1063 if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans), 1064 I965_PIPECONF_ACTIVE, 10)) 1065 drm_err(&dev_priv->drm, 1066 "DSI transcoder not enabled\n"); 1067 } 1068 } 1069 1070 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder, 1071 const struct intel_crtc_state *crtc_state) 1072 { 1073 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1074 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1075 enum port port; 1076 enum transcoder dsi_trans; 1077 u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul; 1078 1079 /* 1080 * escape clock count calculation: 1081 * BYTE_CLK_COUNT = TIME_NS/(8 * UI) 1082 * UI (nsec) = (10^6)/Bitrate 1083 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate 1084 * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS 1085 */ 1086 divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000; 1087 mul = 8 * 1000000; 1088 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul, 1089 divisor); 1090 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor); 1091 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor); 1092 1093 for_each_dsi_port(port, intel_dsi->ports) { 1094 dsi_trans = dsi_port_to_transcoder(port); 1095 1096 /* program hst_tx_timeout */ 1097 tmp = intel_de_read(dev_priv, DSI_HSTX_TO(dsi_trans)); 1098 tmp &= ~HSTX_TIMEOUT_VALUE_MASK; 1099 tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout); 1100 intel_de_write(dev_priv, DSI_HSTX_TO(dsi_trans), tmp); 1101 1102 /* FIXME: DSI_CALIB_TO */ 1103 1104 /* program lp_rx_host timeout */ 1105 tmp = intel_de_read(dev_priv, DSI_LPRX_HOST_TO(dsi_trans)); 1106 tmp &= ~LPRX_TIMEOUT_VALUE_MASK; 1107 tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout); 1108 intel_de_write(dev_priv, DSI_LPRX_HOST_TO(dsi_trans), tmp); 1109 1110 /* FIXME: DSI_PWAIT_TO */ 1111 1112 /* program turn around timeout */ 1113 tmp = intel_de_read(dev_priv, DSI_TA_TO(dsi_trans)); 1114 tmp &= ~TA_TIMEOUT_VALUE_MASK; 1115 tmp |= TA_TIMEOUT_VALUE(ta_timeout); 1116 intel_de_write(dev_priv, DSI_TA_TO(dsi_trans), tmp); 1117 } 1118 } 1119 1120 static void gen11_dsi_config_util_pin(struct intel_encoder *encoder, 1121 bool enable) 1122 { 1123 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1124 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1125 u32 tmp; 1126 1127 /* 1128 * used as TE i/p for DSI0, 1129 * for dual link/DSI1 TE is from slave DSI1 1130 * through GPIO. 1131 */ 1132 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) 1133 return; 1134 1135 tmp = intel_de_read(dev_priv, UTIL_PIN_CTL); 1136 1137 if (enable) { 1138 tmp |= UTIL_PIN_DIRECTION_INPUT; 1139 tmp |= UTIL_PIN_ENABLE; 1140 } else { 1141 tmp &= ~UTIL_PIN_ENABLE; 1142 } 1143 intel_de_write(dev_priv, UTIL_PIN_CTL, tmp); 1144 } 1145 1146 static void 1147 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, 1148 const struct intel_crtc_state *crtc_state) 1149 { 1150 /* step 4a: power up all lanes of the DDI used by DSI */ 1151 gen11_dsi_power_up_lanes(encoder); 1152 1153 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */ 1154 gen11_dsi_config_phy_lanes_sequence(encoder); 1155 1156 /* step 4c: configure voltage swing and skew */ 1157 gen11_dsi_voltage_swing_program_seq(encoder); 1158 1159 /* enable DDI buffer */ 1160 gen11_dsi_enable_ddi_buffer(encoder); 1161 1162 /* setup D-PHY timings */ 1163 gen11_dsi_setup_dphy_timings(encoder, crtc_state); 1164 1165 /* Since transcoder is configured to take events from GPIO */ 1166 gen11_dsi_config_util_pin(encoder, true); 1167 1168 /* step 4h: setup DSI protocol timeouts */ 1169 gen11_dsi_setup_timeouts(encoder, crtc_state); 1170 1171 /* Step (4h, 4i, 4j, 4k): Configure transcoder */ 1172 gen11_dsi_configure_transcoder(encoder, crtc_state); 1173 1174 /* Step 4l: Gate DDI clocks */ 1175 gen11_dsi_gate_clocks(encoder); 1176 } 1177 1178 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) 1179 { 1180 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1181 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1182 struct mipi_dsi_device *dsi; 1183 enum port port; 1184 enum transcoder dsi_trans; 1185 u32 tmp; 1186 int ret; 1187 1188 /* set maximum return packet size */ 1189 for_each_dsi_port(port, intel_dsi->ports) { 1190 dsi_trans = dsi_port_to_transcoder(port); 1191 1192 /* 1193 * FIXME: This uses the number of DW's currently in the payload 1194 * receive queue. This is probably not what we want here. 1195 */ 1196 tmp = intel_de_read(dev_priv, DSI_CMD_RXCTL(dsi_trans)); 1197 tmp &= NUMBER_RX_PLOAD_DW_MASK; 1198 /* multiply "Number Rx Payload DW" by 4 to get max value */ 1199 tmp = tmp * 4; 1200 dsi = intel_dsi->dsi_hosts[port]->device; 1201 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp); 1202 if (ret < 0) 1203 drm_err(&dev_priv->drm, 1204 "error setting max return pkt size%d\n", tmp); 1205 } 1206 1207 /* panel power on related mipi dsi vbt sequences */ 1208 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 1209 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); 1210 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 1211 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 1212 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 1213 1214 /* ensure all panel commands dispatched before enabling transcoder */ 1215 wait_for_cmds_dispatched_to_panel(encoder); 1216 } 1217 1218 static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state, 1219 struct intel_encoder *encoder, 1220 const struct intel_crtc_state *crtc_state, 1221 const struct drm_connector_state *conn_state) 1222 { 1223 /* step2: enable IO power */ 1224 gen11_dsi_enable_io_power(encoder); 1225 1226 /* step3: enable DSI PLL */ 1227 gen11_dsi_program_esc_clk_div(encoder, crtc_state); 1228 } 1229 1230 static void gen11_dsi_pre_enable(struct intel_atomic_state *state, 1231 struct intel_encoder *encoder, 1232 const struct intel_crtc_state *pipe_config, 1233 const struct drm_connector_state *conn_state) 1234 { 1235 /* step3b */ 1236 gen11_dsi_map_pll(encoder, pipe_config); 1237 1238 /* step4: enable DSI port and DPHY */ 1239 gen11_dsi_enable_port_and_phy(encoder, pipe_config); 1240 1241 /* step5: program and powerup panel */ 1242 gen11_dsi_powerup_panel(encoder); 1243 1244 intel_dsc_enable(encoder, pipe_config); 1245 1246 /* step6c: configure transcoder timings */ 1247 gen11_dsi_set_transcoder_timings(encoder, pipe_config); 1248 } 1249 1250 /* 1251 * Wa_1409054076:icl,jsl,ehl 1252 * When pipe A is disabled and MIPI DSI is enabled on pipe B, 1253 * the AMT KVMR feature will incorrectly see pipe A as enabled. 1254 * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave 1255 * it set while DSI is enabled on pipe B 1256 */ 1257 static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder, 1258 enum pipe pipe, bool enable) 1259 { 1260 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1261 1262 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B) 1263 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 1264 IGNORE_KVMR_PIPE_A, 1265 enable ? IGNORE_KVMR_PIPE_A : 0); 1266 } 1267 static void gen11_dsi_enable(struct intel_atomic_state *state, 1268 struct intel_encoder *encoder, 1269 const struct intel_crtc_state *crtc_state, 1270 const struct drm_connector_state *conn_state) 1271 { 1272 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1273 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 1274 1275 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 1276 1277 /* Wa_1409054076:icl,jsl,ehl */ 1278 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true); 1279 1280 /* step6d: enable dsi transcoder */ 1281 gen11_dsi_enable_transcoder(encoder); 1282 1283 /* step7: enable backlight */ 1284 intel_panel_enable_backlight(crtc_state, conn_state); 1285 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 1286 1287 intel_crtc_vblank_on(crtc_state); 1288 } 1289 1290 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) 1291 { 1292 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1293 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1294 enum port port; 1295 enum transcoder dsi_trans; 1296 u32 tmp; 1297 1298 for_each_dsi_port(port, intel_dsi->ports) { 1299 dsi_trans = dsi_port_to_transcoder(port); 1300 1301 /* disable transcoder */ 1302 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1303 tmp &= ~PIPECONF_ENABLE; 1304 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); 1305 1306 /* wait for transcoder to be disabled */ 1307 if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans), 1308 I965_PIPECONF_ACTIVE, 50)) 1309 drm_err(&dev_priv->drm, 1310 "DSI trancoder not disabled\n"); 1311 } 1312 } 1313 1314 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder) 1315 { 1316 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1317 1318 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 1319 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 1320 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 1321 1322 /* ensure cmds dispatched to panel */ 1323 wait_for_cmds_dispatched_to_panel(encoder); 1324 } 1325 1326 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) 1327 { 1328 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1329 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1330 enum port port; 1331 enum transcoder dsi_trans; 1332 u32 tmp; 1333 1334 /* disable periodic update mode */ 1335 if (is_cmd_mode(intel_dsi)) { 1336 for_each_dsi_port(port, intel_dsi->ports) { 1337 tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port)); 1338 tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE; 1339 intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp); 1340 } 1341 } 1342 1343 /* put dsi link in ULPS */ 1344 for_each_dsi_port(port, intel_dsi->ports) { 1345 dsi_trans = dsi_port_to_transcoder(port); 1346 tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)); 1347 tmp |= LINK_ENTER_ULPS; 1348 tmp &= ~LINK_ULPS_TYPE_LP11; 1349 intel_de_write(dev_priv, DSI_LP_MSG(dsi_trans), tmp); 1350 1351 if (wait_for_us((intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & 1352 LINK_IN_ULPS), 1353 10)) 1354 drm_err(&dev_priv->drm, "DSI link not in ULPS\n"); 1355 } 1356 1357 /* disable ddi function */ 1358 for_each_dsi_port(port, intel_dsi->ports) { 1359 dsi_trans = dsi_port_to_transcoder(port); 1360 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 1361 tmp &= ~TRANS_DDI_FUNC_ENABLE; 1362 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp); 1363 } 1364 1365 /* disable port sync mode if dual link */ 1366 if (intel_dsi->dual_link) { 1367 for_each_dsi_port(port, intel_dsi->ports) { 1368 dsi_trans = dsi_port_to_transcoder(port); 1369 tmp = intel_de_read(dev_priv, 1370 TRANS_DDI_FUNC_CTL2(dsi_trans)); 1371 tmp &= ~PORT_SYNC_MODE_ENABLE; 1372 intel_de_write(dev_priv, 1373 TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); 1374 } 1375 } 1376 } 1377 1378 static void gen11_dsi_disable_port(struct intel_encoder *encoder) 1379 { 1380 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1381 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1382 u32 tmp; 1383 enum port port; 1384 1385 gen11_dsi_ungate_clocks(encoder); 1386 for_each_dsi_port(port, intel_dsi->ports) { 1387 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 1388 tmp &= ~DDI_BUF_CTL_ENABLE; 1389 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp); 1390 1391 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 1392 DDI_BUF_IS_IDLE), 1393 8)) 1394 drm_err(&dev_priv->drm, 1395 "DDI port:%c buffer not idle\n", 1396 port_name(port)); 1397 } 1398 gen11_dsi_gate_clocks(encoder); 1399 } 1400 1401 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) 1402 { 1403 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1404 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1405 enum port port; 1406 u32 tmp; 1407 1408 for_each_dsi_port(port, intel_dsi->ports) { 1409 intel_wakeref_t wakeref; 1410 1411 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); 1412 intel_display_power_put(dev_priv, 1413 port == PORT_A ? 1414 POWER_DOMAIN_PORT_DDI_A_IO : 1415 POWER_DOMAIN_PORT_DDI_B_IO, 1416 wakeref); 1417 } 1418 1419 /* set mode to DDI */ 1420 for_each_dsi_port(port, intel_dsi->ports) { 1421 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port)); 1422 tmp &= ~COMBO_PHY_MODE_DSI; 1423 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp); 1424 } 1425 } 1426 1427 static void gen11_dsi_disable(struct intel_atomic_state *state, 1428 struct intel_encoder *encoder, 1429 const struct intel_crtc_state *old_crtc_state, 1430 const struct drm_connector_state *old_conn_state) 1431 { 1432 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1433 struct intel_crtc *crtc = to_intel_crtc(old_conn_state->crtc); 1434 1435 /* step1: turn off backlight */ 1436 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 1437 intel_panel_disable_backlight(old_conn_state); 1438 1439 /* step2d,e: disable transcoder and wait */ 1440 gen11_dsi_disable_transcoder(encoder); 1441 1442 /* Wa_1409054076:icl,jsl,ehl */ 1443 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false); 1444 1445 /* step2f,g: powerdown panel */ 1446 gen11_dsi_powerdown_panel(encoder); 1447 1448 /* step2h,i,j: deconfig trancoder */ 1449 gen11_dsi_deconfigure_trancoder(encoder); 1450 1451 /* step3: disable port */ 1452 gen11_dsi_disable_port(encoder); 1453 1454 gen11_dsi_config_util_pin(encoder, false); 1455 1456 /* step4: disable IO power */ 1457 gen11_dsi_disable_io_power(encoder); 1458 } 1459 1460 static void gen11_dsi_post_disable(struct intel_atomic_state *state, 1461 struct intel_encoder *encoder, 1462 const struct intel_crtc_state *old_crtc_state, 1463 const struct drm_connector_state *old_conn_state) 1464 { 1465 intel_crtc_vblank_off(old_crtc_state); 1466 1467 intel_dsc_disable(old_crtc_state); 1468 1469 skl_scaler_disable(old_crtc_state); 1470 } 1471 1472 static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector, 1473 struct drm_display_mode *mode) 1474 { 1475 /* FIXME: DSC? */ 1476 return intel_dsi_mode_valid(connector, mode); 1477 } 1478 1479 static void gen11_dsi_get_timings(struct intel_encoder *encoder, 1480 struct intel_crtc_state *pipe_config) 1481 { 1482 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1483 struct drm_display_mode *adjusted_mode = 1484 &pipe_config->hw.adjusted_mode; 1485 1486 if (pipe_config->dsc.compressed_bpp) { 1487 int div = pipe_config->dsc.compressed_bpp; 1488 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1489 1490 adjusted_mode->crtc_htotal = 1491 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 1492 adjusted_mode->crtc_hsync_start = 1493 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 1494 adjusted_mode->crtc_hsync_end = 1495 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 1496 } 1497 1498 if (intel_dsi->dual_link) { 1499 adjusted_mode->crtc_hdisplay *= 2; 1500 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1501 adjusted_mode->crtc_hdisplay -= 1502 intel_dsi->pixel_overlap; 1503 adjusted_mode->crtc_htotal *= 2; 1504 } 1505 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1506 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1507 1508 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { 1509 if (intel_dsi->dual_link) { 1510 adjusted_mode->crtc_hsync_start *= 2; 1511 adjusted_mode->crtc_hsync_end *= 2; 1512 } 1513 } 1514 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1515 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1516 } 1517 1518 static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi) 1519 { 1520 struct drm_device *dev = intel_dsi->base.base.dev; 1521 struct drm_i915_private *dev_priv = to_i915(dev); 1522 enum transcoder dsi_trans; 1523 u32 val; 1524 1525 if (intel_dsi->ports == BIT(PORT_B)) 1526 dsi_trans = TRANSCODER_DSI_1; 1527 else 1528 dsi_trans = TRANSCODER_DSI_0; 1529 1530 val = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)); 1531 return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE); 1532 } 1533 1534 static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi, 1535 struct intel_crtc_state *pipe_config) 1536 { 1537 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) 1538 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 | 1539 I915_MODE_FLAG_DSI_USE_TE0; 1540 else if (intel_dsi->ports == BIT(PORT_B)) 1541 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1; 1542 else 1543 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0; 1544 } 1545 1546 static void gen11_dsi_get_config(struct intel_encoder *encoder, 1547 struct intel_crtc_state *pipe_config) 1548 { 1549 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1550 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1551 1552 intel_ddi_get_clock(encoder, pipe_config, icl_ddi_combo_get_pll(encoder)); 1553 1554 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; 1555 if (intel_dsi->dual_link) 1556 pipe_config->hw.adjusted_mode.crtc_clock *= 2; 1557 1558 gen11_dsi_get_timings(encoder, pipe_config); 1559 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1560 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); 1561 1562 /* Get the details on which TE should be enabled */ 1563 if (is_cmd_mode(intel_dsi)) 1564 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1565 1566 if (gen11_dsi_is_periodic_cmd_mode(intel_dsi)) 1567 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE; 1568 } 1569 1570 static void gen11_dsi_sync_state(struct intel_encoder *encoder, 1571 const struct intel_crtc_state *crtc_state) 1572 { 1573 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1574 struct intel_crtc *intel_crtc; 1575 enum pipe pipe; 1576 1577 if (!crtc_state) 1578 return; 1579 1580 intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1581 pipe = intel_crtc->pipe; 1582 1583 /* wa verify 1409054076:icl,jsl,ehl */ 1584 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B && 1585 !(intel_de_read(dev_priv, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A)) 1586 drm_dbg_kms(&dev_priv->drm, 1587 "[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n", 1588 encoder->base.base.id, 1589 encoder->base.name); 1590 } 1591 1592 static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, 1593 struct intel_crtc_state *crtc_state) 1594 { 1595 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1596 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1597 int dsc_max_bpc = DISPLAY_VER(dev_priv) >= 12 ? 12 : 10; 1598 bool use_dsc; 1599 int ret; 1600 1601 use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc); 1602 if (!use_dsc) 1603 return 0; 1604 1605 if (crtc_state->pipe_bpp < 8 * 3) 1606 return -EINVAL; 1607 1608 /* FIXME: split only when necessary */ 1609 if (crtc_state->dsc.slice_count > 1) 1610 crtc_state->dsc.dsc_split = true; 1611 1612 vdsc_cfg->convert_rgb = true; 1613 1614 /* FIXME: initialize from VBT */ 1615 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 1616 1617 ret = intel_dsc_compute_params(encoder, crtc_state); 1618 if (ret) 1619 return ret; 1620 1621 /* DSI specific sanity checks on the common code */ 1622 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable); 1623 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422); 1624 drm_WARN_ON(&dev_priv->drm, 1625 vdsc_cfg->pic_width % vdsc_cfg->slice_width); 1626 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8); 1627 drm_WARN_ON(&dev_priv->drm, 1628 vdsc_cfg->pic_height % vdsc_cfg->slice_height); 1629 1630 ret = drm_dsc_compute_rc_parameters(vdsc_cfg); 1631 if (ret) 1632 return ret; 1633 1634 crtc_state->dsc.compression_enable = true; 1635 1636 return 0; 1637 } 1638 1639 static int gen11_dsi_compute_config(struct intel_encoder *encoder, 1640 struct intel_crtc_state *pipe_config, 1641 struct drm_connector_state *conn_state) 1642 { 1643 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1644 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, 1645 base); 1646 struct intel_connector *intel_connector = intel_dsi->attached_connector; 1647 const struct drm_display_mode *fixed_mode = 1648 intel_connector->panel.fixed_mode; 1649 struct drm_display_mode *adjusted_mode = 1650 &pipe_config->hw.adjusted_mode; 1651 int ret; 1652 1653 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1654 intel_fixed_panel_mode(fixed_mode, adjusted_mode); 1655 1656 ret = intel_pch_panel_fitting(pipe_config, conn_state); 1657 if (ret) 1658 return ret; 1659 1660 adjusted_mode->flags = 0; 1661 1662 /* Dual link goes to trancoder DSI'0' */ 1663 if (intel_dsi->ports == BIT(PORT_B)) 1664 pipe_config->cpu_transcoder = TRANSCODER_DSI_1; 1665 else 1666 pipe_config->cpu_transcoder = TRANSCODER_DSI_0; 1667 1668 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 1669 pipe_config->pipe_bpp = 24; 1670 else 1671 pipe_config->pipe_bpp = 18; 1672 1673 pipe_config->clock_set = true; 1674 1675 if (gen11_dsi_dsc_compute_config(encoder, pipe_config)) 1676 drm_dbg_kms(&i915->drm, "Attempting to use DSC failed\n"); 1677 1678 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5; 1679 1680 /* 1681 * In case of TE GATE cmd mode, we 1682 * receive TE from the slave if 1683 * dual link is enabled 1684 */ 1685 if (is_cmd_mode(intel_dsi)) 1686 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1687 1688 return 0; 1689 } 1690 1691 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder, 1692 struct intel_crtc_state *crtc_state) 1693 { 1694 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1695 1696 get_dsi_io_power_domains(i915, 1697 enc_to_intel_dsi(encoder)); 1698 } 1699 1700 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, 1701 enum pipe *pipe) 1702 { 1703 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1704 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1705 enum transcoder dsi_trans; 1706 intel_wakeref_t wakeref; 1707 enum port port; 1708 bool ret = false; 1709 u32 tmp; 1710 1711 wakeref = intel_display_power_get_if_enabled(dev_priv, 1712 encoder->power_domain); 1713 if (!wakeref) 1714 return false; 1715 1716 for_each_dsi_port(port, intel_dsi->ports) { 1717 dsi_trans = dsi_port_to_transcoder(port); 1718 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 1719 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1720 case TRANS_DDI_EDP_INPUT_A_ON: 1721 *pipe = PIPE_A; 1722 break; 1723 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1724 *pipe = PIPE_B; 1725 break; 1726 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1727 *pipe = PIPE_C; 1728 break; 1729 case TRANS_DDI_EDP_INPUT_D_ONOFF: 1730 *pipe = PIPE_D; 1731 break; 1732 default: 1733 drm_err(&dev_priv->drm, "Invalid PIPE input\n"); 1734 goto out; 1735 } 1736 1737 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1738 ret = tmp & PIPECONF_ENABLE; 1739 } 1740 out: 1741 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1742 return ret; 1743 } 1744 1745 static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder, 1746 struct intel_crtc_state *crtc_state) 1747 { 1748 if (crtc_state->dsc.compression_enable) { 1749 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n"); 1750 crtc_state->uapi.mode_changed = true; 1751 1752 return false; 1753 } 1754 1755 return true; 1756 } 1757 1758 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder) 1759 { 1760 intel_encoder_destroy(encoder); 1761 } 1762 1763 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = { 1764 .destroy = gen11_dsi_encoder_destroy, 1765 }; 1766 1767 static const struct drm_connector_funcs gen11_dsi_connector_funcs = { 1768 .detect = intel_panel_detect, 1769 .late_register = intel_connector_register, 1770 .early_unregister = intel_connector_unregister, 1771 .destroy = intel_connector_destroy, 1772 .fill_modes = drm_helper_probe_single_connector_modes, 1773 .atomic_get_property = intel_digital_connector_atomic_get_property, 1774 .atomic_set_property = intel_digital_connector_atomic_set_property, 1775 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1776 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1777 }; 1778 1779 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = { 1780 .get_modes = intel_dsi_get_modes, 1781 .mode_valid = gen11_dsi_mode_valid, 1782 .atomic_check = intel_digital_connector_atomic_check, 1783 }; 1784 1785 static int gen11_dsi_host_attach(struct mipi_dsi_host *host, 1786 struct mipi_dsi_device *dsi) 1787 { 1788 return 0; 1789 } 1790 1791 static int gen11_dsi_host_detach(struct mipi_dsi_host *host, 1792 struct mipi_dsi_device *dsi) 1793 { 1794 return 0; 1795 } 1796 1797 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host, 1798 const struct mipi_dsi_msg *msg) 1799 { 1800 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 1801 struct mipi_dsi_packet dsi_pkt; 1802 ssize_t ret; 1803 bool enable_lpdt = false; 1804 1805 ret = mipi_dsi_create_packet(&dsi_pkt, msg); 1806 if (ret < 0) 1807 return ret; 1808 1809 if (msg->flags & MIPI_DSI_MSG_USE_LPM) 1810 enable_lpdt = true; 1811 1812 /* send packet header */ 1813 ret = dsi_send_pkt_hdr(intel_dsi_host, dsi_pkt, enable_lpdt); 1814 if (ret < 0) 1815 return ret; 1816 1817 /* only long packet contains payload */ 1818 if (mipi_dsi_packet_format_is_long(msg->type)) { 1819 ret = dsi_send_pkt_payld(intel_dsi_host, dsi_pkt); 1820 if (ret < 0) 1821 return ret; 1822 } 1823 1824 //TODO: add payload receive code if needed 1825 1826 ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length; 1827 1828 return ret; 1829 } 1830 1831 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = { 1832 .attach = gen11_dsi_host_attach, 1833 .detach = gen11_dsi_host_detach, 1834 .transfer = gen11_dsi_host_transfer, 1835 }; 1836 1837 #define ICL_PREPARE_CNT_MAX 0x7 1838 #define ICL_CLK_ZERO_CNT_MAX 0xf 1839 #define ICL_TRAIL_CNT_MAX 0x7 1840 #define ICL_TCLK_PRE_CNT_MAX 0x3 1841 #define ICL_TCLK_POST_CNT_MAX 0x7 1842 #define ICL_HS_ZERO_CNT_MAX 0xf 1843 #define ICL_EXIT_ZERO_CNT_MAX 0x7 1844 1845 static void icl_dphy_param_init(struct intel_dsi *intel_dsi) 1846 { 1847 struct drm_device *dev = intel_dsi->base.base.dev; 1848 struct drm_i915_private *dev_priv = to_i915(dev); 1849 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 1850 u32 tlpx_ns; 1851 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1852 u32 ths_prepare_ns, tclk_trail_ns; 1853 u32 hs_zero_cnt; 1854 u32 tclk_pre_cnt, tclk_post_cnt; 1855 1856 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1857 1858 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1859 ths_prepare_ns = max(mipi_config->ths_prepare, 1860 mipi_config->tclk_prepare); 1861 1862 /* 1863 * prepare cnt in escape clocks 1864 * this field represents a hexadecimal value with a precision 1865 * of 1.2 – i.e. the most significant bit is the integer 1866 * and the least significant 2 bits are fraction bits. 1867 * so, the field can represent a range of 0.25 to 1.75 1868 */ 1869 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns); 1870 if (prepare_cnt > ICL_PREPARE_CNT_MAX) { 1871 drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n", 1872 prepare_cnt); 1873 prepare_cnt = ICL_PREPARE_CNT_MAX; 1874 } 1875 1876 /* clk zero count in escape clocks */ 1877 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero - 1878 ths_prepare_ns, tlpx_ns); 1879 if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) { 1880 drm_dbg_kms(&dev_priv->drm, 1881 "clk_zero_cnt out of range (%d)\n", clk_zero_cnt); 1882 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX; 1883 } 1884 1885 /* trail cnt in escape clocks*/ 1886 trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns); 1887 if (trail_cnt > ICL_TRAIL_CNT_MAX) { 1888 drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n", 1889 trail_cnt); 1890 trail_cnt = ICL_TRAIL_CNT_MAX; 1891 } 1892 1893 /* tclk pre count in escape clocks */ 1894 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); 1895 if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) { 1896 drm_dbg_kms(&dev_priv->drm, 1897 "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt); 1898 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX; 1899 } 1900 1901 /* tclk post count in escape clocks */ 1902 tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns); 1903 if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) { 1904 drm_dbg_kms(&dev_priv->drm, 1905 "tclk_post_cnt out of range (%d)\n", 1906 tclk_post_cnt); 1907 tclk_post_cnt = ICL_TCLK_POST_CNT_MAX; 1908 } 1909 1910 /* hs zero cnt in escape clocks */ 1911 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - 1912 ths_prepare_ns, tlpx_ns); 1913 if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) { 1914 drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n", 1915 hs_zero_cnt); 1916 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX; 1917 } 1918 1919 /* hs exit zero cnt in escape clocks */ 1920 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns); 1921 if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) { 1922 drm_dbg_kms(&dev_priv->drm, 1923 "exit_zero_cnt out of range (%d)\n", 1924 exit_zero_cnt); 1925 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX; 1926 } 1927 1928 /* clock lane dphy timings */ 1929 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE | 1930 CLK_PREPARE(prepare_cnt) | 1931 CLK_ZERO_OVERRIDE | 1932 CLK_ZERO(clk_zero_cnt) | 1933 CLK_PRE_OVERRIDE | 1934 CLK_PRE(tclk_pre_cnt) | 1935 CLK_POST_OVERRIDE | 1936 CLK_POST(tclk_post_cnt) | 1937 CLK_TRAIL_OVERRIDE | 1938 CLK_TRAIL(trail_cnt)); 1939 1940 /* data lanes dphy timings */ 1941 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | 1942 HS_PREPARE(prepare_cnt) | 1943 HS_ZERO_OVERRIDE | 1944 HS_ZERO(hs_zero_cnt) | 1945 HS_TRAIL_OVERRIDE | 1946 HS_TRAIL(trail_cnt) | 1947 HS_EXIT_OVERRIDE | 1948 HS_EXIT(exit_zero_cnt)); 1949 1950 intel_dsi_log_params(intel_dsi); 1951 } 1952 1953 static void icl_dsi_add_properties(struct intel_connector *connector) 1954 { 1955 u32 allowed_scalers; 1956 1957 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | 1958 BIT(DRM_MODE_SCALE_FULLSCREEN) | 1959 BIT(DRM_MODE_SCALE_CENTER); 1960 1961 drm_connector_attach_scaling_mode_property(&connector->base, 1962 allowed_scalers); 1963 1964 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; 1965 1966 drm_connector_set_panel_orientation_with_quirk(&connector->base, 1967 intel_dsi_get_panel_orientation(connector), 1968 connector->panel.fixed_mode->hdisplay, 1969 connector->panel.fixed_mode->vdisplay); 1970 } 1971 1972 void icl_dsi_init(struct drm_i915_private *dev_priv) 1973 { 1974 struct drm_device *dev = &dev_priv->drm; 1975 struct intel_dsi *intel_dsi; 1976 struct intel_encoder *encoder; 1977 struct intel_connector *intel_connector; 1978 struct drm_connector *connector; 1979 struct drm_display_mode *fixed_mode; 1980 enum port port; 1981 1982 if (!intel_bios_is_dsi_present(dev_priv, &port)) 1983 return; 1984 1985 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 1986 if (!intel_dsi) 1987 return; 1988 1989 intel_connector = intel_connector_alloc(); 1990 if (!intel_connector) { 1991 kfree(intel_dsi); 1992 return; 1993 } 1994 1995 encoder = &intel_dsi->base; 1996 intel_dsi->attached_connector = intel_connector; 1997 connector = &intel_connector->base; 1998 1999 /* register DSI encoder with DRM subsystem */ 2000 drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs, 2001 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port)); 2002 2003 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable; 2004 encoder->pre_enable = gen11_dsi_pre_enable; 2005 encoder->enable = gen11_dsi_enable; 2006 encoder->disable = gen11_dsi_disable; 2007 encoder->post_disable = gen11_dsi_post_disable; 2008 encoder->port = port; 2009 encoder->get_config = gen11_dsi_get_config; 2010 encoder->sync_state = gen11_dsi_sync_state; 2011 encoder->update_pipe = intel_panel_update_backlight; 2012 encoder->compute_config = gen11_dsi_compute_config; 2013 encoder->get_hw_state = gen11_dsi_get_hw_state; 2014 encoder->initial_fastset_check = gen11_dsi_initial_fastset_check; 2015 encoder->type = INTEL_OUTPUT_DSI; 2016 encoder->cloneable = 0; 2017 encoder->pipe_mask = ~0; 2018 encoder->power_domain = POWER_DOMAIN_PORT_DSI; 2019 encoder->get_power_domains = gen11_dsi_get_power_domains; 2020 encoder->disable_clock = gen11_dsi_gate_clocks; 2021 encoder->is_clock_enabled = gen11_dsi_is_clock_enabled; 2022 2023 /* register DSI connector with DRM subsystem */ 2024 drm_connector_init(dev, connector, &gen11_dsi_connector_funcs, 2025 DRM_MODE_CONNECTOR_DSI); 2026 drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs); 2027 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 2028 connector->interlace_allowed = false; 2029 connector->doublescan_allowed = false; 2030 intel_connector->get_hw_state = intel_connector_get_hw_state; 2031 2032 /* attach connector to encoder */ 2033 intel_connector_attach_encoder(intel_connector, encoder); 2034 2035 mutex_lock(&dev->mode_config.mutex); 2036 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector); 2037 mutex_unlock(&dev->mode_config.mutex); 2038 2039 if (!fixed_mode) { 2040 drm_err(&dev_priv->drm, "DSI fixed mode info missing\n"); 2041 goto err; 2042 } 2043 2044 intel_panel_init(&intel_connector->panel, fixed_mode, NULL); 2045 intel_panel_setup_backlight(connector, INVALID_PIPE); 2046 2047 if (dev_priv->vbt.dsi.config->dual_link) 2048 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); 2049 else 2050 intel_dsi->ports = BIT(port); 2051 2052 intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports; 2053 intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports; 2054 2055 for_each_dsi_port(port, intel_dsi->ports) { 2056 struct intel_dsi_host *host; 2057 2058 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port); 2059 if (!host) 2060 goto err; 2061 2062 intel_dsi->dsi_hosts[port] = host; 2063 } 2064 2065 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 2066 drm_dbg_kms(&dev_priv->drm, "no device found\n"); 2067 goto err; 2068 } 2069 2070 icl_dphy_param_init(intel_dsi); 2071 2072 icl_dsi_add_properties(intel_connector); 2073 return; 2074 2075 err: 2076 drm_connector_cleanup(connector); 2077 drm_encoder_cleanup(&encoder->base); 2078 kfree(intel_dsi); 2079 kfree(intel_connector); 2080 } 2081