1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/bitfield.h> 32 #include <linux/hdmi.h> 33 #include <linux/i2c.h> 34 #include <linux/kernel.h> 35 #include <linux/module.h> 36 #include <linux/pci.h> 37 #include <linux/slab.h> 38 #include <linux/vga_switcheroo.h> 39 40 #include <drm/drm_displayid.h> 41 #include <drm/drm_drv.h> 42 #include <drm/drm_edid.h> 43 #include <drm/drm_encoder.h> 44 #include <drm/drm_print.h> 45 46 #include "drm_crtc_internal.h" 47 48 static int oui(u8 first, u8 second, u8 third) 49 { 50 return (first << 16) | (second << 8) | third; 51 } 52 53 #define EDID_EST_TIMINGS 16 54 #define EDID_STD_TIMINGS 8 55 #define EDID_DETAILED_TIMINGS 4 56 57 /* 58 * EDID blocks out in the wild have a variety of bugs, try to collect 59 * them here (note that userspace may work around broken monitors first, 60 * but fixes should make their way here so that the kernel "just works" 61 * on as many displays as possible). 62 */ 63 64 /* First detailed mode wrong, use largest 60Hz mode */ 65 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 66 /* Reported 135MHz pixel clock is too high, needs adjustment */ 67 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 68 /* Prefer the largest mode at 75 Hz */ 69 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 70 /* Detail timing is in cm not mm */ 71 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 72 /* Detailed timing descriptors have bogus size values, so just take the 73 * maximum size and use that. 74 */ 75 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 76 /* use +hsync +vsync for detailed mode */ 77 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 78 /* Force reduced-blanking timings for detailed modes */ 79 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 80 /* Force 8bpc */ 81 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 82 /* Force 12bpc */ 83 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 84 /* Force 6bpc */ 85 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 86 /* Force 10bpc */ 87 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 88 /* Non desktop display (i.e. HMD) */ 89 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 90 /* Cap the DSC target bitrate to 15bpp */ 91 #define EDID_QUIRK_CAP_DSC_15BPP (1 << 13) 92 93 #define MICROSOFT_IEEE_OUI 0xca125c 94 95 struct detailed_mode_closure { 96 struct drm_connector *connector; 97 const struct drm_edid *drm_edid; 98 bool preferred; 99 u32 quirks; 100 int modes; 101 }; 102 103 #define LEVEL_DMT 0 104 #define LEVEL_GTF 1 105 #define LEVEL_GTF2 2 106 #define LEVEL_CVT 3 107 108 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \ 109 { \ 110 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \ 111 product_id), \ 112 .quirks = _quirks \ 113 } 114 115 static const struct edid_quirk { 116 u32 panel_id; 117 u32 quirks; 118 } edid_quirk_list[] = { 119 /* Acer AL1706 */ 120 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60), 121 /* Acer F51 */ 122 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60), 123 124 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 125 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC), 126 127 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 128 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC), 129 130 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 131 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC), 132 133 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 134 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC), 135 136 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 137 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC), 138 139 /* Belinea 10 15 55 */ 140 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60), 141 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60), 142 143 /* Envision Peripherals, Inc. EN-7100e */ 144 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH), 145 /* Envision EN2028 */ 146 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60), 147 148 /* Funai Electronics PM36B */ 149 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 | 150 EDID_QUIRK_DETAILED_IN_CM), 151 152 /* LG 27GP950 */ 153 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP), 154 155 /* LG 27GN950 */ 156 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP), 157 158 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 159 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC), 160 161 /* LG Philips LCD LP154W01-A5 */ 162 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 163 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 164 165 /* Samsung SyncMaster 205BW. Note: irony */ 166 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP), 167 /* Samsung SyncMaster 22[5-6]BW */ 168 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60), 169 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60), 170 171 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 172 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC), 173 174 /* ViewSonic VA2026w */ 175 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING), 176 177 /* Medion MD 30217 PG */ 178 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75), 179 180 /* Lenovo G50 */ 181 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC), 182 183 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 184 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC), 185 186 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 187 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC), 188 189 /* Valve Index Headset */ 190 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP), 191 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP), 192 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP), 193 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP), 194 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP), 195 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP), 196 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP), 197 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP), 198 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP), 199 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP), 200 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP), 201 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP), 202 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP), 203 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP), 204 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP), 205 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP), 206 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP), 207 208 /* HTC Vive and Vive Pro VR Headsets */ 209 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP), 210 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP), 211 212 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 213 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP), 214 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP), 215 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP), 216 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP), 217 218 /* Windows Mixed Reality Headsets */ 219 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP), 220 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP), 221 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP), 222 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP), 223 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP), 224 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP), 225 226 /* Sony PlayStation VR Headset */ 227 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP), 228 229 /* Sensics VR Headsets */ 230 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP), 231 232 /* OSVR HDK and HDK2 VR Headsets */ 233 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP), 234 }; 235 236 /* 237 * Autogenerated from the DMT spec. 238 * This table is copied from xfree86/modes/xf86EdidModes.c. 239 */ 240 static const struct drm_display_mode drm_dmt_modes[] = { 241 /* 0x01 - 640x350@85Hz */ 242 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 243 736, 832, 0, 350, 382, 385, 445, 0, 244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 245 /* 0x02 - 640x400@85Hz */ 246 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 247 736, 832, 0, 400, 401, 404, 445, 0, 248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 249 /* 0x03 - 720x400@85Hz */ 250 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 251 828, 936, 0, 400, 401, 404, 446, 0, 252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 253 /* 0x04 - 640x480@60Hz */ 254 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 255 752, 800, 0, 480, 490, 492, 525, 0, 256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 257 /* 0x05 - 640x480@72Hz */ 258 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 259 704, 832, 0, 480, 489, 492, 520, 0, 260 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 261 /* 0x06 - 640x480@75Hz */ 262 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 263 720, 840, 0, 480, 481, 484, 500, 0, 264 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 265 /* 0x07 - 640x480@85Hz */ 266 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 267 752, 832, 0, 480, 481, 484, 509, 0, 268 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 269 /* 0x08 - 800x600@56Hz */ 270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 271 896, 1024, 0, 600, 601, 603, 625, 0, 272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 273 /* 0x09 - 800x600@60Hz */ 274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 275 968, 1056, 0, 600, 601, 605, 628, 0, 276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 277 /* 0x0a - 800x600@72Hz */ 278 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 279 976, 1040, 0, 600, 637, 643, 666, 0, 280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 281 /* 0x0b - 800x600@75Hz */ 282 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 283 896, 1056, 0, 600, 601, 604, 625, 0, 284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 285 /* 0x0c - 800x600@85Hz */ 286 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 287 896, 1048, 0, 600, 601, 604, 631, 0, 288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 289 /* 0x0d - 800x600@120Hz RB */ 290 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 291 880, 960, 0, 600, 603, 607, 636, 0, 292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 293 /* 0x0e - 848x480@60Hz */ 294 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 295 976, 1088, 0, 480, 486, 494, 517, 0, 296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 297 /* 0x0f - 1024x768@43Hz, interlace */ 298 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 299 1208, 1264, 0, 768, 768, 776, 817, 0, 300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 301 DRM_MODE_FLAG_INTERLACE) }, 302 /* 0x10 - 1024x768@60Hz */ 303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 304 1184, 1344, 0, 768, 771, 777, 806, 0, 305 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 306 /* 0x11 - 1024x768@70Hz */ 307 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 308 1184, 1328, 0, 768, 771, 777, 806, 0, 309 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 310 /* 0x12 - 1024x768@75Hz */ 311 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 312 1136, 1312, 0, 768, 769, 772, 800, 0, 313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 314 /* 0x13 - 1024x768@85Hz */ 315 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 316 1168, 1376, 0, 768, 769, 772, 808, 0, 317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 318 /* 0x14 - 1024x768@120Hz RB */ 319 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 320 1104, 1184, 0, 768, 771, 775, 813, 0, 321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 322 /* 0x15 - 1152x864@75Hz */ 323 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 324 1344, 1600, 0, 864, 865, 868, 900, 0, 325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 326 /* 0x55 - 1280x720@60Hz */ 327 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 328 1430, 1650, 0, 720, 725, 730, 750, 0, 329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 330 /* 0x16 - 1280x768@60Hz RB */ 331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 332 1360, 1440, 0, 768, 771, 778, 790, 0, 333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 334 /* 0x17 - 1280x768@60Hz */ 335 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 336 1472, 1664, 0, 768, 771, 778, 798, 0, 337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 338 /* 0x18 - 1280x768@75Hz */ 339 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 340 1488, 1696, 0, 768, 771, 778, 805, 0, 341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 342 /* 0x19 - 1280x768@85Hz */ 343 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 344 1496, 1712, 0, 768, 771, 778, 809, 0, 345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 346 /* 0x1a - 1280x768@120Hz RB */ 347 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 348 1360, 1440, 0, 768, 771, 778, 813, 0, 349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 350 /* 0x1b - 1280x800@60Hz RB */ 351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 352 1360, 1440, 0, 800, 803, 809, 823, 0, 353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 354 /* 0x1c - 1280x800@60Hz */ 355 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 356 1480, 1680, 0, 800, 803, 809, 831, 0, 357 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 358 /* 0x1d - 1280x800@75Hz */ 359 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 360 1488, 1696, 0, 800, 803, 809, 838, 0, 361 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 362 /* 0x1e - 1280x800@85Hz */ 363 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 364 1496, 1712, 0, 800, 803, 809, 843, 0, 365 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 366 /* 0x1f - 1280x800@120Hz RB */ 367 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 368 1360, 1440, 0, 800, 803, 809, 847, 0, 369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 370 /* 0x20 - 1280x960@60Hz */ 371 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 372 1488, 1800, 0, 960, 961, 964, 1000, 0, 373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 374 /* 0x21 - 1280x960@85Hz */ 375 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 376 1504, 1728, 0, 960, 961, 964, 1011, 0, 377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 378 /* 0x22 - 1280x960@120Hz RB */ 379 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 380 1360, 1440, 0, 960, 963, 967, 1017, 0, 381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 382 /* 0x23 - 1280x1024@60Hz */ 383 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 384 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 386 /* 0x24 - 1280x1024@75Hz */ 387 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 388 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 390 /* 0x25 - 1280x1024@85Hz */ 391 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 392 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 394 /* 0x26 - 1280x1024@120Hz RB */ 395 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 396 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 398 /* 0x27 - 1360x768@60Hz */ 399 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 400 1536, 1792, 0, 768, 771, 777, 795, 0, 401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 402 /* 0x28 - 1360x768@120Hz RB */ 403 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 404 1440, 1520, 0, 768, 771, 776, 813, 0, 405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 406 /* 0x51 - 1366x768@60Hz */ 407 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 408 1579, 1792, 0, 768, 771, 774, 798, 0, 409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 410 /* 0x56 - 1366x768@60Hz */ 411 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 412 1436, 1500, 0, 768, 769, 772, 800, 0, 413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 414 /* 0x29 - 1400x1050@60Hz RB */ 415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 416 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 418 /* 0x2a - 1400x1050@60Hz */ 419 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 420 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 422 /* 0x2b - 1400x1050@75Hz */ 423 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 424 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 426 /* 0x2c - 1400x1050@85Hz */ 427 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 428 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 430 /* 0x2d - 1400x1050@120Hz RB */ 431 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 432 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 434 /* 0x2e - 1440x900@60Hz RB */ 435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 436 1520, 1600, 0, 900, 903, 909, 926, 0, 437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 438 /* 0x2f - 1440x900@60Hz */ 439 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 440 1672, 1904, 0, 900, 903, 909, 934, 0, 441 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 442 /* 0x30 - 1440x900@75Hz */ 443 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 444 1688, 1936, 0, 900, 903, 909, 942, 0, 445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 446 /* 0x31 - 1440x900@85Hz */ 447 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 448 1696, 1952, 0, 900, 903, 909, 948, 0, 449 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 450 /* 0x32 - 1440x900@120Hz RB */ 451 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 452 1520, 1600, 0, 900, 903, 909, 953, 0, 453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 454 /* 0x53 - 1600x900@60Hz */ 455 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 456 1704, 1800, 0, 900, 901, 904, 1000, 0, 457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 458 /* 0x33 - 1600x1200@60Hz */ 459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 462 /* 0x34 - 1600x1200@65Hz */ 463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 464 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 466 /* 0x35 - 1600x1200@70Hz */ 467 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 468 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 470 /* 0x36 - 1600x1200@75Hz */ 471 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 472 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 474 /* 0x37 - 1600x1200@85Hz */ 475 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 476 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 478 /* 0x38 - 1600x1200@120Hz RB */ 479 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 480 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 482 /* 0x39 - 1680x1050@60Hz RB */ 483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 484 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 486 /* 0x3a - 1680x1050@60Hz */ 487 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 488 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 490 /* 0x3b - 1680x1050@75Hz */ 491 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 492 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 494 /* 0x3c - 1680x1050@85Hz */ 495 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 496 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 498 /* 0x3d - 1680x1050@120Hz RB */ 499 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 500 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 502 /* 0x3e - 1792x1344@60Hz */ 503 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 504 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 506 /* 0x3f - 1792x1344@75Hz */ 507 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 508 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 510 /* 0x40 - 1792x1344@120Hz RB */ 511 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 512 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 514 /* 0x41 - 1856x1392@60Hz */ 515 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 516 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 517 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 518 /* 0x42 - 1856x1392@75Hz */ 519 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 520 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 522 /* 0x43 - 1856x1392@120Hz RB */ 523 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 524 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 526 /* 0x52 - 1920x1080@60Hz */ 527 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 528 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 530 /* 0x44 - 1920x1200@60Hz RB */ 531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 532 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 534 /* 0x45 - 1920x1200@60Hz */ 535 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 536 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 538 /* 0x46 - 1920x1200@75Hz */ 539 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 540 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 541 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 542 /* 0x47 - 1920x1200@85Hz */ 543 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 544 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 546 /* 0x48 - 1920x1200@120Hz RB */ 547 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 548 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 550 /* 0x49 - 1920x1440@60Hz */ 551 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 552 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 553 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 554 /* 0x4a - 1920x1440@75Hz */ 555 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 556 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 558 /* 0x4b - 1920x1440@120Hz RB */ 559 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 560 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 562 /* 0x54 - 2048x1152@60Hz */ 563 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 564 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 566 /* 0x4c - 2560x1600@60Hz RB */ 567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 568 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 570 /* 0x4d - 2560x1600@60Hz */ 571 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 572 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 573 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 574 /* 0x4e - 2560x1600@75Hz */ 575 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 576 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 577 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 578 /* 0x4f - 2560x1600@85Hz */ 579 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 580 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 581 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 582 /* 0x50 - 2560x1600@120Hz RB */ 583 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 584 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 586 /* 0x57 - 4096x2160@60Hz RB */ 587 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 588 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 589 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 590 /* 0x58 - 4096x2160@59.94Hz RB */ 591 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 592 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 593 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 594 }; 595 596 /* 597 * These more or less come from the DMT spec. The 720x400 modes are 598 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 599 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 600 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 601 * mode. 602 * 603 * The DMT modes have been fact-checked; the rest are mild guesses. 604 */ 605 static const struct drm_display_mode edid_est_modes[] = { 606 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 607 968, 1056, 0, 600, 601, 605, 628, 0, 608 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 609 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 610 896, 1024, 0, 600, 601, 603, 625, 0, 611 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 612 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 613 720, 840, 0, 480, 481, 484, 500, 0, 614 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 615 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 616 704, 832, 0, 480, 489, 492, 520, 0, 617 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 618 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 619 768, 864, 0, 480, 483, 486, 525, 0, 620 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 621 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 622 752, 800, 0, 480, 490, 492, 525, 0, 623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 624 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 625 846, 900, 0, 400, 421, 423, 449, 0, 626 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 627 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 628 846, 900, 0, 400, 412, 414, 449, 0, 629 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 630 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 631 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 632 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 633 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 634 1136, 1312, 0, 768, 769, 772, 800, 0, 635 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 636 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 637 1184, 1328, 0, 768, 771, 777, 806, 0, 638 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 639 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 640 1184, 1344, 0, 768, 771, 777, 806, 0, 641 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 642 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 643 1208, 1264, 0, 768, 768, 776, 817, 0, 644 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 645 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 646 928, 1152, 0, 624, 625, 628, 667, 0, 647 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 648 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 649 896, 1056, 0, 600, 601, 604, 625, 0, 650 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 651 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 652 976, 1040, 0, 600, 637, 643, 666, 0, 653 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 654 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 655 1344, 1600, 0, 864, 865, 868, 900, 0, 656 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 657 }; 658 659 struct minimode { 660 short w; 661 short h; 662 short r; 663 short rb; 664 }; 665 666 static const struct minimode est3_modes[] = { 667 /* byte 6 */ 668 { 640, 350, 85, 0 }, 669 { 640, 400, 85, 0 }, 670 { 720, 400, 85, 0 }, 671 { 640, 480, 85, 0 }, 672 { 848, 480, 60, 0 }, 673 { 800, 600, 85, 0 }, 674 { 1024, 768, 85, 0 }, 675 { 1152, 864, 75, 0 }, 676 /* byte 7 */ 677 { 1280, 768, 60, 1 }, 678 { 1280, 768, 60, 0 }, 679 { 1280, 768, 75, 0 }, 680 { 1280, 768, 85, 0 }, 681 { 1280, 960, 60, 0 }, 682 { 1280, 960, 85, 0 }, 683 { 1280, 1024, 60, 0 }, 684 { 1280, 1024, 85, 0 }, 685 /* byte 8 */ 686 { 1360, 768, 60, 0 }, 687 { 1440, 900, 60, 1 }, 688 { 1440, 900, 60, 0 }, 689 { 1440, 900, 75, 0 }, 690 { 1440, 900, 85, 0 }, 691 { 1400, 1050, 60, 1 }, 692 { 1400, 1050, 60, 0 }, 693 { 1400, 1050, 75, 0 }, 694 /* byte 9 */ 695 { 1400, 1050, 85, 0 }, 696 { 1680, 1050, 60, 1 }, 697 { 1680, 1050, 60, 0 }, 698 { 1680, 1050, 75, 0 }, 699 { 1680, 1050, 85, 0 }, 700 { 1600, 1200, 60, 0 }, 701 { 1600, 1200, 65, 0 }, 702 { 1600, 1200, 70, 0 }, 703 /* byte 10 */ 704 { 1600, 1200, 75, 0 }, 705 { 1600, 1200, 85, 0 }, 706 { 1792, 1344, 60, 0 }, 707 { 1792, 1344, 75, 0 }, 708 { 1856, 1392, 60, 0 }, 709 { 1856, 1392, 75, 0 }, 710 { 1920, 1200, 60, 1 }, 711 { 1920, 1200, 60, 0 }, 712 /* byte 11 */ 713 { 1920, 1200, 75, 0 }, 714 { 1920, 1200, 85, 0 }, 715 { 1920, 1440, 60, 0 }, 716 { 1920, 1440, 75, 0 }, 717 }; 718 719 static const struct minimode extra_modes[] = { 720 { 1024, 576, 60, 0 }, 721 { 1366, 768, 60, 0 }, 722 { 1600, 900, 60, 0 }, 723 { 1680, 945, 60, 0 }, 724 { 1920, 1080, 60, 0 }, 725 { 2048, 1152, 60, 0 }, 726 { 2048, 1536, 60, 0 }, 727 }; 728 729 /* 730 * From CEA/CTA-861 spec. 731 * 732 * Do not access directly, instead always use cea_mode_for_vic(). 733 */ 734 static const struct drm_display_mode edid_cea_modes_1[] = { 735 /* 1 - 640x480@60Hz 4:3 */ 736 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 737 752, 800, 0, 480, 490, 492, 525, 0, 738 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 739 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 740 /* 2 - 720x480@60Hz 4:3 */ 741 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 742 798, 858, 0, 480, 489, 495, 525, 0, 743 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 744 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 745 /* 3 - 720x480@60Hz 16:9 */ 746 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 747 798, 858, 0, 480, 489, 495, 525, 0, 748 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 749 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 750 /* 4 - 1280x720@60Hz 16:9 */ 751 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 752 1430, 1650, 0, 720, 725, 730, 750, 0, 753 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 754 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 755 /* 5 - 1920x1080i@60Hz 16:9 */ 756 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 757 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 758 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 759 DRM_MODE_FLAG_INTERLACE), 760 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 761 /* 6 - 720(1440)x480i@60Hz 4:3 */ 762 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 763 801, 858, 0, 480, 488, 494, 525, 0, 764 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 765 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 766 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 767 /* 7 - 720(1440)x480i@60Hz 16:9 */ 768 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 769 801, 858, 0, 480, 488, 494, 525, 0, 770 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 771 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 772 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 773 /* 8 - 720(1440)x240@60Hz 4:3 */ 774 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 775 801, 858, 0, 240, 244, 247, 262, 0, 776 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 777 DRM_MODE_FLAG_DBLCLK), 778 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 779 /* 9 - 720(1440)x240@60Hz 16:9 */ 780 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 781 801, 858, 0, 240, 244, 247, 262, 0, 782 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 783 DRM_MODE_FLAG_DBLCLK), 784 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 785 /* 10 - 2880x480i@60Hz 4:3 */ 786 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 787 3204, 3432, 0, 480, 488, 494, 525, 0, 788 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 789 DRM_MODE_FLAG_INTERLACE), 790 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 791 /* 11 - 2880x480i@60Hz 16:9 */ 792 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 793 3204, 3432, 0, 480, 488, 494, 525, 0, 794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 795 DRM_MODE_FLAG_INTERLACE), 796 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 797 /* 12 - 2880x240@60Hz 4:3 */ 798 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 799 3204, 3432, 0, 240, 244, 247, 262, 0, 800 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 801 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 802 /* 13 - 2880x240@60Hz 16:9 */ 803 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 804 3204, 3432, 0, 240, 244, 247, 262, 0, 805 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 806 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 807 /* 14 - 1440x480@60Hz 4:3 */ 808 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 809 1596, 1716, 0, 480, 489, 495, 525, 0, 810 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 811 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 812 /* 15 - 1440x480@60Hz 16:9 */ 813 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 814 1596, 1716, 0, 480, 489, 495, 525, 0, 815 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 816 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 817 /* 16 - 1920x1080@60Hz 16:9 */ 818 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 819 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 820 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 821 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 822 /* 17 - 720x576@50Hz 4:3 */ 823 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 824 796, 864, 0, 576, 581, 586, 625, 0, 825 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 826 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 827 /* 18 - 720x576@50Hz 16:9 */ 828 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 829 796, 864, 0, 576, 581, 586, 625, 0, 830 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 831 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 832 /* 19 - 1280x720@50Hz 16:9 */ 833 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 834 1760, 1980, 0, 720, 725, 730, 750, 0, 835 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 836 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 837 /* 20 - 1920x1080i@50Hz 16:9 */ 838 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 839 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 840 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 841 DRM_MODE_FLAG_INTERLACE), 842 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 843 /* 21 - 720(1440)x576i@50Hz 4:3 */ 844 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 845 795, 864, 0, 576, 580, 586, 625, 0, 846 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 847 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 848 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 849 /* 22 - 720(1440)x576i@50Hz 16:9 */ 850 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 851 795, 864, 0, 576, 580, 586, 625, 0, 852 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 853 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 854 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 855 /* 23 - 720(1440)x288@50Hz 4:3 */ 856 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 857 795, 864, 0, 288, 290, 293, 312, 0, 858 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 859 DRM_MODE_FLAG_DBLCLK), 860 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 861 /* 24 - 720(1440)x288@50Hz 16:9 */ 862 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 863 795, 864, 0, 288, 290, 293, 312, 0, 864 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 865 DRM_MODE_FLAG_DBLCLK), 866 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 867 /* 25 - 2880x576i@50Hz 4:3 */ 868 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 869 3180, 3456, 0, 576, 580, 586, 625, 0, 870 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 871 DRM_MODE_FLAG_INTERLACE), 872 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 873 /* 26 - 2880x576i@50Hz 16:9 */ 874 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 875 3180, 3456, 0, 576, 580, 586, 625, 0, 876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 877 DRM_MODE_FLAG_INTERLACE), 878 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 879 /* 27 - 2880x288@50Hz 4:3 */ 880 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 881 3180, 3456, 0, 288, 290, 293, 312, 0, 882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 883 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 884 /* 28 - 2880x288@50Hz 16:9 */ 885 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 886 3180, 3456, 0, 288, 290, 293, 312, 0, 887 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 888 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 889 /* 29 - 1440x576@50Hz 4:3 */ 890 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 891 1592, 1728, 0, 576, 581, 586, 625, 0, 892 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 893 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 894 /* 30 - 1440x576@50Hz 16:9 */ 895 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 896 1592, 1728, 0, 576, 581, 586, 625, 0, 897 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 898 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 899 /* 31 - 1920x1080@50Hz 16:9 */ 900 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 901 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 902 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 903 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 904 /* 32 - 1920x1080@24Hz 16:9 */ 905 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 906 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 907 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 908 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 909 /* 33 - 1920x1080@25Hz 16:9 */ 910 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 911 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 912 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 913 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 914 /* 34 - 1920x1080@30Hz 16:9 */ 915 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 916 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 917 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 918 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 919 /* 35 - 2880x480@60Hz 4:3 */ 920 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 921 3192, 3432, 0, 480, 489, 495, 525, 0, 922 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 923 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 924 /* 36 - 2880x480@60Hz 16:9 */ 925 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 926 3192, 3432, 0, 480, 489, 495, 525, 0, 927 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 928 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 929 /* 37 - 2880x576@50Hz 4:3 */ 930 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 931 3184, 3456, 0, 576, 581, 586, 625, 0, 932 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 933 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 934 /* 38 - 2880x576@50Hz 16:9 */ 935 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 936 3184, 3456, 0, 576, 581, 586, 625, 0, 937 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 938 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 939 /* 39 - 1920x1080i@50Hz 16:9 */ 940 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 941 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 942 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 943 DRM_MODE_FLAG_INTERLACE), 944 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 945 /* 40 - 1920x1080i@100Hz 16:9 */ 946 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 947 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 948 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 949 DRM_MODE_FLAG_INTERLACE), 950 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 951 /* 41 - 1280x720@100Hz 16:9 */ 952 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 953 1760, 1980, 0, 720, 725, 730, 750, 0, 954 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 955 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 956 /* 42 - 720x576@100Hz 4:3 */ 957 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 958 796, 864, 0, 576, 581, 586, 625, 0, 959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 960 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 961 /* 43 - 720x576@100Hz 16:9 */ 962 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 963 796, 864, 0, 576, 581, 586, 625, 0, 964 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 965 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 966 /* 44 - 720(1440)x576i@100Hz 4:3 */ 967 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 968 795, 864, 0, 576, 580, 586, 625, 0, 969 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 970 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 971 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 972 /* 45 - 720(1440)x576i@100Hz 16:9 */ 973 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 974 795, 864, 0, 576, 580, 586, 625, 0, 975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 976 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 977 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 978 /* 46 - 1920x1080i@120Hz 16:9 */ 979 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 980 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 981 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 982 DRM_MODE_FLAG_INTERLACE), 983 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 984 /* 47 - 1280x720@120Hz 16:9 */ 985 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 986 1430, 1650, 0, 720, 725, 730, 750, 0, 987 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 988 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 989 /* 48 - 720x480@120Hz 4:3 */ 990 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 991 798, 858, 0, 480, 489, 495, 525, 0, 992 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 993 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 994 /* 49 - 720x480@120Hz 16:9 */ 995 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 996 798, 858, 0, 480, 489, 495, 525, 0, 997 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 998 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 999 /* 50 - 720(1440)x480i@120Hz 4:3 */ 1000 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1001 801, 858, 0, 480, 488, 494, 525, 0, 1002 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1003 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1004 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1005 /* 51 - 720(1440)x480i@120Hz 16:9 */ 1006 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1007 801, 858, 0, 480, 488, 494, 525, 0, 1008 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1009 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1010 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1011 /* 52 - 720x576@200Hz 4:3 */ 1012 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1013 796, 864, 0, 576, 581, 586, 625, 0, 1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1015 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1016 /* 53 - 720x576@200Hz 16:9 */ 1017 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1018 796, 864, 0, 576, 581, 586, 625, 0, 1019 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1020 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1021 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1022 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1023 795, 864, 0, 576, 580, 586, 625, 0, 1024 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1025 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1026 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1027 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1028 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1029 795, 864, 0, 576, 580, 586, 625, 0, 1030 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1031 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1032 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1033 /* 56 - 720x480@240Hz 4:3 */ 1034 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1035 798, 858, 0, 480, 489, 495, 525, 0, 1036 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1037 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1038 /* 57 - 720x480@240Hz 16:9 */ 1039 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1040 798, 858, 0, 480, 489, 495, 525, 0, 1041 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1042 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1043 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1044 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1045 801, 858, 0, 480, 488, 494, 525, 0, 1046 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1047 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1048 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1049 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1050 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1051 801, 858, 0, 480, 488, 494, 525, 0, 1052 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1053 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1054 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1055 /* 60 - 1280x720@24Hz 16:9 */ 1056 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1057 3080, 3300, 0, 720, 725, 730, 750, 0, 1058 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1059 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1060 /* 61 - 1280x720@25Hz 16:9 */ 1061 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1062 3740, 3960, 0, 720, 725, 730, 750, 0, 1063 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1064 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1065 /* 62 - 1280x720@30Hz 16:9 */ 1066 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1067 3080, 3300, 0, 720, 725, 730, 750, 0, 1068 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1069 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1070 /* 63 - 1920x1080@120Hz 16:9 */ 1071 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1072 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1073 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1074 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1075 /* 64 - 1920x1080@100Hz 16:9 */ 1076 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1077 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1079 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1080 /* 65 - 1280x720@24Hz 64:27 */ 1081 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1082 3080, 3300, 0, 720, 725, 730, 750, 0, 1083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1084 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1085 /* 66 - 1280x720@25Hz 64:27 */ 1086 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1087 3740, 3960, 0, 720, 725, 730, 750, 0, 1088 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1089 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1090 /* 67 - 1280x720@30Hz 64:27 */ 1091 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1092 3080, 3300, 0, 720, 725, 730, 750, 0, 1093 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1094 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1095 /* 68 - 1280x720@50Hz 64:27 */ 1096 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1097 1760, 1980, 0, 720, 725, 730, 750, 0, 1098 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1099 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1100 /* 69 - 1280x720@60Hz 64:27 */ 1101 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1102 1430, 1650, 0, 720, 725, 730, 750, 0, 1103 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1104 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1105 /* 70 - 1280x720@100Hz 64:27 */ 1106 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1107 1760, 1980, 0, 720, 725, 730, 750, 0, 1108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1109 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1110 /* 71 - 1280x720@120Hz 64:27 */ 1111 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1112 1430, 1650, 0, 720, 725, 730, 750, 0, 1113 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1114 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1115 /* 72 - 1920x1080@24Hz 64:27 */ 1116 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1117 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1118 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1119 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1120 /* 73 - 1920x1080@25Hz 64:27 */ 1121 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1122 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1123 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1124 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1125 /* 74 - 1920x1080@30Hz 64:27 */ 1126 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1127 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1129 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1130 /* 75 - 1920x1080@50Hz 64:27 */ 1131 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1132 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1133 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1134 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1135 /* 76 - 1920x1080@60Hz 64:27 */ 1136 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1137 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1139 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1140 /* 77 - 1920x1080@100Hz 64:27 */ 1141 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1142 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1143 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1144 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1145 /* 78 - 1920x1080@120Hz 64:27 */ 1146 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1147 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1149 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1150 /* 79 - 1680x720@24Hz 64:27 */ 1151 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1152 3080, 3300, 0, 720, 725, 730, 750, 0, 1153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1154 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1155 /* 80 - 1680x720@25Hz 64:27 */ 1156 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1157 2948, 3168, 0, 720, 725, 730, 750, 0, 1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1159 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1160 /* 81 - 1680x720@30Hz 64:27 */ 1161 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1162 2420, 2640, 0, 720, 725, 730, 750, 0, 1163 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1164 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1165 /* 82 - 1680x720@50Hz 64:27 */ 1166 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1167 1980, 2200, 0, 720, 725, 730, 750, 0, 1168 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1169 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1170 /* 83 - 1680x720@60Hz 64:27 */ 1171 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1172 1980, 2200, 0, 720, 725, 730, 750, 0, 1173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1174 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1175 /* 84 - 1680x720@100Hz 64:27 */ 1176 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1177 1780, 2000, 0, 720, 725, 730, 825, 0, 1178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1179 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1180 /* 85 - 1680x720@120Hz 64:27 */ 1181 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1182 1780, 2000, 0, 720, 725, 730, 825, 0, 1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1184 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1185 /* 86 - 2560x1080@24Hz 64:27 */ 1186 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1187 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1189 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1190 /* 87 - 2560x1080@25Hz 64:27 */ 1191 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1192 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1194 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1195 /* 88 - 2560x1080@30Hz 64:27 */ 1196 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1197 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1199 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1200 /* 89 - 2560x1080@50Hz 64:27 */ 1201 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1202 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1204 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1205 /* 90 - 2560x1080@60Hz 64:27 */ 1206 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1207 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1209 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1210 /* 91 - 2560x1080@100Hz 64:27 */ 1211 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1212 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1214 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1215 /* 92 - 2560x1080@120Hz 64:27 */ 1216 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1217 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1219 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1220 /* 93 - 3840x2160@24Hz 16:9 */ 1221 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1222 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1224 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1225 /* 94 - 3840x2160@25Hz 16:9 */ 1226 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1227 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1229 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1230 /* 95 - 3840x2160@30Hz 16:9 */ 1231 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1232 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1234 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1235 /* 96 - 3840x2160@50Hz 16:9 */ 1236 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1237 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1239 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1240 /* 97 - 3840x2160@60Hz 16:9 */ 1241 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1242 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1244 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1245 /* 98 - 4096x2160@24Hz 256:135 */ 1246 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1247 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1249 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1250 /* 99 - 4096x2160@25Hz 256:135 */ 1251 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1252 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1254 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1255 /* 100 - 4096x2160@30Hz 256:135 */ 1256 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1257 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1259 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1260 /* 101 - 4096x2160@50Hz 256:135 */ 1261 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1262 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1264 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1265 /* 102 - 4096x2160@60Hz 256:135 */ 1266 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1267 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1269 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1270 /* 103 - 3840x2160@24Hz 64:27 */ 1271 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1272 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1274 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1275 /* 104 - 3840x2160@25Hz 64:27 */ 1276 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1277 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1279 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1280 /* 105 - 3840x2160@30Hz 64:27 */ 1281 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1282 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1284 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1285 /* 106 - 3840x2160@50Hz 64:27 */ 1286 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1287 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1289 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1290 /* 107 - 3840x2160@60Hz 64:27 */ 1291 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1292 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1294 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1295 /* 108 - 1280x720@48Hz 16:9 */ 1296 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1297 2280, 2500, 0, 720, 725, 730, 750, 0, 1298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1299 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1300 /* 109 - 1280x720@48Hz 64:27 */ 1301 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1302 2280, 2500, 0, 720, 725, 730, 750, 0, 1303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1304 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1305 /* 110 - 1680x720@48Hz 64:27 */ 1306 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1307 2530, 2750, 0, 720, 725, 730, 750, 0, 1308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1309 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1310 /* 111 - 1920x1080@48Hz 16:9 */ 1311 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1312 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1314 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1315 /* 112 - 1920x1080@48Hz 64:27 */ 1316 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1317 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1319 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1320 /* 113 - 2560x1080@48Hz 64:27 */ 1321 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1322 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1324 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1325 /* 114 - 3840x2160@48Hz 16:9 */ 1326 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1327 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1329 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1330 /* 115 - 4096x2160@48Hz 256:135 */ 1331 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1332 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1334 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1335 /* 116 - 3840x2160@48Hz 64:27 */ 1336 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1337 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1339 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1340 /* 117 - 3840x2160@100Hz 16:9 */ 1341 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1342 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1344 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1345 /* 118 - 3840x2160@120Hz 16:9 */ 1346 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1347 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1349 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1350 /* 119 - 3840x2160@100Hz 64:27 */ 1351 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1352 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1354 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1355 /* 120 - 3840x2160@120Hz 64:27 */ 1356 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1357 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1359 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1360 /* 121 - 5120x2160@24Hz 64:27 */ 1361 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1362 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1364 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1365 /* 122 - 5120x2160@25Hz 64:27 */ 1366 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1367 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1369 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1370 /* 123 - 5120x2160@30Hz 64:27 */ 1371 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1372 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1374 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1375 /* 124 - 5120x2160@48Hz 64:27 */ 1376 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1377 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1379 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1380 /* 125 - 5120x2160@50Hz 64:27 */ 1381 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1382 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1383 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1384 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1385 /* 126 - 5120x2160@60Hz 64:27 */ 1386 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1387 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1389 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1390 /* 127 - 5120x2160@100Hz 64:27 */ 1391 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1392 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1394 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1395 }; 1396 1397 /* 1398 * From CEA/CTA-861 spec. 1399 * 1400 * Do not access directly, instead always use cea_mode_for_vic(). 1401 */ 1402 static const struct drm_display_mode edid_cea_modes_193[] = { 1403 /* 193 - 5120x2160@120Hz 64:27 */ 1404 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1405 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1407 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1408 /* 194 - 7680x4320@24Hz 16:9 */ 1409 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1410 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1412 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1413 /* 195 - 7680x4320@25Hz 16:9 */ 1414 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1415 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1417 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1418 /* 196 - 7680x4320@30Hz 16:9 */ 1419 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1420 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1422 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1423 /* 197 - 7680x4320@48Hz 16:9 */ 1424 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1425 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1426 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1427 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1428 /* 198 - 7680x4320@50Hz 16:9 */ 1429 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1430 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1432 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1433 /* 199 - 7680x4320@60Hz 16:9 */ 1434 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1435 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1437 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1438 /* 200 - 7680x4320@100Hz 16:9 */ 1439 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1440 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1442 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1443 /* 201 - 7680x4320@120Hz 16:9 */ 1444 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1445 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1446 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1447 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1448 /* 202 - 7680x4320@24Hz 64:27 */ 1449 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1450 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1451 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1452 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1453 /* 203 - 7680x4320@25Hz 64:27 */ 1454 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1455 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1457 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1458 /* 204 - 7680x4320@30Hz 64:27 */ 1459 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1460 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1462 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1463 /* 205 - 7680x4320@48Hz 64:27 */ 1464 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1465 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1467 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1468 /* 206 - 7680x4320@50Hz 64:27 */ 1469 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1470 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1472 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1473 /* 207 - 7680x4320@60Hz 64:27 */ 1474 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1475 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1477 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1478 /* 208 - 7680x4320@100Hz 64:27 */ 1479 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1480 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1482 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1483 /* 209 - 7680x4320@120Hz 64:27 */ 1484 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1485 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1487 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1488 /* 210 - 10240x4320@24Hz 64:27 */ 1489 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1490 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1492 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1493 /* 211 - 10240x4320@25Hz 64:27 */ 1494 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1495 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1497 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1498 /* 212 - 10240x4320@30Hz 64:27 */ 1499 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1500 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1502 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1503 /* 213 - 10240x4320@48Hz 64:27 */ 1504 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1505 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1507 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1508 /* 214 - 10240x4320@50Hz 64:27 */ 1509 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1510 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1512 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1513 /* 215 - 10240x4320@60Hz 64:27 */ 1514 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1515 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1517 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1518 /* 216 - 10240x4320@100Hz 64:27 */ 1519 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1520 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1522 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1523 /* 217 - 10240x4320@120Hz 64:27 */ 1524 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1525 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1527 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1528 /* 218 - 4096x2160@100Hz 256:135 */ 1529 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1530 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1531 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1532 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1533 /* 219 - 4096x2160@120Hz 256:135 */ 1534 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1535 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1536 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1537 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1538 }; 1539 1540 /* 1541 * HDMI 1.4 4k modes. Index using the VIC. 1542 */ 1543 static const struct drm_display_mode edid_4k_modes[] = { 1544 /* 0 - dummy, VICs start at 1 */ 1545 { }, 1546 /* 1 - 3840x2160@30Hz */ 1547 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1548 3840, 4016, 4104, 4400, 0, 1549 2160, 2168, 2178, 2250, 0, 1550 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1551 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1552 /* 2 - 3840x2160@25Hz */ 1553 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1554 3840, 4896, 4984, 5280, 0, 1555 2160, 2168, 2178, 2250, 0, 1556 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1557 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1558 /* 3 - 3840x2160@24Hz */ 1559 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1560 3840, 5116, 5204, 5500, 0, 1561 2160, 2168, 2178, 2250, 0, 1562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1563 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1564 /* 4 - 4096x2160@24Hz (SMPTE) */ 1565 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1566 4096, 5116, 5204, 5500, 0, 1567 2160, 2168, 2178, 2250, 0, 1568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1569 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1570 }; 1571 1572 /*** DDC fetch and block validation ***/ 1573 1574 /* 1575 * The opaque EDID type, internal to drm_edid.c. 1576 */ 1577 struct drm_edid { 1578 /* Size allocated for edid */ 1579 size_t size; 1580 const struct edid *edid; 1581 }; 1582 1583 static bool version_greater(const struct drm_edid *drm_edid, 1584 u8 version, u8 revision) 1585 { 1586 const struct edid *edid = drm_edid->edid; 1587 1588 return edid->version > version || 1589 (edid->version == version && edid->revision > revision); 1590 } 1591 1592 static int edid_hfeeodb_extension_block_count(const struct edid *edid); 1593 1594 static int edid_hfeeodb_block_count(const struct edid *edid) 1595 { 1596 int eeodb = edid_hfeeodb_extension_block_count(edid); 1597 1598 return eeodb ? eeodb + 1 : 0; 1599 } 1600 1601 static int edid_extension_block_count(const struct edid *edid) 1602 { 1603 return edid->extensions; 1604 } 1605 1606 static int edid_block_count(const struct edid *edid) 1607 { 1608 return edid_extension_block_count(edid) + 1; 1609 } 1610 1611 static int edid_size_by_blocks(int num_blocks) 1612 { 1613 return num_blocks * EDID_LENGTH; 1614 } 1615 1616 static int edid_size(const struct edid *edid) 1617 { 1618 return edid_size_by_blocks(edid_block_count(edid)); 1619 } 1620 1621 static const void *edid_block_data(const struct edid *edid, int index) 1622 { 1623 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH); 1624 1625 return edid + index; 1626 } 1627 1628 static const void *edid_extension_block_data(const struct edid *edid, int index) 1629 { 1630 return edid_block_data(edid, index + 1); 1631 } 1632 1633 static int drm_edid_block_count(const struct drm_edid *drm_edid) 1634 { 1635 int num_blocks; 1636 1637 /* Starting point */ 1638 num_blocks = edid_block_count(drm_edid->edid); 1639 1640 /* HF-EEODB override */ 1641 if (drm_edid->size >= edid_size_by_blocks(2)) { 1642 int eeodb; 1643 1644 /* 1645 * Note: HF-EEODB may specify a smaller extension count than the 1646 * regular one. Unlike in buffer allocation, here we can use it. 1647 */ 1648 eeodb = edid_hfeeodb_block_count(drm_edid->edid); 1649 if (eeodb) 1650 num_blocks = eeodb; 1651 } 1652 1653 /* Limit by allocated size */ 1654 num_blocks = min(num_blocks, (int)drm_edid->size / EDID_LENGTH); 1655 1656 return num_blocks; 1657 } 1658 1659 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid) 1660 { 1661 return drm_edid_block_count(drm_edid) - 1; 1662 } 1663 1664 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index) 1665 { 1666 return edid_block_data(drm_edid->edid, index); 1667 } 1668 1669 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid, 1670 int index) 1671 { 1672 return edid_extension_block_data(drm_edid->edid, index); 1673 } 1674 1675 /* 1676 * Initializer helper for legacy interfaces, where we have no choice but to 1677 * trust edid size. Not for general purpose use. 1678 */ 1679 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid, 1680 const struct edid *edid) 1681 { 1682 if (!edid) 1683 return NULL; 1684 1685 memset(drm_edid, 0, sizeof(*drm_edid)); 1686 1687 drm_edid->edid = edid; 1688 drm_edid->size = edid_size(edid); 1689 1690 return drm_edid; 1691 } 1692 1693 /* 1694 * EDID base and extension block iterator. 1695 * 1696 * struct drm_edid_iter iter; 1697 * const u8 *block; 1698 * 1699 * drm_edid_iter_begin(drm_edid, &iter); 1700 * drm_edid_iter_for_each(block, &iter) { 1701 * // do stuff with block 1702 * } 1703 * drm_edid_iter_end(&iter); 1704 */ 1705 struct drm_edid_iter { 1706 const struct drm_edid *drm_edid; 1707 1708 /* Current block index. */ 1709 int index; 1710 }; 1711 1712 static void drm_edid_iter_begin(const struct drm_edid *drm_edid, 1713 struct drm_edid_iter *iter) 1714 { 1715 memset(iter, 0, sizeof(*iter)); 1716 1717 iter->drm_edid = drm_edid; 1718 } 1719 1720 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter) 1721 { 1722 const void *block = NULL; 1723 1724 if (!iter->drm_edid) 1725 return NULL; 1726 1727 if (iter->index < drm_edid_block_count(iter->drm_edid)) 1728 block = drm_edid_block_data(iter->drm_edid, iter->index++); 1729 1730 return block; 1731 } 1732 1733 #define drm_edid_iter_for_each(__block, __iter) \ 1734 while (((__block) = __drm_edid_iter_next(__iter))) 1735 1736 static void drm_edid_iter_end(struct drm_edid_iter *iter) 1737 { 1738 memset(iter, 0, sizeof(*iter)); 1739 } 1740 1741 static const u8 edid_header[] = { 1742 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1743 }; 1744 1745 static void edid_header_fix(void *edid) 1746 { 1747 memcpy(edid, edid_header, sizeof(edid_header)); 1748 } 1749 1750 /** 1751 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1752 * @_edid: pointer to raw base EDID block 1753 * 1754 * Sanity check the header of the base EDID block. 1755 * 1756 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1757 */ 1758 int drm_edid_header_is_valid(const void *_edid) 1759 { 1760 const struct edid *edid = _edid; 1761 int i, score = 0; 1762 1763 for (i = 0; i < sizeof(edid_header); i++) { 1764 if (edid->header[i] == edid_header[i]) 1765 score++; 1766 } 1767 1768 return score; 1769 } 1770 EXPORT_SYMBOL(drm_edid_header_is_valid); 1771 1772 static int edid_fixup __read_mostly = 6; 1773 module_param_named(edid_fixup, edid_fixup, int, 0400); 1774 MODULE_PARM_DESC(edid_fixup, 1775 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1776 1777 static int edid_block_compute_checksum(const void *_block) 1778 { 1779 const u8 *block = _block; 1780 int i; 1781 u8 csum = 0, crc = 0; 1782 1783 for (i = 0; i < EDID_LENGTH - 1; i++) 1784 csum += block[i]; 1785 1786 crc = 0x100 - csum; 1787 1788 return crc; 1789 } 1790 1791 static int edid_block_get_checksum(const void *_block) 1792 { 1793 const struct edid *block = _block; 1794 1795 return block->checksum; 1796 } 1797 1798 static int edid_block_tag(const void *_block) 1799 { 1800 const u8 *block = _block; 1801 1802 return block[0]; 1803 } 1804 1805 static bool edid_block_is_zero(const void *edid) 1806 { 1807 return !memchr_inv(edid, 0, EDID_LENGTH); 1808 } 1809 1810 /** 1811 * drm_edid_are_equal - compare two edid blobs. 1812 * @edid1: pointer to first blob 1813 * @edid2: pointer to second blob 1814 * This helper can be used during probing to determine if 1815 * edid had changed. 1816 */ 1817 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2) 1818 { 1819 int edid1_len, edid2_len; 1820 bool edid1_present = edid1 != NULL; 1821 bool edid2_present = edid2 != NULL; 1822 1823 if (edid1_present != edid2_present) 1824 return false; 1825 1826 if (edid1) { 1827 edid1_len = edid_size(edid1); 1828 edid2_len = edid_size(edid2); 1829 1830 if (edid1_len != edid2_len) 1831 return false; 1832 1833 if (memcmp(edid1, edid2, edid1_len)) 1834 return false; 1835 } 1836 1837 return true; 1838 } 1839 EXPORT_SYMBOL(drm_edid_are_equal); 1840 1841 enum edid_block_status { 1842 EDID_BLOCK_OK = 0, 1843 EDID_BLOCK_READ_FAIL, 1844 EDID_BLOCK_NULL, 1845 EDID_BLOCK_ZERO, 1846 EDID_BLOCK_HEADER_CORRUPT, 1847 EDID_BLOCK_HEADER_REPAIR, 1848 EDID_BLOCK_HEADER_FIXED, 1849 EDID_BLOCK_CHECKSUM, 1850 EDID_BLOCK_VERSION, 1851 }; 1852 1853 static enum edid_block_status edid_block_check(const void *_block, 1854 bool is_base_block) 1855 { 1856 const struct edid *block = _block; 1857 1858 if (!block) 1859 return EDID_BLOCK_NULL; 1860 1861 if (is_base_block) { 1862 int score = drm_edid_header_is_valid(block); 1863 1864 if (score < clamp(edid_fixup, 0, 8)) { 1865 if (edid_block_is_zero(block)) 1866 return EDID_BLOCK_ZERO; 1867 else 1868 return EDID_BLOCK_HEADER_CORRUPT; 1869 } 1870 1871 if (score < 8) 1872 return EDID_BLOCK_HEADER_REPAIR; 1873 } 1874 1875 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) { 1876 if (edid_block_is_zero(block)) 1877 return EDID_BLOCK_ZERO; 1878 else 1879 return EDID_BLOCK_CHECKSUM; 1880 } 1881 1882 if (is_base_block) { 1883 if (block->version != 1) 1884 return EDID_BLOCK_VERSION; 1885 } 1886 1887 return EDID_BLOCK_OK; 1888 } 1889 1890 static bool edid_block_status_valid(enum edid_block_status status, int tag) 1891 { 1892 return status == EDID_BLOCK_OK || 1893 status == EDID_BLOCK_HEADER_FIXED || 1894 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT); 1895 } 1896 1897 static bool edid_block_valid(const void *block, bool base) 1898 { 1899 return edid_block_status_valid(edid_block_check(block, base), 1900 edid_block_tag(block)); 1901 } 1902 1903 static void edid_block_status_print(enum edid_block_status status, 1904 const struct edid *block, 1905 int block_num) 1906 { 1907 switch (status) { 1908 case EDID_BLOCK_OK: 1909 break; 1910 case EDID_BLOCK_READ_FAIL: 1911 pr_debug("EDID block %d read failed\n", block_num); 1912 break; 1913 case EDID_BLOCK_NULL: 1914 pr_debug("EDID block %d pointer is NULL\n", block_num); 1915 break; 1916 case EDID_BLOCK_ZERO: 1917 pr_notice("EDID block %d is all zeroes\n", block_num); 1918 break; 1919 case EDID_BLOCK_HEADER_CORRUPT: 1920 pr_notice("EDID has corrupt header\n"); 1921 break; 1922 case EDID_BLOCK_HEADER_REPAIR: 1923 pr_debug("EDID corrupt header needs repair\n"); 1924 break; 1925 case EDID_BLOCK_HEADER_FIXED: 1926 pr_debug("EDID corrupt header fixed\n"); 1927 break; 1928 case EDID_BLOCK_CHECKSUM: 1929 if (edid_block_status_valid(status, edid_block_tag(block))) { 1930 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n", 1931 block_num, edid_block_tag(block), 1932 edid_block_compute_checksum(block)); 1933 } else { 1934 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n", 1935 block_num, edid_block_tag(block), 1936 edid_block_compute_checksum(block)); 1937 } 1938 break; 1939 case EDID_BLOCK_VERSION: 1940 pr_notice("EDID has major version %d, instead of 1\n", 1941 block->version); 1942 break; 1943 default: 1944 WARN(1, "EDID block %d unknown edid block status code %d\n", 1945 block_num, status); 1946 break; 1947 } 1948 } 1949 1950 static void edid_block_dump(const char *level, const void *block, int block_num) 1951 { 1952 enum edid_block_status status; 1953 char prefix[20]; 1954 1955 status = edid_block_check(block, block_num == 0); 1956 if (status == EDID_BLOCK_ZERO) 1957 snprintf(prefix, sizeof(prefix), "\t[%02x] ZERO ", block_num); 1958 else if (!edid_block_status_valid(status, edid_block_tag(block))) 1959 snprintf(prefix, sizeof(prefix), "\t[%02x] BAD ", block_num); 1960 else 1961 snprintf(prefix, sizeof(prefix), "\t[%02x] GOOD ", block_num); 1962 1963 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1, 1964 block, EDID_LENGTH, false); 1965 } 1966 1967 /** 1968 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1969 * @_block: pointer to raw EDID block 1970 * @block_num: type of block to validate (0 for base, extension otherwise) 1971 * @print_bad_edid: if true, dump bad EDID blocks to the console 1972 * @edid_corrupt: if true, the header or checksum is invalid 1973 * 1974 * Validate a base or extension EDID block and optionally dump bad blocks to 1975 * the console. 1976 * 1977 * Return: True if the block is valid, false otherwise. 1978 */ 1979 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid, 1980 bool *edid_corrupt) 1981 { 1982 struct edid *block = (struct edid *)_block; 1983 enum edid_block_status status; 1984 bool is_base_block = block_num == 0; 1985 bool valid; 1986 1987 if (WARN_ON(!block)) 1988 return false; 1989 1990 status = edid_block_check(block, is_base_block); 1991 if (status == EDID_BLOCK_HEADER_REPAIR) { 1992 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1993 edid_header_fix(block); 1994 1995 /* Retry with fixed header, update status if that worked. */ 1996 status = edid_block_check(block, is_base_block); 1997 if (status == EDID_BLOCK_OK) 1998 status = EDID_BLOCK_HEADER_FIXED; 1999 } 2000 2001 if (edid_corrupt) { 2002 /* 2003 * Unknown major version isn't corrupt but we can't use it. Only 2004 * the base block can reset edid_corrupt to false. 2005 */ 2006 if (is_base_block && 2007 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)) 2008 *edid_corrupt = false; 2009 else if (status != EDID_BLOCK_OK) 2010 *edid_corrupt = true; 2011 } 2012 2013 edid_block_status_print(status, block, block_num); 2014 2015 /* Determine whether we can use this block with this status. */ 2016 valid = edid_block_status_valid(status, edid_block_tag(block)); 2017 2018 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) { 2019 pr_notice("Raw EDID:\n"); 2020 edid_block_dump(KERN_NOTICE, block, block_num); 2021 } 2022 2023 return valid; 2024 } 2025 EXPORT_SYMBOL(drm_edid_block_valid); 2026 2027 /** 2028 * drm_edid_is_valid - sanity check EDID data 2029 * @edid: EDID data 2030 * 2031 * Sanity-check an entire EDID record (including extensions) 2032 * 2033 * Return: True if the EDID data is valid, false otherwise. 2034 */ 2035 bool drm_edid_is_valid(struct edid *edid) 2036 { 2037 int i; 2038 2039 if (!edid) 2040 return false; 2041 2042 for (i = 0; i < edid_block_count(edid); i++) { 2043 void *block = (void *)edid_block_data(edid, i); 2044 2045 if (!drm_edid_block_valid(block, i, true, NULL)) 2046 return false; 2047 } 2048 2049 return true; 2050 } 2051 EXPORT_SYMBOL(drm_edid_is_valid); 2052 2053 static struct edid *edid_filter_invalid_blocks(struct edid *edid, 2054 size_t *alloc_size) 2055 { 2056 struct edid *new; 2057 int i, valid_blocks = 0; 2058 2059 /* 2060 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert 2061 * back to regular extension count here. We don't want to start 2062 * modifying the HF-EEODB extension too. 2063 */ 2064 for (i = 0; i < edid_block_count(edid); i++) { 2065 const void *src_block = edid_block_data(edid, i); 2066 2067 if (edid_block_valid(src_block, i == 0)) { 2068 void *dst_block = (void *)edid_block_data(edid, valid_blocks); 2069 2070 memmove(dst_block, src_block, EDID_LENGTH); 2071 valid_blocks++; 2072 } 2073 } 2074 2075 /* We already trusted the base block to be valid here... */ 2076 if (WARN_ON(!valid_blocks)) { 2077 kfree(edid); 2078 return NULL; 2079 } 2080 2081 edid->extensions = valid_blocks - 1; 2082 edid->checksum = edid_block_compute_checksum(edid); 2083 2084 *alloc_size = edid_size_by_blocks(valid_blocks); 2085 2086 #ifdef __linux__ 2087 new = krealloc(edid, *alloc_size, GFP_KERNEL); 2088 if (!new) 2089 kfree(edid); 2090 #else 2091 new = kmalloc(*alloc_size, GFP_KERNEL); 2092 if (!new) 2093 kfree(edid); 2094 memcpy(new, edid, EDID_LENGTH); 2095 kfree(edid); 2096 #endif 2097 2098 return new; 2099 } 2100 2101 #define DDC_SEGMENT_ADDR 0x30 2102 /** 2103 * drm_do_probe_ddc_edid() - get EDID information via I2C 2104 * @data: I2C device adapter 2105 * @buf: EDID data buffer to be filled 2106 * @block: 128 byte EDID block to start fetching from 2107 * @len: EDID data buffer length to fetch 2108 * 2109 * Try to fetch EDID information by calling I2C driver functions. 2110 * 2111 * Return: 0 on success or -1 on failure. 2112 */ 2113 static int 2114 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 2115 { 2116 struct i2c_adapter *adapter = data; 2117 unsigned char start = block * EDID_LENGTH; 2118 unsigned char segment = block >> 1; 2119 unsigned char xfers = segment ? 3 : 2; 2120 int ret, retries = 5; 2121 2122 /* 2123 * The core I2C driver will automatically retry the transfer if the 2124 * adapter reports EAGAIN. However, we find that bit-banging transfers 2125 * are susceptible to errors under a heavily loaded machine and 2126 * generate spurious NAKs and timeouts. Retrying the transfer 2127 * of the individual block a few times seems to overcome this. 2128 */ 2129 do { 2130 struct i2c_msg msgs[] = { 2131 { 2132 .addr = DDC_SEGMENT_ADDR, 2133 .flags = 0, 2134 .len = 1, 2135 .buf = &segment, 2136 }, { 2137 .addr = DDC_ADDR, 2138 .flags = 0, 2139 .len = 1, 2140 .buf = &start, 2141 }, { 2142 .addr = DDC_ADDR, 2143 .flags = I2C_M_RD, 2144 .len = len, 2145 .buf = buf, 2146 } 2147 }; 2148 2149 /* 2150 * Avoid sending the segment addr to not upset non-compliant 2151 * DDC monitors. 2152 */ 2153 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 2154 2155 if (ret == -ENXIO) { 2156 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 2157 adapter->name); 2158 break; 2159 } 2160 } while (ret != xfers && --retries); 2161 2162 return ret == xfers ? 0 : -1; 2163 } 2164 2165 static void connector_bad_edid(struct drm_connector *connector, 2166 const struct edid *edid, int num_blocks) 2167 { 2168 int i; 2169 u8 last_block; 2170 2171 /* 2172 * 0x7e in the EDID is the number of extension blocks. The EDID 2173 * is 1 (base block) + num_ext_blocks big. That means we can think 2174 * of 0x7e in the EDID of the _index_ of the last block in the 2175 * combined chunk of memory. 2176 */ 2177 last_block = edid->extensions; 2178 2179 /* Calculate real checksum for the last edid extension block data */ 2180 if (last_block < num_blocks) 2181 connector->real_edid_checksum = 2182 edid_block_compute_checksum(edid + last_block); 2183 2184 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 2185 return; 2186 2187 drm_dbg_kms(connector->dev, "%s: EDID is invalid:\n", connector->name); 2188 for (i = 0; i < num_blocks; i++) 2189 edid_block_dump(KERN_DEBUG, edid + i, i); 2190 } 2191 2192 /* Get override or firmware EDID */ 2193 static struct edid *drm_get_override_edid(struct drm_connector *connector, 2194 size_t *alloc_size) 2195 { 2196 struct edid *override = NULL; 2197 2198 if (connector->override_edid) 2199 override = drm_edid_duplicate(connector->edid_blob_ptr->data); 2200 2201 if (!override) 2202 override = drm_load_edid_firmware(connector); 2203 2204 /* FIXME: Get alloc size from deeper down the stack */ 2205 if (!IS_ERR_OR_NULL(override) && alloc_size) 2206 *alloc_size = edid_size(override); 2207 2208 return IS_ERR(override) ? NULL : override; 2209 } 2210 2211 /* For debugfs edid_override implementation */ 2212 int drm_edid_override_set(struct drm_connector *connector, const void *edid, 2213 size_t size) 2214 { 2215 int ret; 2216 2217 if (size < EDID_LENGTH || edid_size(edid) > size) 2218 return -EINVAL; 2219 2220 connector->override_edid = false; 2221 2222 ret = drm_connector_update_edid_property(connector, edid); 2223 if (!ret) 2224 connector->override_edid = true; 2225 2226 return ret; 2227 } 2228 2229 /* For debugfs edid_override implementation */ 2230 int drm_edid_override_reset(struct drm_connector *connector) 2231 { 2232 connector->override_edid = false; 2233 2234 return drm_connector_update_edid_property(connector, NULL); 2235 } 2236 2237 /** 2238 * drm_add_override_edid_modes - add modes from override/firmware EDID 2239 * @connector: connector we're probing 2240 * 2241 * Add modes from the override/firmware EDID, if available. Only to be used from 2242 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 2243 * failed during drm_get_edid() and caused the override/firmware EDID to be 2244 * skipped. 2245 * 2246 * Return: The number of modes added or 0 if we couldn't find any. 2247 */ 2248 int drm_add_override_edid_modes(struct drm_connector *connector) 2249 { 2250 struct edid *override; 2251 int num_modes = 0; 2252 2253 override = drm_get_override_edid(connector, NULL); 2254 if (override) { 2255 drm_connector_update_edid_property(connector, override); 2256 num_modes = drm_add_edid_modes(connector, override); 2257 kfree(override); 2258 2259 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 2260 connector->base.id, connector->name, num_modes); 2261 } 2262 2263 return num_modes; 2264 } 2265 EXPORT_SYMBOL(drm_add_override_edid_modes); 2266 2267 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len); 2268 2269 static enum edid_block_status edid_block_read(void *block, unsigned int block_num, 2270 read_block_fn read_block, 2271 void *context) 2272 { 2273 enum edid_block_status status; 2274 bool is_base_block = block_num == 0; 2275 int try; 2276 2277 for (try = 0; try < 4; try++) { 2278 if (read_block(context, block, block_num, EDID_LENGTH)) 2279 return EDID_BLOCK_READ_FAIL; 2280 2281 status = edid_block_check(block, is_base_block); 2282 if (status == EDID_BLOCK_HEADER_REPAIR) { 2283 edid_header_fix(block); 2284 2285 /* Retry with fixed header, update status if that worked. */ 2286 status = edid_block_check(block, is_base_block); 2287 if (status == EDID_BLOCK_OK) 2288 status = EDID_BLOCK_HEADER_FIXED; 2289 } 2290 2291 if (edid_block_status_valid(status, edid_block_tag(block))) 2292 break; 2293 2294 /* Fail early for unrepairable base block all zeros. */ 2295 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO) 2296 break; 2297 } 2298 2299 return status; 2300 } 2301 2302 static struct edid *_drm_do_get_edid(struct drm_connector *connector, 2303 read_block_fn read_block, void *context, 2304 size_t *size) 2305 { 2306 enum edid_block_status status; 2307 int i, num_blocks, invalid_blocks = 0; 2308 struct edid *edid, *new; 2309 size_t alloc_size = EDID_LENGTH; 2310 2311 edid = drm_get_override_edid(connector, &alloc_size); 2312 if (edid) 2313 goto ok; 2314 2315 edid = kmalloc(alloc_size, GFP_KERNEL); 2316 if (!edid) 2317 return NULL; 2318 2319 status = edid_block_read(edid, 0, read_block, context); 2320 2321 edid_block_status_print(status, edid, 0); 2322 2323 if (status == EDID_BLOCK_READ_FAIL) 2324 goto fail; 2325 2326 /* FIXME: Clarify what a corrupt EDID actually means. */ 2327 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION) 2328 connector->edid_corrupt = false; 2329 else 2330 connector->edid_corrupt = true; 2331 2332 if (!edid_block_status_valid(status, edid_block_tag(edid))) { 2333 if (status == EDID_BLOCK_ZERO) 2334 connector->null_edid_counter++; 2335 2336 connector_bad_edid(connector, edid, 1); 2337 goto fail; 2338 } 2339 2340 if (!edid_extension_block_count(edid)) 2341 goto ok; 2342 2343 alloc_size = edid_size(edid); 2344 #ifdef __linux__ 2345 new = krealloc(edid, alloc_size, GFP_KERNEL); 2346 if (!new) 2347 goto fail; 2348 #else 2349 new = kmalloc(alloc_size, GFP_KERNEL); 2350 if (!new) 2351 goto fail; 2352 memcpy(new, edid, EDID_LENGTH); 2353 kfree(edid); 2354 #endif 2355 edid = new; 2356 2357 num_blocks = edid_block_count(edid); 2358 for (i = 1; i < num_blocks; i++) { 2359 void *block = (void *)edid_block_data(edid, i); 2360 2361 status = edid_block_read(block, i, read_block, context); 2362 2363 edid_block_status_print(status, block, i); 2364 2365 if (!edid_block_status_valid(status, edid_block_tag(block))) { 2366 if (status == EDID_BLOCK_READ_FAIL) 2367 goto fail; 2368 invalid_blocks++; 2369 } else if (i == 1) { 2370 /* 2371 * If the first EDID extension is a CTA extension, and 2372 * the first Data Block is HF-EEODB, override the 2373 * extension block count. 2374 * 2375 * Note: HF-EEODB could specify a smaller extension 2376 * count too, but we can't risk allocating a smaller 2377 * amount. 2378 */ 2379 int eeodb = edid_hfeeodb_block_count(edid); 2380 2381 if (eeodb > num_blocks) { 2382 num_blocks = eeodb; 2383 alloc_size = edid_size_by_blocks(num_blocks); 2384 #ifdef __linux__ 2385 new = krealloc(edid, alloc_size, GFP_KERNEL); 2386 if (!new) 2387 goto fail; 2388 #else 2389 new = kmalloc(alloc_size, GFP_KERNEL); 2390 if (!new) 2391 goto fail; 2392 memcpy(new, edid, EDID_LENGTH); 2393 kfree(edid); 2394 #endif 2395 edid = new; 2396 } 2397 } 2398 } 2399 2400 if (invalid_blocks) { 2401 connector_bad_edid(connector, edid, num_blocks); 2402 2403 edid = edid_filter_invalid_blocks(edid, &alloc_size); 2404 } 2405 2406 ok: 2407 if (size) 2408 *size = alloc_size; 2409 2410 return edid; 2411 2412 fail: 2413 kfree(edid); 2414 return NULL; 2415 } 2416 2417 /** 2418 * drm_do_get_edid - get EDID data using a custom EDID block read function 2419 * @connector: connector we're probing 2420 * @read_block: EDID block read function 2421 * @context: private data passed to the block read function 2422 * 2423 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2424 * exposes a different interface to read EDID blocks this function can be used 2425 * to get EDID data using a custom block read function. 2426 * 2427 * As in the general case the DDC bus is accessible by the kernel at the I2C 2428 * level, drivers must make all reasonable efforts to expose it as an I2C 2429 * adapter and use drm_get_edid() instead of abusing this function. 2430 * 2431 * The EDID may be overridden using debugfs override_edid or firmware EDID 2432 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 2433 * order. Having either of them bypasses actual EDID reads. 2434 * 2435 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2436 */ 2437 struct edid *drm_do_get_edid(struct drm_connector *connector, 2438 read_block_fn read_block, 2439 void *context) 2440 { 2441 return _drm_do_get_edid(connector, read_block, context, NULL); 2442 } 2443 EXPORT_SYMBOL_GPL(drm_do_get_edid); 2444 2445 /** 2446 * drm_edid_raw - Get a pointer to the raw EDID data. 2447 * @drm_edid: drm_edid container 2448 * 2449 * Get a pointer to the raw EDID data. 2450 * 2451 * This is for transition only. Avoid using this like the plague. 2452 * 2453 * Return: Pointer to raw EDID data. 2454 */ 2455 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid) 2456 { 2457 if (!drm_edid || !drm_edid->size) 2458 return NULL; 2459 2460 /* 2461 * Do not return pointers where relying on EDID extension count would 2462 * lead to buffer overflow. 2463 */ 2464 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size)) 2465 return NULL; 2466 2467 return drm_edid->edid; 2468 } 2469 EXPORT_SYMBOL(drm_edid_raw); 2470 2471 /* Allocate struct drm_edid container *without* duplicating the edid data */ 2472 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size) 2473 { 2474 struct drm_edid *drm_edid; 2475 2476 if (!edid || !size || size < EDID_LENGTH) 2477 return NULL; 2478 2479 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL); 2480 if (drm_edid) { 2481 drm_edid->edid = edid; 2482 drm_edid->size = size; 2483 } 2484 2485 return drm_edid; 2486 } 2487 2488 /** 2489 * drm_edid_alloc - Allocate a new drm_edid container 2490 * @edid: Pointer to raw EDID data 2491 * @size: Size of memory allocated for EDID 2492 * 2493 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass 2494 * the actual size that has been allocated for the data. There is no validation 2495 * of the raw EDID data against the size, but at least the EDID base block must 2496 * fit in the buffer. 2497 * 2498 * The returned pointer must be freed using drm_edid_free(). 2499 * 2500 * Return: drm_edid container, or NULL on errors 2501 */ 2502 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size) 2503 { 2504 const struct drm_edid *drm_edid; 2505 2506 if (!edid || !size || size < EDID_LENGTH) 2507 return NULL; 2508 2509 edid = kmemdup(edid, size, GFP_KERNEL); 2510 if (!edid) 2511 return NULL; 2512 2513 drm_edid = _drm_edid_alloc(edid, size); 2514 if (!drm_edid) 2515 kfree(edid); 2516 2517 return drm_edid; 2518 } 2519 EXPORT_SYMBOL(drm_edid_alloc); 2520 2521 /** 2522 * drm_edid_dup - Duplicate a drm_edid container 2523 * @drm_edid: EDID to duplicate 2524 * 2525 * The returned pointer must be freed using drm_edid_free(). 2526 * 2527 * Returns: drm_edid container copy, or NULL on errors 2528 */ 2529 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid) 2530 { 2531 if (!drm_edid) 2532 return NULL; 2533 2534 return drm_edid_alloc(drm_edid->edid, drm_edid->size); 2535 } 2536 EXPORT_SYMBOL(drm_edid_dup); 2537 2538 /** 2539 * drm_edid_free - Free the drm_edid container 2540 * @drm_edid: EDID to free 2541 */ 2542 void drm_edid_free(const struct drm_edid *drm_edid) 2543 { 2544 if (!drm_edid) 2545 return; 2546 2547 kfree(drm_edid->edid); 2548 kfree(drm_edid); 2549 } 2550 EXPORT_SYMBOL(drm_edid_free); 2551 2552 /** 2553 * drm_probe_ddc() - probe DDC presence 2554 * @adapter: I2C adapter to probe 2555 * 2556 * Return: True on success, false on failure. 2557 */ 2558 bool 2559 drm_probe_ddc(struct i2c_adapter *adapter) 2560 { 2561 unsigned char out; 2562 2563 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2564 } 2565 EXPORT_SYMBOL(drm_probe_ddc); 2566 2567 /** 2568 * drm_get_edid - get EDID data, if available 2569 * @connector: connector we're probing 2570 * @adapter: I2C adapter to use for DDC 2571 * 2572 * Poke the given I2C channel to grab EDID data if possible. If found, 2573 * attach it to the connector. 2574 * 2575 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2576 */ 2577 struct edid *drm_get_edid(struct drm_connector *connector, 2578 struct i2c_adapter *adapter) 2579 { 2580 struct edid *edid; 2581 2582 if (connector->force == DRM_FORCE_OFF) 2583 return NULL; 2584 2585 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2586 return NULL; 2587 2588 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL); 2589 drm_connector_update_edid_property(connector, edid); 2590 return edid; 2591 } 2592 EXPORT_SYMBOL(drm_get_edid); 2593 2594 /** 2595 * drm_edid_read_custom - Read EDID data using given EDID block read function 2596 * @connector: Connector to use 2597 * @read_block: EDID block read function 2598 * @context: Private data passed to the block read function 2599 * 2600 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2601 * exposes a different interface to read EDID blocks this function can be used 2602 * to get EDID data using a custom block read function. 2603 * 2604 * As in the general case the DDC bus is accessible by the kernel at the I2C 2605 * level, drivers must make all reasonable efforts to expose it as an I2C 2606 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing 2607 * this function. 2608 * 2609 * The EDID may be overridden using debugfs override_edid or firmware EDID 2610 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 2611 * order. Having either of them bypasses actual EDID reads. 2612 * 2613 * The returned pointer must be freed using drm_edid_free(). 2614 * 2615 * Return: Pointer to EDID, or NULL if probe/read failed. 2616 */ 2617 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector, 2618 read_block_fn read_block, 2619 void *context) 2620 { 2621 const struct drm_edid *drm_edid; 2622 struct edid *edid; 2623 size_t size = 0; 2624 2625 edid = _drm_do_get_edid(connector, read_block, context, &size); 2626 if (!edid) 2627 return NULL; 2628 2629 /* Sanity check for now */ 2630 drm_WARN_ON(connector->dev, !size); 2631 2632 drm_edid = _drm_edid_alloc(edid, size); 2633 if (!drm_edid) 2634 kfree(edid); 2635 2636 return drm_edid; 2637 } 2638 EXPORT_SYMBOL(drm_edid_read_custom); 2639 2640 /** 2641 * drm_edid_read_ddc - Read EDID data using given I2C adapter 2642 * @connector: Connector to use 2643 * @adapter: I2C adapter to use for DDC 2644 * 2645 * Read EDID using the given I2C adapter. 2646 * 2647 * The EDID may be overridden using debugfs override_edid or firmware EDID 2648 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 2649 * order. Having either of them bypasses actual EDID reads. 2650 * 2651 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and 2652 * using drm_edid_read() instead of this function. 2653 * 2654 * The returned pointer must be freed using drm_edid_free(). 2655 * 2656 * Return: Pointer to EDID, or NULL if probe/read failed. 2657 */ 2658 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector, 2659 struct i2c_adapter *adapter) 2660 { 2661 const struct drm_edid *drm_edid; 2662 2663 if (connector->force == DRM_FORCE_OFF) 2664 return NULL; 2665 2666 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2667 return NULL; 2668 2669 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter); 2670 2671 /* Note: Do *not* call connector updates here. */ 2672 2673 return drm_edid; 2674 } 2675 EXPORT_SYMBOL(drm_edid_read_ddc); 2676 2677 /** 2678 * drm_edid_read - Read EDID data using connector's I2C adapter 2679 * @connector: Connector to use 2680 * 2681 * Read EDID using the connector's I2C adapter. 2682 * 2683 * The EDID may be overridden using debugfs override_edid or firmware EDID 2684 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 2685 * order. Having either of them bypasses actual EDID reads. 2686 * 2687 * The returned pointer must be freed using drm_edid_free(). 2688 * 2689 * Return: Pointer to EDID, or NULL if probe/read failed. 2690 */ 2691 const struct drm_edid *drm_edid_read(struct drm_connector *connector) 2692 { 2693 if (drm_WARN_ON(connector->dev, !connector->ddc)) 2694 return NULL; 2695 2696 return drm_edid_read_ddc(connector, connector->ddc); 2697 } 2698 EXPORT_SYMBOL(drm_edid_read); 2699 2700 static u32 edid_extract_panel_id(const struct edid *edid) 2701 { 2702 /* 2703 * We represent the ID as a 32-bit number so it can easily be compared 2704 * with "==". 2705 * 2706 * NOTE that we deal with endianness differently for the top half 2707 * of this ID than for the bottom half. The bottom half (the product 2708 * id) gets decoded as little endian by the EDID_PRODUCT_ID because 2709 * that's how everyone seems to interpret it. The top half (the mfg_id) 2710 * gets stored as big endian because that makes 2711 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier 2712 * to write (it's easier to extract the ASCII). It doesn't really 2713 * matter, though, as long as the number here is unique. 2714 */ 2715 return (u32)edid->mfg_id[0] << 24 | 2716 (u32)edid->mfg_id[1] << 16 | 2717 (u32)EDID_PRODUCT_ID(edid); 2718 } 2719 2720 /** 2721 * drm_edid_get_panel_id - Get a panel's ID through DDC 2722 * @adapter: I2C adapter to use for DDC 2723 * 2724 * This function reads the first block of the EDID of a panel and (assuming 2725 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value 2726 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's 2727 * supposed to be different for each different modem of panel. 2728 * 2729 * This function is intended to be used during early probing on devices where 2730 * more than one panel might be present. Because of its intended use it must 2731 * assume that the EDID of the panel is correct, at least as far as the ID 2732 * is concerned (in other words, we don't process any overrides here). 2733 * 2734 * NOTE: it's expected that this function and drm_do_get_edid() will both 2735 * be read the EDID, but there is no caching between them. Since we're only 2736 * reading the first block, hopefully this extra overhead won't be too big. 2737 * 2738 * Return: A 32-bit ID that should be different for each make/model of panel. 2739 * See the functions drm_edid_encode_panel_id() and 2740 * drm_edid_decode_panel_id() for some details on the structure of this 2741 * ID. 2742 */ 2743 2744 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter) 2745 { 2746 enum edid_block_status status; 2747 void *base_block; 2748 u32 panel_id = 0; 2749 2750 /* 2751 * There are no manufacturer IDs of 0, so if there is a problem reading 2752 * the EDID then we'll just return 0. 2753 */ 2754 2755 base_block = kmalloc(EDID_LENGTH, GFP_KERNEL); 2756 if (!base_block) 2757 return 0; 2758 2759 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter); 2760 2761 edid_block_status_print(status, base_block, 0); 2762 2763 if (edid_block_status_valid(status, edid_block_tag(base_block))) 2764 panel_id = edid_extract_panel_id(base_block); 2765 2766 kfree(base_block); 2767 2768 return panel_id; 2769 } 2770 EXPORT_SYMBOL(drm_edid_get_panel_id); 2771 2772 /** 2773 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2774 * @connector: connector we're probing 2775 * @adapter: I2C adapter to use for DDC 2776 * 2777 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2778 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2779 * switch DDC to the GPU which is retrieving EDID. 2780 * 2781 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2782 */ 2783 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2784 struct i2c_adapter *adapter) 2785 { 2786 STUB(); 2787 return NULL; 2788 #ifdef notyet 2789 struct drm_device *dev = connector->dev; 2790 struct pci_dev *pdev = to_pci_dev(dev->dev); 2791 struct edid *edid; 2792 2793 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2794 return NULL; 2795 2796 vga_switcheroo_lock_ddc(pdev); 2797 edid = drm_get_edid(connector, adapter); 2798 vga_switcheroo_unlock_ddc(pdev); 2799 2800 return edid; 2801 #endif 2802 } 2803 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2804 2805 /** 2806 * drm_edid_duplicate - duplicate an EDID and the extensions 2807 * @edid: EDID to duplicate 2808 * 2809 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2810 */ 2811 struct edid *drm_edid_duplicate(const struct edid *edid) 2812 { 2813 return kmemdup(edid, edid_size(edid), GFP_KERNEL); 2814 } 2815 EXPORT_SYMBOL(drm_edid_duplicate); 2816 2817 /*** EDID parsing ***/ 2818 2819 /** 2820 * edid_get_quirks - return quirk flags for a given EDID 2821 * @drm_edid: EDID to process 2822 * 2823 * This tells subsequent routines what fixes they need to apply. 2824 */ 2825 static u32 edid_get_quirks(const struct drm_edid *drm_edid) 2826 { 2827 u32 panel_id = edid_extract_panel_id(drm_edid->edid); 2828 const struct edid_quirk *quirk; 2829 int i; 2830 2831 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2832 quirk = &edid_quirk_list[i]; 2833 if (quirk->panel_id == panel_id) 2834 return quirk->quirks; 2835 } 2836 2837 return 0; 2838 } 2839 2840 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2841 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2842 2843 /* 2844 * Walk the mode list for connector, clearing the preferred status on existing 2845 * modes and setting it anew for the right mode ala quirks. 2846 */ 2847 static void edid_fixup_preferred(struct drm_connector *connector, 2848 u32 quirks) 2849 { 2850 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2851 int target_refresh = 0; 2852 int cur_vrefresh, preferred_vrefresh; 2853 2854 if (list_empty(&connector->probed_modes)) 2855 return; 2856 2857 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 2858 target_refresh = 60; 2859 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 2860 target_refresh = 75; 2861 2862 preferred_mode = list_first_entry(&connector->probed_modes, 2863 struct drm_display_mode, head); 2864 2865 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 2866 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2867 2868 if (cur_mode == preferred_mode) 2869 continue; 2870 2871 /* Largest mode is preferred */ 2872 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 2873 preferred_mode = cur_mode; 2874 2875 cur_vrefresh = drm_mode_vrefresh(cur_mode); 2876 preferred_vrefresh = drm_mode_vrefresh(preferred_mode); 2877 /* At a given size, try to get closest to target refresh */ 2878 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2879 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2880 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2881 preferred_mode = cur_mode; 2882 } 2883 } 2884 2885 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 2886 } 2887 2888 static bool 2889 mode_is_rb(const struct drm_display_mode *mode) 2890 { 2891 return (mode->htotal - mode->hdisplay == 160) && 2892 (mode->hsync_end - mode->hdisplay == 80) && 2893 (mode->hsync_end - mode->hsync_start == 32) && 2894 (mode->vsync_start - mode->vdisplay == 3); 2895 } 2896 2897 /* 2898 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 2899 * @dev: Device to duplicate against 2900 * @hsize: Mode width 2901 * @vsize: Mode height 2902 * @fresh: Mode refresh rate 2903 * @rb: Mode reduced-blanking-ness 2904 * 2905 * Walk the DMT mode list looking for a match for the given parameters. 2906 * 2907 * Return: A newly allocated copy of the mode, or NULL if not found. 2908 */ 2909 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 2910 int hsize, int vsize, int fresh, 2911 bool rb) 2912 { 2913 int i; 2914 2915 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2916 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 2917 2918 if (hsize != ptr->hdisplay) 2919 continue; 2920 if (vsize != ptr->vdisplay) 2921 continue; 2922 if (fresh != drm_mode_vrefresh(ptr)) 2923 continue; 2924 if (rb != mode_is_rb(ptr)) 2925 continue; 2926 2927 return drm_mode_duplicate(dev, ptr); 2928 } 2929 2930 return NULL; 2931 } 2932 EXPORT_SYMBOL(drm_mode_find_dmt); 2933 2934 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type) 2935 { 2936 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 2937 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2); 2938 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3); 2939 2940 return descriptor->pixel_clock == 0 && 2941 descriptor->data.other_data.pad1 == 0 && 2942 descriptor->data.other_data.type == type; 2943 } 2944 2945 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor) 2946 { 2947 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 2948 2949 return descriptor->pixel_clock != 0; 2950 } 2951 2952 typedef void detailed_cb(const struct detailed_timing *timing, void *closure); 2953 2954 static void 2955 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 2956 { 2957 int i, n; 2958 u8 d = ext[0x02]; 2959 const u8 *det_base = ext + d; 2960 2961 if (d < 4 || d > 127) 2962 return; 2963 2964 n = (127 - d) / 18; 2965 for (i = 0; i < n; i++) 2966 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 2967 } 2968 2969 static void 2970 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 2971 { 2972 unsigned int i, n = min((int)ext[0x02], 6); 2973 const u8 *det_base = ext + 5; 2974 2975 if (ext[0x01] != 1) 2976 return; /* unknown version */ 2977 2978 for (i = 0; i < n; i++) 2979 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 2980 } 2981 2982 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid, 2983 detailed_cb *cb, void *closure) 2984 { 2985 struct drm_edid_iter edid_iter; 2986 const u8 *ext; 2987 int i; 2988 2989 if (!drm_edid) 2990 return; 2991 2992 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 2993 cb(&drm_edid->edid->detailed_timings[i], closure); 2994 2995 drm_edid_iter_begin(drm_edid, &edid_iter); 2996 drm_edid_iter_for_each(ext, &edid_iter) { 2997 switch (*ext) { 2998 case CEA_EXT: 2999 cea_for_each_detailed_block(ext, cb, closure); 3000 break; 3001 case VTB_EXT: 3002 vtb_for_each_detailed_block(ext, cb, closure); 3003 break; 3004 default: 3005 break; 3006 } 3007 } 3008 drm_edid_iter_end(&edid_iter); 3009 } 3010 3011 static void 3012 is_rb(const struct detailed_timing *descriptor, void *data) 3013 { 3014 bool *res = data; 3015 3016 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3017 return; 3018 3019 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3020 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15); 3021 3022 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG && 3023 descriptor->data.other_data.data.range.formula.cvt.flags & 0x10) 3024 *res = true; 3025 } 3026 3027 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 3028 static bool 3029 drm_monitor_supports_rb(const struct drm_edid *drm_edid) 3030 { 3031 if (drm_edid->edid->revision >= 4) { 3032 bool ret = false; 3033 3034 drm_for_each_detailed_block(drm_edid, is_rb, &ret); 3035 return ret; 3036 } 3037 3038 return ((drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 3039 } 3040 3041 static void 3042 find_gtf2(const struct detailed_timing *descriptor, void *data) 3043 { 3044 const struct detailed_timing **res = data; 3045 3046 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3047 return; 3048 3049 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3050 3051 if (descriptor->data.other_data.data.range.flags == 0x02) 3052 *res = descriptor; 3053 } 3054 3055 /* Secondary GTF curve kicks in above some break frequency */ 3056 static int 3057 drm_gtf2_hbreak(const struct drm_edid *drm_edid) 3058 { 3059 const struct detailed_timing *descriptor = NULL; 3060 3061 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3062 3063 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12); 3064 3065 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0; 3066 } 3067 3068 static int 3069 drm_gtf2_2c(const struct drm_edid *drm_edid) 3070 { 3071 const struct detailed_timing *descriptor = NULL; 3072 3073 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3074 3075 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13); 3076 3077 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0; 3078 } 3079 3080 static int 3081 drm_gtf2_m(const struct drm_edid *drm_edid) 3082 { 3083 const struct detailed_timing *descriptor = NULL; 3084 3085 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3086 3087 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14); 3088 3089 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0; 3090 } 3091 3092 static int 3093 drm_gtf2_k(const struct drm_edid *drm_edid) 3094 { 3095 const struct detailed_timing *descriptor = NULL; 3096 3097 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3098 3099 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16); 3100 3101 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0; 3102 } 3103 3104 static int 3105 drm_gtf2_2j(const struct drm_edid *drm_edid) 3106 { 3107 const struct detailed_timing *descriptor = NULL; 3108 3109 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3110 3111 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17); 3112 3113 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0; 3114 } 3115 3116 /* Get standard timing level (CVT/GTF/DMT). */ 3117 static int standard_timing_level(const struct drm_edid *drm_edid) 3118 { 3119 const struct edid *edid = drm_edid->edid; 3120 3121 if (edid->revision >= 2) { 3122 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 3123 return LEVEL_CVT; 3124 if (drm_gtf2_hbreak(drm_edid)) 3125 return LEVEL_GTF2; 3126 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 3127 return LEVEL_GTF; 3128 } 3129 return LEVEL_DMT; 3130 } 3131 3132 /* 3133 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 3134 * monitors fill with ascii space (0x20) instead. 3135 */ 3136 static int 3137 bad_std_timing(u8 a, u8 b) 3138 { 3139 return (a == 0x00 && b == 0x00) || 3140 (a == 0x01 && b == 0x01) || 3141 (a == 0x20 && b == 0x20); 3142 } 3143 3144 static int drm_mode_hsync(const struct drm_display_mode *mode) 3145 { 3146 if (mode->htotal <= 0) 3147 return 0; 3148 3149 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 3150 } 3151 3152 /* 3153 * Take the standard timing params (in this case width, aspect, and refresh) 3154 * and convert them into a real mode using CVT/GTF/DMT. 3155 */ 3156 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector, 3157 const struct drm_edid *drm_edid, 3158 const struct std_timing *t) 3159 { 3160 struct drm_device *dev = connector->dev; 3161 struct drm_display_mode *m, *mode = NULL; 3162 int hsize, vsize; 3163 int vrefresh_rate; 3164 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 3165 >> EDID_TIMING_ASPECT_SHIFT; 3166 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 3167 >> EDID_TIMING_VFREQ_SHIFT; 3168 int timing_level = standard_timing_level(drm_edid); 3169 3170 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 3171 return NULL; 3172 3173 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 3174 hsize = t->hsize * 8 + 248; 3175 /* vrefresh_rate = vfreq + 60 */ 3176 vrefresh_rate = vfreq + 60; 3177 /* the vdisplay is calculated based on the aspect ratio */ 3178 if (aspect_ratio == 0) { 3179 if (drm_edid->edid->revision < 3) 3180 vsize = hsize; 3181 else 3182 vsize = (hsize * 10) / 16; 3183 } else if (aspect_ratio == 1) 3184 vsize = (hsize * 3) / 4; 3185 else if (aspect_ratio == 2) 3186 vsize = (hsize * 4) / 5; 3187 else 3188 vsize = (hsize * 9) / 16; 3189 3190 /* HDTV hack, part 1 */ 3191 if (vrefresh_rate == 60 && 3192 ((hsize == 1360 && vsize == 765) || 3193 (hsize == 1368 && vsize == 769))) { 3194 hsize = 1366; 3195 vsize = 768; 3196 } 3197 3198 /* 3199 * If this connector already has a mode for this size and refresh 3200 * rate (because it came from detailed or CVT info), use that 3201 * instead. This way we don't have to guess at interlace or 3202 * reduced blanking. 3203 */ 3204 list_for_each_entry(m, &connector->probed_modes, head) 3205 if (m->hdisplay == hsize && m->vdisplay == vsize && 3206 drm_mode_vrefresh(m) == vrefresh_rate) 3207 return NULL; 3208 3209 /* HDTV hack, part 2 */ 3210 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 3211 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 3212 false); 3213 if (!mode) 3214 return NULL; 3215 mode->hdisplay = 1366; 3216 mode->hsync_start = mode->hsync_start - 1; 3217 mode->hsync_end = mode->hsync_end - 1; 3218 return mode; 3219 } 3220 3221 /* check whether it can be found in default mode table */ 3222 if (drm_monitor_supports_rb(drm_edid)) { 3223 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 3224 true); 3225 if (mode) 3226 return mode; 3227 } 3228 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 3229 if (mode) 3230 return mode; 3231 3232 /* okay, generate it */ 3233 switch (timing_level) { 3234 case LEVEL_DMT: 3235 break; 3236 case LEVEL_GTF: 3237 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3238 break; 3239 case LEVEL_GTF2: 3240 /* 3241 * This is potentially wrong if there's ever a monitor with 3242 * more than one ranges section, each claiming a different 3243 * secondary GTF curve. Please don't do that. 3244 */ 3245 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3246 if (!mode) 3247 return NULL; 3248 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) { 3249 drm_mode_destroy(dev, mode); 3250 mode = drm_gtf_mode_complex(dev, hsize, vsize, 3251 vrefresh_rate, 0, 0, 3252 drm_gtf2_m(drm_edid), 3253 drm_gtf2_2c(drm_edid), 3254 drm_gtf2_k(drm_edid), 3255 drm_gtf2_2j(drm_edid)); 3256 } 3257 break; 3258 case LEVEL_CVT: 3259 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 3260 false); 3261 break; 3262 } 3263 return mode; 3264 } 3265 3266 /* 3267 * EDID is delightfully ambiguous about how interlaced modes are to be 3268 * encoded. Our internal representation is of frame height, but some 3269 * HDTV detailed timings are encoded as field height. 3270 * 3271 * The format list here is from CEA, in frame size. Technically we 3272 * should be checking refresh rate too. Whatever. 3273 */ 3274 static void 3275 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 3276 const struct detailed_pixel_timing *pt) 3277 { 3278 int i; 3279 static const struct { 3280 int w, h; 3281 } cea_interlaced[] = { 3282 { 1920, 1080 }, 3283 { 720, 480 }, 3284 { 1440, 480 }, 3285 { 2880, 480 }, 3286 { 720, 576 }, 3287 { 1440, 576 }, 3288 { 2880, 576 }, 3289 }; 3290 3291 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 3292 return; 3293 3294 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 3295 if ((mode->hdisplay == cea_interlaced[i].w) && 3296 (mode->vdisplay == cea_interlaced[i].h / 2)) { 3297 mode->vdisplay *= 2; 3298 mode->vsync_start *= 2; 3299 mode->vsync_end *= 2; 3300 mode->vtotal *= 2; 3301 mode->vtotal |= 1; 3302 } 3303 } 3304 3305 mode->flags |= DRM_MODE_FLAG_INTERLACE; 3306 } 3307 3308 /* 3309 * Create a new mode from an EDID detailed timing section. An EDID detailed 3310 * timing block contains enough info for us to create and return a new struct 3311 * drm_display_mode. 3312 */ 3313 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 3314 const struct drm_edid *drm_edid, 3315 const struct detailed_timing *timing, 3316 u32 quirks) 3317 { 3318 struct drm_display_mode *mode; 3319 const struct detailed_pixel_timing *pt = &timing->data.pixel_data; 3320 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 3321 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 3322 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 3323 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 3324 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 3325 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 3326 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 3327 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 3328 3329 /* ignore tiny modes */ 3330 if (hactive < 64 || vactive < 64) 3331 return NULL; 3332 3333 if (pt->misc & DRM_EDID_PT_STEREO) { 3334 DRM_DEBUG_KMS("stereo mode not supported\n"); 3335 return NULL; 3336 } 3337 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 3338 DRM_DEBUG_KMS("composite sync not supported\n"); 3339 } 3340 3341 /* it is incorrect if hsync/vsync width is zero */ 3342 if (!hsync_pulse_width || !vsync_pulse_width) { 3343 DRM_DEBUG_KMS("Incorrect Detailed timing. " 3344 "Wrong Hsync/Vsync pulse width\n"); 3345 return NULL; 3346 } 3347 3348 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 3349 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 3350 if (!mode) 3351 return NULL; 3352 3353 goto set_size; 3354 } 3355 3356 mode = drm_mode_create(dev); 3357 if (!mode) 3358 return NULL; 3359 3360 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 3361 mode->clock = 1088 * 10; 3362 else 3363 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 3364 3365 mode->hdisplay = hactive; 3366 mode->hsync_start = mode->hdisplay + hsync_offset; 3367 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 3368 mode->htotal = mode->hdisplay + hblank; 3369 3370 mode->vdisplay = vactive; 3371 mode->vsync_start = mode->vdisplay + vsync_offset; 3372 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 3373 mode->vtotal = mode->vdisplay + vblank; 3374 3375 /* Some EDIDs have bogus h/vtotal values */ 3376 if (mode->hsync_end > mode->htotal) 3377 mode->htotal = mode->hsync_end + 1; 3378 if (mode->vsync_end > mode->vtotal) 3379 mode->vtotal = mode->vsync_end + 1; 3380 3381 drm_mode_do_interlace_quirk(mode, pt); 3382 3383 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 3384 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC; 3385 } else { 3386 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3387 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3388 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3389 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3390 } 3391 3392 set_size: 3393 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 3394 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 3395 3396 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 3397 mode->width_mm *= 10; 3398 mode->height_mm *= 10; 3399 } 3400 3401 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 3402 mode->width_mm = drm_edid->edid->width_cm * 10; 3403 mode->height_mm = drm_edid->edid->height_cm * 10; 3404 } 3405 3406 mode->type = DRM_MODE_TYPE_DRIVER; 3407 drm_mode_set_name(mode); 3408 3409 return mode; 3410 } 3411 3412 static bool 3413 mode_in_hsync_range(const struct drm_display_mode *mode, 3414 const struct edid *edid, const u8 *t) 3415 { 3416 int hsync, hmin, hmax; 3417 3418 hmin = t[7]; 3419 if (edid->revision >= 4) 3420 hmin += ((t[4] & 0x04) ? 255 : 0); 3421 hmax = t[8]; 3422 if (edid->revision >= 4) 3423 hmax += ((t[4] & 0x08) ? 255 : 0); 3424 hsync = drm_mode_hsync(mode); 3425 3426 return (hsync <= hmax && hsync >= hmin); 3427 } 3428 3429 static bool 3430 mode_in_vsync_range(const struct drm_display_mode *mode, 3431 const struct edid *edid, const u8 *t) 3432 { 3433 int vsync, vmin, vmax; 3434 3435 vmin = t[5]; 3436 if (edid->revision >= 4) 3437 vmin += ((t[4] & 0x01) ? 255 : 0); 3438 vmax = t[6]; 3439 if (edid->revision >= 4) 3440 vmax += ((t[4] & 0x02) ? 255 : 0); 3441 vsync = drm_mode_vrefresh(mode); 3442 3443 return (vsync <= vmax && vsync >= vmin); 3444 } 3445 3446 static u32 3447 range_pixel_clock(const struct edid *edid, const u8 *t) 3448 { 3449 /* unspecified */ 3450 if (t[9] == 0 || t[9] == 255) 3451 return 0; 3452 3453 /* 1.4 with CVT support gives us real precision, yay */ 3454 if (edid->revision >= 4 && t[10] == 0x04) 3455 return (t[9] * 10000) - ((t[12] >> 2) * 250); 3456 3457 /* 1.3 is pathetic, so fuzz up a bit */ 3458 return t[9] * 10000 + 5001; 3459 } 3460 3461 static bool mode_in_range(const struct drm_display_mode *mode, 3462 const struct drm_edid *drm_edid, 3463 const struct detailed_timing *timing) 3464 { 3465 const struct edid *edid = drm_edid->edid; 3466 u32 max_clock; 3467 const u8 *t = (const u8 *)timing; 3468 3469 if (!mode_in_hsync_range(mode, edid, t)) 3470 return false; 3471 3472 if (!mode_in_vsync_range(mode, edid, t)) 3473 return false; 3474 3475 if ((max_clock = range_pixel_clock(edid, t))) 3476 if (mode->clock > max_clock) 3477 return false; 3478 3479 /* 1.4 max horizontal check */ 3480 if (edid->revision >= 4 && t[10] == 0x04) 3481 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 3482 return false; 3483 3484 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid)) 3485 return false; 3486 3487 return true; 3488 } 3489 3490 static bool valid_inferred_mode(const struct drm_connector *connector, 3491 const struct drm_display_mode *mode) 3492 { 3493 const struct drm_display_mode *m; 3494 bool ok = false; 3495 3496 list_for_each_entry(m, &connector->probed_modes, head) { 3497 if (mode->hdisplay == m->hdisplay && 3498 mode->vdisplay == m->vdisplay && 3499 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 3500 return false; /* duplicated */ 3501 if (mode->hdisplay <= m->hdisplay && 3502 mode->vdisplay <= m->vdisplay) 3503 ok = true; 3504 } 3505 return ok; 3506 } 3507 3508 static int drm_dmt_modes_for_range(struct drm_connector *connector, 3509 const struct drm_edid *drm_edid, 3510 const struct detailed_timing *timing) 3511 { 3512 int i, modes = 0; 3513 struct drm_display_mode *newmode; 3514 struct drm_device *dev = connector->dev; 3515 3516 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3517 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) && 3518 valid_inferred_mode(connector, drm_dmt_modes + i)) { 3519 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 3520 if (newmode) { 3521 drm_mode_probed_add(connector, newmode); 3522 modes++; 3523 } 3524 } 3525 } 3526 3527 return modes; 3528 } 3529 3530 /* fix up 1366x768 mode from 1368x768; 3531 * GFT/CVT can't express 1366 width which isn't dividable by 8 3532 */ 3533 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 3534 { 3535 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 3536 mode->hdisplay = 1366; 3537 mode->hsync_start--; 3538 mode->hsync_end--; 3539 drm_mode_set_name(mode); 3540 } 3541 } 3542 3543 static int drm_gtf_modes_for_range(struct drm_connector *connector, 3544 const struct drm_edid *drm_edid, 3545 const struct detailed_timing *timing) 3546 { 3547 int i, modes = 0; 3548 struct drm_display_mode *newmode; 3549 struct drm_device *dev = connector->dev; 3550 3551 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3552 const struct minimode *m = &extra_modes[i]; 3553 3554 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 3555 if (!newmode) 3556 return modes; 3557 3558 drm_mode_fixup_1366x768(newmode); 3559 if (!mode_in_range(newmode, drm_edid, timing) || 3560 !valid_inferred_mode(connector, newmode)) { 3561 drm_mode_destroy(dev, newmode); 3562 continue; 3563 } 3564 3565 drm_mode_probed_add(connector, newmode); 3566 modes++; 3567 } 3568 3569 return modes; 3570 } 3571 3572 static int drm_cvt_modes_for_range(struct drm_connector *connector, 3573 const struct drm_edid *drm_edid, 3574 const struct detailed_timing *timing) 3575 { 3576 int i, modes = 0; 3577 struct drm_display_mode *newmode; 3578 struct drm_device *dev = connector->dev; 3579 bool rb = drm_monitor_supports_rb(drm_edid); 3580 3581 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3582 const struct minimode *m = &extra_modes[i]; 3583 3584 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 3585 if (!newmode) 3586 return modes; 3587 3588 drm_mode_fixup_1366x768(newmode); 3589 if (!mode_in_range(newmode, drm_edid, timing) || 3590 !valid_inferred_mode(connector, newmode)) { 3591 drm_mode_destroy(dev, newmode); 3592 continue; 3593 } 3594 3595 drm_mode_probed_add(connector, newmode); 3596 modes++; 3597 } 3598 3599 return modes; 3600 } 3601 3602 static void 3603 do_inferred_modes(const struct detailed_timing *timing, void *c) 3604 { 3605 struct detailed_mode_closure *closure = c; 3606 const struct detailed_non_pixel *data = &timing->data.other_data; 3607 const struct detailed_data_monitor_range *range = &data->data.range; 3608 3609 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 3610 return; 3611 3612 closure->modes += drm_dmt_modes_for_range(closure->connector, 3613 closure->drm_edid, 3614 timing); 3615 3616 if (!version_greater(closure->drm_edid, 1, 1)) 3617 return; /* GTF not defined yet */ 3618 3619 switch (range->flags) { 3620 case 0x02: /* secondary gtf, XXX could do more */ 3621 case 0x00: /* default gtf */ 3622 closure->modes += drm_gtf_modes_for_range(closure->connector, 3623 closure->drm_edid, 3624 timing); 3625 break; 3626 case 0x04: /* cvt, only in 1.4+ */ 3627 if (!version_greater(closure->drm_edid, 1, 3)) 3628 break; 3629 3630 closure->modes += drm_cvt_modes_for_range(closure->connector, 3631 closure->drm_edid, 3632 timing); 3633 break; 3634 case 0x01: /* just the ranges, no formula */ 3635 default: 3636 break; 3637 } 3638 } 3639 3640 static int add_inferred_modes(struct drm_connector *connector, 3641 const struct drm_edid *drm_edid) 3642 { 3643 struct detailed_mode_closure closure = { 3644 .connector = connector, 3645 .drm_edid = drm_edid, 3646 }; 3647 3648 if (version_greater(drm_edid, 1, 0)) 3649 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure); 3650 3651 return closure.modes; 3652 } 3653 3654 static int 3655 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing) 3656 { 3657 int i, j, m, modes = 0; 3658 struct drm_display_mode *mode; 3659 const u8 *est = ((const u8 *)timing) + 6; 3660 3661 for (i = 0; i < 6; i++) { 3662 for (j = 7; j >= 0; j--) { 3663 m = (i * 8) + (7 - j); 3664 if (m >= ARRAY_SIZE(est3_modes)) 3665 break; 3666 if (est[i] & (1 << j)) { 3667 mode = drm_mode_find_dmt(connector->dev, 3668 est3_modes[m].w, 3669 est3_modes[m].h, 3670 est3_modes[m].r, 3671 est3_modes[m].rb); 3672 if (mode) { 3673 drm_mode_probed_add(connector, mode); 3674 modes++; 3675 } 3676 } 3677 } 3678 } 3679 3680 return modes; 3681 } 3682 3683 static void 3684 do_established_modes(const struct detailed_timing *timing, void *c) 3685 { 3686 struct detailed_mode_closure *closure = c; 3687 3688 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS)) 3689 return; 3690 3691 closure->modes += drm_est3_modes(closure->connector, timing); 3692 } 3693 3694 /* 3695 * Get established modes from EDID and add them. Each EDID block contains a 3696 * bitmap of the supported "established modes" list (defined above). Tease them 3697 * out and add them to the global modes list. 3698 */ 3699 static int add_established_modes(struct drm_connector *connector, 3700 const struct drm_edid *drm_edid) 3701 { 3702 struct drm_device *dev = connector->dev; 3703 const struct edid *edid = drm_edid->edid; 3704 unsigned long est_bits = edid->established_timings.t1 | 3705 (edid->established_timings.t2 << 8) | 3706 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 3707 int i, modes = 0; 3708 struct detailed_mode_closure closure = { 3709 .connector = connector, 3710 .drm_edid = drm_edid, 3711 }; 3712 3713 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 3714 if (est_bits & (1<<i)) { 3715 struct drm_display_mode *newmode; 3716 3717 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 3718 if (newmode) { 3719 drm_mode_probed_add(connector, newmode); 3720 modes++; 3721 } 3722 } 3723 } 3724 3725 if (version_greater(drm_edid, 1, 0)) 3726 drm_for_each_detailed_block(drm_edid, do_established_modes, 3727 &closure); 3728 3729 return modes + closure.modes; 3730 } 3731 3732 static void 3733 do_standard_modes(const struct detailed_timing *timing, void *c) 3734 { 3735 struct detailed_mode_closure *closure = c; 3736 const struct detailed_non_pixel *data = &timing->data.other_data; 3737 struct drm_connector *connector = closure->connector; 3738 int i; 3739 3740 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES)) 3741 return; 3742 3743 for (i = 0; i < 6; i++) { 3744 const struct std_timing *std = &data->data.timings[i]; 3745 struct drm_display_mode *newmode; 3746 3747 newmode = drm_mode_std(connector, closure->drm_edid, std); 3748 if (newmode) { 3749 drm_mode_probed_add(connector, newmode); 3750 closure->modes++; 3751 } 3752 } 3753 } 3754 3755 /* 3756 * Get standard modes from EDID and add them. Standard modes can be calculated 3757 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and 3758 * add them to the list. 3759 */ 3760 static int add_standard_modes(struct drm_connector *connector, 3761 const struct drm_edid *drm_edid) 3762 { 3763 int i, modes = 0; 3764 struct detailed_mode_closure closure = { 3765 .connector = connector, 3766 .drm_edid = drm_edid, 3767 }; 3768 3769 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3770 struct drm_display_mode *newmode; 3771 3772 newmode = drm_mode_std(connector, drm_edid, 3773 &drm_edid->edid->standard_timings[i]); 3774 if (newmode) { 3775 drm_mode_probed_add(connector, newmode); 3776 modes++; 3777 } 3778 } 3779 3780 if (version_greater(drm_edid, 1, 0)) 3781 drm_for_each_detailed_block(drm_edid, do_standard_modes, 3782 &closure); 3783 3784 /* XXX should also look for standard codes in VTB blocks */ 3785 3786 return modes + closure.modes; 3787 } 3788 3789 static int drm_cvt_modes(struct drm_connector *connector, 3790 const struct detailed_timing *timing) 3791 { 3792 int i, j, modes = 0; 3793 struct drm_display_mode *newmode; 3794 struct drm_device *dev = connector->dev; 3795 const struct cvt_timing *cvt; 3796 const int rates[] = { 60, 85, 75, 60, 50 }; 3797 const u8 empty[3] = { 0, 0, 0 }; 3798 3799 for (i = 0; i < 4; i++) { 3800 int width, height; 3801 3802 cvt = &(timing->data.other_data.data.cvt[i]); 3803 3804 if (!memcmp(cvt->code, empty, 3)) 3805 continue; 3806 3807 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3808 switch (cvt->code[1] & 0x0c) { 3809 /* default - because compiler doesn't see that we've enumerated all cases */ 3810 default: 3811 case 0x00: 3812 width = height * 4 / 3; 3813 break; 3814 case 0x04: 3815 width = height * 16 / 9; 3816 break; 3817 case 0x08: 3818 width = height * 16 / 10; 3819 break; 3820 case 0x0c: 3821 width = height * 15 / 9; 3822 break; 3823 } 3824 3825 for (j = 1; j < 5; j++) { 3826 if (cvt->code[2] & (1 << j)) { 3827 newmode = drm_cvt_mode(dev, width, height, 3828 rates[j], j == 0, 3829 false, false); 3830 if (newmode) { 3831 drm_mode_probed_add(connector, newmode); 3832 modes++; 3833 } 3834 } 3835 } 3836 } 3837 3838 return modes; 3839 } 3840 3841 static void 3842 do_cvt_mode(const struct detailed_timing *timing, void *c) 3843 { 3844 struct detailed_mode_closure *closure = c; 3845 3846 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE)) 3847 return; 3848 3849 closure->modes += drm_cvt_modes(closure->connector, timing); 3850 } 3851 3852 static int 3853 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid) 3854 { 3855 struct detailed_mode_closure closure = { 3856 .connector = connector, 3857 .drm_edid = drm_edid, 3858 }; 3859 3860 if (version_greater(drm_edid, 1, 2)) 3861 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure); 3862 3863 /* XXX should also look for CVT codes in VTB blocks */ 3864 3865 return closure.modes; 3866 } 3867 3868 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 3869 3870 static void 3871 do_detailed_mode(const struct detailed_timing *timing, void *c) 3872 { 3873 struct detailed_mode_closure *closure = c; 3874 struct drm_display_mode *newmode; 3875 3876 if (!is_detailed_timing_descriptor(timing)) 3877 return; 3878 3879 newmode = drm_mode_detailed(closure->connector->dev, 3880 closure->drm_edid, timing, 3881 closure->quirks); 3882 if (!newmode) 3883 return; 3884 3885 if (closure->preferred) 3886 newmode->type |= DRM_MODE_TYPE_PREFERRED; 3887 3888 /* 3889 * Detailed modes are limited to 10kHz pixel clock resolution, 3890 * so fix up anything that looks like CEA/HDMI mode, but the clock 3891 * is just slightly off. 3892 */ 3893 fixup_detailed_cea_mode_clock(newmode); 3894 3895 drm_mode_probed_add(closure->connector, newmode); 3896 closure->modes++; 3897 closure->preferred = false; 3898 } 3899 3900 /* 3901 * add_detailed_modes - Add modes from detailed timings 3902 * @connector: attached connector 3903 * @drm_edid: EDID block to scan 3904 * @quirks: quirks to apply 3905 */ 3906 static int add_detailed_modes(struct drm_connector *connector, 3907 const struct drm_edid *drm_edid, u32 quirks) 3908 { 3909 struct detailed_mode_closure closure = { 3910 .connector = connector, 3911 .drm_edid = drm_edid, 3912 .preferred = true, 3913 .quirks = quirks, 3914 }; 3915 3916 if (closure.preferred && !version_greater(drm_edid, 1, 3)) 3917 closure.preferred = 3918 (drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 3919 3920 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure); 3921 3922 return closure.modes; 3923 } 3924 3925 /* CTA-861-H Table 60 - CTA Tag Codes */ 3926 #define CTA_DB_AUDIO 1 3927 #define CTA_DB_VIDEO 2 3928 #define CTA_DB_VENDOR 3 3929 #define CTA_DB_SPEAKER 4 3930 #define CTA_DB_EXTENDED_TAG 7 3931 3932 /* CTA-861-H Table 62 - CTA Extended Tag Codes */ 3933 #define CTA_EXT_DB_VIDEO_CAP 0 3934 #define CTA_EXT_DB_VENDOR 1 3935 #define CTA_EXT_DB_HDR_STATIC_METADATA 6 3936 #define CTA_EXT_DB_420_VIDEO_DATA 14 3937 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15 3938 #define CTA_EXT_DB_HF_EEODB 0x78 3939 #define CTA_EXT_DB_HF_SCDB 0x79 3940 3941 #define EDID_BASIC_AUDIO (1 << 6) 3942 #define EDID_CEA_YCRCB444 (1 << 5) 3943 #define EDID_CEA_YCRCB422 (1 << 4) 3944 #define EDID_CEA_VCDB_QS (1 << 6) 3945 3946 /* 3947 * Search EDID for CEA extension block. 3948 * 3949 * FIXME: Prefer not returning pointers to raw EDID data. 3950 */ 3951 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid, 3952 int ext_id, int *ext_index) 3953 { 3954 const u8 *edid_ext = NULL; 3955 int i; 3956 3957 /* No EDID or EDID extensions */ 3958 if (!drm_edid || !drm_edid_extension_block_count(drm_edid)) 3959 return NULL; 3960 3961 /* Find CEA extension */ 3962 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) { 3963 edid_ext = drm_edid_extension_block_data(drm_edid, i); 3964 if (edid_block_tag(edid_ext) == ext_id) 3965 break; 3966 } 3967 3968 if (i >= drm_edid_extension_block_count(drm_edid)) 3969 return NULL; 3970 3971 *ext_index = i + 1; 3972 3973 return edid_ext; 3974 } 3975 3976 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */ 3977 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid) 3978 { 3979 const struct displayid_block *block; 3980 struct displayid_iter iter; 3981 int ext_index = 0; 3982 bool found = false; 3983 3984 /* Look for a top level CEA extension block */ 3985 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index)) 3986 return true; 3987 3988 /* CEA blocks can also be found embedded in a DisplayID block */ 3989 displayid_iter_edid_begin(drm_edid, &iter); 3990 displayid_iter_for_each(block, &iter) { 3991 if (block->tag == DATA_BLOCK_CTA) { 3992 found = true; 3993 break; 3994 } 3995 } 3996 displayid_iter_end(&iter); 3997 3998 return found; 3999 } 4000 4001 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 4002 { 4003 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 4004 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 4005 4006 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 4007 return &edid_cea_modes_1[vic - 1]; 4008 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 4009 return &edid_cea_modes_193[vic - 193]; 4010 return NULL; 4011 } 4012 4013 static u8 cea_num_vics(void) 4014 { 4015 return 193 + ARRAY_SIZE(edid_cea_modes_193); 4016 } 4017 4018 static u8 cea_next_vic(u8 vic) 4019 { 4020 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 4021 vic = 193; 4022 return vic; 4023 } 4024 4025 /* 4026 * Calculate the alternate clock for the CEA mode 4027 * (60Hz vs. 59.94Hz etc.) 4028 */ 4029 static unsigned int 4030 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 4031 { 4032 unsigned int clock = cea_mode->clock; 4033 4034 if (drm_mode_vrefresh(cea_mode) % 6 != 0) 4035 return clock; 4036 4037 /* 4038 * edid_cea_modes contains the 59.94Hz 4039 * variant for 240 and 480 line modes, 4040 * and the 60Hz variant otherwise. 4041 */ 4042 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 4043 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 4044 else 4045 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 4046 4047 return clock; 4048 } 4049 4050 static bool 4051 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 4052 { 4053 /* 4054 * For certain VICs the spec allows the vertical 4055 * front porch to vary by one or two lines. 4056 * 4057 * cea_modes[] stores the variant with the shortest 4058 * vertical front porch. We can adjust the mode to 4059 * get the other variants by simply increasing the 4060 * vertical front porch length. 4061 */ 4062 #ifdef notyet 4063 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 4064 cea_mode_for_vic(9)->vtotal != 262 || 4065 cea_mode_for_vic(12)->vtotal != 262 || 4066 cea_mode_for_vic(13)->vtotal != 262 || 4067 cea_mode_for_vic(23)->vtotal != 312 || 4068 cea_mode_for_vic(24)->vtotal != 312 || 4069 cea_mode_for_vic(27)->vtotal != 312 || 4070 cea_mode_for_vic(28)->vtotal != 312); 4071 #endif 4072 4073 if (((vic == 8 || vic == 9 || 4074 vic == 12 || vic == 13) && mode->vtotal < 263) || 4075 ((vic == 23 || vic == 24 || 4076 vic == 27 || vic == 28) && mode->vtotal < 314)) { 4077 mode->vsync_start++; 4078 mode->vsync_end++; 4079 mode->vtotal++; 4080 4081 return true; 4082 } 4083 4084 return false; 4085 } 4086 4087 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 4088 unsigned int clock_tolerance) 4089 { 4090 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4091 u8 vic; 4092 4093 if (!to_match->clock) 4094 return 0; 4095 4096 if (to_match->picture_aspect_ratio) 4097 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4098 4099 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4100 struct drm_display_mode cea_mode; 4101 unsigned int clock1, clock2; 4102 4103 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4104 4105 /* Check both 60Hz and 59.94Hz */ 4106 clock1 = cea_mode.clock; 4107 clock2 = cea_mode_alternate_clock(&cea_mode); 4108 4109 if (abs(to_match->clock - clock1) > clock_tolerance && 4110 abs(to_match->clock - clock2) > clock_tolerance) 4111 continue; 4112 4113 do { 4114 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4115 return vic; 4116 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4117 } 4118 4119 return 0; 4120 } 4121 4122 /** 4123 * drm_match_cea_mode - look for a CEA mode matching given mode 4124 * @to_match: display mode 4125 * 4126 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 4127 * mode. 4128 */ 4129 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 4130 { 4131 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4132 u8 vic; 4133 4134 if (!to_match->clock) 4135 return 0; 4136 4137 if (to_match->picture_aspect_ratio) 4138 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4139 4140 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4141 struct drm_display_mode cea_mode; 4142 unsigned int clock1, clock2; 4143 4144 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4145 4146 /* Check both 60Hz and 59.94Hz */ 4147 clock1 = cea_mode.clock; 4148 clock2 = cea_mode_alternate_clock(&cea_mode); 4149 4150 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 4151 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 4152 continue; 4153 4154 do { 4155 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4156 return vic; 4157 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4158 } 4159 4160 return 0; 4161 } 4162 EXPORT_SYMBOL(drm_match_cea_mode); 4163 4164 static bool drm_valid_cea_vic(u8 vic) 4165 { 4166 return cea_mode_for_vic(vic) != NULL; 4167 } 4168 4169 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 4170 { 4171 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 4172 4173 if (mode) 4174 return mode->picture_aspect_ratio; 4175 4176 return HDMI_PICTURE_ASPECT_NONE; 4177 } 4178 4179 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 4180 { 4181 return edid_4k_modes[video_code].picture_aspect_ratio; 4182 } 4183 4184 /* 4185 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 4186 * specific block). 4187 */ 4188 static unsigned int 4189 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 4190 { 4191 return cea_mode_alternate_clock(hdmi_mode); 4192 } 4193 4194 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 4195 unsigned int clock_tolerance) 4196 { 4197 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4198 u8 vic; 4199 4200 if (!to_match->clock) 4201 return 0; 4202 4203 if (to_match->picture_aspect_ratio) 4204 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4205 4206 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4207 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4208 unsigned int clock1, clock2; 4209 4210 /* Make sure to also match alternate clocks */ 4211 clock1 = hdmi_mode->clock; 4212 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4213 4214 if (abs(to_match->clock - clock1) > clock_tolerance && 4215 abs(to_match->clock - clock2) > clock_tolerance) 4216 continue; 4217 4218 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 4219 return vic; 4220 } 4221 4222 return 0; 4223 } 4224 4225 /* 4226 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 4227 * @to_match: display mode 4228 * 4229 * An HDMI mode is one defined in the HDMI vendor specific block. 4230 * 4231 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 4232 */ 4233 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 4234 { 4235 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4236 u8 vic; 4237 4238 if (!to_match->clock) 4239 return 0; 4240 4241 if (to_match->picture_aspect_ratio) 4242 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4243 4244 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4245 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4246 unsigned int clock1, clock2; 4247 4248 /* Make sure to also match alternate clocks */ 4249 clock1 = hdmi_mode->clock; 4250 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4251 4252 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 4253 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 4254 drm_mode_match(to_match, hdmi_mode, match_flags)) 4255 return vic; 4256 } 4257 return 0; 4258 } 4259 4260 static bool drm_valid_hdmi_vic(u8 vic) 4261 { 4262 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 4263 } 4264 4265 static int add_alternate_cea_modes(struct drm_connector *connector, 4266 const struct drm_edid *drm_edid) 4267 { 4268 struct drm_device *dev = connector->dev; 4269 struct drm_display_mode *mode, *tmp; 4270 DRM_LIST_HEAD(list); 4271 int modes = 0; 4272 4273 /* Don't add CTA modes if the CTA extension block is missing */ 4274 if (!drm_edid_has_cta_extension(drm_edid)) 4275 return 0; 4276 4277 /* 4278 * Go through all probed modes and create a new mode 4279 * with the alternate clock for certain CEA modes. 4280 */ 4281 list_for_each_entry(mode, &connector->probed_modes, head) { 4282 const struct drm_display_mode *cea_mode = NULL; 4283 struct drm_display_mode *newmode; 4284 u8 vic = drm_match_cea_mode(mode); 4285 unsigned int clock1, clock2; 4286 4287 if (drm_valid_cea_vic(vic)) { 4288 cea_mode = cea_mode_for_vic(vic); 4289 clock2 = cea_mode_alternate_clock(cea_mode); 4290 } else { 4291 vic = drm_match_hdmi_mode(mode); 4292 if (drm_valid_hdmi_vic(vic)) { 4293 cea_mode = &edid_4k_modes[vic]; 4294 clock2 = hdmi_mode_alternate_clock(cea_mode); 4295 } 4296 } 4297 4298 if (!cea_mode) 4299 continue; 4300 4301 clock1 = cea_mode->clock; 4302 4303 if (clock1 == clock2) 4304 continue; 4305 4306 if (mode->clock != clock1 && mode->clock != clock2) 4307 continue; 4308 4309 newmode = drm_mode_duplicate(dev, cea_mode); 4310 if (!newmode) 4311 continue; 4312 4313 /* Carry over the stereo flags */ 4314 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 4315 4316 /* 4317 * The current mode could be either variant. Make 4318 * sure to pick the "other" clock for the new mode. 4319 */ 4320 if (mode->clock != clock1) 4321 newmode->clock = clock1; 4322 else 4323 newmode->clock = clock2; 4324 4325 list_add_tail(&newmode->head, &list); 4326 } 4327 4328 list_for_each_entry_safe(mode, tmp, &list, head) { 4329 list_del(&mode->head); 4330 drm_mode_probed_add(connector, mode); 4331 modes++; 4332 } 4333 4334 return modes; 4335 } 4336 4337 static u8 svd_to_vic(u8 svd) 4338 { 4339 /* 0-6 bit vic, 7th bit native mode indicator */ 4340 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 4341 return svd & 127; 4342 4343 return svd; 4344 } 4345 4346 static struct drm_display_mode * 4347 drm_display_mode_from_vic_index(struct drm_connector *connector, 4348 const u8 *video_db, u8 video_len, 4349 u8 video_index) 4350 { 4351 struct drm_device *dev = connector->dev; 4352 struct drm_display_mode *newmode; 4353 u8 vic; 4354 4355 if (video_db == NULL || video_index >= video_len) 4356 return NULL; 4357 4358 /* CEA modes are numbered 1..127 */ 4359 vic = svd_to_vic(video_db[video_index]); 4360 if (!drm_valid_cea_vic(vic)) 4361 return NULL; 4362 4363 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 4364 if (!newmode) 4365 return NULL; 4366 4367 return newmode; 4368 } 4369 4370 /* 4371 * do_y420vdb_modes - Parse YCBCR 420 only modes 4372 * @connector: connector corresponding to the HDMI sink 4373 * @svds: start of the data block of CEA YCBCR 420 VDB 4374 * @len: length of the CEA YCBCR 420 VDB 4375 * 4376 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 4377 * which contains modes which can be supported in YCBCR 420 4378 * output format only. 4379 */ 4380 static int do_y420vdb_modes(struct drm_connector *connector, 4381 const u8 *svds, u8 svds_len) 4382 { 4383 int modes = 0, i; 4384 struct drm_device *dev = connector->dev; 4385 struct drm_display_info *info = &connector->display_info; 4386 struct drm_hdmi_info *hdmi = &info->hdmi; 4387 4388 for (i = 0; i < svds_len; i++) { 4389 u8 vic = svd_to_vic(svds[i]); 4390 struct drm_display_mode *newmode; 4391 4392 if (!drm_valid_cea_vic(vic)) 4393 continue; 4394 4395 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 4396 if (!newmode) 4397 break; 4398 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 4399 drm_mode_probed_add(connector, newmode); 4400 modes++; 4401 } 4402 4403 if (modes > 0) 4404 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 4405 return modes; 4406 } 4407 4408 /* 4409 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 4410 * @connector: connector corresponding to the HDMI sink 4411 * @vic: CEA vic for the video mode to be added in the map 4412 * 4413 * Makes an entry for a videomode in the YCBCR 420 bitmap 4414 */ 4415 static void 4416 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 4417 { 4418 u8 vic = svd_to_vic(svd); 4419 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4420 4421 if (!drm_valid_cea_vic(vic)) 4422 return; 4423 4424 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 4425 } 4426 4427 /** 4428 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC 4429 * @dev: DRM device 4430 * @video_code: CEA VIC of the mode 4431 * 4432 * Creates a new mode matching the specified CEA VIC. 4433 * 4434 * Returns: A new drm_display_mode on success or NULL on failure 4435 */ 4436 struct drm_display_mode * 4437 drm_display_mode_from_cea_vic(struct drm_device *dev, 4438 u8 video_code) 4439 { 4440 const struct drm_display_mode *cea_mode; 4441 struct drm_display_mode *newmode; 4442 4443 cea_mode = cea_mode_for_vic(video_code); 4444 if (!cea_mode) 4445 return NULL; 4446 4447 newmode = drm_mode_duplicate(dev, cea_mode); 4448 if (!newmode) 4449 return NULL; 4450 4451 return newmode; 4452 } 4453 EXPORT_SYMBOL(drm_display_mode_from_cea_vic); 4454 4455 static int 4456 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 4457 { 4458 int i, modes = 0; 4459 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4460 4461 for (i = 0; i < len; i++) { 4462 struct drm_display_mode *mode; 4463 4464 mode = drm_display_mode_from_vic_index(connector, db, len, i); 4465 if (mode) { 4466 /* 4467 * YCBCR420 capability block contains a bitmap which 4468 * gives the index of CEA modes from CEA VDB, which 4469 * can support YCBCR 420 sampling output also (apart 4470 * from RGB/YCBCR444 etc). 4471 * For example, if the bit 0 in bitmap is set, 4472 * first mode in VDB can support YCBCR420 output too. 4473 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 4474 */ 4475 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 4476 drm_add_cmdb_modes(connector, db[i]); 4477 4478 drm_mode_probed_add(connector, mode); 4479 modes++; 4480 } 4481 } 4482 4483 return modes; 4484 } 4485 4486 struct stereo_mandatory_mode { 4487 int width, height, vrefresh; 4488 unsigned int flags; 4489 }; 4490 4491 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 4492 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4493 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4494 { 1920, 1080, 50, 4495 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4496 { 1920, 1080, 60, 4497 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4498 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4499 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4500 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4501 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 4502 }; 4503 4504 static bool 4505 stereo_match_mandatory(const struct drm_display_mode *mode, 4506 const struct stereo_mandatory_mode *stereo_mode) 4507 { 4508 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 4509 4510 return mode->hdisplay == stereo_mode->width && 4511 mode->vdisplay == stereo_mode->height && 4512 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 4513 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 4514 } 4515 4516 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 4517 { 4518 struct drm_device *dev = connector->dev; 4519 const struct drm_display_mode *mode; 4520 struct list_head stereo_modes; 4521 int modes = 0, i; 4522 4523 INIT_LIST_HEAD(&stereo_modes); 4524 4525 list_for_each_entry(mode, &connector->probed_modes, head) { 4526 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 4527 const struct stereo_mandatory_mode *mandatory; 4528 struct drm_display_mode *new_mode; 4529 4530 if (!stereo_match_mandatory(mode, 4531 &stereo_mandatory_modes[i])) 4532 continue; 4533 4534 mandatory = &stereo_mandatory_modes[i]; 4535 new_mode = drm_mode_duplicate(dev, mode); 4536 if (!new_mode) 4537 continue; 4538 4539 new_mode->flags |= mandatory->flags; 4540 list_add_tail(&new_mode->head, &stereo_modes); 4541 modes++; 4542 } 4543 } 4544 4545 list_splice_tail(&stereo_modes, &connector->probed_modes); 4546 4547 return modes; 4548 } 4549 4550 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 4551 { 4552 struct drm_device *dev = connector->dev; 4553 struct drm_display_mode *newmode; 4554 4555 if (!drm_valid_hdmi_vic(vic)) { 4556 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 4557 return 0; 4558 } 4559 4560 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 4561 if (!newmode) 4562 return 0; 4563 4564 drm_mode_probed_add(connector, newmode); 4565 4566 return 1; 4567 } 4568 4569 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 4570 const u8 *video_db, u8 video_len, u8 video_index) 4571 { 4572 struct drm_display_mode *newmode; 4573 int modes = 0; 4574 4575 if (structure & (1 << 0)) { 4576 newmode = drm_display_mode_from_vic_index(connector, video_db, 4577 video_len, 4578 video_index); 4579 if (newmode) { 4580 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 4581 drm_mode_probed_add(connector, newmode); 4582 modes++; 4583 } 4584 } 4585 if (structure & (1 << 6)) { 4586 newmode = drm_display_mode_from_vic_index(connector, video_db, 4587 video_len, 4588 video_index); 4589 if (newmode) { 4590 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4591 drm_mode_probed_add(connector, newmode); 4592 modes++; 4593 } 4594 } 4595 if (structure & (1 << 8)) { 4596 newmode = drm_display_mode_from_vic_index(connector, video_db, 4597 video_len, 4598 video_index); 4599 if (newmode) { 4600 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4601 drm_mode_probed_add(connector, newmode); 4602 modes++; 4603 } 4604 } 4605 4606 return modes; 4607 } 4608 4609 /* 4610 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 4611 * @connector: connector corresponding to the HDMI sink 4612 * @db: start of the CEA vendor specific block 4613 * @len: length of the CEA block payload, ie. one can access up to db[len] 4614 * 4615 * Parses the HDMI VSDB looking for modes to add to @connector. This function 4616 * also adds the stereo 3d modes when applicable. 4617 */ 4618 static int 4619 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 4620 const u8 *video_db, u8 video_len) 4621 { 4622 struct drm_display_info *info = &connector->display_info; 4623 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 4624 u8 vic_len, hdmi_3d_len = 0; 4625 u16 mask; 4626 u16 structure_all; 4627 4628 if (len < 8) 4629 goto out; 4630 4631 /* no HDMI_Video_Present */ 4632 if (!(db[8] & (1 << 5))) 4633 goto out; 4634 4635 /* Latency_Fields_Present */ 4636 if (db[8] & (1 << 7)) 4637 offset += 2; 4638 4639 /* I_Latency_Fields_Present */ 4640 if (db[8] & (1 << 6)) 4641 offset += 2; 4642 4643 /* the declared length is not long enough for the 2 first bytes 4644 * of additional video format capabilities */ 4645 if (len < (8 + offset + 2)) 4646 goto out; 4647 4648 /* 3D_Present */ 4649 offset++; 4650 if (db[8 + offset] & (1 << 7)) { 4651 modes += add_hdmi_mandatory_stereo_modes(connector); 4652 4653 /* 3D_Multi_present */ 4654 multi_present = (db[8 + offset] & 0x60) >> 5; 4655 } 4656 4657 offset++; 4658 vic_len = db[8 + offset] >> 5; 4659 hdmi_3d_len = db[8 + offset] & 0x1f; 4660 4661 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 4662 u8 vic; 4663 4664 vic = db[9 + offset + i]; 4665 modes += add_hdmi_mode(connector, vic); 4666 } 4667 offset += 1 + vic_len; 4668 4669 if (multi_present == 1) 4670 multi_len = 2; 4671 else if (multi_present == 2) 4672 multi_len = 4; 4673 else 4674 multi_len = 0; 4675 4676 if (len < (8 + offset + hdmi_3d_len - 1)) 4677 goto out; 4678 4679 if (hdmi_3d_len < multi_len) 4680 goto out; 4681 4682 if (multi_present == 1 || multi_present == 2) { 4683 /* 3D_Structure_ALL */ 4684 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 4685 4686 /* check if 3D_MASK is present */ 4687 if (multi_present == 2) 4688 mask = (db[10 + offset] << 8) | db[11 + offset]; 4689 else 4690 mask = 0xffff; 4691 4692 for (i = 0; i < 16; i++) { 4693 if (mask & (1 << i)) 4694 modes += add_3d_struct_modes(connector, 4695 structure_all, 4696 video_db, 4697 video_len, i); 4698 } 4699 } 4700 4701 offset += multi_len; 4702 4703 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 4704 int vic_index; 4705 struct drm_display_mode *newmode = NULL; 4706 unsigned int newflag = 0; 4707 bool detail_present; 4708 4709 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 4710 4711 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 4712 break; 4713 4714 /* 2D_VIC_order_X */ 4715 vic_index = db[8 + offset + i] >> 4; 4716 4717 /* 3D_Structure_X */ 4718 switch (db[8 + offset + i] & 0x0f) { 4719 case 0: 4720 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 4721 break; 4722 case 6: 4723 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4724 break; 4725 case 8: 4726 /* 3D_Detail_X */ 4727 if ((db[9 + offset + i] >> 4) == 1) 4728 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4729 break; 4730 } 4731 4732 if (newflag != 0) { 4733 newmode = drm_display_mode_from_vic_index(connector, 4734 video_db, 4735 video_len, 4736 vic_index); 4737 4738 if (newmode) { 4739 newmode->flags |= newflag; 4740 drm_mode_probed_add(connector, newmode); 4741 modes++; 4742 } 4743 } 4744 4745 if (detail_present) 4746 i++; 4747 } 4748 4749 out: 4750 if (modes > 0) 4751 info->has_hdmi_infoframe = true; 4752 return modes; 4753 } 4754 4755 static int 4756 cea_revision(const u8 *cea) 4757 { 4758 /* 4759 * FIXME is this correct for the DispID variant? 4760 * The DispID spec doesn't really specify whether 4761 * this is the revision of the CEA extension or 4762 * the DispID CEA data block. And the only value 4763 * given as an example is 0. 4764 */ 4765 return cea[1]; 4766 } 4767 4768 /* 4769 * CTA Data Block iterator. 4770 * 4771 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID 4772 * CTA Data Blocks. 4773 * 4774 * struct cea_db *db: 4775 * struct cea_db_iter iter; 4776 * 4777 * cea_db_iter_edid_begin(edid, &iter); 4778 * cea_db_iter_for_each(db, &iter) { 4779 * // do stuff with db 4780 * } 4781 * cea_db_iter_end(&iter); 4782 */ 4783 struct cea_db_iter { 4784 struct drm_edid_iter edid_iter; 4785 struct displayid_iter displayid_iter; 4786 4787 /* Current Data Block Collection. */ 4788 const u8 *collection; 4789 4790 /* Current Data Block index in current collection. */ 4791 int index; 4792 4793 /* End index in current collection. */ 4794 int end; 4795 }; 4796 4797 /* CTA-861-H section 7.4 CTA Data BLock Collection */ 4798 struct cea_db { 4799 u8 tag_length; 4800 u8 data[]; 4801 } __packed; 4802 4803 static int cea_db_tag(const struct cea_db *db) 4804 { 4805 return db->tag_length >> 5; 4806 } 4807 4808 static int cea_db_payload_len(const void *_db) 4809 { 4810 /* FIXME: Transition to passing struct cea_db * everywhere. */ 4811 const struct cea_db *db = _db; 4812 4813 return db->tag_length & 0x1f; 4814 } 4815 4816 static const void *cea_db_data(const struct cea_db *db) 4817 { 4818 return db->data; 4819 } 4820 4821 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag) 4822 { 4823 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG && 4824 cea_db_payload_len(db) >= 1 && 4825 db->data[0] == tag; 4826 } 4827 4828 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui) 4829 { 4830 const u8 *data = cea_db_data(db); 4831 4832 return cea_db_tag(db) == CTA_DB_VENDOR && 4833 cea_db_payload_len(db) >= 3 && 4834 oui(data[2], data[1], data[0]) == vendor_oui; 4835 } 4836 4837 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid, 4838 struct cea_db_iter *iter) 4839 { 4840 memset(iter, 0, sizeof(*iter)); 4841 4842 drm_edid_iter_begin(drm_edid, &iter->edid_iter); 4843 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter); 4844 } 4845 4846 static const struct cea_db * 4847 __cea_db_iter_current_block(const struct cea_db_iter *iter) 4848 { 4849 const struct cea_db *db; 4850 4851 if (!iter->collection) 4852 return NULL; 4853 4854 db = (const struct cea_db *)&iter->collection[iter->index]; 4855 4856 if (iter->index + sizeof(*db) <= iter->end && 4857 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end) 4858 return db; 4859 4860 return NULL; 4861 } 4862 4863 /* 4864 * References: 4865 * - CTA-861-H section 7.3.3 CTA Extension Version 3 4866 */ 4867 static int cea_db_collection_size(const u8 *cta) 4868 { 4869 u8 d = cta[2]; 4870 4871 if (d < 4 || d > 127) 4872 return 0; 4873 4874 return d - 4; 4875 } 4876 4877 /* 4878 * References: 4879 * - VESA E-EDID v1.4 4880 * - CTA-861-H section 7.3.3 CTA Extension Version 3 4881 */ 4882 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter) 4883 { 4884 const u8 *ext; 4885 4886 drm_edid_iter_for_each(ext, &iter->edid_iter) { 4887 int size; 4888 4889 /* Only support CTA Extension revision 3+ */ 4890 if (ext[0] != CEA_EXT || cea_revision(ext) < 3) 4891 continue; 4892 4893 size = cea_db_collection_size(ext); 4894 if (!size) 4895 continue; 4896 4897 iter->index = 4; 4898 iter->end = iter->index + size; 4899 4900 return ext; 4901 } 4902 4903 return NULL; 4904 } 4905 4906 /* 4907 * References: 4908 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block 4909 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block 4910 * 4911 * Note that the above do not specify any connection between DisplayID Data 4912 * Block revision and CTA Extension versions. 4913 */ 4914 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter) 4915 { 4916 const struct displayid_block *block; 4917 4918 displayid_iter_for_each(block, &iter->displayid_iter) { 4919 if (block->tag != DATA_BLOCK_CTA) 4920 continue; 4921 4922 /* 4923 * The displayid iterator has already verified the block bounds 4924 * in displayid_iter_block(). 4925 */ 4926 iter->index = sizeof(*block); 4927 iter->end = iter->index + block->num_bytes; 4928 4929 return block; 4930 } 4931 4932 return NULL; 4933 } 4934 4935 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter) 4936 { 4937 const struct cea_db *db; 4938 4939 if (iter->collection) { 4940 /* Current collection should always be valid. */ 4941 db = __cea_db_iter_current_block(iter); 4942 if (WARN_ON(!db)) { 4943 iter->collection = NULL; 4944 return NULL; 4945 } 4946 4947 /* Next block in CTA Data Block Collection */ 4948 iter->index += sizeof(*db) + cea_db_payload_len(db); 4949 4950 db = __cea_db_iter_current_block(iter); 4951 if (db) 4952 return db; 4953 } 4954 4955 for (;;) { 4956 /* 4957 * Find the next CTA Data Block Collection. First iterate all 4958 * the EDID CTA Extensions, then all the DisplayID CTA blocks. 4959 * 4960 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID 4961 * Extension, it's recommended that DisplayID extensions are 4962 * exposed after all of the CTA Extensions. 4963 */ 4964 iter->collection = __cea_db_iter_edid_next(iter); 4965 if (!iter->collection) 4966 iter->collection = __cea_db_iter_displayid_next(iter); 4967 4968 if (!iter->collection) 4969 return NULL; 4970 4971 db = __cea_db_iter_current_block(iter); 4972 if (db) 4973 return db; 4974 } 4975 } 4976 4977 #define cea_db_iter_for_each(__db, __iter) \ 4978 while (((__db) = __cea_db_iter_next(__iter))) 4979 4980 static void cea_db_iter_end(struct cea_db_iter *iter) 4981 { 4982 displayid_iter_end(&iter->displayid_iter); 4983 drm_edid_iter_end(&iter->edid_iter); 4984 4985 memset(iter, 0, sizeof(*iter)); 4986 } 4987 4988 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db) 4989 { 4990 return cea_db_is_vendor(db, HDMI_IEEE_OUI) && 4991 cea_db_payload_len(db) >= 5; 4992 } 4993 4994 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db) 4995 { 4996 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) && 4997 cea_db_payload_len(db) >= 7; 4998 } 4999 5000 static bool cea_db_is_hdmi_forum_eeodb(const void *db) 5001 { 5002 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) && 5003 cea_db_payload_len(db) >= 2; 5004 } 5005 5006 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db) 5007 { 5008 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) && 5009 cea_db_payload_len(db) == 21; 5010 } 5011 5012 static bool cea_db_is_vcdb(const struct cea_db *db) 5013 { 5014 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) && 5015 cea_db_payload_len(db) == 2; 5016 } 5017 5018 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db) 5019 { 5020 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) && 5021 cea_db_payload_len(db) >= 7; 5022 } 5023 5024 static bool cea_db_is_y420cmdb(const struct cea_db *db) 5025 { 5026 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP); 5027 } 5028 5029 static bool cea_db_is_y420vdb(const struct cea_db *db) 5030 { 5031 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA); 5032 } 5033 5034 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db) 5035 { 5036 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) && 5037 cea_db_payload_len(db) >= 3; 5038 } 5039 5040 /* 5041 * Get the HF-EEODB override extension block count from EDID. 5042 * 5043 * The passed in EDID may be partially read, as long as it has at least two 5044 * blocks (base block and one extension block) if EDID extension count is > 0. 5045 * 5046 * Note that this is *not* how you should parse CTA Data Blocks in general; this 5047 * is only to handle partially read EDIDs. Normally, use the CTA Data Block 5048 * iterators instead. 5049 * 5050 * References: 5051 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block 5052 */ 5053 static int edid_hfeeodb_extension_block_count(const struct edid *edid) 5054 { 5055 const u8 *cta; 5056 5057 /* No extensions according to base block, no HF-EEODB. */ 5058 if (!edid_extension_block_count(edid)) 5059 return 0; 5060 5061 /* HF-EEODB is always in the first EDID extension block only */ 5062 cta = edid_extension_block_data(edid, 0); 5063 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3) 5064 return 0; 5065 5066 /* Need to have the data block collection, and at least 3 bytes. */ 5067 if (cea_db_collection_size(cta) < 3) 5068 return 0; 5069 5070 /* 5071 * Sinks that include the HF-EEODB in their E-EDID shall include one and 5072 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4 5073 * through 6 of Block 1 of the E-EDID. 5074 */ 5075 if (!cea_db_is_hdmi_forum_eeodb(&cta[4])) 5076 return 0; 5077 5078 return cta[4 + 2]; 5079 } 5080 5081 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 5082 const u8 *db) 5083 { 5084 struct drm_display_info *info = &connector->display_info; 5085 struct drm_hdmi_info *hdmi = &info->hdmi; 5086 u8 map_len = cea_db_payload_len(db) - 1; 5087 u8 count; 5088 u64 map = 0; 5089 5090 if (map_len == 0) { 5091 /* All CEA modes support ycbcr420 sampling also.*/ 5092 hdmi->y420_cmdb_map = U64_MAX; 5093 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 5094 return; 5095 } 5096 5097 /* 5098 * This map indicates which of the existing CEA block modes 5099 * from VDB can support YCBCR420 output too. So if bit=0 is 5100 * set, first mode from VDB can support YCBCR420 output too. 5101 * We will parse and keep this map, before parsing VDB itself 5102 * to avoid going through the same block again and again. 5103 * 5104 * Spec is not clear about max possible size of this block. 5105 * Clamping max bitmap block size at 8 bytes. Every byte can 5106 * address 8 CEA modes, in this way this map can address 5107 * 8*8 = first 64 SVDs. 5108 */ 5109 if (WARN_ON_ONCE(map_len > 8)) 5110 map_len = 8; 5111 5112 for (count = 0; count < map_len; count++) 5113 map |= (u64)db[2 + count] << (8 * count); 5114 5115 if (map) 5116 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 5117 5118 hdmi->y420_cmdb_map = map; 5119 } 5120 5121 static int add_cea_modes(struct drm_connector *connector, 5122 const struct drm_edid *drm_edid) 5123 { 5124 const struct cea_db *db; 5125 struct cea_db_iter iter; 5126 const u8 *hdmi = NULL, *video = NULL; 5127 u8 hdmi_len = 0, video_len = 0; 5128 int modes = 0; 5129 5130 cea_db_iter_edid_begin(drm_edid, &iter); 5131 cea_db_iter_for_each(db, &iter) { 5132 if (cea_db_tag(db) == CTA_DB_VIDEO) { 5133 video = cea_db_data(db); 5134 video_len = cea_db_payload_len(db); 5135 modes += do_cea_modes(connector, video, video_len); 5136 } else if (cea_db_is_hdmi_vsdb(db)) { 5137 /* FIXME: Switch to use cea_db_data() */ 5138 hdmi = (const u8 *)db; 5139 hdmi_len = cea_db_payload_len(db); 5140 } else if (cea_db_is_y420vdb(db)) { 5141 const u8 *vdb420 = cea_db_data(db) + 1; 5142 5143 /* Add 4:2:0(only) modes present in EDID */ 5144 modes += do_y420vdb_modes(connector, vdb420, 5145 cea_db_payload_len(db) - 1); 5146 } 5147 } 5148 cea_db_iter_end(&iter); 5149 5150 /* 5151 * We parse the HDMI VSDB after having added the cea modes as we will be 5152 * patching their flags when the sink supports stereo 3D. 5153 */ 5154 if (hdmi) 5155 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, 5156 video, video_len); 5157 5158 return modes; 5159 } 5160 5161 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 5162 { 5163 const struct drm_display_mode *cea_mode; 5164 int clock1, clock2, clock; 5165 u8 vic; 5166 const char *type; 5167 5168 /* 5169 * allow 5kHz clock difference either way to account for 5170 * the 10kHz clock resolution limit of detailed timings. 5171 */ 5172 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 5173 if (drm_valid_cea_vic(vic)) { 5174 type = "CEA"; 5175 cea_mode = cea_mode_for_vic(vic); 5176 clock1 = cea_mode->clock; 5177 clock2 = cea_mode_alternate_clock(cea_mode); 5178 } else { 5179 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 5180 if (drm_valid_hdmi_vic(vic)) { 5181 type = "HDMI"; 5182 cea_mode = &edid_4k_modes[vic]; 5183 clock1 = cea_mode->clock; 5184 clock2 = hdmi_mode_alternate_clock(cea_mode); 5185 } else { 5186 return; 5187 } 5188 } 5189 5190 /* pick whichever is closest */ 5191 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 5192 clock = clock1; 5193 else 5194 clock = clock2; 5195 5196 if (mode->clock == clock) 5197 return; 5198 5199 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 5200 type, vic, mode->clock, clock); 5201 mode->clock = clock; 5202 } 5203 5204 static void drm_calculate_luminance_range(struct drm_connector *connector) 5205 { 5206 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1; 5207 struct drm_luminance_range_info *luminance_range = 5208 &connector->display_info.luminance_range; 5209 static const u8 pre_computed_values[] = { 5210 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69, 5211 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98 5212 }; 5213 u32 max_avg, min_cll, max, min, q, r; 5214 5215 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1))) 5216 return; 5217 5218 max_avg = hdr_metadata->max_fall; 5219 min_cll = hdr_metadata->min_cll; 5220 5221 /* 5222 * From the specification (CTA-861-G), for calculating the maximum 5223 * luminance we need to use: 5224 * Luminance = 50*2**(CV/32) 5225 * Where CV is a one-byte value. 5226 * For calculating this expression we may need float point precision; 5227 * to avoid this complexity level, we take advantage that CV is divided 5228 * by a constant. From the Euclids division algorithm, we know that CV 5229 * can be written as: CV = 32*q + r. Next, we replace CV in the 5230 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just 5231 * need to pre-compute the value of r/32. For pre-computing the values 5232 * We just used the following Ruby line: 5233 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round} 5234 * The results of the above expressions can be verified at 5235 * pre_computed_values. 5236 */ 5237 q = max_avg >> 5; 5238 r = max_avg % 32; 5239 max = (1 << q) * pre_computed_values[r]; 5240 5241 /* min luminance: maxLum * (CV/255)^2 / 100 */ 5242 q = DIV_ROUND_CLOSEST(min_cll, 255); 5243 min = max * DIV_ROUND_CLOSEST((q * q), 100); 5244 5245 luminance_range->min_luminance = min; 5246 luminance_range->max_luminance = max; 5247 } 5248 5249 static uint8_t eotf_supported(const u8 *edid_ext) 5250 { 5251 return edid_ext[2] & 5252 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 5253 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 5254 BIT(HDMI_EOTF_SMPTE_ST2084) | 5255 BIT(HDMI_EOTF_BT_2100_HLG)); 5256 } 5257 5258 static uint8_t hdr_metadata_type(const u8 *edid_ext) 5259 { 5260 return edid_ext[3] & 5261 BIT(HDMI_STATIC_METADATA_TYPE1); 5262 } 5263 5264 static void 5265 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 5266 { 5267 u16 len; 5268 5269 len = cea_db_payload_len(db); 5270 5271 connector->hdr_sink_metadata.hdmi_type1.eotf = 5272 eotf_supported(db); 5273 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 5274 hdr_metadata_type(db); 5275 5276 if (len >= 4) 5277 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 5278 if (len >= 5) 5279 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 5280 if (len >= 6) { 5281 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 5282 5283 /* Calculate only when all values are available */ 5284 drm_calculate_luminance_range(connector); 5285 } 5286 } 5287 5288 static void 5289 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 5290 { 5291 u8 len = cea_db_payload_len(db); 5292 5293 if (len >= 6 && (db[6] & (1 << 7))) 5294 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 5295 if (len >= 8) { 5296 connector->latency_present[0] = db[8] >> 7; 5297 connector->latency_present[1] = (db[8] >> 6) & 1; 5298 } 5299 if (len >= 9) 5300 connector->video_latency[0] = db[9]; 5301 if (len >= 10) 5302 connector->audio_latency[0] = db[10]; 5303 if (len >= 11) 5304 connector->video_latency[1] = db[11]; 5305 if (len >= 12) 5306 connector->audio_latency[1] = db[12]; 5307 5308 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 5309 "video latency %d %d, " 5310 "audio latency %d %d\n", 5311 connector->latency_present[0], 5312 connector->latency_present[1], 5313 connector->video_latency[0], 5314 connector->video_latency[1], 5315 connector->audio_latency[0], 5316 connector->audio_latency[1]); 5317 } 5318 5319 static void 5320 monitor_name(const struct detailed_timing *timing, void *data) 5321 { 5322 const char **res = data; 5323 5324 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME)) 5325 return; 5326 5327 *res = timing->data.other_data.data.str.str; 5328 } 5329 5330 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13]) 5331 { 5332 const char *edid_name = NULL; 5333 int mnl; 5334 5335 if (!drm_edid || !name) 5336 return 0; 5337 5338 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name); 5339 for (mnl = 0; edid_name && mnl < 13; mnl++) { 5340 if (edid_name[mnl] == 0x0a) 5341 break; 5342 5343 name[mnl] = edid_name[mnl]; 5344 } 5345 5346 return mnl; 5347 } 5348 5349 /** 5350 * drm_edid_get_monitor_name - fetch the monitor name from the edid 5351 * @edid: monitor EDID information 5352 * @name: pointer to a character array to hold the name of the monitor 5353 * @bufsize: The size of the name buffer (should be at least 14 chars.) 5354 * 5355 */ 5356 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize) 5357 { 5358 int name_length = 0; 5359 5360 if (bufsize <= 0) 5361 return; 5362 5363 if (edid) { 5364 char buf[13]; 5365 struct drm_edid drm_edid = { 5366 .edid = edid, 5367 .size = edid_size(edid), 5368 }; 5369 5370 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1); 5371 memcpy(name, buf, name_length); 5372 } 5373 5374 name[name_length] = '\0'; 5375 } 5376 EXPORT_SYMBOL(drm_edid_get_monitor_name); 5377 5378 static void clear_eld(struct drm_connector *connector) 5379 { 5380 memset(connector->eld, 0, sizeof(connector->eld)); 5381 5382 connector->latency_present[0] = false; 5383 connector->latency_present[1] = false; 5384 connector->video_latency[0] = 0; 5385 connector->audio_latency[0] = 0; 5386 connector->video_latency[1] = 0; 5387 connector->audio_latency[1] = 0; 5388 } 5389 5390 /* 5391 * drm_edid_to_eld - build ELD from EDID 5392 * @connector: connector corresponding to the HDMI/DP sink 5393 * @drm_edid: EDID to parse 5394 * 5395 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 5396 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 5397 */ 5398 static void drm_edid_to_eld(struct drm_connector *connector, 5399 const struct drm_edid *drm_edid) 5400 { 5401 const struct drm_display_info *info = &connector->display_info; 5402 const struct cea_db *db; 5403 struct cea_db_iter iter; 5404 uint8_t *eld = connector->eld; 5405 int total_sad_count = 0; 5406 int mnl; 5407 5408 clear_eld(connector); 5409 5410 if (!drm_edid) 5411 return; 5412 5413 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 5414 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); 5415 5416 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT; 5417 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 5418 5419 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 5420 5421 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0]; 5422 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1]; 5423 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0]; 5424 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1]; 5425 5426 cea_db_iter_edid_begin(drm_edid, &iter); 5427 cea_db_iter_for_each(db, &iter) { 5428 const u8 *data = cea_db_data(db); 5429 int len = cea_db_payload_len(db); 5430 int sad_count; 5431 5432 switch (cea_db_tag(db)) { 5433 case CTA_DB_AUDIO: 5434 /* Audio Data Block, contains SADs */ 5435 sad_count = min(len / 3, 15 - total_sad_count); 5436 if (sad_count >= 1) 5437 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 5438 data, sad_count * 3); 5439 total_sad_count += sad_count; 5440 break; 5441 case CTA_DB_SPEAKER: 5442 /* Speaker Allocation Data Block */ 5443 if (len >= 1) 5444 eld[DRM_ELD_SPEAKER] = data[0]; 5445 break; 5446 case CTA_DB_VENDOR: 5447 /* HDMI Vendor-Specific Data Block */ 5448 if (cea_db_is_hdmi_vsdb(db)) 5449 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db); 5450 break; 5451 default: 5452 break; 5453 } 5454 } 5455 cea_db_iter_end(&iter); 5456 5457 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 5458 5459 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 5460 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 5461 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 5462 else 5463 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 5464 5465 eld[DRM_ELD_BASELINE_ELD_LEN] = 5466 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 5467 5468 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 5469 drm_eld_size(eld), total_sad_count); 5470 } 5471 5472 static int _drm_edid_to_sad(const struct drm_edid *drm_edid, 5473 struct cea_sad **sads) 5474 { 5475 const struct cea_db *db; 5476 struct cea_db_iter iter; 5477 int count = 0; 5478 5479 cea_db_iter_edid_begin(drm_edid, &iter); 5480 cea_db_iter_for_each(db, &iter) { 5481 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5482 int j; 5483 5484 count = cea_db_payload_len(db) / 3; /* SAD is 3B */ 5485 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 5486 if (!*sads) 5487 return -ENOMEM; 5488 for (j = 0; j < count; j++) { 5489 const u8 *sad = &db->data[j * 3]; 5490 5491 (*sads)[j].format = (sad[0] & 0x78) >> 3; 5492 (*sads)[j].channels = sad[0] & 0x7; 5493 (*sads)[j].freq = sad[1] & 0x7F; 5494 (*sads)[j].byte2 = sad[2]; 5495 } 5496 break; 5497 } 5498 } 5499 cea_db_iter_end(&iter); 5500 5501 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count); 5502 5503 return count; 5504 } 5505 5506 /** 5507 * drm_edid_to_sad - extracts SADs from EDID 5508 * @edid: EDID to parse 5509 * @sads: pointer that will be set to the extracted SADs 5510 * 5511 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 5512 * 5513 * Note: The returned pointer needs to be freed using kfree(). 5514 * 5515 * Return: The number of found SADs or negative number on error. 5516 */ 5517 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads) 5518 { 5519 struct drm_edid drm_edid; 5520 5521 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads); 5522 } 5523 EXPORT_SYMBOL(drm_edid_to_sad); 5524 5525 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid, 5526 u8 **sadb) 5527 { 5528 const struct cea_db *db; 5529 struct cea_db_iter iter; 5530 int count = 0; 5531 5532 cea_db_iter_edid_begin(drm_edid, &iter); 5533 cea_db_iter_for_each(db, &iter) { 5534 if (cea_db_tag(db) == CTA_DB_SPEAKER && 5535 cea_db_payload_len(db) == 3) { 5536 *sadb = kmemdup(db->data, cea_db_payload_len(db), 5537 GFP_KERNEL); 5538 if (!*sadb) 5539 return -ENOMEM; 5540 count = cea_db_payload_len(db); 5541 break; 5542 } 5543 } 5544 cea_db_iter_end(&iter); 5545 5546 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count); 5547 5548 return count; 5549 } 5550 5551 /** 5552 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 5553 * @edid: EDID to parse 5554 * @sadb: pointer to the speaker block 5555 * 5556 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 5557 * 5558 * Note: The returned pointer needs to be freed using kfree(). 5559 * 5560 * Return: The number of found Speaker Allocation Blocks or negative number on 5561 * error. 5562 */ 5563 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb) 5564 { 5565 struct drm_edid drm_edid; 5566 5567 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid), 5568 sadb); 5569 } 5570 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 5571 5572 /** 5573 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 5574 * @connector: connector associated with the HDMI/DP sink 5575 * @mode: the display mode 5576 * 5577 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 5578 * the sink doesn't support audio or video. 5579 */ 5580 int drm_av_sync_delay(struct drm_connector *connector, 5581 const struct drm_display_mode *mode) 5582 { 5583 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 5584 int a, v; 5585 5586 if (!connector->latency_present[0]) 5587 return 0; 5588 if (!connector->latency_present[1]) 5589 i = 0; 5590 5591 a = connector->audio_latency[i]; 5592 v = connector->video_latency[i]; 5593 5594 /* 5595 * HDMI/DP sink doesn't support audio or video? 5596 */ 5597 if (a == 255 || v == 255) 5598 return 0; 5599 5600 /* 5601 * Convert raw EDID values to millisecond. 5602 * Treat unknown latency as 0ms. 5603 */ 5604 if (a) 5605 a = min(2 * (a - 1), 500); 5606 if (v) 5607 v = min(2 * (v - 1), 500); 5608 5609 return max(v - a, 0); 5610 } 5611 EXPORT_SYMBOL(drm_av_sync_delay); 5612 5613 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid) 5614 { 5615 const struct cea_db *db; 5616 struct cea_db_iter iter; 5617 bool hdmi = false; 5618 5619 /* 5620 * Because HDMI identifier is in Vendor Specific Block, 5621 * search it from all data blocks of CEA extension. 5622 */ 5623 cea_db_iter_edid_begin(drm_edid, &iter); 5624 cea_db_iter_for_each(db, &iter) { 5625 if (cea_db_is_hdmi_vsdb(db)) { 5626 hdmi = true; 5627 break; 5628 } 5629 } 5630 cea_db_iter_end(&iter); 5631 5632 return hdmi; 5633 } 5634 5635 /** 5636 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 5637 * @edid: monitor EDID information 5638 * 5639 * Parse the CEA extension according to CEA-861-B. 5640 * 5641 * Drivers that have added the modes parsed from EDID to drm_display_info 5642 * should use &drm_display_info.is_hdmi instead of calling this function. 5643 * 5644 * Return: True if the monitor is HDMI, false if not or unknown. 5645 */ 5646 bool drm_detect_hdmi_monitor(const struct edid *edid) 5647 { 5648 struct drm_edid drm_edid; 5649 5650 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid)); 5651 } 5652 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 5653 5654 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid) 5655 { 5656 struct drm_edid_iter edid_iter; 5657 const struct cea_db *db; 5658 struct cea_db_iter iter; 5659 const u8 *edid_ext; 5660 bool has_audio = false; 5661 5662 drm_edid_iter_begin(drm_edid, &edid_iter); 5663 drm_edid_iter_for_each(edid_ext, &edid_iter) { 5664 if (edid_ext[0] == CEA_EXT) { 5665 has_audio = edid_ext[3] & EDID_BASIC_AUDIO; 5666 if (has_audio) 5667 break; 5668 } 5669 } 5670 drm_edid_iter_end(&edid_iter); 5671 5672 if (has_audio) { 5673 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 5674 goto end; 5675 } 5676 5677 cea_db_iter_edid_begin(drm_edid, &iter); 5678 cea_db_iter_for_each(db, &iter) { 5679 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5680 const u8 *data = cea_db_data(db); 5681 int i; 5682 5683 for (i = 0; i < cea_db_payload_len(db); i += 3) 5684 DRM_DEBUG_KMS("CEA audio format %d\n", 5685 (data[i] >> 3) & 0xf); 5686 has_audio = true; 5687 break; 5688 } 5689 } 5690 cea_db_iter_end(&iter); 5691 5692 end: 5693 return has_audio; 5694 } 5695 5696 /** 5697 * drm_detect_monitor_audio - check monitor audio capability 5698 * @edid: EDID block to scan 5699 * 5700 * Monitor should have CEA extension block. 5701 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 5702 * audio' only. If there is any audio extension block and supported 5703 * audio format, assume at least 'basic audio' support, even if 'basic 5704 * audio' is not defined in EDID. 5705 * 5706 * Return: True if the monitor supports audio, false otherwise. 5707 */ 5708 bool drm_detect_monitor_audio(const struct edid *edid) 5709 { 5710 struct drm_edid drm_edid; 5711 5712 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid)); 5713 } 5714 EXPORT_SYMBOL(drm_detect_monitor_audio); 5715 5716 5717 /** 5718 * drm_default_rgb_quant_range - default RGB quantization range 5719 * @mode: display mode 5720 * 5721 * Determine the default RGB quantization range for the mode, 5722 * as specified in CEA-861. 5723 * 5724 * Return: The default RGB quantization range for the mode 5725 */ 5726 enum hdmi_quantization_range 5727 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 5728 { 5729 /* All CEA modes other than VIC 1 use limited quantization range. */ 5730 return drm_match_cea_mode(mode) > 1 ? 5731 HDMI_QUANTIZATION_RANGE_LIMITED : 5732 HDMI_QUANTIZATION_RANGE_FULL; 5733 } 5734 EXPORT_SYMBOL(drm_default_rgb_quant_range); 5735 5736 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 5737 { 5738 struct drm_display_info *info = &connector->display_info; 5739 5740 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]); 5741 5742 if (db[2] & EDID_CEA_VCDB_QS) 5743 info->rgb_quant_range_selectable = true; 5744 } 5745 5746 static 5747 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) 5748 { 5749 switch (max_frl_rate) { 5750 case 1: 5751 *max_lanes = 3; 5752 *max_rate_per_lane = 3; 5753 break; 5754 case 2: 5755 *max_lanes = 3; 5756 *max_rate_per_lane = 6; 5757 break; 5758 case 3: 5759 *max_lanes = 4; 5760 *max_rate_per_lane = 6; 5761 break; 5762 case 4: 5763 *max_lanes = 4; 5764 *max_rate_per_lane = 8; 5765 break; 5766 case 5: 5767 *max_lanes = 4; 5768 *max_rate_per_lane = 10; 5769 break; 5770 case 6: 5771 *max_lanes = 4; 5772 *max_rate_per_lane = 12; 5773 break; 5774 case 0: 5775 default: 5776 *max_lanes = 0; 5777 *max_rate_per_lane = 0; 5778 } 5779 } 5780 5781 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 5782 const u8 *db) 5783 { 5784 u8 dc_mask; 5785 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 5786 5787 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 5788 hdmi->y420_dc_modes = dc_mask; 5789 } 5790 5791 /* Sink Capability Data Structure */ 5792 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector, 5793 const u8 *hf_scds) 5794 { 5795 struct drm_display_info *display = &connector->display_info; 5796 struct drm_hdmi_info *hdmi = &display->hdmi; 5797 5798 display->has_hdmi_infoframe = true; 5799 5800 if (hf_scds[6] & 0x80) { 5801 hdmi->scdc.supported = true; 5802 if (hf_scds[6] & 0x40) 5803 hdmi->scdc.read_request = true; 5804 } 5805 5806 /* 5807 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 5808 * And as per the spec, three factors confirm this: 5809 * * Availability of a HF-VSDB block in EDID (check) 5810 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 5811 * * SCDC support available (let's check) 5812 * Lets check it out. 5813 */ 5814 5815 if (hf_scds[5]) { 5816 /* max clock is 5000 KHz times block value */ 5817 u32 max_tmds_clock = hf_scds[5] * 5000; 5818 struct drm_scdc *scdc = &hdmi->scdc; 5819 5820 if (max_tmds_clock > 340000) { 5821 display->max_tmds_clock = max_tmds_clock; 5822 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 5823 display->max_tmds_clock); 5824 } 5825 5826 if (scdc->supported) { 5827 scdc->scrambling.supported = true; 5828 5829 /* Few sinks support scrambling for clocks < 340M */ 5830 if ((hf_scds[6] & 0x8)) 5831 scdc->scrambling.low_rates = true; 5832 } 5833 } 5834 5835 if (hf_scds[7]) { 5836 u8 max_frl_rate; 5837 u8 dsc_max_frl_rate; 5838 u8 dsc_max_slices; 5839 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; 5840 5841 DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n"); 5842 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; 5843 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, 5844 &hdmi->max_frl_rate_per_lane); 5845 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2; 5846 5847 if (hdmi_dsc->v_1p2) { 5848 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420; 5849 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP; 5850 5851 if (hf_scds[11] & DRM_EDID_DSC_16BPC) 5852 hdmi_dsc->bpc_supported = 16; 5853 else if (hf_scds[11] & DRM_EDID_DSC_12BPC) 5854 hdmi_dsc->bpc_supported = 12; 5855 else if (hf_scds[11] & DRM_EDID_DSC_10BPC) 5856 hdmi_dsc->bpc_supported = 10; 5857 else 5858 /* Supports min 8 BPC if DSC 1.2 is supported*/ 5859 hdmi_dsc->bpc_supported = 8; 5860 5861 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; 5862 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, 5863 &hdmi_dsc->max_frl_rate_per_lane); 5864 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; 5865 5866 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES; 5867 switch (dsc_max_slices) { 5868 case 1: 5869 hdmi_dsc->max_slices = 1; 5870 hdmi_dsc->clk_per_slice = 340; 5871 break; 5872 case 2: 5873 hdmi_dsc->max_slices = 2; 5874 hdmi_dsc->clk_per_slice = 340; 5875 break; 5876 case 3: 5877 hdmi_dsc->max_slices = 4; 5878 hdmi_dsc->clk_per_slice = 340; 5879 break; 5880 case 4: 5881 hdmi_dsc->max_slices = 8; 5882 hdmi_dsc->clk_per_slice = 340; 5883 break; 5884 case 5: 5885 hdmi_dsc->max_slices = 8; 5886 hdmi_dsc->clk_per_slice = 400; 5887 break; 5888 case 6: 5889 hdmi_dsc->max_slices = 12; 5890 hdmi_dsc->clk_per_slice = 400; 5891 break; 5892 case 7: 5893 hdmi_dsc->max_slices = 16; 5894 hdmi_dsc->clk_per_slice = 400; 5895 break; 5896 case 0: 5897 default: 5898 hdmi_dsc->max_slices = 0; 5899 hdmi_dsc->clk_per_slice = 0; 5900 } 5901 } 5902 } 5903 5904 drm_parse_ycbcr420_deep_color_info(connector, hf_scds); 5905 } 5906 5907 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 5908 const u8 *hdmi) 5909 { 5910 struct drm_display_info *info = &connector->display_info; 5911 unsigned int dc_bpc = 0; 5912 5913 /* HDMI supports at least 8 bpc */ 5914 info->bpc = 8; 5915 5916 if (cea_db_payload_len(hdmi) < 6) 5917 return; 5918 5919 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 5920 dc_bpc = 10; 5921 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30; 5922 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 5923 connector->name); 5924 } 5925 5926 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 5927 dc_bpc = 12; 5928 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36; 5929 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 5930 connector->name); 5931 } 5932 5933 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 5934 dc_bpc = 16; 5935 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48; 5936 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 5937 connector->name); 5938 } 5939 5940 if (dc_bpc == 0) { 5941 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 5942 connector->name); 5943 return; 5944 } 5945 5946 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 5947 connector->name, dc_bpc); 5948 info->bpc = dc_bpc; 5949 5950 /* YCRCB444 is optional according to spec. */ 5951 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 5952 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes; 5953 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 5954 connector->name); 5955 } 5956 5957 /* 5958 * Spec says that if any deep color mode is supported at all, 5959 * then deep color 36 bit must be supported. 5960 */ 5961 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 5962 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 5963 connector->name); 5964 } 5965 } 5966 5967 static void 5968 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 5969 { 5970 struct drm_display_info *info = &connector->display_info; 5971 u8 len = cea_db_payload_len(db); 5972 5973 info->is_hdmi = true; 5974 5975 if (len >= 6) 5976 info->dvi_dual = db[6] & 1; 5977 if (len >= 7) 5978 info->max_tmds_clock = db[7] * 5000; 5979 5980 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 5981 "max TMDS clock %d kHz\n", 5982 info->dvi_dual, 5983 info->max_tmds_clock); 5984 5985 drm_parse_hdmi_deep_color_info(connector, db); 5986 } 5987 5988 /* 5989 * See EDID extension for head-mounted and specialized monitors, specified at: 5990 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension 5991 */ 5992 static void drm_parse_microsoft_vsdb(struct drm_connector *connector, 5993 const u8 *db) 5994 { 5995 struct drm_display_info *info = &connector->display_info; 5996 u8 version = db[4]; 5997 bool desktop_usage = db[5] & BIT(6); 5998 5999 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */ 6000 if (version == 1 || version == 2 || (version == 3 && !desktop_usage)) 6001 info->non_desktop = true; 6002 6003 drm_dbg_kms(connector->dev, "HMD or specialized display VSDB version %u: 0x%02x\n", 6004 version, db[5]); 6005 } 6006 6007 static void drm_parse_cea_ext(struct drm_connector *connector, 6008 const struct drm_edid *drm_edid) 6009 { 6010 struct drm_display_info *info = &connector->display_info; 6011 struct drm_edid_iter edid_iter; 6012 const struct cea_db *db; 6013 struct cea_db_iter iter; 6014 const u8 *edid_ext; 6015 6016 drm_edid_iter_begin(drm_edid, &edid_iter); 6017 drm_edid_iter_for_each(edid_ext, &edid_iter) { 6018 if (edid_ext[0] != CEA_EXT) 6019 continue; 6020 6021 if (!info->cea_rev) 6022 info->cea_rev = edid_ext[1]; 6023 6024 if (info->cea_rev != edid_ext[1]) 6025 DRM_DEBUG_KMS("CEA extension version mismatch %u != %u\n", 6026 info->cea_rev, edid_ext[1]); 6027 6028 /* The existence of a CTA extension should imply RGB support */ 6029 info->color_formats = DRM_COLOR_FORMAT_RGB444; 6030 if (edid_ext[3] & EDID_CEA_YCRCB444) 6031 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 6032 if (edid_ext[3] & EDID_CEA_YCRCB422) 6033 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 6034 } 6035 drm_edid_iter_end(&edid_iter); 6036 6037 cea_db_iter_edid_begin(drm_edid, &iter); 6038 cea_db_iter_for_each(db, &iter) { 6039 /* FIXME: convert parsers to use struct cea_db */ 6040 const u8 *data = (const u8 *)db; 6041 6042 if (cea_db_is_hdmi_vsdb(db)) 6043 drm_parse_hdmi_vsdb_video(connector, data); 6044 else if (cea_db_is_hdmi_forum_vsdb(db) || 6045 cea_db_is_hdmi_forum_scdb(db)) 6046 drm_parse_hdmi_forum_scds(connector, data); 6047 else if (cea_db_is_microsoft_vsdb(db)) 6048 drm_parse_microsoft_vsdb(connector, data); 6049 else if (cea_db_is_y420cmdb(db)) 6050 drm_parse_y420cmdb_bitmap(connector, data); 6051 else if (cea_db_is_vcdb(db)) 6052 drm_parse_vcdb(connector, data); 6053 else if (cea_db_is_hdmi_hdr_metadata_block(db)) 6054 drm_parse_hdr_metadata_block(connector, data); 6055 } 6056 cea_db_iter_end(&iter); 6057 } 6058 6059 static 6060 void get_monitor_range(const struct detailed_timing *timing, void *c) 6061 { 6062 struct detailed_mode_closure *closure = c; 6063 struct drm_display_info *info = &closure->connector->display_info; 6064 struct drm_monitor_range_info *monitor_range = &info->monitor_range; 6065 const struct detailed_non_pixel *data = &timing->data.other_data; 6066 const struct detailed_data_monitor_range *range = &data->data.range; 6067 const struct edid *edid = closure->drm_edid->edid; 6068 6069 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 6070 return; 6071 6072 /* 6073 * Check for flag range limits only. If flag == 1 then 6074 * no additional timing information provided. 6075 * Default GTF, GTF Secondary curve and CVT are not 6076 * supported 6077 */ 6078 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 6079 return; 6080 6081 monitor_range->min_vfreq = range->min_vfreq; 6082 monitor_range->max_vfreq = range->max_vfreq; 6083 6084 if (edid->revision >= 4) { 6085 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ) 6086 monitor_range->min_vfreq += 255; 6087 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ) 6088 monitor_range->max_vfreq += 255; 6089 } 6090 } 6091 6092 static void drm_get_monitor_range(struct drm_connector *connector, 6093 const struct drm_edid *drm_edid) 6094 { 6095 const struct drm_display_info *info = &connector->display_info; 6096 struct detailed_mode_closure closure = { 6097 .connector = connector, 6098 .drm_edid = drm_edid, 6099 }; 6100 6101 if (!version_greater(drm_edid, 1, 1)) 6102 return; 6103 6104 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure); 6105 6106 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 6107 info->monitor_range.min_vfreq, 6108 info->monitor_range.max_vfreq); 6109 } 6110 6111 static void drm_parse_vesa_mso_data(struct drm_connector *connector, 6112 const struct displayid_block *block) 6113 { 6114 struct displayid_vesa_vendor_specific_block *vesa = 6115 (struct displayid_vesa_vendor_specific_block *)block; 6116 struct drm_display_info *info = &connector->display_info; 6117 6118 if (block->num_bytes < 3) { 6119 drm_dbg_kms(connector->dev, "Unexpected vendor block size %u\n", 6120 block->num_bytes); 6121 return; 6122 } 6123 6124 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI) 6125 return; 6126 6127 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) { 6128 drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n"); 6129 return; 6130 } 6131 6132 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) { 6133 default: 6134 drm_dbg_kms(connector->dev, "Reserved MSO mode value\n"); 6135 fallthrough; 6136 case 0: 6137 info->mso_stream_count = 0; 6138 break; 6139 case 1: 6140 info->mso_stream_count = 2; /* 2 or 4 links */ 6141 break; 6142 case 2: 6143 info->mso_stream_count = 4; /* 4 links */ 6144 break; 6145 } 6146 6147 if (!info->mso_stream_count) { 6148 info->mso_pixel_overlap = 0; 6149 return; 6150 } 6151 6152 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); 6153 if (info->mso_pixel_overlap > 8) { 6154 drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n", 6155 info->mso_pixel_overlap); 6156 info->mso_pixel_overlap = 8; 6157 } 6158 6159 drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n", 6160 info->mso_stream_count, info->mso_pixel_overlap); 6161 } 6162 6163 static void drm_update_mso(struct drm_connector *connector, 6164 const struct drm_edid *drm_edid) 6165 { 6166 const struct displayid_block *block; 6167 struct displayid_iter iter; 6168 6169 displayid_iter_edid_begin(drm_edid, &iter); 6170 displayid_iter_for_each(block, &iter) { 6171 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC) 6172 drm_parse_vesa_mso_data(connector, block); 6173 } 6174 displayid_iter_end(&iter); 6175 } 6176 6177 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 6178 * all of the values which would have been set from EDID 6179 */ 6180 static void drm_reset_display_info(struct drm_connector *connector) 6181 { 6182 struct drm_display_info *info = &connector->display_info; 6183 6184 info->width_mm = 0; 6185 info->height_mm = 0; 6186 6187 info->bpc = 0; 6188 info->color_formats = 0; 6189 info->cea_rev = 0; 6190 info->max_tmds_clock = 0; 6191 info->dvi_dual = false; 6192 info->is_hdmi = false; 6193 info->has_hdmi_infoframe = false; 6194 info->rgb_quant_range_selectable = false; 6195 memset(&info->hdmi, 0, sizeof(info->hdmi)); 6196 6197 info->edid_hdmi_rgb444_dc_modes = 0; 6198 info->edid_hdmi_ycbcr444_dc_modes = 0; 6199 6200 info->non_desktop = 0; 6201 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 6202 memset(&info->luminance_range, 0, sizeof(info->luminance_range)); 6203 6204 info->mso_stream_count = 0; 6205 info->mso_pixel_overlap = 0; 6206 info->max_dsc_bpp = 0; 6207 } 6208 6209 static u32 update_display_info(struct drm_connector *connector, 6210 const struct drm_edid *drm_edid) 6211 { 6212 struct drm_display_info *info = &connector->display_info; 6213 const struct edid *edid = drm_edid->edid; 6214 6215 u32 quirks = edid_get_quirks(drm_edid); 6216 6217 drm_reset_display_info(connector); 6218 6219 info->width_mm = edid->width_cm * 10; 6220 info->height_mm = edid->height_cm * 10; 6221 6222 drm_get_monitor_range(connector, drm_edid); 6223 6224 if (edid->revision < 3) 6225 goto out; 6226 6227 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 6228 goto out; 6229 6230 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 6231 drm_parse_cea_ext(connector, drm_edid); 6232 6233 /* 6234 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 6235 * 6236 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 6237 * tells us to assume 8 bpc color depth if the EDID doesn't have 6238 * extensions which tell otherwise. 6239 */ 6240 if (info->bpc == 0 && edid->revision == 3 && 6241 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 6242 info->bpc = 8; 6243 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 6244 connector->name, info->bpc); 6245 } 6246 6247 /* Only defined for 1.4 with digital displays */ 6248 if (edid->revision < 4) 6249 goto out; 6250 6251 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 6252 case DRM_EDID_DIGITAL_DEPTH_6: 6253 info->bpc = 6; 6254 break; 6255 case DRM_EDID_DIGITAL_DEPTH_8: 6256 info->bpc = 8; 6257 break; 6258 case DRM_EDID_DIGITAL_DEPTH_10: 6259 info->bpc = 10; 6260 break; 6261 case DRM_EDID_DIGITAL_DEPTH_12: 6262 info->bpc = 12; 6263 break; 6264 case DRM_EDID_DIGITAL_DEPTH_14: 6265 info->bpc = 14; 6266 break; 6267 case DRM_EDID_DIGITAL_DEPTH_16: 6268 info->bpc = 16; 6269 break; 6270 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 6271 default: 6272 info->bpc = 0; 6273 break; 6274 } 6275 6276 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 6277 connector->name, info->bpc); 6278 6279 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 6280 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 6281 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 6282 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 6283 6284 drm_update_mso(connector, drm_edid); 6285 6286 out: 6287 if (quirks & EDID_QUIRK_NON_DESKTOP) { 6288 drm_dbg_kms(connector->dev, "Non-desktop display%s\n", 6289 info->non_desktop ? " (redundant quirk)" : ""); 6290 info->non_desktop = true; 6291 } 6292 6293 if (quirks & EDID_QUIRK_CAP_DSC_15BPP) 6294 info->max_dsc_bpp = 15; 6295 6296 return quirks; 6297 } 6298 6299 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 6300 struct displayid_detailed_timings_1 *timings, 6301 bool type_7) 6302 { 6303 struct drm_display_mode *mode; 6304 unsigned pixel_clock = (timings->pixel_clock[0] | 6305 (timings->pixel_clock[1] << 8) | 6306 (timings->pixel_clock[2] << 16)) + 1; 6307 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 6308 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 6309 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 6310 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 6311 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 6312 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 6313 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 6314 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 6315 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 6316 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 6317 6318 mode = drm_mode_create(dev); 6319 if (!mode) 6320 return NULL; 6321 6322 /* resolution is kHz for type VII, and 10 kHz for type I */ 6323 mode->clock = type_7 ? pixel_clock : pixel_clock * 10; 6324 mode->hdisplay = hactive; 6325 mode->hsync_start = mode->hdisplay + hsync; 6326 mode->hsync_end = mode->hsync_start + hsync_width; 6327 mode->htotal = mode->hdisplay + hblank; 6328 6329 mode->vdisplay = vactive; 6330 mode->vsync_start = mode->vdisplay + vsync; 6331 mode->vsync_end = mode->vsync_start + vsync_width; 6332 mode->vtotal = mode->vdisplay + vblank; 6333 6334 mode->flags = 0; 6335 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 6336 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 6337 mode->type = DRM_MODE_TYPE_DRIVER; 6338 6339 if (timings->flags & 0x80) 6340 mode->type |= DRM_MODE_TYPE_PREFERRED; 6341 drm_mode_set_name(mode); 6342 6343 return mode; 6344 } 6345 6346 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 6347 const struct displayid_block *block) 6348 { 6349 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 6350 int i; 6351 int num_timings; 6352 struct drm_display_mode *newmode; 6353 int num_modes = 0; 6354 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING; 6355 /* blocks must be multiple of 20 bytes length */ 6356 if (block->num_bytes % 20) 6357 return 0; 6358 6359 num_timings = block->num_bytes / 20; 6360 for (i = 0; i < num_timings; i++) { 6361 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 6362 6363 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7); 6364 if (!newmode) 6365 continue; 6366 6367 drm_mode_probed_add(connector, newmode); 6368 num_modes++; 6369 } 6370 return num_modes; 6371 } 6372 6373 static int add_displayid_detailed_modes(struct drm_connector *connector, 6374 const struct drm_edid *drm_edid) 6375 { 6376 const struct displayid_block *block; 6377 struct displayid_iter iter; 6378 int num_modes = 0; 6379 6380 displayid_iter_edid_begin(drm_edid, &iter); 6381 displayid_iter_for_each(block, &iter) { 6382 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING || 6383 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING) 6384 num_modes += add_displayid_detailed_1_modes(connector, block); 6385 } 6386 displayid_iter_end(&iter); 6387 6388 return num_modes; 6389 } 6390 6391 static int _drm_edid_connector_update(struct drm_connector *connector, 6392 const struct drm_edid *drm_edid) 6393 { 6394 int num_modes = 0; 6395 u32 quirks; 6396 6397 if (!drm_edid) { 6398 drm_reset_display_info(connector); 6399 clear_eld(connector); 6400 return 0; 6401 } 6402 6403 /* 6404 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 6405 * To avoid multiple parsing of same block, lets parse that map 6406 * from sink info, before parsing CEA modes. 6407 */ 6408 quirks = update_display_info(connector, drm_edid); 6409 6410 /* Depends on info->cea_rev set by update_display_info() above */ 6411 drm_edid_to_eld(connector, drm_edid); 6412 6413 /* 6414 * EDID spec says modes should be preferred in this order: 6415 * - preferred detailed mode 6416 * - other detailed modes from base block 6417 * - detailed modes from extension blocks 6418 * - CVT 3-byte code modes 6419 * - standard timing codes 6420 * - established timing codes 6421 * - modes inferred from GTF or CVT range information 6422 * 6423 * We get this pretty much right. 6424 * 6425 * XXX order for additional mode types in extension blocks? 6426 */ 6427 num_modes += add_detailed_modes(connector, drm_edid, quirks); 6428 num_modes += add_cvt_modes(connector, drm_edid); 6429 num_modes += add_standard_modes(connector, drm_edid); 6430 num_modes += add_established_modes(connector, drm_edid); 6431 num_modes += add_cea_modes(connector, drm_edid); 6432 num_modes += add_alternate_cea_modes(connector, drm_edid); 6433 num_modes += add_displayid_detailed_modes(connector, drm_edid); 6434 if (drm_edid->edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 6435 num_modes += add_inferred_modes(connector, drm_edid); 6436 6437 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 6438 edid_fixup_preferred(connector, quirks); 6439 6440 if (quirks & EDID_QUIRK_FORCE_6BPC) 6441 connector->display_info.bpc = 6; 6442 6443 if (quirks & EDID_QUIRK_FORCE_8BPC) 6444 connector->display_info.bpc = 8; 6445 6446 if (quirks & EDID_QUIRK_FORCE_10BPC) 6447 connector->display_info.bpc = 10; 6448 6449 if (quirks & EDID_QUIRK_FORCE_12BPC) 6450 connector->display_info.bpc = 12; 6451 6452 return num_modes; 6453 } 6454 6455 static void _drm_update_tile_info(struct drm_connector *connector, 6456 const struct drm_edid *drm_edid); 6457 6458 static int _drm_edid_connector_property_update(struct drm_connector *connector, 6459 const struct drm_edid *drm_edid) 6460 { 6461 struct drm_device *dev = connector->dev; 6462 int ret; 6463 6464 if (connector->edid_blob_ptr) { 6465 const struct edid *old_edid = connector->edid_blob_ptr->data; 6466 6467 if (old_edid) { 6468 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) { 6469 connector->epoch_counter++; 6470 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n", 6471 connector->base.id, connector->name, 6472 connector->epoch_counter); 6473 } 6474 } 6475 } 6476 6477 ret = drm_property_replace_global_blob(dev, 6478 &connector->edid_blob_ptr, 6479 drm_edid ? drm_edid->size : 0, 6480 drm_edid ? drm_edid->edid : NULL, 6481 &connector->base, 6482 dev->mode_config.edid_property); 6483 if (ret) { 6484 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n", 6485 connector->base.id, connector->name, ret); 6486 goto out; 6487 } 6488 6489 ret = drm_object_property_set_value(&connector->base, 6490 dev->mode_config.non_desktop_property, 6491 connector->display_info.non_desktop); 6492 if (ret) { 6493 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n", 6494 connector->base.id, connector->name, ret); 6495 goto out; 6496 } 6497 6498 ret = drm_connector_set_tile_property(connector); 6499 if (ret) { 6500 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n", 6501 connector->base.id, connector->name, ret); 6502 goto out; 6503 } 6504 6505 out: 6506 return ret; 6507 } 6508 6509 /** 6510 * drm_edid_connector_update - Update connector information from EDID 6511 * @connector: Connector 6512 * @drm_edid: EDID 6513 * 6514 * Update the connector mode list, display info, ELD, HDR metadata, relevant 6515 * properties, etc. from the passed in EDID. 6516 * 6517 * If EDID is NULL, reset the information. 6518 * 6519 * Return: The number of modes added or 0 if we couldn't find any. 6520 */ 6521 int drm_edid_connector_update(struct drm_connector *connector, 6522 const struct drm_edid *drm_edid) 6523 { 6524 int count; 6525 6526 /* 6527 * FIXME: Reconcile the differences in override_edid handling between 6528 * this and drm_connector_update_edid_property(). 6529 * 6530 * If override_edid is set, and the EDID passed in here originates from 6531 * drm_edid_read() and friends, it will be the override EDID, and there 6532 * are no issues. drm_connector_update_edid_property() ignoring requests 6533 * to set the EDID dates back to a time when override EDID was not 6534 * handled at the low level EDID read. 6535 * 6536 * The only way the EDID passed in here can be different from the 6537 * override EDID is when a driver passes in an EDID that does *not* 6538 * originate from drm_edid_read() and friends, or passes in a stale 6539 * cached version. This, in turn, is a question of when an override EDID 6540 * set via debugfs should take effect. 6541 */ 6542 6543 count = _drm_edid_connector_update(connector, drm_edid); 6544 6545 _drm_update_tile_info(connector, drm_edid); 6546 6547 /* Note: Ignore errors for now. */ 6548 _drm_edid_connector_property_update(connector, drm_edid); 6549 6550 return count; 6551 } 6552 EXPORT_SYMBOL(drm_edid_connector_update); 6553 6554 static int _drm_connector_update_edid_property(struct drm_connector *connector, 6555 const struct drm_edid *drm_edid) 6556 { 6557 /* ignore requests to set edid when overridden */ 6558 if (connector->override_edid) 6559 return 0; 6560 6561 /* 6562 * Set the display info, using edid if available, otherwise resetting 6563 * the values to defaults. This duplicates the work done in 6564 * drm_add_edid_modes, but that function is not consistently called 6565 * before this one in all drivers and the computation is cheap enough 6566 * that it seems better to duplicate it rather than attempt to ensure 6567 * some arbitrary ordering of calls. 6568 */ 6569 if (drm_edid) 6570 update_display_info(connector, drm_edid); 6571 else 6572 drm_reset_display_info(connector); 6573 6574 _drm_update_tile_info(connector, drm_edid); 6575 6576 return _drm_edid_connector_property_update(connector, drm_edid); 6577 } 6578 6579 /** 6580 * drm_connector_update_edid_property - update the edid property of a connector 6581 * @connector: drm connector 6582 * @edid: new value of the edid property 6583 * 6584 * This function creates a new blob modeset object and assigns its id to the 6585 * connector's edid property. 6586 * Since we also parse tile information from EDID's displayID block, we also 6587 * set the connector's tile property here. See drm_connector_set_tile_property() 6588 * for more details. 6589 * 6590 * This function is deprecated. Use drm_edid_connector_update() instead. 6591 * 6592 * Returns: 6593 * Zero on success, negative errno on failure. 6594 */ 6595 int drm_connector_update_edid_property(struct drm_connector *connector, 6596 const struct edid *edid) 6597 { 6598 struct drm_edid drm_edid; 6599 6600 return _drm_connector_update_edid_property(connector, 6601 drm_edid_legacy_init(&drm_edid, edid)); 6602 } 6603 EXPORT_SYMBOL(drm_connector_update_edid_property); 6604 6605 /** 6606 * drm_add_edid_modes - add modes from EDID data, if available 6607 * @connector: connector we're probing 6608 * @edid: EDID data 6609 * 6610 * Add the specified modes to the connector's mode list. Also fills out the 6611 * &drm_display_info structure and ELD in @connector with any information which 6612 * can be derived from the edid. 6613 * 6614 * This function is deprecated. Use drm_edid_connector_update() instead. 6615 * 6616 * Return: The number of modes added or 0 if we couldn't find any. 6617 */ 6618 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 6619 { 6620 struct drm_edid drm_edid; 6621 6622 if (edid && !drm_edid_is_valid(edid)) { 6623 drm_warn(connector->dev, "%s: EDID invalid.\n", 6624 connector->name); 6625 edid = NULL; 6626 } 6627 6628 return _drm_edid_connector_update(connector, 6629 drm_edid_legacy_init(&drm_edid, edid)); 6630 } 6631 EXPORT_SYMBOL(drm_add_edid_modes); 6632 6633 /** 6634 * drm_add_modes_noedid - add modes for the connectors without EDID 6635 * @connector: connector we're probing 6636 * @hdisplay: the horizontal display limit 6637 * @vdisplay: the vertical display limit 6638 * 6639 * Add the specified modes to the connector's mode list. Only when the 6640 * hdisplay/vdisplay is not beyond the given limit, it will be added. 6641 * 6642 * Return: The number of modes added or 0 if we couldn't find any. 6643 */ 6644 int drm_add_modes_noedid(struct drm_connector *connector, 6645 int hdisplay, int vdisplay) 6646 { 6647 int i, count, num_modes = 0; 6648 struct drm_display_mode *mode; 6649 struct drm_device *dev = connector->dev; 6650 6651 count = ARRAY_SIZE(drm_dmt_modes); 6652 if (hdisplay < 0) 6653 hdisplay = 0; 6654 if (vdisplay < 0) 6655 vdisplay = 0; 6656 6657 for (i = 0; i < count; i++) { 6658 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 6659 6660 if (hdisplay && vdisplay) { 6661 /* 6662 * Only when two are valid, they will be used to check 6663 * whether the mode should be added to the mode list of 6664 * the connector. 6665 */ 6666 if (ptr->hdisplay > hdisplay || 6667 ptr->vdisplay > vdisplay) 6668 continue; 6669 } 6670 if (drm_mode_vrefresh(ptr) > 61) 6671 continue; 6672 mode = drm_mode_duplicate(dev, ptr); 6673 if (mode) { 6674 drm_mode_probed_add(connector, mode); 6675 num_modes++; 6676 } 6677 } 6678 return num_modes; 6679 } 6680 EXPORT_SYMBOL(drm_add_modes_noedid); 6681 6682 /** 6683 * drm_set_preferred_mode - Sets the preferred mode of a connector 6684 * @connector: connector whose mode list should be processed 6685 * @hpref: horizontal resolution of preferred mode 6686 * @vpref: vertical resolution of preferred mode 6687 * 6688 * Marks a mode as preferred if it matches the resolution specified by @hpref 6689 * and @vpref. 6690 */ 6691 void drm_set_preferred_mode(struct drm_connector *connector, 6692 int hpref, int vpref) 6693 { 6694 struct drm_display_mode *mode; 6695 6696 list_for_each_entry(mode, &connector->probed_modes, head) { 6697 if (mode->hdisplay == hpref && 6698 mode->vdisplay == vpref) 6699 mode->type |= DRM_MODE_TYPE_PREFERRED; 6700 } 6701 } 6702 EXPORT_SYMBOL(drm_set_preferred_mode); 6703 6704 static bool is_hdmi2_sink(const struct drm_connector *connector) 6705 { 6706 /* 6707 * FIXME: sil-sii8620 doesn't have a connector around when 6708 * we need one, so we have to be prepared for a NULL connector. 6709 */ 6710 if (!connector) 6711 return true; 6712 6713 return connector->display_info.hdmi.scdc.supported || 6714 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420; 6715 } 6716 6717 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, 6718 const struct drm_display_mode *mode) 6719 { 6720 bool has_hdmi_infoframe = connector ? 6721 connector->display_info.has_hdmi_infoframe : false; 6722 6723 if (!has_hdmi_infoframe) 6724 return 0; 6725 6726 /* No HDMI VIC when signalling 3D video format */ 6727 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 6728 return 0; 6729 6730 return drm_match_hdmi_mode(mode); 6731 } 6732 6733 static u8 drm_mode_cea_vic(const struct drm_connector *connector, 6734 const struct drm_display_mode *mode) 6735 { 6736 /* 6737 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 6738 * we should send its VIC in vendor infoframes, else send the 6739 * VIC in AVI infoframes. Lets check if this mode is present in 6740 * HDMI 1.4b 4K modes 6741 */ 6742 if (drm_mode_hdmi_vic(connector, mode)) 6743 return 0; 6744 6745 return drm_match_cea_mode(mode); 6746 } 6747 6748 /* 6749 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that 6750 * conform to HDMI 1.4. 6751 * 6752 * HDMI 1.4 (CTA-861-D) VIC range: [1..64] 6753 * HDMI 2.0 (CTA-861-F) VIC range: [1..107] 6754 */ 6755 static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic) 6756 { 6757 if (!is_hdmi2_sink(connector) && vic > 64) 6758 return 0; 6759 6760 return vic; 6761 } 6762 6763 /** 6764 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 6765 * data from a DRM display mode 6766 * @frame: HDMI AVI infoframe 6767 * @connector: the connector 6768 * @mode: DRM display mode 6769 * 6770 * Return: 0 on success or a negative error code on failure. 6771 */ 6772 int 6773 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 6774 const struct drm_connector *connector, 6775 const struct drm_display_mode *mode) 6776 { 6777 enum hdmi_picture_aspect picture_aspect; 6778 u8 vic, hdmi_vic; 6779 6780 if (!frame || !mode) 6781 return -EINVAL; 6782 6783 hdmi_avi_infoframe_init(frame); 6784 6785 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 6786 frame->pixel_repeat = 1; 6787 6788 vic = drm_mode_cea_vic(connector, mode); 6789 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 6790 6791 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 6792 6793 /* 6794 * As some drivers don't support atomic, we can't use connector state. 6795 * So just initialize the frame with default values, just the same way 6796 * as it's done with other properties here. 6797 */ 6798 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 6799 frame->itc = 0; 6800 6801 /* 6802 * Populate picture aspect ratio from either 6803 * user input (if specified) or from the CEA/HDMI mode lists. 6804 */ 6805 picture_aspect = mode->picture_aspect_ratio; 6806 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 6807 if (vic) 6808 picture_aspect = drm_get_cea_aspect_ratio(vic); 6809 else if (hdmi_vic) 6810 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 6811 } 6812 6813 /* 6814 * The infoframe can't convey anything but none, 4:3 6815 * and 16:9, so if the user has asked for anything else 6816 * we can only satisfy it by specifying the right VIC. 6817 */ 6818 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 6819 if (vic) { 6820 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 6821 return -EINVAL; 6822 } else if (hdmi_vic) { 6823 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 6824 return -EINVAL; 6825 } else { 6826 return -EINVAL; 6827 } 6828 6829 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 6830 } 6831 6832 frame->video_code = vic_for_avi_infoframe(connector, vic); 6833 frame->picture_aspect = picture_aspect; 6834 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 6835 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 6836 6837 return 0; 6838 } 6839 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 6840 6841 /** 6842 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 6843 * quantization range information 6844 * @frame: HDMI AVI infoframe 6845 * @connector: the connector 6846 * @mode: DRM display mode 6847 * @rgb_quant_range: RGB quantization range (Q) 6848 */ 6849 void 6850 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 6851 const struct drm_connector *connector, 6852 const struct drm_display_mode *mode, 6853 enum hdmi_quantization_range rgb_quant_range) 6854 { 6855 const struct drm_display_info *info = &connector->display_info; 6856 6857 /* 6858 * CEA-861: 6859 * "A Source shall not send a non-zero Q value that does not correspond 6860 * to the default RGB Quantization Range for the transmitted Picture 6861 * unless the Sink indicates support for the Q bit in a Video 6862 * Capabilities Data Block." 6863 * 6864 * HDMI 2.0 recommends sending non-zero Q when it does match the 6865 * default RGB quantization range for the mode, even when QS=0. 6866 */ 6867 if (info->rgb_quant_range_selectable || 6868 rgb_quant_range == drm_default_rgb_quant_range(mode)) 6869 frame->quantization_range = rgb_quant_range; 6870 else 6871 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 6872 6873 /* 6874 * CEA-861-F: 6875 * "When transmitting any RGB colorimetry, the Source should set the 6876 * YQ-field to match the RGB Quantization Range being transmitted 6877 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 6878 * set YQ=1) and the Sink shall ignore the YQ-field." 6879 * 6880 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 6881 * by non-zero YQ when receiving RGB. There doesn't seem to be any 6882 * good way to tell which version of CEA-861 the sink supports, so 6883 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 6884 * on on CEA-861-F. 6885 */ 6886 if (!is_hdmi2_sink(connector) || 6887 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 6888 frame->ycc_quantization_range = 6889 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 6890 else 6891 frame->ycc_quantization_range = 6892 HDMI_YCC_QUANTIZATION_RANGE_FULL; 6893 } 6894 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 6895 6896 static enum hdmi_3d_structure 6897 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 6898 { 6899 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 6900 6901 switch (layout) { 6902 case DRM_MODE_FLAG_3D_FRAME_PACKING: 6903 return HDMI_3D_STRUCTURE_FRAME_PACKING; 6904 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 6905 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 6906 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 6907 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 6908 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 6909 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 6910 case DRM_MODE_FLAG_3D_L_DEPTH: 6911 return HDMI_3D_STRUCTURE_L_DEPTH; 6912 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 6913 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 6914 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 6915 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 6916 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 6917 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 6918 default: 6919 return HDMI_3D_STRUCTURE_INVALID; 6920 } 6921 } 6922 6923 /** 6924 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 6925 * data from a DRM display mode 6926 * @frame: HDMI vendor infoframe 6927 * @connector: the connector 6928 * @mode: DRM display mode 6929 * 6930 * Note that there's is a need to send HDMI vendor infoframes only when using a 6931 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 6932 * function will return -EINVAL, error that can be safely ignored. 6933 * 6934 * Return: 0 on success or a negative error code on failure. 6935 */ 6936 int 6937 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 6938 const struct drm_connector *connector, 6939 const struct drm_display_mode *mode) 6940 { 6941 /* 6942 * FIXME: sil-sii8620 doesn't have a connector around when 6943 * we need one, so we have to be prepared for a NULL connector. 6944 */ 6945 bool has_hdmi_infoframe = connector ? 6946 connector->display_info.has_hdmi_infoframe : false; 6947 int err; 6948 6949 if (!frame || !mode) 6950 return -EINVAL; 6951 6952 if (!has_hdmi_infoframe) 6953 return -EINVAL; 6954 6955 err = hdmi_vendor_infoframe_init(frame); 6956 if (err < 0) 6957 return err; 6958 6959 /* 6960 * Even if it's not absolutely necessary to send the infoframe 6961 * (ie.vic==0 and s3d_struct==0) we will still send it if we 6962 * know that the sink can handle it. This is based on a 6963 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 6964 * have trouble realizing that they should switch from 3D to 2D 6965 * mode if the source simply stops sending the infoframe when 6966 * it wants to switch from 3D to 2D. 6967 */ 6968 frame->vic = drm_mode_hdmi_vic(connector, mode); 6969 frame->s3d_struct = s3d_structure_from_display_mode(mode); 6970 6971 return 0; 6972 } 6973 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 6974 6975 static void drm_parse_tiled_block(struct drm_connector *connector, 6976 const struct displayid_block *block) 6977 { 6978 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 6979 u16 w, h; 6980 u8 tile_v_loc, tile_h_loc; 6981 u8 num_v_tile, num_h_tile; 6982 struct drm_tile_group *tg; 6983 6984 w = tile->tile_size[0] | tile->tile_size[1] << 8; 6985 h = tile->tile_size[2] | tile->tile_size[3] << 8; 6986 6987 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 6988 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 6989 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 6990 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 6991 6992 connector->has_tile = true; 6993 if (tile->tile_cap & 0x80) 6994 connector->tile_is_single_monitor = true; 6995 6996 connector->num_h_tile = num_h_tile + 1; 6997 connector->num_v_tile = num_v_tile + 1; 6998 connector->tile_h_loc = tile_h_loc; 6999 connector->tile_v_loc = tile_v_loc; 7000 connector->tile_h_size = w + 1; 7001 connector->tile_v_size = h + 1; 7002 7003 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 7004 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 7005 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 7006 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 7007 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 7008 7009 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 7010 if (!tg) 7011 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 7012 if (!tg) 7013 return; 7014 7015 if (connector->tile_group != tg) { 7016 /* if we haven't got a pointer, 7017 take the reference, drop ref to old tile group */ 7018 if (connector->tile_group) 7019 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7020 connector->tile_group = tg; 7021 } else { 7022 /* if same tile group, then release the ref we just took. */ 7023 drm_mode_put_tile_group(connector->dev, tg); 7024 } 7025 } 7026 7027 static void _drm_update_tile_info(struct drm_connector *connector, 7028 const struct drm_edid *drm_edid) 7029 { 7030 const struct displayid_block *block; 7031 struct displayid_iter iter; 7032 7033 connector->has_tile = false; 7034 7035 displayid_iter_edid_begin(drm_edid, &iter); 7036 displayid_iter_for_each(block, &iter) { 7037 if (block->tag == DATA_BLOCK_TILED_DISPLAY) 7038 drm_parse_tiled_block(connector, block); 7039 } 7040 displayid_iter_end(&iter); 7041 7042 if (!connector->has_tile && connector->tile_group) { 7043 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7044 connector->tile_group = NULL; 7045 } 7046 } 7047