1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/hdmi.h> 32 #include <linux/i2c.h> 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/pci.h> 36 #include <linux/slab.h> 37 #include <linux/vga_switcheroo.h> 38 39 #include <drm/drm_displayid.h> 40 #include <drm/drm_drv.h> 41 #include <drm/drm_edid.h> 42 #include <drm/drm_encoder.h> 43 #include <drm/drm_print.h> 44 #include <drm/drm_scdc_helper.h> 45 46 #include "drm_crtc_internal.h" 47 48 #define version_greater(edid, maj, min) \ 49 (((edid)->version > (maj)) || \ 50 ((edid)->version == (maj) && (edid)->revision > (min))) 51 52 #define EDID_EST_TIMINGS 16 53 #define EDID_STD_TIMINGS 8 54 #define EDID_DETAILED_TIMINGS 4 55 56 /* 57 * EDID blocks out in the wild have a variety of bugs, try to collect 58 * them here (note that userspace may work around broken monitors first, 59 * but fixes should make their way here so that the kernel "just works" 60 * on as many displays as possible). 61 */ 62 63 /* First detailed mode wrong, use largest 60Hz mode */ 64 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 65 /* Reported 135MHz pixel clock is too high, needs adjustment */ 66 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 67 /* Prefer the largest mode at 75 Hz */ 68 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 69 /* Detail timing is in cm not mm */ 70 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 71 /* Detailed timing descriptors have bogus size values, so just take the 72 * maximum size and use that. 73 */ 74 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 75 /* use +hsync +vsync for detailed mode */ 76 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 77 /* Force reduced-blanking timings for detailed modes */ 78 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 79 /* Force 8bpc */ 80 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 81 /* Force 12bpc */ 82 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 83 /* Force 6bpc */ 84 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 85 /* Force 10bpc */ 86 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 87 /* Non desktop display (i.e. HMD) */ 88 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 89 90 struct detailed_mode_closure { 91 struct drm_connector *connector; 92 struct edid *edid; 93 bool preferred; 94 u32 quirks; 95 int modes; 96 }; 97 98 #define LEVEL_DMT 0 99 #define LEVEL_GTF 1 100 #define LEVEL_GTF2 2 101 #define LEVEL_CVT 3 102 103 static const struct edid_quirk { 104 char vendor[4]; 105 int product_id; 106 u32 quirks; 107 } edid_quirk_list[] = { 108 /* Acer AL1706 */ 109 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 110 /* Acer F51 */ 111 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 112 113 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 114 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 115 116 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 117 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC }, 118 119 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 120 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC }, 121 122 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 123 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC }, 124 125 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 126 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC }, 127 128 /* Belinea 10 15 55 */ 129 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 130 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 131 132 /* Envision Peripherals, Inc. EN-7100e */ 133 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 134 /* Envision EN2028 */ 135 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 136 137 /* Funai Electronics PM36B */ 138 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 139 EDID_QUIRK_DETAILED_IN_CM }, 140 141 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 142 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 143 144 /* LG Philips LCD LP154W01-A5 */ 145 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 146 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 147 148 /* Samsung SyncMaster 205BW. Note: irony */ 149 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 150 /* Samsung SyncMaster 22[5-6]BW */ 151 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 152 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 153 154 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 155 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 156 157 /* ViewSonic VA2026w */ 158 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 159 160 /* Medion MD 30217 PG */ 161 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 162 163 /* Lenovo G50 */ 164 { "SDC", 18514, EDID_QUIRK_FORCE_6BPC }, 165 166 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 167 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 168 169 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 170 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 171 172 /* Valve Index Headset */ 173 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP }, 174 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP }, 175 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP }, 176 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP }, 177 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP }, 178 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP }, 179 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP }, 180 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP }, 181 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP }, 182 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP }, 183 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP }, 184 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP }, 185 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP }, 186 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP }, 187 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP }, 188 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP }, 189 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP }, 190 191 /* HTC Vive and Vive Pro VR Headsets */ 192 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP }, 193 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP }, 194 195 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 196 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP }, 197 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP }, 198 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP }, 199 { "OVR", 0x0012, EDID_QUIRK_NON_DESKTOP }, 200 201 /* Windows Mixed Reality Headsets */ 202 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 203 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP }, 204 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP }, 205 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP }, 206 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP }, 207 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 208 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP }, 209 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP }, 210 211 /* Sony PlayStation VR Headset */ 212 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP }, 213 214 /* Sensics VR Headsets */ 215 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP }, 216 217 /* OSVR HDK and HDK2 VR Headsets */ 218 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP }, 219 }; 220 221 /* 222 * Autogenerated from the DMT spec. 223 * This table is copied from xfree86/modes/xf86EdidModes.c. 224 */ 225 static const struct drm_display_mode drm_dmt_modes[] = { 226 /* 0x01 - 640x350@85Hz */ 227 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 228 736, 832, 0, 350, 382, 385, 445, 0, 229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 230 /* 0x02 - 640x400@85Hz */ 231 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 232 736, 832, 0, 400, 401, 404, 445, 0, 233 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 234 /* 0x03 - 720x400@85Hz */ 235 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 236 828, 936, 0, 400, 401, 404, 446, 0, 237 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 238 /* 0x04 - 640x480@60Hz */ 239 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 240 752, 800, 0, 480, 490, 492, 525, 0, 241 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 242 /* 0x05 - 640x480@72Hz */ 243 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 244 704, 832, 0, 480, 489, 492, 520, 0, 245 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 246 /* 0x06 - 640x480@75Hz */ 247 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 248 720, 840, 0, 480, 481, 484, 500, 0, 249 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 250 /* 0x07 - 640x480@85Hz */ 251 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 252 752, 832, 0, 480, 481, 484, 509, 0, 253 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 254 /* 0x08 - 800x600@56Hz */ 255 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 256 896, 1024, 0, 600, 601, 603, 625, 0, 257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 258 /* 0x09 - 800x600@60Hz */ 259 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 260 968, 1056, 0, 600, 601, 605, 628, 0, 261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 262 /* 0x0a - 800x600@72Hz */ 263 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 264 976, 1040, 0, 600, 637, 643, 666, 0, 265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 266 /* 0x0b - 800x600@75Hz */ 267 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 268 896, 1056, 0, 600, 601, 604, 625, 0, 269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 270 /* 0x0c - 800x600@85Hz */ 271 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 272 896, 1048, 0, 600, 601, 604, 631, 0, 273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 274 /* 0x0d - 800x600@120Hz RB */ 275 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 276 880, 960, 0, 600, 603, 607, 636, 0, 277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 278 /* 0x0e - 848x480@60Hz */ 279 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 280 976, 1088, 0, 480, 486, 494, 517, 0, 281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 282 /* 0x0f - 1024x768@43Hz, interlace */ 283 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 284 1208, 1264, 0, 768, 768, 776, 817, 0, 285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 286 DRM_MODE_FLAG_INTERLACE) }, 287 /* 0x10 - 1024x768@60Hz */ 288 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 289 1184, 1344, 0, 768, 771, 777, 806, 0, 290 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 291 /* 0x11 - 1024x768@70Hz */ 292 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 293 1184, 1328, 0, 768, 771, 777, 806, 0, 294 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 295 /* 0x12 - 1024x768@75Hz */ 296 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 297 1136, 1312, 0, 768, 769, 772, 800, 0, 298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 299 /* 0x13 - 1024x768@85Hz */ 300 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 301 1168, 1376, 0, 768, 769, 772, 808, 0, 302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 303 /* 0x14 - 1024x768@120Hz RB */ 304 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 305 1104, 1184, 0, 768, 771, 775, 813, 0, 306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 307 /* 0x15 - 1152x864@75Hz */ 308 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 309 1344, 1600, 0, 864, 865, 868, 900, 0, 310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 311 /* 0x55 - 1280x720@60Hz */ 312 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 313 1430, 1650, 0, 720, 725, 730, 750, 0, 314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 315 /* 0x16 - 1280x768@60Hz RB */ 316 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 317 1360, 1440, 0, 768, 771, 778, 790, 0, 318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 319 /* 0x17 - 1280x768@60Hz */ 320 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 321 1472, 1664, 0, 768, 771, 778, 798, 0, 322 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 323 /* 0x18 - 1280x768@75Hz */ 324 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 325 1488, 1696, 0, 768, 771, 778, 805, 0, 326 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 327 /* 0x19 - 1280x768@85Hz */ 328 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 329 1496, 1712, 0, 768, 771, 778, 809, 0, 330 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 331 /* 0x1a - 1280x768@120Hz RB */ 332 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 333 1360, 1440, 0, 768, 771, 778, 813, 0, 334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 335 /* 0x1b - 1280x800@60Hz RB */ 336 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 337 1360, 1440, 0, 800, 803, 809, 823, 0, 338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 339 /* 0x1c - 1280x800@60Hz */ 340 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 341 1480, 1680, 0, 800, 803, 809, 831, 0, 342 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 343 /* 0x1d - 1280x800@75Hz */ 344 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 345 1488, 1696, 0, 800, 803, 809, 838, 0, 346 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 347 /* 0x1e - 1280x800@85Hz */ 348 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 349 1496, 1712, 0, 800, 803, 809, 843, 0, 350 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 351 /* 0x1f - 1280x800@120Hz RB */ 352 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 353 1360, 1440, 0, 800, 803, 809, 847, 0, 354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 355 /* 0x20 - 1280x960@60Hz */ 356 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 357 1488, 1800, 0, 960, 961, 964, 1000, 0, 358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 359 /* 0x21 - 1280x960@85Hz */ 360 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 361 1504, 1728, 0, 960, 961, 964, 1011, 0, 362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 363 /* 0x22 - 1280x960@120Hz RB */ 364 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 365 1360, 1440, 0, 960, 963, 967, 1017, 0, 366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 367 /* 0x23 - 1280x1024@60Hz */ 368 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 369 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 371 /* 0x24 - 1280x1024@75Hz */ 372 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 373 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 375 /* 0x25 - 1280x1024@85Hz */ 376 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 377 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 379 /* 0x26 - 1280x1024@120Hz RB */ 380 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 381 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 383 /* 0x27 - 1360x768@60Hz */ 384 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 385 1536, 1792, 0, 768, 771, 777, 795, 0, 386 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 387 /* 0x28 - 1360x768@120Hz RB */ 388 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 389 1440, 1520, 0, 768, 771, 776, 813, 0, 390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 391 /* 0x51 - 1366x768@60Hz */ 392 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 393 1579, 1792, 0, 768, 771, 774, 798, 0, 394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 395 /* 0x56 - 1366x768@60Hz */ 396 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 397 1436, 1500, 0, 768, 769, 772, 800, 0, 398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 399 /* 0x29 - 1400x1050@60Hz RB */ 400 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 401 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 403 /* 0x2a - 1400x1050@60Hz */ 404 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 405 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 406 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 407 /* 0x2b - 1400x1050@75Hz */ 408 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 409 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 410 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 411 /* 0x2c - 1400x1050@85Hz */ 412 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 413 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 414 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 415 /* 0x2d - 1400x1050@120Hz RB */ 416 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 417 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 419 /* 0x2e - 1440x900@60Hz RB */ 420 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 421 1520, 1600, 0, 900, 903, 909, 926, 0, 422 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 423 /* 0x2f - 1440x900@60Hz */ 424 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 425 1672, 1904, 0, 900, 903, 909, 934, 0, 426 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 427 /* 0x30 - 1440x900@75Hz */ 428 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 429 1688, 1936, 0, 900, 903, 909, 942, 0, 430 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 431 /* 0x31 - 1440x900@85Hz */ 432 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 433 1696, 1952, 0, 900, 903, 909, 948, 0, 434 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 435 /* 0x32 - 1440x900@120Hz RB */ 436 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 437 1520, 1600, 0, 900, 903, 909, 953, 0, 438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 439 /* 0x53 - 1600x900@60Hz */ 440 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 441 1704, 1800, 0, 900, 901, 904, 1000, 0, 442 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 443 /* 0x33 - 1600x1200@60Hz */ 444 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 445 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 446 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 447 /* 0x34 - 1600x1200@65Hz */ 448 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 449 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 451 /* 0x35 - 1600x1200@70Hz */ 452 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 453 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 455 /* 0x36 - 1600x1200@75Hz */ 456 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 457 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 459 /* 0x37 - 1600x1200@85Hz */ 460 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 461 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 463 /* 0x38 - 1600x1200@120Hz RB */ 464 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 465 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 467 /* 0x39 - 1680x1050@60Hz RB */ 468 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 469 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 471 /* 0x3a - 1680x1050@60Hz */ 472 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 473 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 474 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 475 /* 0x3b - 1680x1050@75Hz */ 476 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 477 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 478 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 479 /* 0x3c - 1680x1050@85Hz */ 480 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 481 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 482 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 483 /* 0x3d - 1680x1050@120Hz RB */ 484 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 485 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 487 /* 0x3e - 1792x1344@60Hz */ 488 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 489 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 490 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 491 /* 0x3f - 1792x1344@75Hz */ 492 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 493 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 494 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 495 /* 0x40 - 1792x1344@120Hz RB */ 496 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 497 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 499 /* 0x41 - 1856x1392@60Hz */ 500 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 501 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 502 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 503 /* 0x42 - 1856x1392@75Hz */ 504 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 505 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 506 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 507 /* 0x43 - 1856x1392@120Hz RB */ 508 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 509 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 511 /* 0x52 - 1920x1080@60Hz */ 512 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 513 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 514 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 515 /* 0x44 - 1920x1200@60Hz RB */ 516 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 517 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 519 /* 0x45 - 1920x1200@60Hz */ 520 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 521 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 522 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 523 /* 0x46 - 1920x1200@75Hz */ 524 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 525 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 526 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 527 /* 0x47 - 1920x1200@85Hz */ 528 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 529 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 530 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 531 /* 0x48 - 1920x1200@120Hz RB */ 532 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 533 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 535 /* 0x49 - 1920x1440@60Hz */ 536 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 537 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 538 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 539 /* 0x4a - 1920x1440@75Hz */ 540 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 541 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 542 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 543 /* 0x4b - 1920x1440@120Hz RB */ 544 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 545 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 547 /* 0x54 - 2048x1152@60Hz */ 548 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 549 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 550 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 551 /* 0x4c - 2560x1600@60Hz RB */ 552 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 553 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 554 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 555 /* 0x4d - 2560x1600@60Hz */ 556 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 557 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 558 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 559 /* 0x4e - 2560x1600@75Hz */ 560 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 561 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 562 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 563 /* 0x4f - 2560x1600@85Hz */ 564 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 565 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 566 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 567 /* 0x50 - 2560x1600@120Hz RB */ 568 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 569 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 570 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 571 /* 0x57 - 4096x2160@60Hz RB */ 572 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 573 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 574 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 575 /* 0x58 - 4096x2160@59.94Hz RB */ 576 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 577 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 578 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 579 }; 580 581 /* 582 * These more or less come from the DMT spec. The 720x400 modes are 583 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 584 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 585 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 586 * mode. 587 * 588 * The DMT modes have been fact-checked; the rest are mild guesses. 589 */ 590 static const struct drm_display_mode edid_est_modes[] = { 591 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 592 968, 1056, 0, 600, 601, 605, 628, 0, 593 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 594 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 595 896, 1024, 0, 600, 601, 603, 625, 0, 596 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 597 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 598 720, 840, 0, 480, 481, 484, 500, 0, 599 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 600 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 601 704, 832, 0, 480, 489, 492, 520, 0, 602 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 603 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 604 768, 864, 0, 480, 483, 486, 525, 0, 605 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 606 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 607 752, 800, 0, 480, 490, 492, 525, 0, 608 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 609 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 610 846, 900, 0, 400, 421, 423, 449, 0, 611 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 612 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 613 846, 900, 0, 400, 412, 414, 449, 0, 614 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 615 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 616 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 617 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 618 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 619 1136, 1312, 0, 768, 769, 772, 800, 0, 620 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 621 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 622 1184, 1328, 0, 768, 771, 777, 806, 0, 623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 624 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 625 1184, 1344, 0, 768, 771, 777, 806, 0, 626 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 627 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 628 1208, 1264, 0, 768, 768, 776, 817, 0, 629 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 630 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 631 928, 1152, 0, 624, 625, 628, 667, 0, 632 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 633 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 634 896, 1056, 0, 600, 601, 604, 625, 0, 635 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 636 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 637 976, 1040, 0, 600, 637, 643, 666, 0, 638 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 639 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 640 1344, 1600, 0, 864, 865, 868, 900, 0, 641 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 642 }; 643 644 struct minimode { 645 short w; 646 short h; 647 short r; 648 short rb; 649 }; 650 651 static const struct minimode est3_modes[] = { 652 /* byte 6 */ 653 { 640, 350, 85, 0 }, 654 { 640, 400, 85, 0 }, 655 { 720, 400, 85, 0 }, 656 { 640, 480, 85, 0 }, 657 { 848, 480, 60, 0 }, 658 { 800, 600, 85, 0 }, 659 { 1024, 768, 85, 0 }, 660 { 1152, 864, 75, 0 }, 661 /* byte 7 */ 662 { 1280, 768, 60, 1 }, 663 { 1280, 768, 60, 0 }, 664 { 1280, 768, 75, 0 }, 665 { 1280, 768, 85, 0 }, 666 { 1280, 960, 60, 0 }, 667 { 1280, 960, 85, 0 }, 668 { 1280, 1024, 60, 0 }, 669 { 1280, 1024, 85, 0 }, 670 /* byte 8 */ 671 { 1360, 768, 60, 0 }, 672 { 1440, 900, 60, 1 }, 673 { 1440, 900, 60, 0 }, 674 { 1440, 900, 75, 0 }, 675 { 1440, 900, 85, 0 }, 676 { 1400, 1050, 60, 1 }, 677 { 1400, 1050, 60, 0 }, 678 { 1400, 1050, 75, 0 }, 679 /* byte 9 */ 680 { 1400, 1050, 85, 0 }, 681 { 1680, 1050, 60, 1 }, 682 { 1680, 1050, 60, 0 }, 683 { 1680, 1050, 75, 0 }, 684 { 1680, 1050, 85, 0 }, 685 { 1600, 1200, 60, 0 }, 686 { 1600, 1200, 65, 0 }, 687 { 1600, 1200, 70, 0 }, 688 /* byte 10 */ 689 { 1600, 1200, 75, 0 }, 690 { 1600, 1200, 85, 0 }, 691 { 1792, 1344, 60, 0 }, 692 { 1792, 1344, 75, 0 }, 693 { 1856, 1392, 60, 0 }, 694 { 1856, 1392, 75, 0 }, 695 { 1920, 1200, 60, 1 }, 696 { 1920, 1200, 60, 0 }, 697 /* byte 11 */ 698 { 1920, 1200, 75, 0 }, 699 { 1920, 1200, 85, 0 }, 700 { 1920, 1440, 60, 0 }, 701 { 1920, 1440, 75, 0 }, 702 }; 703 704 static const struct minimode extra_modes[] = { 705 { 1024, 576, 60, 0 }, 706 { 1366, 768, 60, 0 }, 707 { 1600, 900, 60, 0 }, 708 { 1680, 945, 60, 0 }, 709 { 1920, 1080, 60, 0 }, 710 { 2048, 1152, 60, 0 }, 711 { 2048, 1536, 60, 0 }, 712 }; 713 714 /* 715 * From CEA/CTA-861 spec. 716 * 717 * Do not access directly, instead always use cea_mode_for_vic(). 718 */ 719 static const struct drm_display_mode edid_cea_modes_1[] = { 720 /* 1 - 640x480@60Hz 4:3 */ 721 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 722 752, 800, 0, 480, 490, 492, 525, 0, 723 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 724 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 725 /* 2 - 720x480@60Hz 4:3 */ 726 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 727 798, 858, 0, 480, 489, 495, 525, 0, 728 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 729 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 730 /* 3 - 720x480@60Hz 16:9 */ 731 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 732 798, 858, 0, 480, 489, 495, 525, 0, 733 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 734 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 735 /* 4 - 1280x720@60Hz 16:9 */ 736 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 737 1430, 1650, 0, 720, 725, 730, 750, 0, 738 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 739 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 740 /* 5 - 1920x1080i@60Hz 16:9 */ 741 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 742 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 743 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 744 DRM_MODE_FLAG_INTERLACE), 745 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 746 /* 6 - 720(1440)x480i@60Hz 4:3 */ 747 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 748 801, 858, 0, 480, 488, 494, 525, 0, 749 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 750 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 751 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 752 /* 7 - 720(1440)x480i@60Hz 16:9 */ 753 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 754 801, 858, 0, 480, 488, 494, 525, 0, 755 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 756 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 757 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 758 /* 8 - 720(1440)x240@60Hz 4:3 */ 759 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 760 801, 858, 0, 240, 244, 247, 262, 0, 761 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 762 DRM_MODE_FLAG_DBLCLK), 763 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 764 /* 9 - 720(1440)x240@60Hz 16:9 */ 765 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 766 801, 858, 0, 240, 244, 247, 262, 0, 767 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 768 DRM_MODE_FLAG_DBLCLK), 769 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 770 /* 10 - 2880x480i@60Hz 4:3 */ 771 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 772 3204, 3432, 0, 480, 488, 494, 525, 0, 773 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 774 DRM_MODE_FLAG_INTERLACE), 775 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 776 /* 11 - 2880x480i@60Hz 16:9 */ 777 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 778 3204, 3432, 0, 480, 488, 494, 525, 0, 779 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 780 DRM_MODE_FLAG_INTERLACE), 781 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 782 /* 12 - 2880x240@60Hz 4:3 */ 783 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 784 3204, 3432, 0, 240, 244, 247, 262, 0, 785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 786 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 787 /* 13 - 2880x240@60Hz 16:9 */ 788 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 789 3204, 3432, 0, 240, 244, 247, 262, 0, 790 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 791 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 792 /* 14 - 1440x480@60Hz 4:3 */ 793 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 794 1596, 1716, 0, 480, 489, 495, 525, 0, 795 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 796 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 797 /* 15 - 1440x480@60Hz 16:9 */ 798 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 799 1596, 1716, 0, 480, 489, 495, 525, 0, 800 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 801 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 802 /* 16 - 1920x1080@60Hz 16:9 */ 803 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 804 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 805 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 806 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 807 /* 17 - 720x576@50Hz 4:3 */ 808 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 809 796, 864, 0, 576, 581, 586, 625, 0, 810 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 811 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 812 /* 18 - 720x576@50Hz 16:9 */ 813 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 814 796, 864, 0, 576, 581, 586, 625, 0, 815 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 816 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 817 /* 19 - 1280x720@50Hz 16:9 */ 818 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 819 1760, 1980, 0, 720, 725, 730, 750, 0, 820 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 821 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 822 /* 20 - 1920x1080i@50Hz 16:9 */ 823 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 824 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 825 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 826 DRM_MODE_FLAG_INTERLACE), 827 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 828 /* 21 - 720(1440)x576i@50Hz 4:3 */ 829 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 830 795, 864, 0, 576, 580, 586, 625, 0, 831 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 832 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 833 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 834 /* 22 - 720(1440)x576i@50Hz 16:9 */ 835 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 836 795, 864, 0, 576, 580, 586, 625, 0, 837 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 838 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 839 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 840 /* 23 - 720(1440)x288@50Hz 4:3 */ 841 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 842 795, 864, 0, 288, 290, 293, 312, 0, 843 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 844 DRM_MODE_FLAG_DBLCLK), 845 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 846 /* 24 - 720(1440)x288@50Hz 16:9 */ 847 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 848 795, 864, 0, 288, 290, 293, 312, 0, 849 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 850 DRM_MODE_FLAG_DBLCLK), 851 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 852 /* 25 - 2880x576i@50Hz 4:3 */ 853 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 854 3180, 3456, 0, 576, 580, 586, 625, 0, 855 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 856 DRM_MODE_FLAG_INTERLACE), 857 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 858 /* 26 - 2880x576i@50Hz 16:9 */ 859 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 860 3180, 3456, 0, 576, 580, 586, 625, 0, 861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 862 DRM_MODE_FLAG_INTERLACE), 863 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 864 /* 27 - 2880x288@50Hz 4:3 */ 865 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 866 3180, 3456, 0, 288, 290, 293, 312, 0, 867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 868 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 869 /* 28 - 2880x288@50Hz 16:9 */ 870 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 871 3180, 3456, 0, 288, 290, 293, 312, 0, 872 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 873 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 874 /* 29 - 1440x576@50Hz 4:3 */ 875 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 876 1592, 1728, 0, 576, 581, 586, 625, 0, 877 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 878 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 879 /* 30 - 1440x576@50Hz 16:9 */ 880 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 881 1592, 1728, 0, 576, 581, 586, 625, 0, 882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 883 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 884 /* 31 - 1920x1080@50Hz 16:9 */ 885 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 886 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 887 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 888 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 889 /* 32 - 1920x1080@24Hz 16:9 */ 890 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 891 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 892 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 893 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 894 /* 33 - 1920x1080@25Hz 16:9 */ 895 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 896 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 897 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 898 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 899 /* 34 - 1920x1080@30Hz 16:9 */ 900 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 901 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 902 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 903 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 904 /* 35 - 2880x480@60Hz 4:3 */ 905 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 906 3192, 3432, 0, 480, 489, 495, 525, 0, 907 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 908 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 909 /* 36 - 2880x480@60Hz 16:9 */ 910 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 911 3192, 3432, 0, 480, 489, 495, 525, 0, 912 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 913 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 914 /* 37 - 2880x576@50Hz 4:3 */ 915 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 916 3184, 3456, 0, 576, 581, 586, 625, 0, 917 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 918 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 919 /* 38 - 2880x576@50Hz 16:9 */ 920 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 921 3184, 3456, 0, 576, 581, 586, 625, 0, 922 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 923 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 924 /* 39 - 1920x1080i@50Hz 16:9 */ 925 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 926 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 927 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 928 DRM_MODE_FLAG_INTERLACE), 929 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 930 /* 40 - 1920x1080i@100Hz 16:9 */ 931 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 932 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 933 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 934 DRM_MODE_FLAG_INTERLACE), 935 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 936 /* 41 - 1280x720@100Hz 16:9 */ 937 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 938 1760, 1980, 0, 720, 725, 730, 750, 0, 939 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 940 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 941 /* 42 - 720x576@100Hz 4:3 */ 942 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 943 796, 864, 0, 576, 581, 586, 625, 0, 944 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 945 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 946 /* 43 - 720x576@100Hz 16:9 */ 947 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 948 796, 864, 0, 576, 581, 586, 625, 0, 949 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 950 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 951 /* 44 - 720(1440)x576i@100Hz 4:3 */ 952 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 953 795, 864, 0, 576, 580, 586, 625, 0, 954 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 955 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 956 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 957 /* 45 - 720(1440)x576i@100Hz 16:9 */ 958 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 959 795, 864, 0, 576, 580, 586, 625, 0, 960 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 961 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 962 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 963 /* 46 - 1920x1080i@120Hz 16:9 */ 964 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 965 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 966 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 967 DRM_MODE_FLAG_INTERLACE), 968 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 969 /* 47 - 1280x720@120Hz 16:9 */ 970 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 971 1430, 1650, 0, 720, 725, 730, 750, 0, 972 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 973 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 974 /* 48 - 720x480@120Hz 4:3 */ 975 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 976 798, 858, 0, 480, 489, 495, 525, 0, 977 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 978 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 979 /* 49 - 720x480@120Hz 16:9 */ 980 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 981 798, 858, 0, 480, 489, 495, 525, 0, 982 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 983 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 984 /* 50 - 720(1440)x480i@120Hz 4:3 */ 985 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 986 801, 858, 0, 480, 488, 494, 525, 0, 987 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 988 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 989 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 990 /* 51 - 720(1440)x480i@120Hz 16:9 */ 991 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 992 801, 858, 0, 480, 488, 494, 525, 0, 993 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 994 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 995 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 996 /* 52 - 720x576@200Hz 4:3 */ 997 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 998 796, 864, 0, 576, 581, 586, 625, 0, 999 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1000 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1001 /* 53 - 720x576@200Hz 16:9 */ 1002 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1003 796, 864, 0, 576, 581, 586, 625, 0, 1004 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1005 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1006 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1007 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1008 795, 864, 0, 576, 580, 586, 625, 0, 1009 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1010 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1011 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1012 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1013 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1014 795, 864, 0, 576, 580, 586, 625, 0, 1015 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1016 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1017 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1018 /* 56 - 720x480@240Hz 4:3 */ 1019 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1020 798, 858, 0, 480, 489, 495, 525, 0, 1021 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1022 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1023 /* 57 - 720x480@240Hz 16:9 */ 1024 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1025 798, 858, 0, 480, 489, 495, 525, 0, 1026 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1027 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1028 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1029 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1030 801, 858, 0, 480, 488, 494, 525, 0, 1031 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1032 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1033 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1034 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1035 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1036 801, 858, 0, 480, 488, 494, 525, 0, 1037 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1038 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1039 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1040 /* 60 - 1280x720@24Hz 16:9 */ 1041 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1042 3080, 3300, 0, 720, 725, 730, 750, 0, 1043 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1044 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1045 /* 61 - 1280x720@25Hz 16:9 */ 1046 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1047 3740, 3960, 0, 720, 725, 730, 750, 0, 1048 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1049 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1050 /* 62 - 1280x720@30Hz 16:9 */ 1051 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1052 3080, 3300, 0, 720, 725, 730, 750, 0, 1053 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1054 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1055 /* 63 - 1920x1080@120Hz 16:9 */ 1056 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1057 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1058 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1059 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1060 /* 64 - 1920x1080@100Hz 16:9 */ 1061 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1062 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1063 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1064 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1065 /* 65 - 1280x720@24Hz 64:27 */ 1066 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1067 3080, 3300, 0, 720, 725, 730, 750, 0, 1068 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1069 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1070 /* 66 - 1280x720@25Hz 64:27 */ 1071 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1072 3740, 3960, 0, 720, 725, 730, 750, 0, 1073 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1074 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1075 /* 67 - 1280x720@30Hz 64:27 */ 1076 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1077 3080, 3300, 0, 720, 725, 730, 750, 0, 1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1079 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1080 /* 68 - 1280x720@50Hz 64:27 */ 1081 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1082 1760, 1980, 0, 720, 725, 730, 750, 0, 1083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1084 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1085 /* 69 - 1280x720@60Hz 64:27 */ 1086 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1087 1430, 1650, 0, 720, 725, 730, 750, 0, 1088 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1089 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1090 /* 70 - 1280x720@100Hz 64:27 */ 1091 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1092 1760, 1980, 0, 720, 725, 730, 750, 0, 1093 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1094 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1095 /* 71 - 1280x720@120Hz 64:27 */ 1096 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1097 1430, 1650, 0, 720, 725, 730, 750, 0, 1098 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1099 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1100 /* 72 - 1920x1080@24Hz 64:27 */ 1101 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1102 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1103 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1104 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1105 /* 73 - 1920x1080@25Hz 64:27 */ 1106 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1107 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1109 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1110 /* 74 - 1920x1080@30Hz 64:27 */ 1111 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1112 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1113 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1114 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1115 /* 75 - 1920x1080@50Hz 64:27 */ 1116 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1117 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1118 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1119 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1120 /* 76 - 1920x1080@60Hz 64:27 */ 1121 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1122 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1123 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1124 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1125 /* 77 - 1920x1080@100Hz 64:27 */ 1126 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1127 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1129 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1130 /* 78 - 1920x1080@120Hz 64:27 */ 1131 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1132 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1133 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1134 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1135 /* 79 - 1680x720@24Hz 64:27 */ 1136 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1137 3080, 3300, 0, 720, 725, 730, 750, 0, 1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1139 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1140 /* 80 - 1680x720@25Hz 64:27 */ 1141 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1142 2948, 3168, 0, 720, 725, 730, 750, 0, 1143 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1144 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1145 /* 81 - 1680x720@30Hz 64:27 */ 1146 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1147 2420, 2640, 0, 720, 725, 730, 750, 0, 1148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1149 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1150 /* 82 - 1680x720@50Hz 64:27 */ 1151 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1152 1980, 2200, 0, 720, 725, 730, 750, 0, 1153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1154 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1155 /* 83 - 1680x720@60Hz 64:27 */ 1156 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1157 1980, 2200, 0, 720, 725, 730, 750, 0, 1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1159 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1160 /* 84 - 1680x720@100Hz 64:27 */ 1161 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1162 1780, 2000, 0, 720, 725, 730, 825, 0, 1163 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1164 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1165 /* 85 - 1680x720@120Hz 64:27 */ 1166 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1167 1780, 2000, 0, 720, 725, 730, 825, 0, 1168 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1169 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1170 /* 86 - 2560x1080@24Hz 64:27 */ 1171 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1172 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1174 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1175 /* 87 - 2560x1080@25Hz 64:27 */ 1176 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1177 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1179 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1180 /* 88 - 2560x1080@30Hz 64:27 */ 1181 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1182 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1184 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1185 /* 89 - 2560x1080@50Hz 64:27 */ 1186 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1187 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1189 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1190 /* 90 - 2560x1080@60Hz 64:27 */ 1191 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1192 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1194 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1195 /* 91 - 2560x1080@100Hz 64:27 */ 1196 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1197 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1199 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1200 /* 92 - 2560x1080@120Hz 64:27 */ 1201 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1202 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1204 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1205 /* 93 - 3840x2160@24Hz 16:9 */ 1206 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1207 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1209 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1210 /* 94 - 3840x2160@25Hz 16:9 */ 1211 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1212 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1214 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1215 /* 95 - 3840x2160@30Hz 16:9 */ 1216 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1217 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1219 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1220 /* 96 - 3840x2160@50Hz 16:9 */ 1221 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1222 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1224 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1225 /* 97 - 3840x2160@60Hz 16:9 */ 1226 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1227 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1229 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1230 /* 98 - 4096x2160@24Hz 256:135 */ 1231 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1232 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1234 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1235 /* 99 - 4096x2160@25Hz 256:135 */ 1236 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1237 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1239 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1240 /* 100 - 4096x2160@30Hz 256:135 */ 1241 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1242 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1244 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1245 /* 101 - 4096x2160@50Hz 256:135 */ 1246 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1247 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1249 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1250 /* 102 - 4096x2160@60Hz 256:135 */ 1251 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1252 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1254 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1255 /* 103 - 3840x2160@24Hz 64:27 */ 1256 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1257 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1259 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1260 /* 104 - 3840x2160@25Hz 64:27 */ 1261 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1262 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1264 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1265 /* 105 - 3840x2160@30Hz 64:27 */ 1266 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1267 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1269 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1270 /* 106 - 3840x2160@50Hz 64:27 */ 1271 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1272 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1274 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1275 /* 107 - 3840x2160@60Hz 64:27 */ 1276 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1277 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1279 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1280 /* 108 - 1280x720@48Hz 16:9 */ 1281 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1282 2280, 2500, 0, 720, 725, 730, 750, 0, 1283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1284 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1285 /* 109 - 1280x720@48Hz 64:27 */ 1286 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1287 2280, 2500, 0, 720, 725, 730, 750, 0, 1288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1289 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1290 /* 110 - 1680x720@48Hz 64:27 */ 1291 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1292 2530, 2750, 0, 720, 725, 730, 750, 0, 1293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1294 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1295 /* 111 - 1920x1080@48Hz 16:9 */ 1296 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1297 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1299 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1300 /* 112 - 1920x1080@48Hz 64:27 */ 1301 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1302 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1304 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1305 /* 113 - 2560x1080@48Hz 64:27 */ 1306 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1307 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1309 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1310 /* 114 - 3840x2160@48Hz 16:9 */ 1311 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1312 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1314 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1315 /* 115 - 4096x2160@48Hz 256:135 */ 1316 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1317 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1319 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1320 /* 116 - 3840x2160@48Hz 64:27 */ 1321 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1322 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1324 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1325 /* 117 - 3840x2160@100Hz 16:9 */ 1326 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1327 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1329 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1330 /* 118 - 3840x2160@120Hz 16:9 */ 1331 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1332 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1334 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1335 /* 119 - 3840x2160@100Hz 64:27 */ 1336 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1337 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1339 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1340 /* 120 - 3840x2160@120Hz 64:27 */ 1341 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1342 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1344 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1345 /* 121 - 5120x2160@24Hz 64:27 */ 1346 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1347 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1349 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1350 /* 122 - 5120x2160@25Hz 64:27 */ 1351 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1352 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1354 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1355 /* 123 - 5120x2160@30Hz 64:27 */ 1356 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1357 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1359 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1360 /* 124 - 5120x2160@48Hz 64:27 */ 1361 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1362 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1364 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1365 /* 125 - 5120x2160@50Hz 64:27 */ 1366 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1367 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1369 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1370 /* 126 - 5120x2160@60Hz 64:27 */ 1371 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1372 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1374 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1375 /* 127 - 5120x2160@100Hz 64:27 */ 1376 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1377 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1379 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1380 }; 1381 1382 /* 1383 * From CEA/CTA-861 spec. 1384 * 1385 * Do not access directly, instead always use cea_mode_for_vic(). 1386 */ 1387 static const struct drm_display_mode edid_cea_modes_193[] = { 1388 /* 193 - 5120x2160@120Hz 64:27 */ 1389 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1390 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1391 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1392 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1393 /* 194 - 7680x4320@24Hz 16:9 */ 1394 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1395 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1397 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1398 /* 195 - 7680x4320@25Hz 16:9 */ 1399 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1400 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1402 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1403 /* 196 - 7680x4320@30Hz 16:9 */ 1404 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1405 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1407 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1408 /* 197 - 7680x4320@48Hz 16:9 */ 1409 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1410 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1412 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1413 /* 198 - 7680x4320@50Hz 16:9 */ 1414 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1415 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1417 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1418 /* 199 - 7680x4320@60Hz 16:9 */ 1419 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1420 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1422 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1423 /* 200 - 7680x4320@100Hz 16:9 */ 1424 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1425 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1426 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1427 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1428 /* 201 - 7680x4320@120Hz 16:9 */ 1429 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1430 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1432 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1433 /* 202 - 7680x4320@24Hz 64:27 */ 1434 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1435 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1437 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1438 /* 203 - 7680x4320@25Hz 64:27 */ 1439 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1440 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1442 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1443 /* 204 - 7680x4320@30Hz 64:27 */ 1444 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1445 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1446 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1447 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1448 /* 205 - 7680x4320@48Hz 64:27 */ 1449 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1450 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1451 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1452 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1453 /* 206 - 7680x4320@50Hz 64:27 */ 1454 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1455 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1457 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1458 /* 207 - 7680x4320@60Hz 64:27 */ 1459 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1460 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1462 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1463 /* 208 - 7680x4320@100Hz 64:27 */ 1464 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1465 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1467 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1468 /* 209 - 7680x4320@120Hz 64:27 */ 1469 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1470 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1472 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1473 /* 210 - 10240x4320@24Hz 64:27 */ 1474 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1475 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1477 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1478 /* 211 - 10240x4320@25Hz 64:27 */ 1479 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1480 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1482 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1483 /* 212 - 10240x4320@30Hz 64:27 */ 1484 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1485 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1487 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1488 /* 213 - 10240x4320@48Hz 64:27 */ 1489 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1490 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1492 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1493 /* 214 - 10240x4320@50Hz 64:27 */ 1494 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1495 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1497 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1498 /* 215 - 10240x4320@60Hz 64:27 */ 1499 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1500 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1502 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1503 /* 216 - 10240x4320@100Hz 64:27 */ 1504 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1505 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1507 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1508 /* 217 - 10240x4320@120Hz 64:27 */ 1509 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1510 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1512 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1513 /* 218 - 4096x2160@100Hz 256:135 */ 1514 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1515 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1517 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1518 /* 219 - 4096x2160@120Hz 256:135 */ 1519 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1520 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1522 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1523 }; 1524 1525 /* 1526 * HDMI 1.4 4k modes. Index using the VIC. 1527 */ 1528 static const struct drm_display_mode edid_4k_modes[] = { 1529 /* 0 - dummy, VICs start at 1 */ 1530 { }, 1531 /* 1 - 3840x2160@30Hz */ 1532 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1533 3840, 4016, 4104, 4400, 0, 1534 2160, 2168, 2178, 2250, 0, 1535 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1536 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1537 /* 2 - 3840x2160@25Hz */ 1538 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1539 3840, 4896, 4984, 5280, 0, 1540 2160, 2168, 2178, 2250, 0, 1541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1542 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1543 /* 3 - 3840x2160@24Hz */ 1544 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1545 3840, 5116, 5204, 5500, 0, 1546 2160, 2168, 2178, 2250, 0, 1547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1548 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1549 /* 4 - 4096x2160@24Hz (SMPTE) */ 1550 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1551 4096, 5116, 5204, 5500, 0, 1552 2160, 2168, 2178, 2250, 0, 1553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1554 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1555 }; 1556 1557 /*** DDC fetch and block validation ***/ 1558 1559 static const u8 edid_header[] = { 1560 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1561 }; 1562 1563 /** 1564 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1565 * @raw_edid: pointer to raw base EDID block 1566 * 1567 * Sanity check the header of the base EDID block. 1568 * 1569 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1570 */ 1571 int drm_edid_header_is_valid(const u8 *raw_edid) 1572 { 1573 int i, score = 0; 1574 1575 for (i = 0; i < sizeof(edid_header); i++) 1576 if (raw_edid[i] == edid_header[i]) 1577 score++; 1578 1579 return score; 1580 } 1581 EXPORT_SYMBOL(drm_edid_header_is_valid); 1582 1583 static int edid_fixup __read_mostly = 6; 1584 module_param_named(edid_fixup, edid_fixup, int, 0400); 1585 MODULE_PARM_DESC(edid_fixup, 1586 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1587 1588 static int drm_edid_block_checksum(const u8 *raw_edid) 1589 { 1590 int i; 1591 u8 csum = 0, crc = 0; 1592 1593 for (i = 0; i < EDID_LENGTH - 1; i++) 1594 csum += raw_edid[i]; 1595 1596 crc = 0x100 - csum; 1597 1598 return crc; 1599 } 1600 1601 static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum) 1602 { 1603 if (raw_edid[EDID_LENGTH - 1] != real_checksum) 1604 return true; 1605 else 1606 return false; 1607 } 1608 1609 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1610 { 1611 if (memchr_inv(in_edid, 0, length)) 1612 return false; 1613 1614 return true; 1615 } 1616 1617 /** 1618 * drm_edid_are_equal - compare two edid blobs. 1619 * @edid1: pointer to first blob 1620 * @edid2: pointer to second blob 1621 * This helper can be used during probing to determine if 1622 * edid had changed. 1623 */ 1624 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2) 1625 { 1626 int edid1_len, edid2_len; 1627 bool edid1_present = edid1 != NULL; 1628 bool edid2_present = edid2 != NULL; 1629 1630 if (edid1_present != edid2_present) 1631 return false; 1632 1633 if (edid1) { 1634 edid1_len = EDID_LENGTH * (1 + edid1->extensions); 1635 edid2_len = EDID_LENGTH * (1 + edid2->extensions); 1636 1637 if (edid1_len != edid2_len) 1638 return false; 1639 1640 if (memcmp(edid1, edid2, edid1_len)) 1641 return false; 1642 } 1643 1644 return true; 1645 } 1646 EXPORT_SYMBOL(drm_edid_are_equal); 1647 1648 /** 1649 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1650 * @raw_edid: pointer to raw EDID block 1651 * @block: type of block to validate (0 for base, extension otherwise) 1652 * @print_bad_edid: if true, dump bad EDID blocks to the console 1653 * @edid_corrupt: if true, the header or checksum is invalid 1654 * 1655 * Validate a base or extension EDID block and optionally dump bad blocks to 1656 * the console. 1657 * 1658 * Return: True if the block is valid, false otherwise. 1659 */ 1660 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1661 bool *edid_corrupt) 1662 { 1663 u8 csum; 1664 struct edid *edid = (struct edid *)raw_edid; 1665 1666 if (WARN_ON(!raw_edid)) 1667 return false; 1668 1669 if (edid_fixup > 8 || edid_fixup < 0) 1670 edid_fixup = 6; 1671 1672 if (block == 0) { 1673 int score = drm_edid_header_is_valid(raw_edid); 1674 1675 if (score == 8) { 1676 if (edid_corrupt) 1677 *edid_corrupt = false; 1678 } else if (score >= edid_fixup) { 1679 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1680 * The corrupt flag needs to be set here otherwise, the 1681 * fix-up code here will correct the problem, the 1682 * checksum is correct and the test fails 1683 */ 1684 if (edid_corrupt) 1685 *edid_corrupt = true; 1686 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1687 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1688 } else { 1689 if (edid_corrupt) 1690 *edid_corrupt = true; 1691 goto bad; 1692 } 1693 } 1694 1695 csum = drm_edid_block_checksum(raw_edid); 1696 if (drm_edid_block_checksum_diff(raw_edid, csum)) { 1697 if (edid_corrupt) 1698 *edid_corrupt = true; 1699 1700 /* allow CEA to slide through, switches mangle this */ 1701 if (raw_edid[0] == CEA_EXT) { 1702 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum); 1703 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n"); 1704 } else { 1705 if (print_bad_edid) 1706 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum); 1707 1708 goto bad; 1709 } 1710 } 1711 1712 /* per-block-type checks */ 1713 switch (raw_edid[0]) { 1714 case 0: /* base */ 1715 if (edid->version != 1) { 1716 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version); 1717 goto bad; 1718 } 1719 1720 if (edid->revision > 4) 1721 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1722 break; 1723 1724 default: 1725 break; 1726 } 1727 1728 return true; 1729 1730 bad: 1731 if (print_bad_edid) { 1732 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1733 pr_notice("EDID block is all zeroes\n"); 1734 } else { 1735 pr_notice("Raw EDID:\n"); 1736 print_hex_dump(KERN_NOTICE, 1737 " \t", DUMP_PREFIX_NONE, 16, 1, 1738 raw_edid, EDID_LENGTH, false); 1739 } 1740 } 1741 return false; 1742 } 1743 EXPORT_SYMBOL(drm_edid_block_valid); 1744 1745 /** 1746 * drm_edid_is_valid - sanity check EDID data 1747 * @edid: EDID data 1748 * 1749 * Sanity-check an entire EDID record (including extensions) 1750 * 1751 * Return: True if the EDID data is valid, false otherwise. 1752 */ 1753 bool drm_edid_is_valid(struct edid *edid) 1754 { 1755 int i; 1756 u8 *raw = (u8 *)edid; 1757 1758 if (!edid) 1759 return false; 1760 1761 for (i = 0; i <= edid->extensions; i++) 1762 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1763 return false; 1764 1765 return true; 1766 } 1767 EXPORT_SYMBOL(drm_edid_is_valid); 1768 1769 #define DDC_SEGMENT_ADDR 0x30 1770 /** 1771 * drm_do_probe_ddc_edid() - get EDID information via I2C 1772 * @data: I2C device adapter 1773 * @buf: EDID data buffer to be filled 1774 * @block: 128 byte EDID block to start fetching from 1775 * @len: EDID data buffer length to fetch 1776 * 1777 * Try to fetch EDID information by calling I2C driver functions. 1778 * 1779 * Return: 0 on success or -1 on failure. 1780 */ 1781 static int 1782 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1783 { 1784 struct i2c_adapter *adapter = data; 1785 unsigned char start = block * EDID_LENGTH; 1786 unsigned char segment = block >> 1; 1787 unsigned char xfers = segment ? 3 : 2; 1788 int ret, retries = 5; 1789 1790 /* 1791 * The core I2C driver will automatically retry the transfer if the 1792 * adapter reports EAGAIN. However, we find that bit-banging transfers 1793 * are susceptible to errors under a heavily loaded machine and 1794 * generate spurious NAKs and timeouts. Retrying the transfer 1795 * of the individual block a few times seems to overcome this. 1796 */ 1797 do { 1798 struct i2c_msg msgs[] = { 1799 { 1800 .addr = DDC_SEGMENT_ADDR, 1801 .flags = 0, 1802 .len = 1, 1803 .buf = &segment, 1804 }, { 1805 .addr = DDC_ADDR, 1806 .flags = 0, 1807 .len = 1, 1808 .buf = &start, 1809 }, { 1810 .addr = DDC_ADDR, 1811 .flags = I2C_M_RD, 1812 .len = len, 1813 .buf = buf, 1814 } 1815 }; 1816 1817 /* 1818 * Avoid sending the segment addr to not upset non-compliant 1819 * DDC monitors. 1820 */ 1821 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1822 1823 if (ret == -ENXIO) { 1824 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1825 adapter->name); 1826 break; 1827 } 1828 } while (ret != xfers && --retries); 1829 1830 return ret == xfers ? 0 : -1; 1831 } 1832 1833 static void connector_bad_edid(struct drm_connector *connector, 1834 u8 *edid, int num_blocks) 1835 { 1836 int i; 1837 u8 last_block; 1838 1839 /* 1840 * 0x7e in the EDID is the number of extension blocks. The EDID 1841 * is 1 (base block) + num_ext_blocks big. That means we can think 1842 * of 0x7e in the EDID of the _index_ of the last block in the 1843 * combined chunk of memory. 1844 */ 1845 last_block = edid[0x7e]; 1846 1847 /* Calculate real checksum for the last edid extension block data */ 1848 if (last_block < num_blocks) 1849 connector->real_edid_checksum = 1850 drm_edid_block_checksum(edid + last_block * EDID_LENGTH); 1851 1852 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 1853 return; 1854 1855 drm_dbg_kms(connector->dev, "%s: EDID is invalid:\n", connector->name); 1856 for (i = 0; i < num_blocks; i++) { 1857 u8 *block = edid + i * EDID_LENGTH; 1858 char prefix[20]; 1859 1860 if (drm_edid_is_zero(block, EDID_LENGTH)) 1861 snprintf(prefix, sizeof(prefix), "\t[%02x] ZERO ", i); 1862 else if (!drm_edid_block_valid(block, i, false, NULL)) 1863 snprintf(prefix, sizeof(prefix), "\t[%02x] BAD ", i); 1864 else 1865 snprintf(prefix, sizeof(prefix), "\t[%02x] GOOD ", i); 1866 1867 print_hex_dump(KERN_DEBUG, 1868 prefix, DUMP_PREFIX_NONE, 16, 1, 1869 block, EDID_LENGTH, false); 1870 } 1871 } 1872 1873 /* Get override or firmware EDID */ 1874 static struct edid *drm_get_override_edid(struct drm_connector *connector) 1875 { 1876 struct edid *override = NULL; 1877 1878 if (connector->override_edid) 1879 override = drm_edid_duplicate(connector->edid_blob_ptr->data); 1880 1881 if (!override) 1882 override = drm_load_edid_firmware(connector); 1883 1884 return IS_ERR(override) ? NULL : override; 1885 } 1886 1887 /** 1888 * drm_add_override_edid_modes - add modes from override/firmware EDID 1889 * @connector: connector we're probing 1890 * 1891 * Add modes from the override/firmware EDID, if available. Only to be used from 1892 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 1893 * failed during drm_get_edid() and caused the override/firmware EDID to be 1894 * skipped. 1895 * 1896 * Return: The number of modes added or 0 if we couldn't find any. 1897 */ 1898 int drm_add_override_edid_modes(struct drm_connector *connector) 1899 { 1900 struct edid *override; 1901 int num_modes = 0; 1902 1903 override = drm_get_override_edid(connector); 1904 if (override) { 1905 drm_connector_update_edid_property(connector, override); 1906 num_modes = drm_add_edid_modes(connector, override); 1907 kfree(override); 1908 1909 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 1910 connector->base.id, connector->name, num_modes); 1911 } 1912 1913 return num_modes; 1914 } 1915 EXPORT_SYMBOL(drm_add_override_edid_modes); 1916 1917 /** 1918 * drm_do_get_edid - get EDID data using a custom EDID block read function 1919 * @connector: connector we're probing 1920 * @get_edid_block: EDID block read function 1921 * @data: private data passed to the block read function 1922 * 1923 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1924 * exposes a different interface to read EDID blocks this function can be used 1925 * to get EDID data using a custom block read function. 1926 * 1927 * As in the general case the DDC bus is accessible by the kernel at the I2C 1928 * level, drivers must make all reasonable efforts to expose it as an I2C 1929 * adapter and use drm_get_edid() instead of abusing this function. 1930 * 1931 * The EDID may be overridden using debugfs override_edid or firmware EDID 1932 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 1933 * order. Having either of them bypasses actual EDID reads. 1934 * 1935 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1936 */ 1937 struct edid *drm_do_get_edid(struct drm_connector *connector, 1938 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1939 size_t len), 1940 void *data) 1941 { 1942 int i, j = 0, valid_extensions = 0; 1943 u8 *edid, *new; 1944 struct edid *override; 1945 1946 override = drm_get_override_edid(connector); 1947 if (override) 1948 return override; 1949 1950 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1951 return NULL; 1952 1953 /* base block fetch */ 1954 for (i = 0; i < 4; i++) { 1955 if (get_edid_block(data, edid, 0, EDID_LENGTH)) 1956 goto out; 1957 if (drm_edid_block_valid(edid, 0, false, 1958 &connector->edid_corrupt)) 1959 break; 1960 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) { 1961 connector->null_edid_counter++; 1962 goto carp; 1963 } 1964 } 1965 if (i == 4) 1966 goto carp; 1967 1968 /* if there's no extensions, we're done */ 1969 valid_extensions = edid[0x7e]; 1970 if (valid_extensions == 0) 1971 return (struct edid *)edid; 1972 1973 #ifdef __linux__ 1974 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1975 if (!new) 1976 goto out; 1977 #else 1978 new = kmalloc((valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1979 if (!new) 1980 goto out; 1981 memcpy(new, edid, EDID_LENGTH); 1982 kfree(edid); 1983 #endif 1984 edid = new; 1985 1986 for (j = 1; j <= edid[0x7e]; j++) { 1987 u8 *block = edid + j * EDID_LENGTH; 1988 1989 for (i = 0; i < 4; i++) { 1990 if (get_edid_block(data, block, j, EDID_LENGTH)) 1991 goto out; 1992 if (drm_edid_block_valid(block, j, false, NULL)) 1993 break; 1994 } 1995 1996 if (i == 4) 1997 valid_extensions--; 1998 } 1999 2000 if (valid_extensions != edid[0x7e]) { 2001 u8 *base; 2002 2003 connector_bad_edid(connector, edid, edid[0x7e] + 1); 2004 2005 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions; 2006 edid[0x7e] = valid_extensions; 2007 2008 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH, 2009 GFP_KERNEL); 2010 if (!new) 2011 goto out; 2012 2013 base = new; 2014 for (i = 0; i <= edid[0x7e]; i++) { 2015 u8 *block = edid + i * EDID_LENGTH; 2016 2017 if (!drm_edid_block_valid(block, i, false, NULL)) 2018 continue; 2019 2020 memcpy(base, block, EDID_LENGTH); 2021 base += EDID_LENGTH; 2022 } 2023 2024 kfree(edid); 2025 edid = new; 2026 } 2027 2028 return (struct edid *)edid; 2029 2030 carp: 2031 connector_bad_edid(connector, edid, 1); 2032 out: 2033 kfree(edid); 2034 return NULL; 2035 } 2036 EXPORT_SYMBOL_GPL(drm_do_get_edid); 2037 2038 /** 2039 * drm_probe_ddc() - probe DDC presence 2040 * @adapter: I2C adapter to probe 2041 * 2042 * Return: True on success, false on failure. 2043 */ 2044 bool 2045 drm_probe_ddc(struct i2c_adapter *adapter) 2046 { 2047 unsigned char out; 2048 2049 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2050 } 2051 EXPORT_SYMBOL(drm_probe_ddc); 2052 2053 /** 2054 * drm_get_edid - get EDID data, if available 2055 * @connector: connector we're probing 2056 * @adapter: I2C adapter to use for DDC 2057 * 2058 * Poke the given I2C channel to grab EDID data if possible. If found, 2059 * attach it to the connector. 2060 * 2061 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2062 */ 2063 struct edid *drm_get_edid(struct drm_connector *connector, 2064 struct i2c_adapter *adapter) 2065 { 2066 struct edid *edid; 2067 2068 if (connector->force == DRM_FORCE_OFF) 2069 return NULL; 2070 2071 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2072 return NULL; 2073 2074 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 2075 drm_connector_update_edid_property(connector, edid); 2076 return edid; 2077 } 2078 EXPORT_SYMBOL(drm_get_edid); 2079 2080 /** 2081 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2082 * @connector: connector we're probing 2083 * @adapter: I2C adapter to use for DDC 2084 * 2085 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2086 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2087 * switch DDC to the GPU which is retrieving EDID. 2088 * 2089 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2090 */ 2091 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2092 struct i2c_adapter *adapter) 2093 { 2094 STUB(); 2095 return NULL; 2096 #ifdef notyet 2097 struct drm_device *dev = connector->dev; 2098 struct pci_dev *pdev = to_pci_dev(dev->dev); 2099 struct edid *edid; 2100 2101 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2102 return NULL; 2103 2104 vga_switcheroo_lock_ddc(pdev); 2105 edid = drm_get_edid(connector, adapter); 2106 vga_switcheroo_unlock_ddc(pdev); 2107 2108 return edid; 2109 #endif 2110 } 2111 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2112 2113 /** 2114 * drm_edid_duplicate - duplicate an EDID and the extensions 2115 * @edid: EDID to duplicate 2116 * 2117 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2118 */ 2119 struct edid *drm_edid_duplicate(const struct edid *edid) 2120 { 2121 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 2122 } 2123 EXPORT_SYMBOL(drm_edid_duplicate); 2124 2125 /*** EDID parsing ***/ 2126 2127 /** 2128 * edid_vendor - match a string against EDID's obfuscated vendor field 2129 * @edid: EDID to match 2130 * @vendor: vendor string 2131 * 2132 * Returns true if @vendor is in @edid, false otherwise 2133 */ 2134 static bool edid_vendor(const struct edid *edid, const char *vendor) 2135 { 2136 char edid_vendor[3]; 2137 2138 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 2139 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 2140 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 2141 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 2142 2143 return !strncmp(edid_vendor, vendor, 3); 2144 } 2145 2146 /** 2147 * edid_get_quirks - return quirk flags for a given EDID 2148 * @edid: EDID to process 2149 * 2150 * This tells subsequent routines what fixes they need to apply. 2151 */ 2152 static u32 edid_get_quirks(const struct edid *edid) 2153 { 2154 const struct edid_quirk *quirk; 2155 int i; 2156 2157 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2158 quirk = &edid_quirk_list[i]; 2159 2160 if (edid_vendor(edid, quirk->vendor) && 2161 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 2162 return quirk->quirks; 2163 } 2164 2165 return 0; 2166 } 2167 2168 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2169 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2170 2171 /** 2172 * edid_fixup_preferred - set preferred modes based on quirk list 2173 * @connector: has mode list to fix up 2174 * @quirks: quirks list 2175 * 2176 * Walk the mode list for @connector, clearing the preferred status 2177 * on existing modes and setting it anew for the right mode ala @quirks. 2178 */ 2179 static void edid_fixup_preferred(struct drm_connector *connector, 2180 u32 quirks) 2181 { 2182 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2183 int target_refresh = 0; 2184 int cur_vrefresh, preferred_vrefresh; 2185 2186 if (list_empty(&connector->probed_modes)) 2187 return; 2188 2189 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 2190 target_refresh = 60; 2191 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 2192 target_refresh = 75; 2193 2194 preferred_mode = list_first_entry(&connector->probed_modes, 2195 struct drm_display_mode, head); 2196 2197 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 2198 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2199 2200 if (cur_mode == preferred_mode) 2201 continue; 2202 2203 /* Largest mode is preferred */ 2204 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 2205 preferred_mode = cur_mode; 2206 2207 cur_vrefresh = drm_mode_vrefresh(cur_mode); 2208 preferred_vrefresh = drm_mode_vrefresh(preferred_mode); 2209 /* At a given size, try to get closest to target refresh */ 2210 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2211 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2212 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2213 preferred_mode = cur_mode; 2214 } 2215 } 2216 2217 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 2218 } 2219 2220 static bool 2221 mode_is_rb(const struct drm_display_mode *mode) 2222 { 2223 return (mode->htotal - mode->hdisplay == 160) && 2224 (mode->hsync_end - mode->hdisplay == 80) && 2225 (mode->hsync_end - mode->hsync_start == 32) && 2226 (mode->vsync_start - mode->vdisplay == 3); 2227 } 2228 2229 /* 2230 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 2231 * @dev: Device to duplicate against 2232 * @hsize: Mode width 2233 * @vsize: Mode height 2234 * @fresh: Mode refresh rate 2235 * @rb: Mode reduced-blanking-ness 2236 * 2237 * Walk the DMT mode list looking for a match for the given parameters. 2238 * 2239 * Return: A newly allocated copy of the mode, or NULL if not found. 2240 */ 2241 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 2242 int hsize, int vsize, int fresh, 2243 bool rb) 2244 { 2245 int i; 2246 2247 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2248 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 2249 2250 if (hsize != ptr->hdisplay) 2251 continue; 2252 if (vsize != ptr->vdisplay) 2253 continue; 2254 if (fresh != drm_mode_vrefresh(ptr)) 2255 continue; 2256 if (rb != mode_is_rb(ptr)) 2257 continue; 2258 2259 return drm_mode_duplicate(dev, ptr); 2260 } 2261 2262 return NULL; 2263 } 2264 EXPORT_SYMBOL(drm_mode_find_dmt); 2265 2266 static bool is_display_descriptor(const u8 d[18], u8 tag) 2267 { 2268 return d[0] == 0x00 && d[1] == 0x00 && 2269 d[2] == 0x00 && d[3] == tag; 2270 } 2271 2272 static bool is_detailed_timing_descriptor(const u8 d[18]) 2273 { 2274 return d[0] != 0x00 || d[1] != 0x00; 2275 } 2276 2277 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 2278 2279 static void 2280 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 2281 { 2282 int i, n; 2283 u8 d = ext[0x02]; 2284 u8 *det_base = ext + d; 2285 2286 if (d < 4 || d > 127) 2287 return; 2288 2289 n = (127 - d) / 18; 2290 for (i = 0; i < n; i++) 2291 cb((struct detailed_timing *)(det_base + 18 * i), closure); 2292 } 2293 2294 static void 2295 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 2296 { 2297 unsigned int i, n = min((int)ext[0x02], 6); 2298 u8 *det_base = ext + 5; 2299 2300 if (ext[0x01] != 1) 2301 return; /* unknown version */ 2302 2303 for (i = 0; i < n; i++) 2304 cb((struct detailed_timing *)(det_base + 18 * i), closure); 2305 } 2306 2307 static void 2308 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 2309 { 2310 int i; 2311 struct edid *edid = (struct edid *)raw_edid; 2312 2313 if (edid == NULL) 2314 return; 2315 2316 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 2317 cb(&(edid->detailed_timings[i]), closure); 2318 2319 for (i = 1; i <= raw_edid[0x7e]; i++) { 2320 u8 *ext = raw_edid + (i * EDID_LENGTH); 2321 2322 switch (*ext) { 2323 case CEA_EXT: 2324 cea_for_each_detailed_block(ext, cb, closure); 2325 break; 2326 case VTB_EXT: 2327 vtb_for_each_detailed_block(ext, cb, closure); 2328 break; 2329 default: 2330 break; 2331 } 2332 } 2333 } 2334 2335 static void 2336 is_rb(struct detailed_timing *t, void *data) 2337 { 2338 u8 *r = (u8 *)t; 2339 2340 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE)) 2341 return; 2342 2343 if (r[15] & 0x10) 2344 *(bool *)data = true; 2345 } 2346 2347 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 2348 static bool 2349 drm_monitor_supports_rb(struct edid *edid) 2350 { 2351 if (edid->revision >= 4) { 2352 bool ret = false; 2353 2354 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 2355 return ret; 2356 } 2357 2358 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 2359 } 2360 2361 static void 2362 find_gtf2(struct detailed_timing *t, void *data) 2363 { 2364 u8 *r = (u8 *)t; 2365 2366 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE)) 2367 return; 2368 2369 if (r[10] == 0x02) 2370 *(u8 **)data = r; 2371 } 2372 2373 /* Secondary GTF curve kicks in above some break frequency */ 2374 static int 2375 drm_gtf2_hbreak(struct edid *edid) 2376 { 2377 u8 *r = NULL; 2378 2379 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2380 return r ? (r[12] * 2) : 0; 2381 } 2382 2383 static int 2384 drm_gtf2_2c(struct edid *edid) 2385 { 2386 u8 *r = NULL; 2387 2388 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2389 return r ? r[13] : 0; 2390 } 2391 2392 static int 2393 drm_gtf2_m(struct edid *edid) 2394 { 2395 u8 *r = NULL; 2396 2397 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2398 return r ? (r[15] << 8) + r[14] : 0; 2399 } 2400 2401 static int 2402 drm_gtf2_k(struct edid *edid) 2403 { 2404 u8 *r = NULL; 2405 2406 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2407 return r ? r[16] : 0; 2408 } 2409 2410 static int 2411 drm_gtf2_2j(struct edid *edid) 2412 { 2413 u8 *r = NULL; 2414 2415 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2416 return r ? r[17] : 0; 2417 } 2418 2419 /** 2420 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 2421 * @edid: EDID block to scan 2422 */ 2423 static int standard_timing_level(struct edid *edid) 2424 { 2425 if (edid->revision >= 2) { 2426 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 2427 return LEVEL_CVT; 2428 if (drm_gtf2_hbreak(edid)) 2429 return LEVEL_GTF2; 2430 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 2431 return LEVEL_GTF; 2432 } 2433 return LEVEL_DMT; 2434 } 2435 2436 /* 2437 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 2438 * monitors fill with ascii space (0x20) instead. 2439 */ 2440 static int 2441 bad_std_timing(u8 a, u8 b) 2442 { 2443 return (a == 0x00 && b == 0x00) || 2444 (a == 0x01 && b == 0x01) || 2445 (a == 0x20 && b == 0x20); 2446 } 2447 2448 static int drm_mode_hsync(const struct drm_display_mode *mode) 2449 { 2450 if (mode->htotal <= 0) 2451 return 0; 2452 2453 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 2454 } 2455 2456 /** 2457 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 2458 * @connector: connector of for the EDID block 2459 * @edid: EDID block to scan 2460 * @t: standard timing params 2461 * 2462 * Take the standard timing params (in this case width, aspect, and refresh) 2463 * and convert them into a real mode using CVT/GTF/DMT. 2464 */ 2465 static struct drm_display_mode * 2466 drm_mode_std(struct drm_connector *connector, struct edid *edid, 2467 struct std_timing *t) 2468 { 2469 struct drm_device *dev = connector->dev; 2470 struct drm_display_mode *m, *mode = NULL; 2471 int hsize, vsize; 2472 int vrefresh_rate; 2473 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 2474 >> EDID_TIMING_ASPECT_SHIFT; 2475 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 2476 >> EDID_TIMING_VFREQ_SHIFT; 2477 int timing_level = standard_timing_level(edid); 2478 2479 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 2480 return NULL; 2481 2482 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 2483 hsize = t->hsize * 8 + 248; 2484 /* vrefresh_rate = vfreq + 60 */ 2485 vrefresh_rate = vfreq + 60; 2486 /* the vdisplay is calculated based on the aspect ratio */ 2487 if (aspect_ratio == 0) { 2488 if (edid->revision < 3) 2489 vsize = hsize; 2490 else 2491 vsize = (hsize * 10) / 16; 2492 } else if (aspect_ratio == 1) 2493 vsize = (hsize * 3) / 4; 2494 else if (aspect_ratio == 2) 2495 vsize = (hsize * 4) / 5; 2496 else 2497 vsize = (hsize * 9) / 16; 2498 2499 /* HDTV hack, part 1 */ 2500 if (vrefresh_rate == 60 && 2501 ((hsize == 1360 && vsize == 765) || 2502 (hsize == 1368 && vsize == 769))) { 2503 hsize = 1366; 2504 vsize = 768; 2505 } 2506 2507 /* 2508 * If this connector already has a mode for this size and refresh 2509 * rate (because it came from detailed or CVT info), use that 2510 * instead. This way we don't have to guess at interlace or 2511 * reduced blanking. 2512 */ 2513 list_for_each_entry(m, &connector->probed_modes, head) 2514 if (m->hdisplay == hsize && m->vdisplay == vsize && 2515 drm_mode_vrefresh(m) == vrefresh_rate) 2516 return NULL; 2517 2518 /* HDTV hack, part 2 */ 2519 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 2520 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 2521 false); 2522 if (!mode) 2523 return NULL; 2524 mode->hdisplay = 1366; 2525 mode->hsync_start = mode->hsync_start - 1; 2526 mode->hsync_end = mode->hsync_end - 1; 2527 return mode; 2528 } 2529 2530 /* check whether it can be found in default mode table */ 2531 if (drm_monitor_supports_rb(edid)) { 2532 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 2533 true); 2534 if (mode) 2535 return mode; 2536 } 2537 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 2538 if (mode) 2539 return mode; 2540 2541 /* okay, generate it */ 2542 switch (timing_level) { 2543 case LEVEL_DMT: 2544 break; 2545 case LEVEL_GTF: 2546 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2547 break; 2548 case LEVEL_GTF2: 2549 /* 2550 * This is potentially wrong if there's ever a monitor with 2551 * more than one ranges section, each claiming a different 2552 * secondary GTF curve. Please don't do that. 2553 */ 2554 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2555 if (!mode) 2556 return NULL; 2557 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 2558 drm_mode_destroy(dev, mode); 2559 mode = drm_gtf_mode_complex(dev, hsize, vsize, 2560 vrefresh_rate, 0, 0, 2561 drm_gtf2_m(edid), 2562 drm_gtf2_2c(edid), 2563 drm_gtf2_k(edid), 2564 drm_gtf2_2j(edid)); 2565 } 2566 break; 2567 case LEVEL_CVT: 2568 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 2569 false); 2570 break; 2571 } 2572 return mode; 2573 } 2574 2575 /* 2576 * EDID is delightfully ambiguous about how interlaced modes are to be 2577 * encoded. Our internal representation is of frame height, but some 2578 * HDTV detailed timings are encoded as field height. 2579 * 2580 * The format list here is from CEA, in frame size. Technically we 2581 * should be checking refresh rate too. Whatever. 2582 */ 2583 static void 2584 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 2585 struct detailed_pixel_timing *pt) 2586 { 2587 int i; 2588 static const struct { 2589 int w, h; 2590 } cea_interlaced[] = { 2591 { 1920, 1080 }, 2592 { 720, 480 }, 2593 { 1440, 480 }, 2594 { 2880, 480 }, 2595 { 720, 576 }, 2596 { 1440, 576 }, 2597 { 2880, 576 }, 2598 }; 2599 2600 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 2601 return; 2602 2603 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 2604 if ((mode->hdisplay == cea_interlaced[i].w) && 2605 (mode->vdisplay == cea_interlaced[i].h / 2)) { 2606 mode->vdisplay *= 2; 2607 mode->vsync_start *= 2; 2608 mode->vsync_end *= 2; 2609 mode->vtotal *= 2; 2610 mode->vtotal |= 1; 2611 } 2612 } 2613 2614 mode->flags |= DRM_MODE_FLAG_INTERLACE; 2615 } 2616 2617 /** 2618 * drm_mode_detailed - create a new mode from an EDID detailed timing section 2619 * @dev: DRM device (needed to create new mode) 2620 * @edid: EDID block 2621 * @timing: EDID detailed timing info 2622 * @quirks: quirks to apply 2623 * 2624 * An EDID detailed timing block contains enough info for us to create and 2625 * return a new struct drm_display_mode. 2626 */ 2627 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 2628 struct edid *edid, 2629 struct detailed_timing *timing, 2630 u32 quirks) 2631 { 2632 struct drm_display_mode *mode; 2633 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 2634 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 2635 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 2636 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 2637 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 2638 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 2639 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 2640 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 2641 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 2642 2643 /* ignore tiny modes */ 2644 if (hactive < 64 || vactive < 64) 2645 return NULL; 2646 2647 if (pt->misc & DRM_EDID_PT_STEREO) { 2648 DRM_DEBUG_KMS("stereo mode not supported\n"); 2649 return NULL; 2650 } 2651 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 2652 DRM_DEBUG_KMS("composite sync not supported\n"); 2653 } 2654 2655 /* it is incorrect if hsync/vsync width is zero */ 2656 if (!hsync_pulse_width || !vsync_pulse_width) { 2657 DRM_DEBUG_KMS("Incorrect Detailed timing. " 2658 "Wrong Hsync/Vsync pulse width\n"); 2659 return NULL; 2660 } 2661 2662 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 2663 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2664 if (!mode) 2665 return NULL; 2666 2667 goto set_size; 2668 } 2669 2670 mode = drm_mode_create(dev); 2671 if (!mode) 2672 return NULL; 2673 2674 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2675 timing->pixel_clock = cpu_to_le16(1088); 2676 2677 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2678 2679 mode->hdisplay = hactive; 2680 mode->hsync_start = mode->hdisplay + hsync_offset; 2681 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2682 mode->htotal = mode->hdisplay + hblank; 2683 2684 mode->vdisplay = vactive; 2685 mode->vsync_start = mode->vdisplay + vsync_offset; 2686 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2687 mode->vtotal = mode->vdisplay + vblank; 2688 2689 /* Some EDIDs have bogus h/vtotal values */ 2690 if (mode->hsync_end > mode->htotal) 2691 mode->htotal = mode->hsync_end + 1; 2692 if (mode->vsync_end > mode->vtotal) 2693 mode->vtotal = mode->vsync_end + 1; 2694 2695 drm_mode_do_interlace_quirk(mode, pt); 2696 2697 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2698 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 2699 } 2700 2701 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2702 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2703 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2704 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2705 2706 set_size: 2707 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2708 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2709 2710 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2711 mode->width_mm *= 10; 2712 mode->height_mm *= 10; 2713 } 2714 2715 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2716 mode->width_mm = edid->width_cm * 10; 2717 mode->height_mm = edid->height_cm * 10; 2718 } 2719 2720 mode->type = DRM_MODE_TYPE_DRIVER; 2721 drm_mode_set_name(mode); 2722 2723 return mode; 2724 } 2725 2726 static bool 2727 mode_in_hsync_range(const struct drm_display_mode *mode, 2728 struct edid *edid, u8 *t) 2729 { 2730 int hsync, hmin, hmax; 2731 2732 hmin = t[7]; 2733 if (edid->revision >= 4) 2734 hmin += ((t[4] & 0x04) ? 255 : 0); 2735 hmax = t[8]; 2736 if (edid->revision >= 4) 2737 hmax += ((t[4] & 0x08) ? 255 : 0); 2738 hsync = drm_mode_hsync(mode); 2739 2740 return (hsync <= hmax && hsync >= hmin); 2741 } 2742 2743 static bool 2744 mode_in_vsync_range(const struct drm_display_mode *mode, 2745 struct edid *edid, u8 *t) 2746 { 2747 int vsync, vmin, vmax; 2748 2749 vmin = t[5]; 2750 if (edid->revision >= 4) 2751 vmin += ((t[4] & 0x01) ? 255 : 0); 2752 vmax = t[6]; 2753 if (edid->revision >= 4) 2754 vmax += ((t[4] & 0x02) ? 255 : 0); 2755 vsync = drm_mode_vrefresh(mode); 2756 2757 return (vsync <= vmax && vsync >= vmin); 2758 } 2759 2760 static u32 2761 range_pixel_clock(struct edid *edid, u8 *t) 2762 { 2763 /* unspecified */ 2764 if (t[9] == 0 || t[9] == 255) 2765 return 0; 2766 2767 /* 1.4 with CVT support gives us real precision, yay */ 2768 if (edid->revision >= 4 && t[10] == 0x04) 2769 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2770 2771 /* 1.3 is pathetic, so fuzz up a bit */ 2772 return t[9] * 10000 + 5001; 2773 } 2774 2775 static bool 2776 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2777 struct detailed_timing *timing) 2778 { 2779 u32 max_clock; 2780 u8 *t = (u8 *)timing; 2781 2782 if (!mode_in_hsync_range(mode, edid, t)) 2783 return false; 2784 2785 if (!mode_in_vsync_range(mode, edid, t)) 2786 return false; 2787 2788 if ((max_clock = range_pixel_clock(edid, t))) 2789 if (mode->clock > max_clock) 2790 return false; 2791 2792 /* 1.4 max horizontal check */ 2793 if (edid->revision >= 4 && t[10] == 0x04) 2794 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2795 return false; 2796 2797 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2798 return false; 2799 2800 return true; 2801 } 2802 2803 static bool valid_inferred_mode(const struct drm_connector *connector, 2804 const struct drm_display_mode *mode) 2805 { 2806 const struct drm_display_mode *m; 2807 bool ok = false; 2808 2809 list_for_each_entry(m, &connector->probed_modes, head) { 2810 if (mode->hdisplay == m->hdisplay && 2811 mode->vdisplay == m->vdisplay && 2812 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2813 return false; /* duplicated */ 2814 if (mode->hdisplay <= m->hdisplay && 2815 mode->vdisplay <= m->vdisplay) 2816 ok = true; 2817 } 2818 return ok; 2819 } 2820 2821 static int 2822 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2823 struct detailed_timing *timing) 2824 { 2825 int i, modes = 0; 2826 struct drm_display_mode *newmode; 2827 struct drm_device *dev = connector->dev; 2828 2829 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2830 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2831 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2832 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2833 if (newmode) { 2834 drm_mode_probed_add(connector, newmode); 2835 modes++; 2836 } 2837 } 2838 } 2839 2840 return modes; 2841 } 2842 2843 /* fix up 1366x768 mode from 1368x768; 2844 * GFT/CVT can't express 1366 width which isn't dividable by 8 2845 */ 2846 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 2847 { 2848 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2849 mode->hdisplay = 1366; 2850 mode->hsync_start--; 2851 mode->hsync_end--; 2852 drm_mode_set_name(mode); 2853 } 2854 } 2855 2856 static int 2857 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2858 struct detailed_timing *timing) 2859 { 2860 int i, modes = 0; 2861 struct drm_display_mode *newmode; 2862 struct drm_device *dev = connector->dev; 2863 2864 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2865 const struct minimode *m = &extra_modes[i]; 2866 2867 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2868 if (!newmode) 2869 return modes; 2870 2871 drm_mode_fixup_1366x768(newmode); 2872 if (!mode_in_range(newmode, edid, timing) || 2873 !valid_inferred_mode(connector, newmode)) { 2874 drm_mode_destroy(dev, newmode); 2875 continue; 2876 } 2877 2878 drm_mode_probed_add(connector, newmode); 2879 modes++; 2880 } 2881 2882 return modes; 2883 } 2884 2885 static int 2886 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2887 struct detailed_timing *timing) 2888 { 2889 int i, modes = 0; 2890 struct drm_display_mode *newmode; 2891 struct drm_device *dev = connector->dev; 2892 bool rb = drm_monitor_supports_rb(edid); 2893 2894 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2895 const struct minimode *m = &extra_modes[i]; 2896 2897 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2898 if (!newmode) 2899 return modes; 2900 2901 drm_mode_fixup_1366x768(newmode); 2902 if (!mode_in_range(newmode, edid, timing) || 2903 !valid_inferred_mode(connector, newmode)) { 2904 drm_mode_destroy(dev, newmode); 2905 continue; 2906 } 2907 2908 drm_mode_probed_add(connector, newmode); 2909 modes++; 2910 } 2911 2912 return modes; 2913 } 2914 2915 static void 2916 do_inferred_modes(struct detailed_timing *timing, void *c) 2917 { 2918 struct detailed_mode_closure *closure = c; 2919 struct detailed_non_pixel *data = &timing->data.other_data; 2920 struct detailed_data_monitor_range *range = &data->data.range; 2921 2922 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE)) 2923 return; 2924 2925 closure->modes += drm_dmt_modes_for_range(closure->connector, 2926 closure->edid, 2927 timing); 2928 2929 if (!version_greater(closure->edid, 1, 1)) 2930 return; /* GTF not defined yet */ 2931 2932 switch (range->flags) { 2933 case 0x02: /* secondary gtf, XXX could do more */ 2934 case 0x00: /* default gtf */ 2935 closure->modes += drm_gtf_modes_for_range(closure->connector, 2936 closure->edid, 2937 timing); 2938 break; 2939 case 0x04: /* cvt, only in 1.4+ */ 2940 if (!version_greater(closure->edid, 1, 3)) 2941 break; 2942 2943 closure->modes += drm_cvt_modes_for_range(closure->connector, 2944 closure->edid, 2945 timing); 2946 break; 2947 case 0x01: /* just the ranges, no formula */ 2948 default: 2949 break; 2950 } 2951 } 2952 2953 static int 2954 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2955 { 2956 struct detailed_mode_closure closure = { 2957 .connector = connector, 2958 .edid = edid, 2959 }; 2960 2961 if (version_greater(edid, 1, 0)) 2962 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2963 &closure); 2964 2965 return closure.modes; 2966 } 2967 2968 static int 2969 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2970 { 2971 int i, j, m, modes = 0; 2972 struct drm_display_mode *mode; 2973 u8 *est = ((u8 *)timing) + 6; 2974 2975 for (i = 0; i < 6; i++) { 2976 for (j = 7; j >= 0; j--) { 2977 m = (i * 8) + (7 - j); 2978 if (m >= ARRAY_SIZE(est3_modes)) 2979 break; 2980 if (est[i] & (1 << j)) { 2981 mode = drm_mode_find_dmt(connector->dev, 2982 est3_modes[m].w, 2983 est3_modes[m].h, 2984 est3_modes[m].r, 2985 est3_modes[m].rb); 2986 if (mode) { 2987 drm_mode_probed_add(connector, mode); 2988 modes++; 2989 } 2990 } 2991 } 2992 } 2993 2994 return modes; 2995 } 2996 2997 static void 2998 do_established_modes(struct detailed_timing *timing, void *c) 2999 { 3000 struct detailed_mode_closure *closure = c; 3001 3002 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS)) 3003 return; 3004 3005 closure->modes += drm_est3_modes(closure->connector, timing); 3006 } 3007 3008 /** 3009 * add_established_modes - get est. modes from EDID and add them 3010 * @connector: connector to add mode(s) to 3011 * @edid: EDID block to scan 3012 * 3013 * Each EDID block contains a bitmap of the supported "established modes" list 3014 * (defined above). Tease them out and add them to the global modes list. 3015 */ 3016 static int 3017 add_established_modes(struct drm_connector *connector, struct edid *edid) 3018 { 3019 struct drm_device *dev = connector->dev; 3020 unsigned long est_bits = edid->established_timings.t1 | 3021 (edid->established_timings.t2 << 8) | 3022 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 3023 int i, modes = 0; 3024 struct detailed_mode_closure closure = { 3025 .connector = connector, 3026 .edid = edid, 3027 }; 3028 3029 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 3030 if (est_bits & (1<<i)) { 3031 struct drm_display_mode *newmode; 3032 3033 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 3034 if (newmode) { 3035 drm_mode_probed_add(connector, newmode); 3036 modes++; 3037 } 3038 } 3039 } 3040 3041 if (version_greater(edid, 1, 0)) 3042 drm_for_each_detailed_block((u8 *)edid, 3043 do_established_modes, &closure); 3044 3045 return modes + closure.modes; 3046 } 3047 3048 static void 3049 do_standard_modes(struct detailed_timing *timing, void *c) 3050 { 3051 struct detailed_mode_closure *closure = c; 3052 struct detailed_non_pixel *data = &timing->data.other_data; 3053 struct drm_connector *connector = closure->connector; 3054 struct edid *edid = closure->edid; 3055 int i; 3056 3057 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES)) 3058 return; 3059 3060 for (i = 0; i < 6; i++) { 3061 struct std_timing *std = &data->data.timings[i]; 3062 struct drm_display_mode *newmode; 3063 3064 newmode = drm_mode_std(connector, edid, std); 3065 if (newmode) { 3066 drm_mode_probed_add(connector, newmode); 3067 closure->modes++; 3068 } 3069 } 3070 } 3071 3072 /** 3073 * add_standard_modes - get std. modes from EDID and add them 3074 * @connector: connector to add mode(s) to 3075 * @edid: EDID block to scan 3076 * 3077 * Standard modes can be calculated using the appropriate standard (DMT, 3078 * GTF or CVT. Grab them from @edid and add them to the list. 3079 */ 3080 static int 3081 add_standard_modes(struct drm_connector *connector, struct edid *edid) 3082 { 3083 int i, modes = 0; 3084 struct detailed_mode_closure closure = { 3085 .connector = connector, 3086 .edid = edid, 3087 }; 3088 3089 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3090 struct drm_display_mode *newmode; 3091 3092 newmode = drm_mode_std(connector, edid, 3093 &edid->standard_timings[i]); 3094 if (newmode) { 3095 drm_mode_probed_add(connector, newmode); 3096 modes++; 3097 } 3098 } 3099 3100 if (version_greater(edid, 1, 0)) 3101 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 3102 &closure); 3103 3104 /* XXX should also look for standard codes in VTB blocks */ 3105 3106 return modes + closure.modes; 3107 } 3108 3109 static int drm_cvt_modes(struct drm_connector *connector, 3110 struct detailed_timing *timing) 3111 { 3112 int i, j, modes = 0; 3113 struct drm_display_mode *newmode; 3114 struct drm_device *dev = connector->dev; 3115 struct cvt_timing *cvt; 3116 const int rates[] = { 60, 85, 75, 60, 50 }; 3117 const u8 empty[3] = { 0, 0, 0 }; 3118 3119 for (i = 0; i < 4; i++) { 3120 int width, height; 3121 3122 cvt = &(timing->data.other_data.data.cvt[i]); 3123 3124 if (!memcmp(cvt->code, empty, 3)) 3125 continue; 3126 3127 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3128 switch (cvt->code[1] & 0x0c) { 3129 /* default - because compiler doesn't see that we've enumerated all cases */ 3130 default: 3131 case 0x00: 3132 width = height * 4 / 3; 3133 break; 3134 case 0x04: 3135 width = height * 16 / 9; 3136 break; 3137 case 0x08: 3138 width = height * 16 / 10; 3139 break; 3140 case 0x0c: 3141 width = height * 15 / 9; 3142 break; 3143 } 3144 3145 for (j = 1; j < 5; j++) { 3146 if (cvt->code[2] & (1 << j)) { 3147 newmode = drm_cvt_mode(dev, width, height, 3148 rates[j], j == 0, 3149 false, false); 3150 if (newmode) { 3151 drm_mode_probed_add(connector, newmode); 3152 modes++; 3153 } 3154 } 3155 } 3156 } 3157 3158 return modes; 3159 } 3160 3161 static void 3162 do_cvt_mode(struct detailed_timing *timing, void *c) 3163 { 3164 struct detailed_mode_closure *closure = c; 3165 3166 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE)) 3167 return; 3168 3169 closure->modes += drm_cvt_modes(closure->connector, timing); 3170 } 3171 3172 static int 3173 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 3174 { 3175 struct detailed_mode_closure closure = { 3176 .connector = connector, 3177 .edid = edid, 3178 }; 3179 3180 if (version_greater(edid, 1, 2)) 3181 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 3182 3183 /* XXX should also look for CVT codes in VTB blocks */ 3184 3185 return closure.modes; 3186 } 3187 3188 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 3189 3190 static void 3191 do_detailed_mode(struct detailed_timing *timing, void *c) 3192 { 3193 struct detailed_mode_closure *closure = c; 3194 struct drm_display_mode *newmode; 3195 3196 if (!is_detailed_timing_descriptor((const u8 *)timing)) 3197 return; 3198 3199 newmode = drm_mode_detailed(closure->connector->dev, 3200 closure->edid, timing, 3201 closure->quirks); 3202 if (!newmode) 3203 return; 3204 3205 if (closure->preferred) 3206 newmode->type |= DRM_MODE_TYPE_PREFERRED; 3207 3208 /* 3209 * Detailed modes are limited to 10kHz pixel clock resolution, 3210 * so fix up anything that looks like CEA/HDMI mode, but the clock 3211 * is just slightly off. 3212 */ 3213 fixup_detailed_cea_mode_clock(newmode); 3214 3215 drm_mode_probed_add(closure->connector, newmode); 3216 closure->modes++; 3217 closure->preferred = false; 3218 } 3219 3220 /* 3221 * add_detailed_modes - Add modes from detailed timings 3222 * @connector: attached connector 3223 * @edid: EDID block to scan 3224 * @quirks: quirks to apply 3225 */ 3226 static int 3227 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 3228 u32 quirks) 3229 { 3230 struct detailed_mode_closure closure = { 3231 .connector = connector, 3232 .edid = edid, 3233 .preferred = true, 3234 .quirks = quirks, 3235 }; 3236 3237 if (closure.preferred && !version_greater(edid, 1, 3)) 3238 closure.preferred = 3239 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 3240 3241 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 3242 3243 return closure.modes; 3244 } 3245 3246 #define AUDIO_BLOCK 0x01 3247 #define VIDEO_BLOCK 0x02 3248 #define VENDOR_BLOCK 0x03 3249 #define SPEAKER_BLOCK 0x04 3250 #define HDR_STATIC_METADATA_BLOCK 0x6 3251 #define USE_EXTENDED_TAG 0x07 3252 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00 3253 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 3254 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F 3255 #define EDID_BASIC_AUDIO (1 << 6) 3256 #define EDID_CEA_YCRCB444 (1 << 5) 3257 #define EDID_CEA_YCRCB422 (1 << 4) 3258 #define EDID_CEA_VCDB_QS (1 << 6) 3259 3260 /* 3261 * Search EDID for CEA extension block. 3262 */ 3263 const u8 *drm_find_edid_extension(const struct edid *edid, 3264 int ext_id, int *ext_index) 3265 { 3266 const u8 *edid_ext = NULL; 3267 int i; 3268 3269 /* No EDID or EDID extensions */ 3270 if (edid == NULL || edid->extensions == 0) 3271 return NULL; 3272 3273 /* Find CEA extension */ 3274 for (i = *ext_index; i < edid->extensions; i++) { 3275 edid_ext = (const u8 *)edid + EDID_LENGTH * (i + 1); 3276 if (edid_ext[0] == ext_id) 3277 break; 3278 } 3279 3280 if (i >= edid->extensions) 3281 return NULL; 3282 3283 *ext_index = i + 1; 3284 3285 return edid_ext; 3286 } 3287 3288 static const u8 *drm_find_cea_extension(const struct edid *edid) 3289 { 3290 const struct displayid_block *block; 3291 struct displayid_iter iter; 3292 const u8 *cea; 3293 int ext_index = 0; 3294 3295 /* Look for a top level CEA extension block */ 3296 /* FIXME: make callers iterate through multiple CEA ext blocks? */ 3297 cea = drm_find_edid_extension(edid, CEA_EXT, &ext_index); 3298 if (cea) 3299 return cea; 3300 3301 /* CEA blocks can also be found embedded in a DisplayID block */ 3302 displayid_iter_edid_begin(edid, &iter); 3303 displayid_iter_for_each(block, &iter) { 3304 if (block->tag == DATA_BLOCK_CTA) { 3305 cea = (const u8 *)block; 3306 break; 3307 } 3308 } 3309 displayid_iter_end(&iter); 3310 3311 return cea; 3312 } 3313 3314 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 3315 { 3316 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 3317 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 3318 3319 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 3320 return &edid_cea_modes_1[vic - 1]; 3321 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 3322 return &edid_cea_modes_193[vic - 193]; 3323 return NULL; 3324 } 3325 3326 static u8 cea_num_vics(void) 3327 { 3328 return 193 + ARRAY_SIZE(edid_cea_modes_193); 3329 } 3330 3331 static u8 cea_next_vic(u8 vic) 3332 { 3333 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 3334 vic = 193; 3335 return vic; 3336 } 3337 3338 /* 3339 * Calculate the alternate clock for the CEA mode 3340 * (60Hz vs. 59.94Hz etc.) 3341 */ 3342 static unsigned int 3343 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3344 { 3345 unsigned int clock = cea_mode->clock; 3346 3347 if (drm_mode_vrefresh(cea_mode) % 6 != 0) 3348 return clock; 3349 3350 /* 3351 * edid_cea_modes contains the 59.94Hz 3352 * variant for 240 and 480 line modes, 3353 * and the 60Hz variant otherwise. 3354 */ 3355 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3356 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3357 else 3358 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3359 3360 return clock; 3361 } 3362 3363 static bool 3364 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 3365 { 3366 /* 3367 * For certain VICs the spec allows the vertical 3368 * front porch to vary by one or two lines. 3369 * 3370 * cea_modes[] stores the variant with the shortest 3371 * vertical front porch. We can adjust the mode to 3372 * get the other variants by simply increasing the 3373 * vertical front porch length. 3374 */ 3375 #ifdef notyet 3376 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 3377 cea_mode_for_vic(9)->vtotal != 262 || 3378 cea_mode_for_vic(12)->vtotal != 262 || 3379 cea_mode_for_vic(13)->vtotal != 262 || 3380 cea_mode_for_vic(23)->vtotal != 312 || 3381 cea_mode_for_vic(24)->vtotal != 312 || 3382 cea_mode_for_vic(27)->vtotal != 312 || 3383 cea_mode_for_vic(28)->vtotal != 312); 3384 #endif 3385 3386 if (((vic == 8 || vic == 9 || 3387 vic == 12 || vic == 13) && mode->vtotal < 263) || 3388 ((vic == 23 || vic == 24 || 3389 vic == 27 || vic == 28) && mode->vtotal < 314)) { 3390 mode->vsync_start++; 3391 mode->vsync_end++; 3392 mode->vtotal++; 3393 3394 return true; 3395 } 3396 3397 return false; 3398 } 3399 3400 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3401 unsigned int clock_tolerance) 3402 { 3403 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3404 u8 vic; 3405 3406 if (!to_match->clock) 3407 return 0; 3408 3409 if (to_match->picture_aspect_ratio) 3410 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3411 3412 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3413 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); 3414 unsigned int clock1, clock2; 3415 3416 /* Check both 60Hz and 59.94Hz */ 3417 clock1 = cea_mode.clock; 3418 clock2 = cea_mode_alternate_clock(&cea_mode); 3419 3420 if (abs(to_match->clock - clock1) > clock_tolerance && 3421 abs(to_match->clock - clock2) > clock_tolerance) 3422 continue; 3423 3424 do { 3425 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3426 return vic; 3427 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3428 } 3429 3430 return 0; 3431 } 3432 3433 /** 3434 * drm_match_cea_mode - look for a CEA mode matching given mode 3435 * @to_match: display mode 3436 * 3437 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 3438 * mode. 3439 */ 3440 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 3441 { 3442 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3443 u8 vic; 3444 3445 if (!to_match->clock) 3446 return 0; 3447 3448 if (to_match->picture_aspect_ratio) 3449 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3450 3451 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3452 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); 3453 unsigned int clock1, clock2; 3454 3455 /* Check both 60Hz and 59.94Hz */ 3456 clock1 = cea_mode.clock; 3457 clock2 = cea_mode_alternate_clock(&cea_mode); 3458 3459 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 3460 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 3461 continue; 3462 3463 do { 3464 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3465 return vic; 3466 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3467 } 3468 3469 return 0; 3470 } 3471 EXPORT_SYMBOL(drm_match_cea_mode); 3472 3473 static bool drm_valid_cea_vic(u8 vic) 3474 { 3475 return cea_mode_for_vic(vic) != NULL; 3476 } 3477 3478 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 3479 { 3480 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 3481 3482 if (mode) 3483 return mode->picture_aspect_ratio; 3484 3485 return HDMI_PICTURE_ASPECT_NONE; 3486 } 3487 3488 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 3489 { 3490 return edid_4k_modes[video_code].picture_aspect_ratio; 3491 } 3492 3493 /* 3494 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 3495 * specific block). 3496 */ 3497 static unsigned int 3498 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3499 { 3500 return cea_mode_alternate_clock(hdmi_mode); 3501 } 3502 3503 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3504 unsigned int clock_tolerance) 3505 { 3506 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3507 u8 vic; 3508 3509 if (!to_match->clock) 3510 return 0; 3511 3512 if (to_match->picture_aspect_ratio) 3513 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3514 3515 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3516 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3517 unsigned int clock1, clock2; 3518 3519 /* Make sure to also match alternate clocks */ 3520 clock1 = hdmi_mode->clock; 3521 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3522 3523 if (abs(to_match->clock - clock1) > clock_tolerance && 3524 abs(to_match->clock - clock2) > clock_tolerance) 3525 continue; 3526 3527 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 3528 return vic; 3529 } 3530 3531 return 0; 3532 } 3533 3534 /* 3535 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 3536 * @to_match: display mode 3537 * 3538 * An HDMI mode is one defined in the HDMI vendor specific block. 3539 * 3540 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 3541 */ 3542 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 3543 { 3544 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3545 u8 vic; 3546 3547 if (!to_match->clock) 3548 return 0; 3549 3550 if (to_match->picture_aspect_ratio) 3551 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3552 3553 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3554 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3555 unsigned int clock1, clock2; 3556 3557 /* Make sure to also match alternate clocks */ 3558 clock1 = hdmi_mode->clock; 3559 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3560 3561 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 3562 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 3563 drm_mode_match(to_match, hdmi_mode, match_flags)) 3564 return vic; 3565 } 3566 return 0; 3567 } 3568 3569 static bool drm_valid_hdmi_vic(u8 vic) 3570 { 3571 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 3572 } 3573 3574 static int 3575 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 3576 { 3577 struct drm_device *dev = connector->dev; 3578 struct drm_display_mode *mode, *tmp; 3579 DRM_LIST_HEAD(list); 3580 int modes = 0; 3581 3582 /* Don't add CEA modes if the CEA extension block is missing */ 3583 if (!drm_find_cea_extension(edid)) 3584 return 0; 3585 3586 /* 3587 * Go through all probed modes and create a new mode 3588 * with the alternate clock for certain CEA modes. 3589 */ 3590 list_for_each_entry(mode, &connector->probed_modes, head) { 3591 const struct drm_display_mode *cea_mode = NULL; 3592 struct drm_display_mode *newmode; 3593 u8 vic = drm_match_cea_mode(mode); 3594 unsigned int clock1, clock2; 3595 3596 if (drm_valid_cea_vic(vic)) { 3597 cea_mode = cea_mode_for_vic(vic); 3598 clock2 = cea_mode_alternate_clock(cea_mode); 3599 } else { 3600 vic = drm_match_hdmi_mode(mode); 3601 if (drm_valid_hdmi_vic(vic)) { 3602 cea_mode = &edid_4k_modes[vic]; 3603 clock2 = hdmi_mode_alternate_clock(cea_mode); 3604 } 3605 } 3606 3607 if (!cea_mode) 3608 continue; 3609 3610 clock1 = cea_mode->clock; 3611 3612 if (clock1 == clock2) 3613 continue; 3614 3615 if (mode->clock != clock1 && mode->clock != clock2) 3616 continue; 3617 3618 newmode = drm_mode_duplicate(dev, cea_mode); 3619 if (!newmode) 3620 continue; 3621 3622 /* Carry over the stereo flags */ 3623 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 3624 3625 /* 3626 * The current mode could be either variant. Make 3627 * sure to pick the "other" clock for the new mode. 3628 */ 3629 if (mode->clock != clock1) 3630 newmode->clock = clock1; 3631 else 3632 newmode->clock = clock2; 3633 3634 list_add_tail(&newmode->head, &list); 3635 } 3636 3637 list_for_each_entry_safe(mode, tmp, &list, head) { 3638 list_del(&mode->head); 3639 drm_mode_probed_add(connector, mode); 3640 modes++; 3641 } 3642 3643 return modes; 3644 } 3645 3646 static u8 svd_to_vic(u8 svd) 3647 { 3648 /* 0-6 bit vic, 7th bit native mode indicator */ 3649 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 3650 return svd & 127; 3651 3652 return svd; 3653 } 3654 3655 static struct drm_display_mode * 3656 drm_display_mode_from_vic_index(struct drm_connector *connector, 3657 const u8 *video_db, u8 video_len, 3658 u8 video_index) 3659 { 3660 struct drm_device *dev = connector->dev; 3661 struct drm_display_mode *newmode; 3662 u8 vic; 3663 3664 if (video_db == NULL || video_index >= video_len) 3665 return NULL; 3666 3667 /* CEA modes are numbered 1..127 */ 3668 vic = svd_to_vic(video_db[video_index]); 3669 if (!drm_valid_cea_vic(vic)) 3670 return NULL; 3671 3672 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3673 if (!newmode) 3674 return NULL; 3675 3676 return newmode; 3677 } 3678 3679 /* 3680 * do_y420vdb_modes - Parse YCBCR 420 only modes 3681 * @connector: connector corresponding to the HDMI sink 3682 * @svds: start of the data block of CEA YCBCR 420 VDB 3683 * @len: length of the CEA YCBCR 420 VDB 3684 * 3685 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 3686 * which contains modes which can be supported in YCBCR 420 3687 * output format only. 3688 */ 3689 static int do_y420vdb_modes(struct drm_connector *connector, 3690 const u8 *svds, u8 svds_len) 3691 { 3692 int modes = 0, i; 3693 struct drm_device *dev = connector->dev; 3694 struct drm_display_info *info = &connector->display_info; 3695 struct drm_hdmi_info *hdmi = &info->hdmi; 3696 3697 for (i = 0; i < svds_len; i++) { 3698 u8 vic = svd_to_vic(svds[i]); 3699 struct drm_display_mode *newmode; 3700 3701 if (!drm_valid_cea_vic(vic)) 3702 continue; 3703 3704 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3705 if (!newmode) 3706 break; 3707 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 3708 drm_mode_probed_add(connector, newmode); 3709 modes++; 3710 } 3711 3712 if (modes > 0) 3713 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3714 return modes; 3715 } 3716 3717 /* 3718 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 3719 * @connector: connector corresponding to the HDMI sink 3720 * @vic: CEA vic for the video mode to be added in the map 3721 * 3722 * Makes an entry for a videomode in the YCBCR 420 bitmap 3723 */ 3724 static void 3725 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 3726 { 3727 u8 vic = svd_to_vic(svd); 3728 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3729 3730 if (!drm_valid_cea_vic(vic)) 3731 return; 3732 3733 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 3734 } 3735 3736 /** 3737 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC 3738 * @dev: DRM device 3739 * @video_code: CEA VIC of the mode 3740 * 3741 * Creates a new mode matching the specified CEA VIC. 3742 * 3743 * Returns: A new drm_display_mode on success or NULL on failure 3744 */ 3745 struct drm_display_mode * 3746 drm_display_mode_from_cea_vic(struct drm_device *dev, 3747 u8 video_code) 3748 { 3749 const struct drm_display_mode *cea_mode; 3750 struct drm_display_mode *newmode; 3751 3752 cea_mode = cea_mode_for_vic(video_code); 3753 if (!cea_mode) 3754 return NULL; 3755 3756 newmode = drm_mode_duplicate(dev, cea_mode); 3757 if (!newmode) 3758 return NULL; 3759 3760 return newmode; 3761 } 3762 EXPORT_SYMBOL(drm_display_mode_from_cea_vic); 3763 3764 static int 3765 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 3766 { 3767 int i, modes = 0; 3768 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3769 3770 for (i = 0; i < len; i++) { 3771 struct drm_display_mode *mode; 3772 3773 mode = drm_display_mode_from_vic_index(connector, db, len, i); 3774 if (mode) { 3775 /* 3776 * YCBCR420 capability block contains a bitmap which 3777 * gives the index of CEA modes from CEA VDB, which 3778 * can support YCBCR 420 sampling output also (apart 3779 * from RGB/YCBCR444 etc). 3780 * For example, if the bit 0 in bitmap is set, 3781 * first mode in VDB can support YCBCR420 output too. 3782 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 3783 */ 3784 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 3785 drm_add_cmdb_modes(connector, db[i]); 3786 3787 drm_mode_probed_add(connector, mode); 3788 modes++; 3789 } 3790 } 3791 3792 return modes; 3793 } 3794 3795 struct stereo_mandatory_mode { 3796 int width, height, vrefresh; 3797 unsigned int flags; 3798 }; 3799 3800 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 3801 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3802 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3803 { 1920, 1080, 50, 3804 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3805 { 1920, 1080, 60, 3806 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3807 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3808 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3809 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3810 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 3811 }; 3812 3813 static bool 3814 stereo_match_mandatory(const struct drm_display_mode *mode, 3815 const struct stereo_mandatory_mode *stereo_mode) 3816 { 3817 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 3818 3819 return mode->hdisplay == stereo_mode->width && 3820 mode->vdisplay == stereo_mode->height && 3821 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 3822 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 3823 } 3824 3825 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 3826 { 3827 struct drm_device *dev = connector->dev; 3828 const struct drm_display_mode *mode; 3829 struct list_head stereo_modes; 3830 int modes = 0, i; 3831 3832 INIT_LIST_HEAD(&stereo_modes); 3833 3834 list_for_each_entry(mode, &connector->probed_modes, head) { 3835 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 3836 const struct stereo_mandatory_mode *mandatory; 3837 struct drm_display_mode *new_mode; 3838 3839 if (!stereo_match_mandatory(mode, 3840 &stereo_mandatory_modes[i])) 3841 continue; 3842 3843 mandatory = &stereo_mandatory_modes[i]; 3844 new_mode = drm_mode_duplicate(dev, mode); 3845 if (!new_mode) 3846 continue; 3847 3848 new_mode->flags |= mandatory->flags; 3849 list_add_tail(&new_mode->head, &stereo_modes); 3850 modes++; 3851 } 3852 } 3853 3854 list_splice_tail(&stereo_modes, &connector->probed_modes); 3855 3856 return modes; 3857 } 3858 3859 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 3860 { 3861 struct drm_device *dev = connector->dev; 3862 struct drm_display_mode *newmode; 3863 3864 if (!drm_valid_hdmi_vic(vic)) { 3865 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 3866 return 0; 3867 } 3868 3869 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 3870 if (!newmode) 3871 return 0; 3872 3873 drm_mode_probed_add(connector, newmode); 3874 3875 return 1; 3876 } 3877 3878 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 3879 const u8 *video_db, u8 video_len, u8 video_index) 3880 { 3881 struct drm_display_mode *newmode; 3882 int modes = 0; 3883 3884 if (structure & (1 << 0)) { 3885 newmode = drm_display_mode_from_vic_index(connector, video_db, 3886 video_len, 3887 video_index); 3888 if (newmode) { 3889 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 3890 drm_mode_probed_add(connector, newmode); 3891 modes++; 3892 } 3893 } 3894 if (structure & (1 << 6)) { 3895 newmode = drm_display_mode_from_vic_index(connector, video_db, 3896 video_len, 3897 video_index); 3898 if (newmode) { 3899 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3900 drm_mode_probed_add(connector, newmode); 3901 modes++; 3902 } 3903 } 3904 if (structure & (1 << 8)) { 3905 newmode = drm_display_mode_from_vic_index(connector, video_db, 3906 video_len, 3907 video_index); 3908 if (newmode) { 3909 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3910 drm_mode_probed_add(connector, newmode); 3911 modes++; 3912 } 3913 } 3914 3915 return modes; 3916 } 3917 3918 /* 3919 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 3920 * @connector: connector corresponding to the HDMI sink 3921 * @db: start of the CEA vendor specific block 3922 * @len: length of the CEA block payload, ie. one can access up to db[len] 3923 * 3924 * Parses the HDMI VSDB looking for modes to add to @connector. This function 3925 * also adds the stereo 3d modes when applicable. 3926 */ 3927 static int 3928 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 3929 const u8 *video_db, u8 video_len) 3930 { 3931 struct drm_display_info *info = &connector->display_info; 3932 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 3933 u8 vic_len, hdmi_3d_len = 0; 3934 u16 mask; 3935 u16 structure_all; 3936 3937 if (len < 8) 3938 goto out; 3939 3940 /* no HDMI_Video_Present */ 3941 if (!(db[8] & (1 << 5))) 3942 goto out; 3943 3944 /* Latency_Fields_Present */ 3945 if (db[8] & (1 << 7)) 3946 offset += 2; 3947 3948 /* I_Latency_Fields_Present */ 3949 if (db[8] & (1 << 6)) 3950 offset += 2; 3951 3952 /* the declared length is not long enough for the 2 first bytes 3953 * of additional video format capabilities */ 3954 if (len < (8 + offset + 2)) 3955 goto out; 3956 3957 /* 3D_Present */ 3958 offset++; 3959 if (db[8 + offset] & (1 << 7)) { 3960 modes += add_hdmi_mandatory_stereo_modes(connector); 3961 3962 /* 3D_Multi_present */ 3963 multi_present = (db[8 + offset] & 0x60) >> 5; 3964 } 3965 3966 offset++; 3967 vic_len = db[8 + offset] >> 5; 3968 hdmi_3d_len = db[8 + offset] & 0x1f; 3969 3970 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3971 u8 vic; 3972 3973 vic = db[9 + offset + i]; 3974 modes += add_hdmi_mode(connector, vic); 3975 } 3976 offset += 1 + vic_len; 3977 3978 if (multi_present == 1) 3979 multi_len = 2; 3980 else if (multi_present == 2) 3981 multi_len = 4; 3982 else 3983 multi_len = 0; 3984 3985 if (len < (8 + offset + hdmi_3d_len - 1)) 3986 goto out; 3987 3988 if (hdmi_3d_len < multi_len) 3989 goto out; 3990 3991 if (multi_present == 1 || multi_present == 2) { 3992 /* 3D_Structure_ALL */ 3993 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3994 3995 /* check if 3D_MASK is present */ 3996 if (multi_present == 2) 3997 mask = (db[10 + offset] << 8) | db[11 + offset]; 3998 else 3999 mask = 0xffff; 4000 4001 for (i = 0; i < 16; i++) { 4002 if (mask & (1 << i)) 4003 modes += add_3d_struct_modes(connector, 4004 structure_all, 4005 video_db, 4006 video_len, i); 4007 } 4008 } 4009 4010 offset += multi_len; 4011 4012 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 4013 int vic_index; 4014 struct drm_display_mode *newmode = NULL; 4015 unsigned int newflag = 0; 4016 bool detail_present; 4017 4018 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 4019 4020 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 4021 break; 4022 4023 /* 2D_VIC_order_X */ 4024 vic_index = db[8 + offset + i] >> 4; 4025 4026 /* 3D_Structure_X */ 4027 switch (db[8 + offset + i] & 0x0f) { 4028 case 0: 4029 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 4030 break; 4031 case 6: 4032 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4033 break; 4034 case 8: 4035 /* 3D_Detail_X */ 4036 if ((db[9 + offset + i] >> 4) == 1) 4037 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4038 break; 4039 } 4040 4041 if (newflag != 0) { 4042 newmode = drm_display_mode_from_vic_index(connector, 4043 video_db, 4044 video_len, 4045 vic_index); 4046 4047 if (newmode) { 4048 newmode->flags |= newflag; 4049 drm_mode_probed_add(connector, newmode); 4050 modes++; 4051 } 4052 } 4053 4054 if (detail_present) 4055 i++; 4056 } 4057 4058 out: 4059 if (modes > 0) 4060 info->has_hdmi_infoframe = true; 4061 return modes; 4062 } 4063 4064 static int 4065 cea_db_payload_len(const u8 *db) 4066 { 4067 return db[0] & 0x1f; 4068 } 4069 4070 static int 4071 cea_db_extended_tag(const u8 *db) 4072 { 4073 return db[1]; 4074 } 4075 4076 static int 4077 cea_db_tag(const u8 *db) 4078 { 4079 return db[0] >> 5; 4080 } 4081 4082 static int 4083 cea_revision(const u8 *cea) 4084 { 4085 /* 4086 * FIXME is this correct for the DispID variant? 4087 * The DispID spec doesn't really specify whether 4088 * this is the revision of the CEA extension or 4089 * the DispID CEA data block. And the only value 4090 * given as an example is 0. 4091 */ 4092 return cea[1]; 4093 } 4094 4095 static int 4096 cea_db_offsets(const u8 *cea, int *start, int *end) 4097 { 4098 /* DisplayID CTA extension blocks and top-level CEA EDID 4099 * block header definitions differ in the following bytes: 4100 * 1) Byte 2 of the header specifies length differently, 4101 * 2) Byte 3 is only present in the CEA top level block. 4102 * 4103 * The different definitions for byte 2 follow. 4104 * 4105 * DisplayID CTA extension block defines byte 2 as: 4106 * Number of payload bytes 4107 * 4108 * CEA EDID block defines byte 2 as: 4109 * Byte number (decimal) within this block where the 18-byte 4110 * DTDs begin. If no non-DTD data is present in this extension 4111 * block, the value should be set to 04h (the byte after next). 4112 * If set to 00h, there are no DTDs present in this block and 4113 * no non-DTD data. 4114 */ 4115 if (cea[0] == DATA_BLOCK_CTA) { 4116 /* 4117 * for_each_displayid_db() has already verified 4118 * that these stay within expected bounds. 4119 */ 4120 *start = 3; 4121 *end = *start + cea[2]; 4122 } else if (cea[0] == CEA_EXT) { 4123 /* Data block offset in CEA extension block */ 4124 *start = 4; 4125 *end = cea[2]; 4126 if (*end == 0) 4127 *end = 127; 4128 if (*end < 4 || *end > 127) 4129 return -ERANGE; 4130 } else { 4131 return -EOPNOTSUPP; 4132 } 4133 4134 return 0; 4135 } 4136 4137 static bool cea_db_is_hdmi_vsdb(const u8 *db) 4138 { 4139 int hdmi_id; 4140 4141 if (cea_db_tag(db) != VENDOR_BLOCK) 4142 return false; 4143 4144 if (cea_db_payload_len(db) < 5) 4145 return false; 4146 4147 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 4148 4149 return hdmi_id == HDMI_IEEE_OUI; 4150 } 4151 4152 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 4153 { 4154 unsigned int oui; 4155 4156 if (cea_db_tag(db) != VENDOR_BLOCK) 4157 return false; 4158 4159 if (cea_db_payload_len(db) < 7) 4160 return false; 4161 4162 oui = db[3] << 16 | db[2] << 8 | db[1]; 4163 4164 return oui == HDMI_FORUM_IEEE_OUI; 4165 } 4166 4167 static bool cea_db_is_vcdb(const u8 *db) 4168 { 4169 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4170 return false; 4171 4172 if (cea_db_payload_len(db) != 2) 4173 return false; 4174 4175 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK) 4176 return false; 4177 4178 return true; 4179 } 4180 4181 static bool cea_db_is_y420cmdb(const u8 *db) 4182 { 4183 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4184 return false; 4185 4186 if (!cea_db_payload_len(db)) 4187 return false; 4188 4189 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 4190 return false; 4191 4192 return true; 4193 } 4194 4195 static bool cea_db_is_y420vdb(const u8 *db) 4196 { 4197 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4198 return false; 4199 4200 if (!cea_db_payload_len(db)) 4201 return false; 4202 4203 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 4204 return false; 4205 4206 return true; 4207 } 4208 4209 #define for_each_cea_db(cea, i, start, end) \ 4210 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 4211 4212 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 4213 const u8 *db) 4214 { 4215 struct drm_display_info *info = &connector->display_info; 4216 struct drm_hdmi_info *hdmi = &info->hdmi; 4217 u8 map_len = cea_db_payload_len(db) - 1; 4218 u8 count; 4219 u64 map = 0; 4220 4221 if (map_len == 0) { 4222 /* All CEA modes support ycbcr420 sampling also.*/ 4223 hdmi->y420_cmdb_map = U64_MAX; 4224 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 4225 return; 4226 } 4227 4228 /* 4229 * This map indicates which of the existing CEA block modes 4230 * from VDB can support YCBCR420 output too. So if bit=0 is 4231 * set, first mode from VDB can support YCBCR420 output too. 4232 * We will parse and keep this map, before parsing VDB itself 4233 * to avoid going through the same block again and again. 4234 * 4235 * Spec is not clear about max possible size of this block. 4236 * Clamping max bitmap block size at 8 bytes. Every byte can 4237 * address 8 CEA modes, in this way this map can address 4238 * 8*8 = first 64 SVDs. 4239 */ 4240 if (WARN_ON_ONCE(map_len > 8)) 4241 map_len = 8; 4242 4243 for (count = 0; count < map_len; count++) 4244 map |= (u64)db[2 + count] << (8 * count); 4245 4246 if (map) 4247 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 4248 4249 hdmi->y420_cmdb_map = map; 4250 } 4251 4252 static int 4253 add_cea_modes(struct drm_connector *connector, struct edid *edid) 4254 { 4255 const u8 *cea = drm_find_cea_extension(edid); 4256 const u8 *db, *hdmi = NULL, *video = NULL; 4257 u8 dbl, hdmi_len, video_len = 0; 4258 int modes = 0; 4259 4260 if (cea && cea_revision(cea) >= 3) { 4261 int i, start, end; 4262 4263 if (cea_db_offsets(cea, &start, &end)) 4264 return 0; 4265 4266 for_each_cea_db(cea, i, start, end) { 4267 db = &cea[i]; 4268 dbl = cea_db_payload_len(db); 4269 4270 if (cea_db_tag(db) == VIDEO_BLOCK) { 4271 video = db + 1; 4272 video_len = dbl; 4273 modes += do_cea_modes(connector, video, dbl); 4274 } else if (cea_db_is_hdmi_vsdb(db)) { 4275 hdmi = db; 4276 hdmi_len = dbl; 4277 } else if (cea_db_is_y420vdb(db)) { 4278 const u8 *vdb420 = &db[2]; 4279 4280 /* Add 4:2:0(only) modes present in EDID */ 4281 modes += do_y420vdb_modes(connector, 4282 vdb420, 4283 dbl - 1); 4284 } 4285 } 4286 } 4287 4288 /* 4289 * We parse the HDMI VSDB after having added the cea modes as we will 4290 * be patching their flags when the sink supports stereo 3D. 4291 */ 4292 if (hdmi) 4293 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 4294 video_len); 4295 4296 return modes; 4297 } 4298 4299 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 4300 { 4301 const struct drm_display_mode *cea_mode; 4302 int clock1, clock2, clock; 4303 u8 vic; 4304 const char *type; 4305 4306 /* 4307 * allow 5kHz clock difference either way to account for 4308 * the 10kHz clock resolution limit of detailed timings. 4309 */ 4310 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 4311 if (drm_valid_cea_vic(vic)) { 4312 type = "CEA"; 4313 cea_mode = cea_mode_for_vic(vic); 4314 clock1 = cea_mode->clock; 4315 clock2 = cea_mode_alternate_clock(cea_mode); 4316 } else { 4317 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 4318 if (drm_valid_hdmi_vic(vic)) { 4319 type = "HDMI"; 4320 cea_mode = &edid_4k_modes[vic]; 4321 clock1 = cea_mode->clock; 4322 clock2 = hdmi_mode_alternate_clock(cea_mode); 4323 } else { 4324 return; 4325 } 4326 } 4327 4328 /* pick whichever is closest */ 4329 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 4330 clock = clock1; 4331 else 4332 clock = clock2; 4333 4334 if (mode->clock == clock) 4335 return; 4336 4337 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 4338 type, vic, mode->clock, clock); 4339 mode->clock = clock; 4340 } 4341 4342 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db) 4343 { 4344 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4345 return false; 4346 4347 if (db[1] != HDR_STATIC_METADATA_BLOCK) 4348 return false; 4349 4350 if (cea_db_payload_len(db) < 3) 4351 return false; 4352 4353 return true; 4354 } 4355 4356 static uint8_t eotf_supported(const u8 *edid_ext) 4357 { 4358 return edid_ext[2] & 4359 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 4360 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 4361 BIT(HDMI_EOTF_SMPTE_ST2084) | 4362 BIT(HDMI_EOTF_BT_2100_HLG)); 4363 } 4364 4365 static uint8_t hdr_metadata_type(const u8 *edid_ext) 4366 { 4367 return edid_ext[3] & 4368 BIT(HDMI_STATIC_METADATA_TYPE1); 4369 } 4370 4371 static void 4372 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 4373 { 4374 u16 len; 4375 4376 len = cea_db_payload_len(db); 4377 4378 connector->hdr_sink_metadata.hdmi_type1.eotf = 4379 eotf_supported(db); 4380 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 4381 hdr_metadata_type(db); 4382 4383 if (len >= 4) 4384 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 4385 if (len >= 5) 4386 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 4387 if (len >= 6) 4388 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 4389 } 4390 4391 static void 4392 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 4393 { 4394 u8 len = cea_db_payload_len(db); 4395 4396 if (len >= 6 && (db[6] & (1 << 7))) 4397 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 4398 if (len >= 8) { 4399 connector->latency_present[0] = db[8] >> 7; 4400 connector->latency_present[1] = (db[8] >> 6) & 1; 4401 } 4402 if (len >= 9) 4403 connector->video_latency[0] = db[9]; 4404 if (len >= 10) 4405 connector->audio_latency[0] = db[10]; 4406 if (len >= 11) 4407 connector->video_latency[1] = db[11]; 4408 if (len >= 12) 4409 connector->audio_latency[1] = db[12]; 4410 4411 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 4412 "video latency %d %d, " 4413 "audio latency %d %d\n", 4414 connector->latency_present[0], 4415 connector->latency_present[1], 4416 connector->video_latency[0], 4417 connector->video_latency[1], 4418 connector->audio_latency[0], 4419 connector->audio_latency[1]); 4420 } 4421 4422 static void 4423 monitor_name(struct detailed_timing *t, void *data) 4424 { 4425 if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME)) 4426 return; 4427 4428 *(u8 **)data = t->data.other_data.data.str.str; 4429 } 4430 4431 static int get_monitor_name(struct edid *edid, char name[13]) 4432 { 4433 char *edid_name = NULL; 4434 int mnl; 4435 4436 if (!edid || !name) 4437 return 0; 4438 4439 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 4440 for (mnl = 0; edid_name && mnl < 13; mnl++) { 4441 if (edid_name[mnl] == 0x0a) 4442 break; 4443 4444 name[mnl] = edid_name[mnl]; 4445 } 4446 4447 return mnl; 4448 } 4449 4450 /** 4451 * drm_edid_get_monitor_name - fetch the monitor name from the edid 4452 * @edid: monitor EDID information 4453 * @name: pointer to a character array to hold the name of the monitor 4454 * @bufsize: The size of the name buffer (should be at least 14 chars.) 4455 * 4456 */ 4457 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 4458 { 4459 int name_length; 4460 char buf[13]; 4461 4462 if (bufsize <= 0) 4463 return; 4464 4465 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 4466 memcpy(name, buf, name_length); 4467 name[name_length] = '\0'; 4468 } 4469 EXPORT_SYMBOL(drm_edid_get_monitor_name); 4470 4471 static void clear_eld(struct drm_connector *connector) 4472 { 4473 memset(connector->eld, 0, sizeof(connector->eld)); 4474 4475 connector->latency_present[0] = false; 4476 connector->latency_present[1] = false; 4477 connector->video_latency[0] = 0; 4478 connector->audio_latency[0] = 0; 4479 connector->video_latency[1] = 0; 4480 connector->audio_latency[1] = 0; 4481 } 4482 4483 /* 4484 * drm_edid_to_eld - build ELD from EDID 4485 * @connector: connector corresponding to the HDMI/DP sink 4486 * @edid: EDID to parse 4487 * 4488 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 4489 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 4490 */ 4491 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 4492 { 4493 uint8_t *eld = connector->eld; 4494 const u8 *cea; 4495 const u8 *db; 4496 int total_sad_count = 0; 4497 int mnl; 4498 int dbl; 4499 4500 clear_eld(connector); 4501 4502 if (!edid) 4503 return; 4504 4505 cea = drm_find_cea_extension(edid); 4506 if (!cea) { 4507 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 4508 return; 4509 } 4510 4511 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 4512 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); 4513 4514 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT; 4515 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 4516 4517 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 4518 4519 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0]; 4520 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1]; 4521 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0]; 4522 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1]; 4523 4524 if (cea_revision(cea) >= 3) { 4525 int i, start, end; 4526 int sad_count; 4527 4528 if (cea_db_offsets(cea, &start, &end)) { 4529 start = 0; 4530 end = 0; 4531 } 4532 4533 for_each_cea_db(cea, i, start, end) { 4534 db = &cea[i]; 4535 dbl = cea_db_payload_len(db); 4536 4537 switch (cea_db_tag(db)) { 4538 case AUDIO_BLOCK: 4539 /* Audio Data Block, contains SADs */ 4540 sad_count = min(dbl / 3, 15 - total_sad_count); 4541 if (sad_count >= 1) 4542 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 4543 &db[1], sad_count * 3); 4544 total_sad_count += sad_count; 4545 break; 4546 case SPEAKER_BLOCK: 4547 /* Speaker Allocation Data Block */ 4548 if (dbl >= 1) 4549 eld[DRM_ELD_SPEAKER] = db[1]; 4550 break; 4551 case VENDOR_BLOCK: 4552 /* HDMI Vendor-Specific Data Block */ 4553 if (cea_db_is_hdmi_vsdb(db)) 4554 drm_parse_hdmi_vsdb_audio(connector, db); 4555 break; 4556 default: 4557 break; 4558 } 4559 } 4560 } 4561 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 4562 4563 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 4564 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4565 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 4566 else 4567 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 4568 4569 eld[DRM_ELD_BASELINE_ELD_LEN] = 4570 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 4571 4572 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 4573 drm_eld_size(eld), total_sad_count); 4574 } 4575 4576 /** 4577 * drm_edid_to_sad - extracts SADs from EDID 4578 * @edid: EDID to parse 4579 * @sads: pointer that will be set to the extracted SADs 4580 * 4581 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 4582 * 4583 * Note: The returned pointer needs to be freed using kfree(). 4584 * 4585 * Return: The number of found SADs or negative number on error. 4586 */ 4587 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 4588 { 4589 int count = 0; 4590 int i, start, end, dbl; 4591 const u8 *cea; 4592 4593 cea = drm_find_cea_extension(edid); 4594 if (!cea) { 4595 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4596 return 0; 4597 } 4598 4599 if (cea_revision(cea) < 3) { 4600 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4601 return 0; 4602 } 4603 4604 if (cea_db_offsets(cea, &start, &end)) { 4605 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4606 return -EPROTO; 4607 } 4608 4609 for_each_cea_db(cea, i, start, end) { 4610 const u8 *db = &cea[i]; 4611 4612 if (cea_db_tag(db) == AUDIO_BLOCK) { 4613 int j; 4614 4615 dbl = cea_db_payload_len(db); 4616 4617 count = dbl / 3; /* SAD is 3B */ 4618 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 4619 if (!*sads) 4620 return -ENOMEM; 4621 for (j = 0; j < count; j++) { 4622 const u8 *sad = &db[1 + j * 3]; 4623 4624 (*sads)[j].format = (sad[0] & 0x78) >> 3; 4625 (*sads)[j].channels = sad[0] & 0x7; 4626 (*sads)[j].freq = sad[1] & 0x7F; 4627 (*sads)[j].byte2 = sad[2]; 4628 } 4629 break; 4630 } 4631 } 4632 4633 return count; 4634 } 4635 EXPORT_SYMBOL(drm_edid_to_sad); 4636 4637 /** 4638 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 4639 * @edid: EDID to parse 4640 * @sadb: pointer to the speaker block 4641 * 4642 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 4643 * 4644 * Note: The returned pointer needs to be freed using kfree(). 4645 * 4646 * Return: The number of found Speaker Allocation Blocks or negative number on 4647 * error. 4648 */ 4649 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 4650 { 4651 int count = 0; 4652 int i, start, end, dbl; 4653 const u8 *cea; 4654 4655 cea = drm_find_cea_extension(edid); 4656 if (!cea) { 4657 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4658 return 0; 4659 } 4660 4661 if (cea_revision(cea) < 3) { 4662 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4663 return 0; 4664 } 4665 4666 if (cea_db_offsets(cea, &start, &end)) { 4667 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4668 return -EPROTO; 4669 } 4670 4671 for_each_cea_db(cea, i, start, end) { 4672 const u8 *db = &cea[i]; 4673 4674 if (cea_db_tag(db) == SPEAKER_BLOCK) { 4675 dbl = cea_db_payload_len(db); 4676 4677 /* Speaker Allocation Data Block */ 4678 if (dbl == 3) { 4679 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 4680 if (!*sadb) 4681 return -ENOMEM; 4682 count = dbl; 4683 break; 4684 } 4685 } 4686 } 4687 4688 return count; 4689 } 4690 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 4691 4692 /** 4693 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 4694 * @connector: connector associated with the HDMI/DP sink 4695 * @mode: the display mode 4696 * 4697 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 4698 * the sink doesn't support audio or video. 4699 */ 4700 int drm_av_sync_delay(struct drm_connector *connector, 4701 const struct drm_display_mode *mode) 4702 { 4703 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 4704 int a, v; 4705 4706 if (!connector->latency_present[0]) 4707 return 0; 4708 if (!connector->latency_present[1]) 4709 i = 0; 4710 4711 a = connector->audio_latency[i]; 4712 v = connector->video_latency[i]; 4713 4714 /* 4715 * HDMI/DP sink doesn't support audio or video? 4716 */ 4717 if (a == 255 || v == 255) 4718 return 0; 4719 4720 /* 4721 * Convert raw EDID values to millisecond. 4722 * Treat unknown latency as 0ms. 4723 */ 4724 if (a) 4725 a = min(2 * (a - 1), 500); 4726 if (v) 4727 v = min(2 * (v - 1), 500); 4728 4729 return max(v - a, 0); 4730 } 4731 EXPORT_SYMBOL(drm_av_sync_delay); 4732 4733 /** 4734 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 4735 * @edid: monitor EDID information 4736 * 4737 * Parse the CEA extension according to CEA-861-B. 4738 * 4739 * Drivers that have added the modes parsed from EDID to drm_display_info 4740 * should use &drm_display_info.is_hdmi instead of calling this function. 4741 * 4742 * Return: True if the monitor is HDMI, false if not or unknown. 4743 */ 4744 bool drm_detect_hdmi_monitor(struct edid *edid) 4745 { 4746 const u8 *edid_ext; 4747 int i; 4748 int start_offset, end_offset; 4749 4750 edid_ext = drm_find_cea_extension(edid); 4751 if (!edid_ext) 4752 return false; 4753 4754 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4755 return false; 4756 4757 /* 4758 * Because HDMI identifier is in Vendor Specific Block, 4759 * search it from all data blocks of CEA extension. 4760 */ 4761 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4762 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 4763 return true; 4764 } 4765 4766 return false; 4767 } 4768 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 4769 4770 /** 4771 * drm_detect_monitor_audio - check monitor audio capability 4772 * @edid: EDID block to scan 4773 * 4774 * Monitor should have CEA extension block. 4775 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 4776 * audio' only. If there is any audio extension block and supported 4777 * audio format, assume at least 'basic audio' support, even if 'basic 4778 * audio' is not defined in EDID. 4779 * 4780 * Return: True if the monitor supports audio, false otherwise. 4781 */ 4782 bool drm_detect_monitor_audio(struct edid *edid) 4783 { 4784 const u8 *edid_ext; 4785 int i, j; 4786 bool has_audio = false; 4787 int start_offset, end_offset; 4788 4789 edid_ext = drm_find_cea_extension(edid); 4790 if (!edid_ext) 4791 goto end; 4792 4793 has_audio = (edid_ext[0] == CEA_EXT && 4794 (edid_ext[3] & EDID_BASIC_AUDIO) != 0); 4795 4796 if (has_audio) { 4797 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 4798 goto end; 4799 } 4800 4801 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4802 goto end; 4803 4804 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4805 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 4806 has_audio = true; 4807 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 4808 DRM_DEBUG_KMS("CEA audio format %d\n", 4809 (edid_ext[i + j] >> 3) & 0xf); 4810 goto end; 4811 } 4812 } 4813 end: 4814 return has_audio; 4815 } 4816 EXPORT_SYMBOL(drm_detect_monitor_audio); 4817 4818 4819 /** 4820 * drm_default_rgb_quant_range - default RGB quantization range 4821 * @mode: display mode 4822 * 4823 * Determine the default RGB quantization range for the mode, 4824 * as specified in CEA-861. 4825 * 4826 * Return: The default RGB quantization range for the mode 4827 */ 4828 enum hdmi_quantization_range 4829 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 4830 { 4831 /* All CEA modes other than VIC 1 use limited quantization range. */ 4832 return drm_match_cea_mode(mode) > 1 ? 4833 HDMI_QUANTIZATION_RANGE_LIMITED : 4834 HDMI_QUANTIZATION_RANGE_FULL; 4835 } 4836 EXPORT_SYMBOL(drm_default_rgb_quant_range); 4837 4838 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 4839 { 4840 struct drm_display_info *info = &connector->display_info; 4841 4842 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]); 4843 4844 if (db[2] & EDID_CEA_VCDB_QS) 4845 info->rgb_quant_range_selectable = true; 4846 } 4847 4848 static 4849 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) 4850 { 4851 switch (max_frl_rate) { 4852 case 1: 4853 *max_lanes = 3; 4854 *max_rate_per_lane = 3; 4855 break; 4856 case 2: 4857 *max_lanes = 3; 4858 *max_rate_per_lane = 6; 4859 break; 4860 case 3: 4861 *max_lanes = 4; 4862 *max_rate_per_lane = 6; 4863 break; 4864 case 4: 4865 *max_lanes = 4; 4866 *max_rate_per_lane = 8; 4867 break; 4868 case 5: 4869 *max_lanes = 4; 4870 *max_rate_per_lane = 10; 4871 break; 4872 case 6: 4873 *max_lanes = 4; 4874 *max_rate_per_lane = 12; 4875 break; 4876 case 0: 4877 default: 4878 *max_lanes = 0; 4879 *max_rate_per_lane = 0; 4880 } 4881 } 4882 4883 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 4884 const u8 *db) 4885 { 4886 u8 dc_mask; 4887 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4888 4889 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 4890 hdmi->y420_dc_modes = dc_mask; 4891 } 4892 4893 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, 4894 const u8 *hf_vsdb) 4895 { 4896 struct drm_display_info *display = &connector->display_info; 4897 struct drm_hdmi_info *hdmi = &display->hdmi; 4898 4899 display->has_hdmi_infoframe = true; 4900 4901 if (hf_vsdb[6] & 0x80) { 4902 hdmi->scdc.supported = true; 4903 if (hf_vsdb[6] & 0x40) 4904 hdmi->scdc.read_request = true; 4905 } 4906 4907 /* 4908 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 4909 * And as per the spec, three factors confirm this: 4910 * * Availability of a HF-VSDB block in EDID (check) 4911 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 4912 * * SCDC support available (let's check) 4913 * Lets check it out. 4914 */ 4915 4916 if (hf_vsdb[5]) { 4917 /* max clock is 5000 KHz times block value */ 4918 u32 max_tmds_clock = hf_vsdb[5] * 5000; 4919 struct drm_scdc *scdc = &hdmi->scdc; 4920 4921 if (max_tmds_clock > 340000) { 4922 display->max_tmds_clock = max_tmds_clock; 4923 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 4924 display->max_tmds_clock); 4925 } 4926 4927 if (scdc->supported) { 4928 scdc->scrambling.supported = true; 4929 4930 /* Few sinks support scrambling for clocks < 340M */ 4931 if ((hf_vsdb[6] & 0x8)) 4932 scdc->scrambling.low_rates = true; 4933 } 4934 } 4935 4936 if (hf_vsdb[7]) { 4937 u8 max_frl_rate; 4938 u8 dsc_max_frl_rate; 4939 u8 dsc_max_slices; 4940 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; 4941 4942 DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n"); 4943 max_frl_rate = (hf_vsdb[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; 4944 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, 4945 &hdmi->max_frl_rate_per_lane); 4946 hdmi_dsc->v_1p2 = hf_vsdb[11] & DRM_EDID_DSC_1P2; 4947 4948 if (hdmi_dsc->v_1p2) { 4949 hdmi_dsc->native_420 = hf_vsdb[11] & DRM_EDID_DSC_NATIVE_420; 4950 hdmi_dsc->all_bpp = hf_vsdb[11] & DRM_EDID_DSC_ALL_BPP; 4951 4952 if (hf_vsdb[11] & DRM_EDID_DSC_16BPC) 4953 hdmi_dsc->bpc_supported = 16; 4954 else if (hf_vsdb[11] & DRM_EDID_DSC_12BPC) 4955 hdmi_dsc->bpc_supported = 12; 4956 else if (hf_vsdb[11] & DRM_EDID_DSC_10BPC) 4957 hdmi_dsc->bpc_supported = 10; 4958 else 4959 hdmi_dsc->bpc_supported = 0; 4960 4961 dsc_max_frl_rate = (hf_vsdb[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; 4962 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, 4963 &hdmi_dsc->max_frl_rate_per_lane); 4964 hdmi_dsc->total_chunk_kbytes = hf_vsdb[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; 4965 4966 dsc_max_slices = hf_vsdb[12] & DRM_EDID_DSC_MAX_SLICES; 4967 switch (dsc_max_slices) { 4968 case 1: 4969 hdmi_dsc->max_slices = 1; 4970 hdmi_dsc->clk_per_slice = 340; 4971 break; 4972 case 2: 4973 hdmi_dsc->max_slices = 2; 4974 hdmi_dsc->clk_per_slice = 340; 4975 break; 4976 case 3: 4977 hdmi_dsc->max_slices = 4; 4978 hdmi_dsc->clk_per_slice = 340; 4979 break; 4980 case 4: 4981 hdmi_dsc->max_slices = 8; 4982 hdmi_dsc->clk_per_slice = 340; 4983 break; 4984 case 5: 4985 hdmi_dsc->max_slices = 8; 4986 hdmi_dsc->clk_per_slice = 400; 4987 break; 4988 case 6: 4989 hdmi_dsc->max_slices = 12; 4990 hdmi_dsc->clk_per_slice = 400; 4991 break; 4992 case 7: 4993 hdmi_dsc->max_slices = 16; 4994 hdmi_dsc->clk_per_slice = 400; 4995 break; 4996 case 0: 4997 default: 4998 hdmi_dsc->max_slices = 0; 4999 hdmi_dsc->clk_per_slice = 0; 5000 } 5001 } 5002 } 5003 5004 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb); 5005 } 5006 5007 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 5008 const u8 *hdmi) 5009 { 5010 struct drm_display_info *info = &connector->display_info; 5011 unsigned int dc_bpc = 0; 5012 5013 /* HDMI supports at least 8 bpc */ 5014 info->bpc = 8; 5015 5016 if (cea_db_payload_len(hdmi) < 6) 5017 return; 5018 5019 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 5020 dc_bpc = 10; 5021 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30; 5022 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 5023 connector->name); 5024 } 5025 5026 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 5027 dc_bpc = 12; 5028 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36; 5029 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 5030 connector->name); 5031 } 5032 5033 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 5034 dc_bpc = 16; 5035 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48; 5036 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 5037 connector->name); 5038 } 5039 5040 if (dc_bpc == 0) { 5041 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 5042 connector->name); 5043 return; 5044 } 5045 5046 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 5047 connector->name, dc_bpc); 5048 info->bpc = dc_bpc; 5049 5050 /* YCRCB444 is optional according to spec. */ 5051 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 5052 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes; 5053 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 5054 connector->name); 5055 } 5056 5057 /* 5058 * Spec says that if any deep color mode is supported at all, 5059 * then deep color 36 bit must be supported. 5060 */ 5061 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 5062 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 5063 connector->name); 5064 } 5065 } 5066 5067 static void 5068 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 5069 { 5070 struct drm_display_info *info = &connector->display_info; 5071 u8 len = cea_db_payload_len(db); 5072 5073 info->is_hdmi = true; 5074 5075 if (len >= 6) 5076 info->dvi_dual = db[6] & 1; 5077 if (len >= 7) 5078 info->max_tmds_clock = db[7] * 5000; 5079 5080 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 5081 "max TMDS clock %d kHz\n", 5082 info->dvi_dual, 5083 info->max_tmds_clock); 5084 5085 drm_parse_hdmi_deep_color_info(connector, db); 5086 } 5087 5088 static void drm_parse_cea_ext(struct drm_connector *connector, 5089 const struct edid *edid) 5090 { 5091 struct drm_display_info *info = &connector->display_info; 5092 const u8 *edid_ext; 5093 int i, start, end; 5094 5095 edid_ext = drm_find_cea_extension(edid); 5096 if (!edid_ext) 5097 return; 5098 5099 info->cea_rev = edid_ext[1]; 5100 5101 /* The existence of a CEA block should imply RGB support */ 5102 info->color_formats = DRM_COLOR_FORMAT_RGB444; 5103 if (edid_ext[3] & EDID_CEA_YCRCB444) 5104 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 5105 if (edid_ext[3] & EDID_CEA_YCRCB422) 5106 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 5107 5108 if (cea_db_offsets(edid_ext, &start, &end)) 5109 return; 5110 5111 for_each_cea_db(edid_ext, i, start, end) { 5112 const u8 *db = &edid_ext[i]; 5113 5114 if (cea_db_is_hdmi_vsdb(db)) 5115 drm_parse_hdmi_vsdb_video(connector, db); 5116 if (cea_db_is_hdmi_forum_vsdb(db)) 5117 drm_parse_hdmi_forum_vsdb(connector, db); 5118 if (cea_db_is_y420cmdb(db)) 5119 drm_parse_y420cmdb_bitmap(connector, db); 5120 if (cea_db_is_vcdb(db)) 5121 drm_parse_vcdb(connector, db); 5122 if (cea_db_is_hdmi_hdr_metadata_block(db)) 5123 drm_parse_hdr_metadata_block(connector, db); 5124 } 5125 } 5126 5127 static 5128 void get_monitor_range(struct detailed_timing *timing, 5129 void *info_monitor_range) 5130 { 5131 struct drm_monitor_range_info *monitor_range = info_monitor_range; 5132 const struct detailed_non_pixel *data = &timing->data.other_data; 5133 const struct detailed_data_monitor_range *range = &data->data.range; 5134 5135 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE)) 5136 return; 5137 5138 /* 5139 * Check for flag range limits only. If flag == 1 then 5140 * no additional timing information provided. 5141 * Default GTF, GTF Secondary curve and CVT are not 5142 * supported 5143 */ 5144 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 5145 return; 5146 5147 monitor_range->min_vfreq = range->min_vfreq; 5148 monitor_range->max_vfreq = range->max_vfreq; 5149 } 5150 5151 static 5152 void drm_get_monitor_range(struct drm_connector *connector, 5153 const struct edid *edid) 5154 { 5155 struct drm_display_info *info = &connector->display_info; 5156 5157 if (!version_greater(edid, 1, 1)) 5158 return; 5159 5160 drm_for_each_detailed_block((u8 *)edid, get_monitor_range, 5161 &info->monitor_range); 5162 5163 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 5164 info->monitor_range.min_vfreq, 5165 info->monitor_range.max_vfreq); 5166 } 5167 5168 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 5169 * all of the values which would have been set from EDID 5170 */ 5171 void 5172 drm_reset_display_info(struct drm_connector *connector) 5173 { 5174 struct drm_display_info *info = &connector->display_info; 5175 5176 info->width_mm = 0; 5177 info->height_mm = 0; 5178 5179 info->bpc = 0; 5180 info->color_formats = 0; 5181 info->cea_rev = 0; 5182 info->max_tmds_clock = 0; 5183 info->dvi_dual = false; 5184 info->is_hdmi = false; 5185 info->has_hdmi_infoframe = false; 5186 info->rgb_quant_range_selectable = false; 5187 memset(&info->hdmi, 0, sizeof(info->hdmi)); 5188 5189 info->non_desktop = 0; 5190 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 5191 } 5192 5193 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) 5194 { 5195 struct drm_display_info *info = &connector->display_info; 5196 5197 u32 quirks = edid_get_quirks(edid); 5198 5199 drm_reset_display_info(connector); 5200 5201 info->width_mm = edid->width_cm * 10; 5202 info->height_mm = edid->height_cm * 10; 5203 5204 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); 5205 5206 drm_get_monitor_range(connector, edid); 5207 5208 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); 5209 5210 if (edid->revision < 3) 5211 return quirks; 5212 5213 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 5214 return quirks; 5215 5216 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 5217 drm_parse_cea_ext(connector, edid); 5218 5219 /* 5220 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 5221 * 5222 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 5223 * tells us to assume 8 bpc color depth if the EDID doesn't have 5224 * extensions which tell otherwise. 5225 */ 5226 if (info->bpc == 0 && edid->revision == 3 && 5227 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 5228 info->bpc = 8; 5229 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 5230 connector->name, info->bpc); 5231 } 5232 5233 /* Only defined for 1.4 with digital displays */ 5234 if (edid->revision < 4) 5235 return quirks; 5236 5237 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 5238 case DRM_EDID_DIGITAL_DEPTH_6: 5239 info->bpc = 6; 5240 break; 5241 case DRM_EDID_DIGITAL_DEPTH_8: 5242 info->bpc = 8; 5243 break; 5244 case DRM_EDID_DIGITAL_DEPTH_10: 5245 info->bpc = 10; 5246 break; 5247 case DRM_EDID_DIGITAL_DEPTH_12: 5248 info->bpc = 12; 5249 break; 5250 case DRM_EDID_DIGITAL_DEPTH_14: 5251 info->bpc = 14; 5252 break; 5253 case DRM_EDID_DIGITAL_DEPTH_16: 5254 info->bpc = 16; 5255 break; 5256 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 5257 default: 5258 info->bpc = 0; 5259 break; 5260 } 5261 5262 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 5263 connector->name, info->bpc); 5264 5265 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 5266 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 5267 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 5268 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 5269 return quirks; 5270 } 5271 5272 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 5273 struct displayid_detailed_timings_1 *timings) 5274 { 5275 struct drm_display_mode *mode; 5276 unsigned pixel_clock = (timings->pixel_clock[0] | 5277 (timings->pixel_clock[1] << 8) | 5278 (timings->pixel_clock[2] << 16)) + 1; 5279 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 5280 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 5281 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 5282 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 5283 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 5284 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 5285 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 5286 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 5287 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 5288 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 5289 5290 mode = drm_mode_create(dev); 5291 if (!mode) 5292 return NULL; 5293 5294 mode->clock = pixel_clock * 10; 5295 mode->hdisplay = hactive; 5296 mode->hsync_start = mode->hdisplay + hsync; 5297 mode->hsync_end = mode->hsync_start + hsync_width; 5298 mode->htotal = mode->hdisplay + hblank; 5299 5300 mode->vdisplay = vactive; 5301 mode->vsync_start = mode->vdisplay + vsync; 5302 mode->vsync_end = mode->vsync_start + vsync_width; 5303 mode->vtotal = mode->vdisplay + vblank; 5304 5305 mode->flags = 0; 5306 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 5307 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 5308 mode->type = DRM_MODE_TYPE_DRIVER; 5309 5310 if (timings->flags & 0x80) 5311 mode->type |= DRM_MODE_TYPE_PREFERRED; 5312 drm_mode_set_name(mode); 5313 5314 return mode; 5315 } 5316 5317 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 5318 const struct displayid_block *block) 5319 { 5320 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 5321 int i; 5322 int num_timings; 5323 struct drm_display_mode *newmode; 5324 int num_modes = 0; 5325 /* blocks must be multiple of 20 bytes length */ 5326 if (block->num_bytes % 20) 5327 return 0; 5328 5329 num_timings = block->num_bytes / 20; 5330 for (i = 0; i < num_timings; i++) { 5331 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 5332 5333 newmode = drm_mode_displayid_detailed(connector->dev, timings); 5334 if (!newmode) 5335 continue; 5336 5337 drm_mode_probed_add(connector, newmode); 5338 num_modes++; 5339 } 5340 return num_modes; 5341 } 5342 5343 static int add_displayid_detailed_modes(struct drm_connector *connector, 5344 struct edid *edid) 5345 { 5346 const struct displayid_block *block; 5347 struct displayid_iter iter; 5348 int num_modes = 0; 5349 5350 displayid_iter_edid_begin(edid, &iter); 5351 displayid_iter_for_each(block, &iter) { 5352 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING) 5353 num_modes += add_displayid_detailed_1_modes(connector, block); 5354 } 5355 displayid_iter_end(&iter); 5356 5357 return num_modes; 5358 } 5359 5360 /** 5361 * drm_add_edid_modes - add modes from EDID data, if available 5362 * @connector: connector we're probing 5363 * @edid: EDID data 5364 * 5365 * Add the specified modes to the connector's mode list. Also fills out the 5366 * &drm_display_info structure and ELD in @connector with any information which 5367 * can be derived from the edid. 5368 * 5369 * Return: The number of modes added or 0 if we couldn't find any. 5370 */ 5371 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 5372 { 5373 int num_modes = 0; 5374 u32 quirks; 5375 5376 if (edid == NULL) { 5377 clear_eld(connector); 5378 return 0; 5379 } 5380 if (!drm_edid_is_valid(edid)) { 5381 clear_eld(connector); 5382 drm_warn(connector->dev, "%s: EDID invalid.\n", 5383 connector->name); 5384 return 0; 5385 } 5386 5387 drm_edid_to_eld(connector, edid); 5388 5389 /* 5390 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 5391 * To avoid multiple parsing of same block, lets parse that map 5392 * from sink info, before parsing CEA modes. 5393 */ 5394 quirks = drm_add_display_info(connector, edid); 5395 5396 /* 5397 * EDID spec says modes should be preferred in this order: 5398 * - preferred detailed mode 5399 * - other detailed modes from base block 5400 * - detailed modes from extension blocks 5401 * - CVT 3-byte code modes 5402 * - standard timing codes 5403 * - established timing codes 5404 * - modes inferred from GTF or CVT range information 5405 * 5406 * We get this pretty much right. 5407 * 5408 * XXX order for additional mode types in extension blocks? 5409 */ 5410 num_modes += add_detailed_modes(connector, edid, quirks); 5411 num_modes += add_cvt_modes(connector, edid); 5412 num_modes += add_standard_modes(connector, edid); 5413 num_modes += add_established_modes(connector, edid); 5414 num_modes += add_cea_modes(connector, edid); 5415 num_modes += add_alternate_cea_modes(connector, edid); 5416 num_modes += add_displayid_detailed_modes(connector, edid); 5417 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 5418 num_modes += add_inferred_modes(connector, edid); 5419 5420 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 5421 edid_fixup_preferred(connector, quirks); 5422 5423 if (quirks & EDID_QUIRK_FORCE_6BPC) 5424 connector->display_info.bpc = 6; 5425 5426 if (quirks & EDID_QUIRK_FORCE_8BPC) 5427 connector->display_info.bpc = 8; 5428 5429 if (quirks & EDID_QUIRK_FORCE_10BPC) 5430 connector->display_info.bpc = 10; 5431 5432 if (quirks & EDID_QUIRK_FORCE_12BPC) 5433 connector->display_info.bpc = 12; 5434 5435 return num_modes; 5436 } 5437 EXPORT_SYMBOL(drm_add_edid_modes); 5438 5439 /** 5440 * drm_add_modes_noedid - add modes for the connectors without EDID 5441 * @connector: connector we're probing 5442 * @hdisplay: the horizontal display limit 5443 * @vdisplay: the vertical display limit 5444 * 5445 * Add the specified modes to the connector's mode list. Only when the 5446 * hdisplay/vdisplay is not beyond the given limit, it will be added. 5447 * 5448 * Return: The number of modes added or 0 if we couldn't find any. 5449 */ 5450 int drm_add_modes_noedid(struct drm_connector *connector, 5451 int hdisplay, int vdisplay) 5452 { 5453 int i, count, num_modes = 0; 5454 struct drm_display_mode *mode; 5455 struct drm_device *dev = connector->dev; 5456 5457 count = ARRAY_SIZE(drm_dmt_modes); 5458 if (hdisplay < 0) 5459 hdisplay = 0; 5460 if (vdisplay < 0) 5461 vdisplay = 0; 5462 5463 for (i = 0; i < count; i++) { 5464 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 5465 5466 if (hdisplay && vdisplay) { 5467 /* 5468 * Only when two are valid, they will be used to check 5469 * whether the mode should be added to the mode list of 5470 * the connector. 5471 */ 5472 if (ptr->hdisplay > hdisplay || 5473 ptr->vdisplay > vdisplay) 5474 continue; 5475 } 5476 if (drm_mode_vrefresh(ptr) > 61) 5477 continue; 5478 mode = drm_mode_duplicate(dev, ptr); 5479 if (mode) { 5480 drm_mode_probed_add(connector, mode); 5481 num_modes++; 5482 } 5483 } 5484 return num_modes; 5485 } 5486 EXPORT_SYMBOL(drm_add_modes_noedid); 5487 5488 /** 5489 * drm_set_preferred_mode - Sets the preferred mode of a connector 5490 * @connector: connector whose mode list should be processed 5491 * @hpref: horizontal resolution of preferred mode 5492 * @vpref: vertical resolution of preferred mode 5493 * 5494 * Marks a mode as preferred if it matches the resolution specified by @hpref 5495 * and @vpref. 5496 */ 5497 void drm_set_preferred_mode(struct drm_connector *connector, 5498 int hpref, int vpref) 5499 { 5500 struct drm_display_mode *mode; 5501 5502 list_for_each_entry(mode, &connector->probed_modes, head) { 5503 if (mode->hdisplay == hpref && 5504 mode->vdisplay == vpref) 5505 mode->type |= DRM_MODE_TYPE_PREFERRED; 5506 } 5507 } 5508 EXPORT_SYMBOL(drm_set_preferred_mode); 5509 5510 static bool is_hdmi2_sink(const struct drm_connector *connector) 5511 { 5512 /* 5513 * FIXME: sil-sii8620 doesn't have a connector around when 5514 * we need one, so we have to be prepared for a NULL connector. 5515 */ 5516 if (!connector) 5517 return true; 5518 5519 return connector->display_info.hdmi.scdc.supported || 5520 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420; 5521 } 5522 5523 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf) 5524 { 5525 return sink_eotf & BIT(output_eotf); 5526 } 5527 5528 /** 5529 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with 5530 * HDR metadata from userspace 5531 * @frame: HDMI DRM infoframe 5532 * @conn_state: Connector state containing HDR metadata 5533 * 5534 * Return: 0 on success or a negative error code on failure. 5535 */ 5536 int 5537 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame, 5538 const struct drm_connector_state *conn_state) 5539 { 5540 struct drm_connector *connector; 5541 struct hdr_output_metadata *hdr_metadata; 5542 int err; 5543 5544 if (!frame || !conn_state) 5545 return -EINVAL; 5546 5547 connector = conn_state->connector; 5548 5549 if (!conn_state->hdr_output_metadata) 5550 return -EINVAL; 5551 5552 hdr_metadata = conn_state->hdr_output_metadata->data; 5553 5554 if (!hdr_metadata || !connector) 5555 return -EINVAL; 5556 5557 /* Sink EOTF is Bit map while infoframe is absolute values */ 5558 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf, 5559 connector->hdr_sink_metadata.hdmi_type1.eotf)) { 5560 DRM_DEBUG_KMS("EOTF Not Supported\n"); 5561 return -EINVAL; 5562 } 5563 5564 err = hdmi_drm_infoframe_init(frame); 5565 if (err < 0) 5566 return err; 5567 5568 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf; 5569 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type; 5570 5571 BUILD_BUG_ON(sizeof(frame->display_primaries) != 5572 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries)); 5573 BUILD_BUG_ON(sizeof(frame->white_point) != 5574 sizeof(hdr_metadata->hdmi_metadata_type1.white_point)); 5575 5576 memcpy(&frame->display_primaries, 5577 &hdr_metadata->hdmi_metadata_type1.display_primaries, 5578 sizeof(frame->display_primaries)); 5579 5580 memcpy(&frame->white_point, 5581 &hdr_metadata->hdmi_metadata_type1.white_point, 5582 sizeof(frame->white_point)); 5583 5584 frame->max_display_mastering_luminance = 5585 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance; 5586 frame->min_display_mastering_luminance = 5587 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance; 5588 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall; 5589 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll; 5590 5591 return 0; 5592 } 5593 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata); 5594 5595 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, 5596 const struct drm_display_mode *mode) 5597 { 5598 bool has_hdmi_infoframe = connector ? 5599 connector->display_info.has_hdmi_infoframe : false; 5600 5601 if (!has_hdmi_infoframe) 5602 return 0; 5603 5604 /* No HDMI VIC when signalling 3D video format */ 5605 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 5606 return 0; 5607 5608 return drm_match_hdmi_mode(mode); 5609 } 5610 5611 static u8 drm_mode_cea_vic(const struct drm_connector *connector, 5612 const struct drm_display_mode *mode) 5613 { 5614 u8 vic; 5615 5616 /* 5617 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5618 * we should send its VIC in vendor infoframes, else send the 5619 * VIC in AVI infoframes. Lets check if this mode is present in 5620 * HDMI 1.4b 4K modes 5621 */ 5622 if (drm_mode_hdmi_vic(connector, mode)) 5623 return 0; 5624 5625 vic = drm_match_cea_mode(mode); 5626 5627 /* 5628 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5629 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5630 * have to make sure we dont break HDMI 1.4 sinks. 5631 */ 5632 if (!is_hdmi2_sink(connector) && vic > 64) 5633 return 0; 5634 5635 return vic; 5636 } 5637 5638 /** 5639 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 5640 * data from a DRM display mode 5641 * @frame: HDMI AVI infoframe 5642 * @connector: the connector 5643 * @mode: DRM display mode 5644 * 5645 * Return: 0 on success or a negative error code on failure. 5646 */ 5647 int 5648 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5649 const struct drm_connector *connector, 5650 const struct drm_display_mode *mode) 5651 { 5652 enum hdmi_picture_aspect picture_aspect; 5653 u8 vic, hdmi_vic; 5654 5655 if (!frame || !mode) 5656 return -EINVAL; 5657 5658 hdmi_avi_infoframe_init(frame); 5659 5660 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5661 frame->pixel_repeat = 1; 5662 5663 vic = drm_mode_cea_vic(connector, mode); 5664 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 5665 5666 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5667 5668 /* 5669 * As some drivers don't support atomic, we can't use connector state. 5670 * So just initialize the frame with default values, just the same way 5671 * as it's done with other properties here. 5672 */ 5673 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 5674 frame->itc = 0; 5675 5676 /* 5677 * Populate picture aspect ratio from either 5678 * user input (if specified) or from the CEA/HDMI mode lists. 5679 */ 5680 picture_aspect = mode->picture_aspect_ratio; 5681 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 5682 if (vic) 5683 picture_aspect = drm_get_cea_aspect_ratio(vic); 5684 else if (hdmi_vic) 5685 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 5686 } 5687 5688 /* 5689 * The infoframe can't convey anything but none, 4:3 5690 * and 16:9, so if the user has asked for anything else 5691 * we can only satisfy it by specifying the right VIC. 5692 */ 5693 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 5694 if (vic) { 5695 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 5696 return -EINVAL; 5697 } else if (hdmi_vic) { 5698 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 5699 return -EINVAL; 5700 } else { 5701 return -EINVAL; 5702 } 5703 5704 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5705 } 5706 5707 frame->video_code = vic; 5708 frame->picture_aspect = picture_aspect; 5709 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5710 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5711 5712 return 0; 5713 } 5714 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 5715 5716 /* HDMI Colorspace Spec Definitions */ 5717 #define FULL_COLORIMETRY_MASK 0x1FF 5718 #define NORMAL_COLORIMETRY_MASK 0x3 5719 #define EXTENDED_COLORIMETRY_MASK 0x7 5720 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF 5721 5722 #define C(x) ((x) << 0) 5723 #define EC(x) ((x) << 2) 5724 #define ACE(x) ((x) << 5) 5725 5726 #define HDMI_COLORIMETRY_NO_DATA 0x0 5727 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0)) 5728 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0)) 5729 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0)) 5730 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0)) 5731 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0)) 5732 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0)) 5733 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0)) 5734 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0)) 5735 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0)) 5736 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0)) 5737 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0)) 5738 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1)) 5739 5740 static const u32 hdmi_colorimetry_val[] = { 5741 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA, 5742 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC, 5743 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC, 5744 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601, 5745 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709, 5746 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601, 5747 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601, 5748 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB, 5749 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC, 5750 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB, 5751 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC, 5752 }; 5753 5754 #undef C 5755 #undef EC 5756 #undef ACE 5757 5758 /** 5759 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe 5760 * colorspace information 5761 * @frame: HDMI AVI infoframe 5762 * @conn_state: connector state 5763 */ 5764 void 5765 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 5766 const struct drm_connector_state *conn_state) 5767 { 5768 u32 colorimetry_val; 5769 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK; 5770 5771 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val)) 5772 colorimetry_val = HDMI_COLORIMETRY_NO_DATA; 5773 else 5774 colorimetry_val = hdmi_colorimetry_val[colorimetry_index]; 5775 5776 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK; 5777 /* 5778 * ToDo: Extend it for ACE formats as well. Modify the infoframe 5779 * structure and extend it in drivers/video/hdmi 5780 */ 5781 frame->extended_colorimetry = (colorimetry_val >> 2) & 5782 EXTENDED_COLORIMETRY_MASK; 5783 } 5784 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace); 5785 5786 /** 5787 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 5788 * quantization range information 5789 * @frame: HDMI AVI infoframe 5790 * @connector: the connector 5791 * @mode: DRM display mode 5792 * @rgb_quant_range: RGB quantization range (Q) 5793 */ 5794 void 5795 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 5796 const struct drm_connector *connector, 5797 const struct drm_display_mode *mode, 5798 enum hdmi_quantization_range rgb_quant_range) 5799 { 5800 const struct drm_display_info *info = &connector->display_info; 5801 5802 /* 5803 * CEA-861: 5804 * "A Source shall not send a non-zero Q value that does not correspond 5805 * to the default RGB Quantization Range for the transmitted Picture 5806 * unless the Sink indicates support for the Q bit in a Video 5807 * Capabilities Data Block." 5808 * 5809 * HDMI 2.0 recommends sending non-zero Q when it does match the 5810 * default RGB quantization range for the mode, even when QS=0. 5811 */ 5812 if (info->rgb_quant_range_selectable || 5813 rgb_quant_range == drm_default_rgb_quant_range(mode)) 5814 frame->quantization_range = rgb_quant_range; 5815 else 5816 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 5817 5818 /* 5819 * CEA-861-F: 5820 * "When transmitting any RGB colorimetry, the Source should set the 5821 * YQ-field to match the RGB Quantization Range being transmitted 5822 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 5823 * set YQ=1) and the Sink shall ignore the YQ-field." 5824 * 5825 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 5826 * by non-zero YQ when receiving RGB. There doesn't seem to be any 5827 * good way to tell which version of CEA-861 the sink supports, so 5828 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 5829 * on on CEA-861-F. 5830 */ 5831 if (!is_hdmi2_sink(connector) || 5832 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 5833 frame->ycc_quantization_range = 5834 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 5835 else 5836 frame->ycc_quantization_range = 5837 HDMI_YCC_QUANTIZATION_RANGE_FULL; 5838 } 5839 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 5840 5841 /** 5842 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe 5843 * bar information 5844 * @frame: HDMI AVI infoframe 5845 * @conn_state: connector state 5846 */ 5847 void 5848 drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame, 5849 const struct drm_connector_state *conn_state) 5850 { 5851 frame->right_bar = conn_state->tv.margins.right; 5852 frame->left_bar = conn_state->tv.margins.left; 5853 frame->top_bar = conn_state->tv.margins.top; 5854 frame->bottom_bar = conn_state->tv.margins.bottom; 5855 } 5856 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars); 5857 5858 static enum hdmi_3d_structure 5859 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5860 { 5861 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5862 5863 switch (layout) { 5864 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5865 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5866 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5867 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5868 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5869 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5870 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5871 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5872 case DRM_MODE_FLAG_3D_L_DEPTH: 5873 return HDMI_3D_STRUCTURE_L_DEPTH; 5874 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5875 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5876 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5877 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5878 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5879 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5880 default: 5881 return HDMI_3D_STRUCTURE_INVALID; 5882 } 5883 } 5884 5885 /** 5886 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 5887 * data from a DRM display mode 5888 * @frame: HDMI vendor infoframe 5889 * @connector: the connector 5890 * @mode: DRM display mode 5891 * 5892 * Note that there's is a need to send HDMI vendor infoframes only when using a 5893 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 5894 * function will return -EINVAL, error that can be safely ignored. 5895 * 5896 * Return: 0 on success or a negative error code on failure. 5897 */ 5898 int 5899 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5900 const struct drm_connector *connector, 5901 const struct drm_display_mode *mode) 5902 { 5903 /* 5904 * FIXME: sil-sii8620 doesn't have a connector around when 5905 * we need one, so we have to be prepared for a NULL connector. 5906 */ 5907 bool has_hdmi_infoframe = connector ? 5908 connector->display_info.has_hdmi_infoframe : false; 5909 int err; 5910 5911 if (!frame || !mode) 5912 return -EINVAL; 5913 5914 if (!has_hdmi_infoframe) 5915 return -EINVAL; 5916 5917 err = hdmi_vendor_infoframe_init(frame); 5918 if (err < 0) 5919 return err; 5920 5921 /* 5922 * Even if it's not absolutely necessary to send the infoframe 5923 * (ie.vic==0 and s3d_struct==0) we will still send it if we 5924 * know that the sink can handle it. This is based on a 5925 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 5926 * have trouble realizing that they should switch from 3D to 2D 5927 * mode if the source simply stops sending the infoframe when 5928 * it wants to switch from 3D to 2D. 5929 */ 5930 frame->vic = drm_mode_hdmi_vic(connector, mode); 5931 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5932 5933 return 0; 5934 } 5935 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 5936 5937 static void drm_parse_tiled_block(struct drm_connector *connector, 5938 const struct displayid_block *block) 5939 { 5940 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 5941 u16 w, h; 5942 u8 tile_v_loc, tile_h_loc; 5943 u8 num_v_tile, num_h_tile; 5944 struct drm_tile_group *tg; 5945 5946 w = tile->tile_size[0] | tile->tile_size[1] << 8; 5947 h = tile->tile_size[2] | tile->tile_size[3] << 8; 5948 5949 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 5950 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 5951 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 5952 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 5953 5954 connector->has_tile = true; 5955 if (tile->tile_cap & 0x80) 5956 connector->tile_is_single_monitor = true; 5957 5958 connector->num_h_tile = num_h_tile + 1; 5959 connector->num_v_tile = num_v_tile + 1; 5960 connector->tile_h_loc = tile_h_loc; 5961 connector->tile_v_loc = tile_v_loc; 5962 connector->tile_h_size = w + 1; 5963 connector->tile_v_size = h + 1; 5964 5965 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 5966 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 5967 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 5968 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 5969 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 5970 5971 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 5972 if (!tg) 5973 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 5974 if (!tg) 5975 return; 5976 5977 if (connector->tile_group != tg) { 5978 /* if we haven't got a pointer, 5979 take the reference, drop ref to old tile group */ 5980 if (connector->tile_group) 5981 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5982 connector->tile_group = tg; 5983 } else { 5984 /* if same tile group, then release the ref we just took. */ 5985 drm_mode_put_tile_group(connector->dev, tg); 5986 } 5987 } 5988 5989 void drm_update_tile_info(struct drm_connector *connector, 5990 const struct edid *edid) 5991 { 5992 const struct displayid_block *block; 5993 struct displayid_iter iter; 5994 5995 connector->has_tile = false; 5996 5997 displayid_iter_edid_begin(edid, &iter); 5998 displayid_iter_for_each(block, &iter) { 5999 if (block->tag == DATA_BLOCK_TILED_DISPLAY) 6000 drm_parse_tiled_block(connector, block); 6001 } 6002 displayid_iter_end(&iter); 6003 6004 if (!connector->has_tile && connector->tile_group) { 6005 drm_mode_put_tile_group(connector->dev, connector->tile_group); 6006 connector->tile_group = NULL; 6007 } 6008 } 6009