1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 #include <linux/kernel.h> 31 #include <linux/slab.h> 32 #include <linux/hdmi.h> 33 #include <linux/i2c.h> 34 #include <linux/module.h> 35 #include <linux/vga_switcheroo.h> 36 #include <drm/drmP.h> 37 #include <drm/drm_edid.h> 38 #include <drm/drm_encoder.h> 39 #include <drm/drm_displayid.h> 40 #include <drm/drm_scdc_helper.h> 41 42 #include "drm_crtc_internal.h" 43 44 #define version_greater(edid, maj, min) \ 45 (((edid)->version > (maj)) || \ 46 ((edid)->version == (maj) && (edid)->revision > (min))) 47 48 #define EDID_EST_TIMINGS 16 49 #define EDID_STD_TIMINGS 8 50 #define EDID_DETAILED_TIMINGS 4 51 52 /* 53 * EDID blocks out in the wild have a variety of bugs, try to collect 54 * them here (note that userspace may work around broken monitors first, 55 * but fixes should make their way here so that the kernel "just works" 56 * on as many displays as possible). 57 */ 58 59 /* First detailed mode wrong, use largest 60Hz mode */ 60 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 61 /* Reported 135MHz pixel clock is too high, needs adjustment */ 62 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 63 /* Prefer the largest mode at 75 Hz */ 64 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 65 /* Detail timing is in cm not mm */ 66 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 67 /* Detailed timing descriptors have bogus size values, so just take the 68 * maximum size and use that. 69 */ 70 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 71 /* Monitor forgot to set the first detailed is preferred bit. */ 72 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) 73 /* use +hsync +vsync for detailed mode */ 74 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 75 /* Force reduced-blanking timings for detailed modes */ 76 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 77 /* Force 8bpc */ 78 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 79 /* Force 12bpc */ 80 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 81 /* Force 6bpc */ 82 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 83 /* Force 10bpc */ 84 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 85 /* Non desktop display (i.e. HMD) */ 86 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 87 88 struct detailed_mode_closure { 89 struct drm_connector *connector; 90 struct edid *edid; 91 bool preferred; 92 u32 quirks; 93 int modes; 94 }; 95 96 #define LEVEL_DMT 0 97 #define LEVEL_GTF 1 98 #define LEVEL_GTF2 2 99 #define LEVEL_CVT 3 100 101 static const struct edid_quirk { 102 char vendor[4]; 103 int product_id; 104 u32 quirks; 105 } edid_quirk_list[] = { 106 /* Acer AL1706 */ 107 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 108 /* Acer F51 */ 109 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 110 /* Unknown Acer */ 111 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 112 113 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 114 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 115 116 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 117 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC }, 118 119 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 120 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC }, 121 122 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 123 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC }, 124 125 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 126 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC }, 127 128 /* Belinea 10 15 55 */ 129 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 130 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 131 132 /* Envision Peripherals, Inc. EN-7100e */ 133 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 134 /* Envision EN2028 */ 135 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 136 137 /* Funai Electronics PM36B */ 138 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 139 EDID_QUIRK_DETAILED_IN_CM }, 140 141 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 142 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 143 144 /* LG Philips LCD LP154W01-A5 */ 145 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 146 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 147 148 /* Philips 107p5 CRT */ 149 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 150 151 /* Proview AY765C */ 152 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 153 154 /* Samsung SyncMaster 205BW. Note: irony */ 155 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 156 /* Samsung SyncMaster 22[5-6]BW */ 157 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 158 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 159 160 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 161 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 162 163 /* ViewSonic VA2026w */ 164 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 165 166 /* Medion MD 30217 PG */ 167 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 168 169 /* Lenovo G50 */ 170 { "SDC", 18514, EDID_QUIRK_FORCE_6BPC }, 171 172 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 173 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 174 175 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 176 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 177 178 /* Valve Index Headset */ 179 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP }, 180 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP }, 181 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP }, 182 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP }, 183 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP }, 184 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP }, 185 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP }, 186 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP }, 187 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP }, 188 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP }, 189 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP }, 190 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP }, 191 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP }, 192 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP }, 193 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP }, 194 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP }, 195 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP }, 196 197 /* HTC Vive and Vive Pro VR Headsets */ 198 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP }, 199 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP }, 200 201 /* Oculus Rift DK1, DK2, and CV1 VR Headsets */ 202 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP }, 203 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP }, 204 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP }, 205 206 /* Windows Mixed Reality Headsets */ 207 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 208 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP }, 209 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP }, 210 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP }, 211 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP }, 212 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 213 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP }, 214 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP }, 215 216 /* Sony PlayStation VR Headset */ 217 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP }, 218 219 /* Sensics VR Headsets */ 220 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP }, 221 222 /* OSVR HDK and HDK2 VR Headsets */ 223 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP }, 224 }; 225 226 /* 227 * Autogenerated from the DMT spec. 228 * This table is copied from xfree86/modes/xf86EdidModes.c. 229 */ 230 static const struct drm_display_mode drm_dmt_modes[] = { 231 /* 0x01 - 640x350@85Hz */ 232 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 233 736, 832, 0, 350, 382, 385, 445, 0, 234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 235 /* 0x02 - 640x400@85Hz */ 236 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 237 736, 832, 0, 400, 401, 404, 445, 0, 238 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 239 /* 0x03 - 720x400@85Hz */ 240 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 241 828, 936, 0, 400, 401, 404, 446, 0, 242 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 243 /* 0x04 - 640x480@60Hz */ 244 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 245 752, 800, 0, 480, 490, 492, 525, 0, 246 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 247 /* 0x05 - 640x480@72Hz */ 248 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 249 704, 832, 0, 480, 489, 492, 520, 0, 250 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 251 /* 0x06 - 640x480@75Hz */ 252 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 253 720, 840, 0, 480, 481, 484, 500, 0, 254 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 255 /* 0x07 - 640x480@85Hz */ 256 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 257 752, 832, 0, 480, 481, 484, 509, 0, 258 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 259 /* 0x08 - 800x600@56Hz */ 260 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 261 896, 1024, 0, 600, 601, 603, 625, 0, 262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 263 /* 0x09 - 800x600@60Hz */ 264 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 265 968, 1056, 0, 600, 601, 605, 628, 0, 266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 267 /* 0x0a - 800x600@72Hz */ 268 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 269 976, 1040, 0, 600, 637, 643, 666, 0, 270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 271 /* 0x0b - 800x600@75Hz */ 272 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 273 896, 1056, 0, 600, 601, 604, 625, 0, 274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 275 /* 0x0c - 800x600@85Hz */ 276 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 277 896, 1048, 0, 600, 601, 604, 631, 0, 278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 279 /* 0x0d - 800x600@120Hz RB */ 280 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 281 880, 960, 0, 600, 603, 607, 636, 0, 282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 283 /* 0x0e - 848x480@60Hz */ 284 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 285 976, 1088, 0, 480, 486, 494, 517, 0, 286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 287 /* 0x0f - 1024x768@43Hz, interlace */ 288 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 289 1208, 1264, 0, 768, 768, 776, 817, 0, 290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 291 DRM_MODE_FLAG_INTERLACE) }, 292 /* 0x10 - 1024x768@60Hz */ 293 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 294 1184, 1344, 0, 768, 771, 777, 806, 0, 295 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 296 /* 0x11 - 1024x768@70Hz */ 297 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 298 1184, 1328, 0, 768, 771, 777, 806, 0, 299 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 300 /* 0x12 - 1024x768@75Hz */ 301 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 302 1136, 1312, 0, 768, 769, 772, 800, 0, 303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 304 /* 0x13 - 1024x768@85Hz */ 305 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 306 1168, 1376, 0, 768, 769, 772, 808, 0, 307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 308 /* 0x14 - 1024x768@120Hz RB */ 309 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 310 1104, 1184, 0, 768, 771, 775, 813, 0, 311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 312 /* 0x15 - 1152x864@75Hz */ 313 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 314 1344, 1600, 0, 864, 865, 868, 900, 0, 315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 316 /* 0x55 - 1280x720@60Hz */ 317 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 318 1430, 1650, 0, 720, 725, 730, 750, 0, 319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 320 /* 0x16 - 1280x768@60Hz RB */ 321 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 322 1360, 1440, 0, 768, 771, 778, 790, 0, 323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 324 /* 0x17 - 1280x768@60Hz */ 325 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 326 1472, 1664, 0, 768, 771, 778, 798, 0, 327 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 328 /* 0x18 - 1280x768@75Hz */ 329 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 330 1488, 1696, 0, 768, 771, 778, 805, 0, 331 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 332 /* 0x19 - 1280x768@85Hz */ 333 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 334 1496, 1712, 0, 768, 771, 778, 809, 0, 335 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 336 /* 0x1a - 1280x768@120Hz RB */ 337 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 338 1360, 1440, 0, 768, 771, 778, 813, 0, 339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 340 /* 0x1b - 1280x800@60Hz RB */ 341 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 342 1360, 1440, 0, 800, 803, 809, 823, 0, 343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 344 /* 0x1c - 1280x800@60Hz */ 345 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 346 1480, 1680, 0, 800, 803, 809, 831, 0, 347 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 348 /* 0x1d - 1280x800@75Hz */ 349 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 350 1488, 1696, 0, 800, 803, 809, 838, 0, 351 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 352 /* 0x1e - 1280x800@85Hz */ 353 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 354 1496, 1712, 0, 800, 803, 809, 843, 0, 355 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 356 /* 0x1f - 1280x800@120Hz RB */ 357 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 358 1360, 1440, 0, 800, 803, 809, 847, 0, 359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 360 /* 0x20 - 1280x960@60Hz */ 361 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 362 1488, 1800, 0, 960, 961, 964, 1000, 0, 363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 364 /* 0x21 - 1280x960@85Hz */ 365 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 366 1504, 1728, 0, 960, 961, 964, 1011, 0, 367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 368 /* 0x22 - 1280x960@120Hz RB */ 369 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 370 1360, 1440, 0, 960, 963, 967, 1017, 0, 371 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 372 /* 0x23 - 1280x1024@60Hz */ 373 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 374 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 376 /* 0x24 - 1280x1024@75Hz */ 377 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 378 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 380 /* 0x25 - 1280x1024@85Hz */ 381 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 382 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 383 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 384 /* 0x26 - 1280x1024@120Hz RB */ 385 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 386 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 387 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 388 /* 0x27 - 1360x768@60Hz */ 389 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 390 1536, 1792, 0, 768, 771, 777, 795, 0, 391 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 392 /* 0x28 - 1360x768@120Hz RB */ 393 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 394 1440, 1520, 0, 768, 771, 776, 813, 0, 395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 396 /* 0x51 - 1366x768@60Hz */ 397 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 398 1579, 1792, 0, 768, 771, 774, 798, 0, 399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 400 /* 0x56 - 1366x768@60Hz */ 401 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 402 1436, 1500, 0, 768, 769, 772, 800, 0, 403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 404 /* 0x29 - 1400x1050@60Hz RB */ 405 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 406 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 407 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 408 /* 0x2a - 1400x1050@60Hz */ 409 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 410 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 411 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 412 /* 0x2b - 1400x1050@75Hz */ 413 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 414 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 415 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 416 /* 0x2c - 1400x1050@85Hz */ 417 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 418 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 419 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 420 /* 0x2d - 1400x1050@120Hz RB */ 421 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 422 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 424 /* 0x2e - 1440x900@60Hz RB */ 425 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 426 1520, 1600, 0, 900, 903, 909, 926, 0, 427 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 428 /* 0x2f - 1440x900@60Hz */ 429 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 430 1672, 1904, 0, 900, 903, 909, 934, 0, 431 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 432 /* 0x30 - 1440x900@75Hz */ 433 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 434 1688, 1936, 0, 900, 903, 909, 942, 0, 435 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 436 /* 0x31 - 1440x900@85Hz */ 437 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 438 1696, 1952, 0, 900, 903, 909, 948, 0, 439 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 440 /* 0x32 - 1440x900@120Hz RB */ 441 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 442 1520, 1600, 0, 900, 903, 909, 953, 0, 443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 444 /* 0x53 - 1600x900@60Hz */ 445 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 446 1704, 1800, 0, 900, 901, 904, 1000, 0, 447 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 448 /* 0x33 - 1600x1200@60Hz */ 449 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 450 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 451 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 452 /* 0x34 - 1600x1200@65Hz */ 453 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 454 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 455 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 456 /* 0x35 - 1600x1200@70Hz */ 457 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 458 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 460 /* 0x36 - 1600x1200@75Hz */ 461 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 462 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 464 /* 0x37 - 1600x1200@85Hz */ 465 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 466 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 467 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 468 /* 0x38 - 1600x1200@120Hz RB */ 469 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 470 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 472 /* 0x39 - 1680x1050@60Hz RB */ 473 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 474 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 476 /* 0x3a - 1680x1050@60Hz */ 477 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 478 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 479 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 480 /* 0x3b - 1680x1050@75Hz */ 481 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 482 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 483 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 484 /* 0x3c - 1680x1050@85Hz */ 485 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 486 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 487 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 488 /* 0x3d - 1680x1050@120Hz RB */ 489 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 490 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 492 /* 0x3e - 1792x1344@60Hz */ 493 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 494 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 495 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 496 /* 0x3f - 1792x1344@75Hz */ 497 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 498 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 499 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 500 /* 0x40 - 1792x1344@120Hz RB */ 501 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 502 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 504 /* 0x41 - 1856x1392@60Hz */ 505 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 506 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 507 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 508 /* 0x42 - 1856x1392@75Hz */ 509 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 510 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 511 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 512 /* 0x43 - 1856x1392@120Hz RB */ 513 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 514 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 516 /* 0x52 - 1920x1080@60Hz */ 517 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 518 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 519 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 520 /* 0x44 - 1920x1200@60Hz RB */ 521 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 522 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 524 /* 0x45 - 1920x1200@60Hz */ 525 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 526 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 527 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 528 /* 0x46 - 1920x1200@75Hz */ 529 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 530 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 531 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 532 /* 0x47 - 1920x1200@85Hz */ 533 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 534 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 535 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 536 /* 0x48 - 1920x1200@120Hz RB */ 537 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 538 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 540 /* 0x49 - 1920x1440@60Hz */ 541 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 542 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 543 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 544 /* 0x4a - 1920x1440@75Hz */ 545 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 546 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 547 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 548 /* 0x4b - 1920x1440@120Hz RB */ 549 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 550 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 552 /* 0x54 - 2048x1152@60Hz */ 553 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 554 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 555 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 556 /* 0x4c - 2560x1600@60Hz RB */ 557 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 558 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 559 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 560 /* 0x4d - 2560x1600@60Hz */ 561 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 562 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 563 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 564 /* 0x4e - 2560x1600@75Hz */ 565 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 566 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 567 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 568 /* 0x4f - 2560x1600@85Hz */ 569 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 570 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 571 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 572 /* 0x50 - 2560x1600@120Hz RB */ 573 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 574 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 575 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 576 /* 0x57 - 4096x2160@60Hz RB */ 577 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 578 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 579 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 580 /* 0x58 - 4096x2160@59.94Hz RB */ 581 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 582 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 583 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 584 }; 585 586 /* 587 * These more or less come from the DMT spec. The 720x400 modes are 588 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 589 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 590 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 591 * mode. 592 * 593 * The DMT modes have been fact-checked; the rest are mild guesses. 594 */ 595 static const struct drm_display_mode edid_est_modes[] = { 596 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 597 968, 1056, 0, 600, 601, 605, 628, 0, 598 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 599 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 600 896, 1024, 0, 600, 601, 603, 625, 0, 601 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 602 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 603 720, 840, 0, 480, 481, 484, 500, 0, 604 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 605 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 606 704, 832, 0, 480, 489, 492, 520, 0, 607 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 608 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 609 768, 864, 0, 480, 483, 486, 525, 0, 610 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 611 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 612 752, 800, 0, 480, 490, 492, 525, 0, 613 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 614 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 615 846, 900, 0, 400, 421, 423, 449, 0, 616 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 617 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 618 846, 900, 0, 400, 412, 414, 449, 0, 619 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 620 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 621 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 622 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 623 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 624 1136, 1312, 0, 768, 769, 772, 800, 0, 625 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 626 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 627 1184, 1328, 0, 768, 771, 777, 806, 0, 628 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 629 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 630 1184, 1344, 0, 768, 771, 777, 806, 0, 631 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 632 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 633 1208, 1264, 0, 768, 768, 776, 817, 0, 634 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 635 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 636 928, 1152, 0, 624, 625, 628, 667, 0, 637 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 638 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 639 896, 1056, 0, 600, 601, 604, 625, 0, 640 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 641 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 642 976, 1040, 0, 600, 637, 643, 666, 0, 643 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 644 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 645 1344, 1600, 0, 864, 865, 868, 900, 0, 646 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 647 }; 648 649 struct minimode { 650 short w; 651 short h; 652 short r; 653 short rb; 654 }; 655 656 static const struct minimode est3_modes[] = { 657 /* byte 6 */ 658 { 640, 350, 85, 0 }, 659 { 640, 400, 85, 0 }, 660 { 720, 400, 85, 0 }, 661 { 640, 480, 85, 0 }, 662 { 848, 480, 60, 0 }, 663 { 800, 600, 85, 0 }, 664 { 1024, 768, 85, 0 }, 665 { 1152, 864, 75, 0 }, 666 /* byte 7 */ 667 { 1280, 768, 60, 1 }, 668 { 1280, 768, 60, 0 }, 669 { 1280, 768, 75, 0 }, 670 { 1280, 768, 85, 0 }, 671 { 1280, 960, 60, 0 }, 672 { 1280, 960, 85, 0 }, 673 { 1280, 1024, 60, 0 }, 674 { 1280, 1024, 85, 0 }, 675 /* byte 8 */ 676 { 1360, 768, 60, 0 }, 677 { 1440, 900, 60, 1 }, 678 { 1440, 900, 60, 0 }, 679 { 1440, 900, 75, 0 }, 680 { 1440, 900, 85, 0 }, 681 { 1400, 1050, 60, 1 }, 682 { 1400, 1050, 60, 0 }, 683 { 1400, 1050, 75, 0 }, 684 /* byte 9 */ 685 { 1400, 1050, 85, 0 }, 686 { 1680, 1050, 60, 1 }, 687 { 1680, 1050, 60, 0 }, 688 { 1680, 1050, 75, 0 }, 689 { 1680, 1050, 85, 0 }, 690 { 1600, 1200, 60, 0 }, 691 { 1600, 1200, 65, 0 }, 692 { 1600, 1200, 70, 0 }, 693 /* byte 10 */ 694 { 1600, 1200, 75, 0 }, 695 { 1600, 1200, 85, 0 }, 696 { 1792, 1344, 60, 0 }, 697 { 1792, 1344, 75, 0 }, 698 { 1856, 1392, 60, 0 }, 699 { 1856, 1392, 75, 0 }, 700 { 1920, 1200, 60, 1 }, 701 { 1920, 1200, 60, 0 }, 702 /* byte 11 */ 703 { 1920, 1200, 75, 0 }, 704 { 1920, 1200, 85, 0 }, 705 { 1920, 1440, 60, 0 }, 706 { 1920, 1440, 75, 0 }, 707 }; 708 709 static const struct minimode extra_modes[] = { 710 { 1024, 576, 60, 0 }, 711 { 1366, 768, 60, 0 }, 712 { 1600, 900, 60, 0 }, 713 { 1680, 945, 60, 0 }, 714 { 1920, 1080, 60, 0 }, 715 { 2048, 1152, 60, 0 }, 716 { 2048, 1536, 60, 0 }, 717 }; 718 719 /* 720 * Probably taken from CEA-861 spec. 721 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 722 * 723 * Index using the VIC. 724 */ 725 static const struct drm_display_mode edid_cea_modes[] = { 726 /* 0 - dummy, VICs start at 1 */ 727 { }, 728 /* 1 - 640x480@60Hz 4:3 */ 729 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 730 752, 800, 0, 480, 490, 492, 525, 0, 731 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 732 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 733 /* 2 - 720x480@60Hz 4:3 */ 734 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 735 798, 858, 0, 480, 489, 495, 525, 0, 736 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 737 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 738 /* 3 - 720x480@60Hz 16:9 */ 739 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 740 798, 858, 0, 480, 489, 495, 525, 0, 741 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 742 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 743 /* 4 - 1280x720@60Hz 16:9 */ 744 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 745 1430, 1650, 0, 720, 725, 730, 750, 0, 746 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 747 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 748 /* 5 - 1920x1080i@60Hz 16:9 */ 749 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 750 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 751 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 752 DRM_MODE_FLAG_INTERLACE), 753 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 754 /* 6 - 720(1440)x480i@60Hz 4:3 */ 755 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 756 801, 858, 0, 480, 488, 494, 525, 0, 757 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 758 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 759 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 760 /* 7 - 720(1440)x480i@60Hz 16:9 */ 761 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 762 801, 858, 0, 480, 488, 494, 525, 0, 763 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 764 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 765 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 766 /* 8 - 720(1440)x240@60Hz 4:3 */ 767 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 768 801, 858, 0, 240, 244, 247, 262, 0, 769 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 770 DRM_MODE_FLAG_DBLCLK), 771 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 772 /* 9 - 720(1440)x240@60Hz 16:9 */ 773 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 774 801, 858, 0, 240, 244, 247, 262, 0, 775 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 776 DRM_MODE_FLAG_DBLCLK), 777 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 778 /* 10 - 2880x480i@60Hz 4:3 */ 779 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 780 3204, 3432, 0, 480, 488, 494, 525, 0, 781 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 782 DRM_MODE_FLAG_INTERLACE), 783 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 784 /* 11 - 2880x480i@60Hz 16:9 */ 785 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 786 3204, 3432, 0, 480, 488, 494, 525, 0, 787 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 788 DRM_MODE_FLAG_INTERLACE), 789 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 790 /* 12 - 2880x240@60Hz 4:3 */ 791 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 792 3204, 3432, 0, 240, 244, 247, 262, 0, 793 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 794 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 795 /* 13 - 2880x240@60Hz 16:9 */ 796 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 797 3204, 3432, 0, 240, 244, 247, 262, 0, 798 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 799 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 800 /* 14 - 1440x480@60Hz 4:3 */ 801 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 802 1596, 1716, 0, 480, 489, 495, 525, 0, 803 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 804 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 805 /* 15 - 1440x480@60Hz 16:9 */ 806 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 807 1596, 1716, 0, 480, 489, 495, 525, 0, 808 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 809 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 810 /* 16 - 1920x1080@60Hz 16:9 */ 811 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 812 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 813 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 814 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 815 /* 17 - 720x576@50Hz 4:3 */ 816 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 817 796, 864, 0, 576, 581, 586, 625, 0, 818 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 819 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 820 /* 18 - 720x576@50Hz 16:9 */ 821 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 822 796, 864, 0, 576, 581, 586, 625, 0, 823 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 824 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 825 /* 19 - 1280x720@50Hz 16:9 */ 826 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 827 1760, 1980, 0, 720, 725, 730, 750, 0, 828 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 829 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 830 /* 20 - 1920x1080i@50Hz 16:9 */ 831 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 832 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 833 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 834 DRM_MODE_FLAG_INTERLACE), 835 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 836 /* 21 - 720(1440)x576i@50Hz 4:3 */ 837 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 838 795, 864, 0, 576, 580, 586, 625, 0, 839 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 840 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 841 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 842 /* 22 - 720(1440)x576i@50Hz 16:9 */ 843 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 844 795, 864, 0, 576, 580, 586, 625, 0, 845 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 846 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 847 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 848 /* 23 - 720(1440)x288@50Hz 4:3 */ 849 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 850 795, 864, 0, 288, 290, 293, 312, 0, 851 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 852 DRM_MODE_FLAG_DBLCLK), 853 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 854 /* 24 - 720(1440)x288@50Hz 16:9 */ 855 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 856 795, 864, 0, 288, 290, 293, 312, 0, 857 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 858 DRM_MODE_FLAG_DBLCLK), 859 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 860 /* 25 - 2880x576i@50Hz 4:3 */ 861 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 862 3180, 3456, 0, 576, 580, 586, 625, 0, 863 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 864 DRM_MODE_FLAG_INTERLACE), 865 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 866 /* 26 - 2880x576i@50Hz 16:9 */ 867 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 868 3180, 3456, 0, 576, 580, 586, 625, 0, 869 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 870 DRM_MODE_FLAG_INTERLACE), 871 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 872 /* 27 - 2880x288@50Hz 4:3 */ 873 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 874 3180, 3456, 0, 288, 290, 293, 312, 0, 875 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 876 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 877 /* 28 - 2880x288@50Hz 16:9 */ 878 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 879 3180, 3456, 0, 288, 290, 293, 312, 0, 880 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 881 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 882 /* 29 - 1440x576@50Hz 4:3 */ 883 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 884 1592, 1728, 0, 576, 581, 586, 625, 0, 885 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 886 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 887 /* 30 - 1440x576@50Hz 16:9 */ 888 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 889 1592, 1728, 0, 576, 581, 586, 625, 0, 890 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 891 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 892 /* 31 - 1920x1080@50Hz 16:9 */ 893 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 894 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 895 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 896 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 897 /* 32 - 1920x1080@24Hz 16:9 */ 898 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 899 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 900 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 901 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 902 /* 33 - 1920x1080@25Hz 16:9 */ 903 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 904 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 905 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 906 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 907 /* 34 - 1920x1080@30Hz 16:9 */ 908 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 909 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 910 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 911 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 912 /* 35 - 2880x480@60Hz 4:3 */ 913 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 914 3192, 3432, 0, 480, 489, 495, 525, 0, 915 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 916 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 917 /* 36 - 2880x480@60Hz 16:9 */ 918 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 919 3192, 3432, 0, 480, 489, 495, 525, 0, 920 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 921 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 922 /* 37 - 2880x576@50Hz 4:3 */ 923 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 924 3184, 3456, 0, 576, 581, 586, 625, 0, 925 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 926 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 927 /* 38 - 2880x576@50Hz 16:9 */ 928 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 929 3184, 3456, 0, 576, 581, 586, 625, 0, 930 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 931 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 932 /* 39 - 1920x1080i@50Hz 16:9 */ 933 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 934 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 935 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 936 DRM_MODE_FLAG_INTERLACE), 937 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 938 /* 40 - 1920x1080i@100Hz 16:9 */ 939 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 940 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 941 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 942 DRM_MODE_FLAG_INTERLACE), 943 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 944 /* 41 - 1280x720@100Hz 16:9 */ 945 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 946 1760, 1980, 0, 720, 725, 730, 750, 0, 947 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 948 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 949 /* 42 - 720x576@100Hz 4:3 */ 950 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 951 796, 864, 0, 576, 581, 586, 625, 0, 952 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 953 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 954 /* 43 - 720x576@100Hz 16:9 */ 955 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 956 796, 864, 0, 576, 581, 586, 625, 0, 957 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 958 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 959 /* 44 - 720(1440)x576i@100Hz 4:3 */ 960 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 961 795, 864, 0, 576, 580, 586, 625, 0, 962 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 963 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 964 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 965 /* 45 - 720(1440)x576i@100Hz 16:9 */ 966 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 967 795, 864, 0, 576, 580, 586, 625, 0, 968 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 969 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 970 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 971 /* 46 - 1920x1080i@120Hz 16:9 */ 972 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 973 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 974 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 975 DRM_MODE_FLAG_INTERLACE), 976 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 977 /* 47 - 1280x720@120Hz 16:9 */ 978 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 979 1430, 1650, 0, 720, 725, 730, 750, 0, 980 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 981 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 982 /* 48 - 720x480@120Hz 4:3 */ 983 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 984 798, 858, 0, 480, 489, 495, 525, 0, 985 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 986 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 987 /* 49 - 720x480@120Hz 16:9 */ 988 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 989 798, 858, 0, 480, 489, 495, 525, 0, 990 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 991 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 992 /* 50 - 720(1440)x480i@120Hz 4:3 */ 993 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 994 801, 858, 0, 480, 488, 494, 525, 0, 995 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 996 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 997 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 998 /* 51 - 720(1440)x480i@120Hz 16:9 */ 999 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1000 801, 858, 0, 480, 488, 494, 525, 0, 1001 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1002 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1003 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1004 /* 52 - 720x576@200Hz 4:3 */ 1005 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1006 796, 864, 0, 576, 581, 586, 625, 0, 1007 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1008 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1009 /* 53 - 720x576@200Hz 16:9 */ 1010 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1011 796, 864, 0, 576, 581, 586, 625, 0, 1012 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1013 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1014 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1015 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1016 795, 864, 0, 576, 580, 586, 625, 0, 1017 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1018 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1019 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1020 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1021 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1022 795, 864, 0, 576, 580, 586, 625, 0, 1023 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1024 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1025 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1026 /* 56 - 720x480@240Hz 4:3 */ 1027 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1028 798, 858, 0, 480, 489, 495, 525, 0, 1029 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1030 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1031 /* 57 - 720x480@240Hz 16:9 */ 1032 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1033 798, 858, 0, 480, 489, 495, 525, 0, 1034 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1035 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1036 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1037 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1038 801, 858, 0, 480, 488, 494, 525, 0, 1039 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1040 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1041 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1042 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1043 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1044 801, 858, 0, 480, 488, 494, 525, 0, 1045 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1046 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1047 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1048 /* 60 - 1280x720@24Hz 16:9 */ 1049 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1050 3080, 3300, 0, 720, 725, 730, 750, 0, 1051 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1052 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1053 /* 61 - 1280x720@25Hz 16:9 */ 1054 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1055 3740, 3960, 0, 720, 725, 730, 750, 0, 1056 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1057 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1058 /* 62 - 1280x720@30Hz 16:9 */ 1059 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1060 3080, 3300, 0, 720, 725, 730, 750, 0, 1061 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1062 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1063 /* 63 - 1920x1080@120Hz 16:9 */ 1064 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1065 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1066 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1067 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1068 /* 64 - 1920x1080@100Hz 16:9 */ 1069 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1070 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1071 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1072 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1073 /* 65 - 1280x720@24Hz 64:27 */ 1074 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1075 3080, 3300, 0, 720, 725, 730, 750, 0, 1076 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1077 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1078 /* 66 - 1280x720@25Hz 64:27 */ 1079 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1080 3740, 3960, 0, 720, 725, 730, 750, 0, 1081 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1082 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1083 /* 67 - 1280x720@30Hz 64:27 */ 1084 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1085 3080, 3300, 0, 720, 725, 730, 750, 0, 1086 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1087 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1088 /* 68 - 1280x720@50Hz 64:27 */ 1089 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1090 1760, 1980, 0, 720, 725, 730, 750, 0, 1091 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1092 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1093 /* 69 - 1280x720@60Hz 64:27 */ 1094 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1095 1430, 1650, 0, 720, 725, 730, 750, 0, 1096 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1097 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1098 /* 70 - 1280x720@100Hz 64:27 */ 1099 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1100 1760, 1980, 0, 720, 725, 730, 750, 0, 1101 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1102 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1103 /* 71 - 1280x720@120Hz 64:27 */ 1104 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1105 1430, 1650, 0, 720, 725, 730, 750, 0, 1106 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1107 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1108 /* 72 - 1920x1080@24Hz 64:27 */ 1109 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1110 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1111 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1112 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1113 /* 73 - 1920x1080@25Hz 64:27 */ 1114 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1115 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1116 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1117 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1118 /* 74 - 1920x1080@30Hz 64:27 */ 1119 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1120 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1121 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1122 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1123 /* 75 - 1920x1080@50Hz 64:27 */ 1124 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1125 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1126 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1127 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1128 /* 76 - 1920x1080@60Hz 64:27 */ 1129 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1130 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1131 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1132 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1133 /* 77 - 1920x1080@100Hz 64:27 */ 1134 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1135 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1136 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1137 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1138 /* 78 - 1920x1080@120Hz 64:27 */ 1139 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1140 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1141 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1142 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1143 /* 79 - 1680x720@24Hz 64:27 */ 1144 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1145 3080, 3300, 0, 720, 725, 730, 750, 0, 1146 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1147 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1148 /* 80 - 1680x720@25Hz 64:27 */ 1149 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1150 2948, 3168, 0, 720, 725, 730, 750, 0, 1151 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1152 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1153 /* 81 - 1680x720@30Hz 64:27 */ 1154 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1155 2420, 2640, 0, 720, 725, 730, 750, 0, 1156 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1157 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1158 /* 82 - 1680x720@50Hz 64:27 */ 1159 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1160 1980, 2200, 0, 720, 725, 730, 750, 0, 1161 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1162 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1163 /* 83 - 1680x720@60Hz 64:27 */ 1164 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1165 1980, 2200, 0, 720, 725, 730, 750, 0, 1166 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1167 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1168 /* 84 - 1680x720@100Hz 64:27 */ 1169 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1170 1780, 2000, 0, 720, 725, 730, 825, 0, 1171 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1172 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1173 /* 85 - 1680x720@120Hz 64:27 */ 1174 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1175 1780, 2000, 0, 720, 725, 730, 825, 0, 1176 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1177 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1178 /* 86 - 2560x1080@24Hz 64:27 */ 1179 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1180 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1181 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1182 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1183 /* 87 - 2560x1080@25Hz 64:27 */ 1184 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1185 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1186 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1187 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1188 /* 88 - 2560x1080@30Hz 64:27 */ 1189 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1190 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1192 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1193 /* 89 - 2560x1080@50Hz 64:27 */ 1194 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1195 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1197 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1198 /* 90 - 2560x1080@60Hz 64:27 */ 1199 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1200 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1201 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1202 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1203 /* 91 - 2560x1080@100Hz 64:27 */ 1204 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1205 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1206 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1207 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1208 /* 92 - 2560x1080@120Hz 64:27 */ 1209 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1210 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1211 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1212 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1213 /* 93 - 3840x2160@24Hz 16:9 */ 1214 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1215 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1216 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1217 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1218 /* 94 - 3840x2160@25Hz 16:9 */ 1219 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1220 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1221 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1222 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1223 /* 95 - 3840x2160@30Hz 16:9 */ 1224 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1225 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1227 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1228 /* 96 - 3840x2160@50Hz 16:9 */ 1229 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1230 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1232 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1233 /* 97 - 3840x2160@60Hz 16:9 */ 1234 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1235 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1237 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1238 /* 98 - 4096x2160@24Hz 256:135 */ 1239 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1240 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1242 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1243 /* 99 - 4096x2160@25Hz 256:135 */ 1244 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1245 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1247 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1248 /* 100 - 4096x2160@30Hz 256:135 */ 1249 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1250 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1252 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1253 /* 101 - 4096x2160@50Hz 256:135 */ 1254 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1255 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1257 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1258 /* 102 - 4096x2160@60Hz 256:135 */ 1259 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1260 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1262 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1263 /* 103 - 3840x2160@24Hz 64:27 */ 1264 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1265 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1267 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1268 /* 104 - 3840x2160@25Hz 64:27 */ 1269 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1270 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1272 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1273 /* 105 - 3840x2160@30Hz 64:27 */ 1274 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1275 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1277 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1278 /* 106 - 3840x2160@50Hz 64:27 */ 1279 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1280 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1282 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1283 /* 107 - 3840x2160@60Hz 64:27 */ 1284 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1285 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1287 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1288 }; 1289 1290 /* 1291 * HDMI 1.4 4k modes. Index using the VIC. 1292 */ 1293 static const struct drm_display_mode edid_4k_modes[] = { 1294 /* 0 - dummy, VICs start at 1 */ 1295 { }, 1296 /* 1 - 3840x2160@30Hz */ 1297 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1298 3840, 4016, 4104, 4400, 0, 1299 2160, 2168, 2178, 2250, 0, 1300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1301 .vrefresh = 30, }, 1302 /* 2 - 3840x2160@25Hz */ 1303 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1304 3840, 4896, 4984, 5280, 0, 1305 2160, 2168, 2178, 2250, 0, 1306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1307 .vrefresh = 25, }, 1308 /* 3 - 3840x2160@24Hz */ 1309 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1310 3840, 5116, 5204, 5500, 0, 1311 2160, 2168, 2178, 2250, 0, 1312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1313 .vrefresh = 24, }, 1314 /* 4 - 4096x2160@24Hz (SMPTE) */ 1315 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1316 4096, 5116, 5204, 5500, 0, 1317 2160, 2168, 2178, 2250, 0, 1318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1319 .vrefresh = 24, }, 1320 }; 1321 1322 /*** DDC fetch and block validation ***/ 1323 1324 static const u8 edid_header[] = { 1325 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1326 }; 1327 1328 /** 1329 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1330 * @raw_edid: pointer to raw base EDID block 1331 * 1332 * Sanity check the header of the base EDID block. 1333 * 1334 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1335 */ 1336 int drm_edid_header_is_valid(const u8 *raw_edid) 1337 { 1338 int i, score = 0; 1339 1340 for (i = 0; i < sizeof(edid_header); i++) 1341 if (raw_edid[i] == edid_header[i]) 1342 score++; 1343 1344 return score; 1345 } 1346 EXPORT_SYMBOL(drm_edid_header_is_valid); 1347 1348 static int edid_fixup __read_mostly = 6; 1349 module_param_named(edid_fixup, edid_fixup, int, 0400); 1350 MODULE_PARM_DESC(edid_fixup, 1351 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1352 1353 static void drm_get_displayid(struct drm_connector *connector, 1354 struct edid *edid); 1355 static int validate_displayid(u8 *displayid, int length, int idx); 1356 1357 static int drm_edid_block_checksum(const u8 *raw_edid) 1358 { 1359 int i; 1360 u8 csum = 0; 1361 for (i = 0; i < EDID_LENGTH; i++) 1362 csum += raw_edid[i]; 1363 1364 return csum; 1365 } 1366 1367 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1368 { 1369 if (memchr_inv(in_edid, 0, length)) 1370 return false; 1371 1372 return true; 1373 } 1374 1375 /** 1376 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1377 * @raw_edid: pointer to raw EDID block 1378 * @block: type of block to validate (0 for base, extension otherwise) 1379 * @print_bad_edid: if true, dump bad EDID blocks to the console 1380 * @edid_corrupt: if true, the header or checksum is invalid 1381 * 1382 * Validate a base or extension EDID block and optionally dump bad blocks to 1383 * the console. 1384 * 1385 * Return: True if the block is valid, false otherwise. 1386 */ 1387 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1388 bool *edid_corrupt) 1389 { 1390 u8 csum; 1391 struct edid *edid = (struct edid *)raw_edid; 1392 1393 if (WARN_ON(!raw_edid)) 1394 return false; 1395 1396 if (edid_fixup > 8 || edid_fixup < 0) 1397 edid_fixup = 6; 1398 1399 if (block == 0) { 1400 int score = drm_edid_header_is_valid(raw_edid); 1401 if (score == 8) { 1402 if (edid_corrupt) 1403 *edid_corrupt = false; 1404 } else if (score >= edid_fixup) { 1405 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1406 * The corrupt flag needs to be set here otherwise, the 1407 * fix-up code here will correct the problem, the 1408 * checksum is correct and the test fails 1409 */ 1410 if (edid_corrupt) 1411 *edid_corrupt = true; 1412 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1413 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1414 } else { 1415 if (edid_corrupt) 1416 *edid_corrupt = true; 1417 goto bad; 1418 } 1419 } 1420 1421 csum = drm_edid_block_checksum(raw_edid); 1422 if (csum) { 1423 if (edid_corrupt) 1424 *edid_corrupt = true; 1425 1426 /* allow CEA to slide through, switches mangle this */ 1427 if (raw_edid[0] == CEA_EXT) { 1428 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum); 1429 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n"); 1430 } else { 1431 if (print_bad_edid) 1432 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum); 1433 1434 goto bad; 1435 } 1436 } 1437 1438 /* per-block-type checks */ 1439 switch (raw_edid[0]) { 1440 case 0: /* base */ 1441 if (edid->version != 1) { 1442 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version); 1443 goto bad; 1444 } 1445 1446 if (edid->revision > 4) 1447 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1448 break; 1449 1450 default: 1451 break; 1452 } 1453 1454 return true; 1455 1456 bad: 1457 if (print_bad_edid) { 1458 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1459 pr_notice("EDID block is all zeroes\n"); 1460 } else { 1461 pr_notice("Raw EDID:\n"); 1462 print_hex_dump(KERN_NOTICE, 1463 " \t", DUMP_PREFIX_NONE, 16, 1, 1464 raw_edid, EDID_LENGTH, false); 1465 } 1466 } 1467 return false; 1468 } 1469 EXPORT_SYMBOL(drm_edid_block_valid); 1470 1471 /** 1472 * drm_edid_is_valid - sanity check EDID data 1473 * @edid: EDID data 1474 * 1475 * Sanity-check an entire EDID record (including extensions) 1476 * 1477 * Return: True if the EDID data is valid, false otherwise. 1478 */ 1479 bool drm_edid_is_valid(struct edid *edid) 1480 { 1481 int i; 1482 u8 *raw = (u8 *)edid; 1483 1484 if (!edid) 1485 return false; 1486 1487 for (i = 0; i <= edid->extensions; i++) 1488 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1489 return false; 1490 1491 return true; 1492 } 1493 EXPORT_SYMBOL(drm_edid_is_valid); 1494 1495 #define DDC_SEGMENT_ADDR 0x30 1496 /** 1497 * drm_do_probe_ddc_edid() - get EDID information via I2C 1498 * @data: I2C device adapter 1499 * @buf: EDID data buffer to be filled 1500 * @block: 128 byte EDID block to start fetching from 1501 * @len: EDID data buffer length to fetch 1502 * 1503 * Try to fetch EDID information by calling I2C driver functions. 1504 * 1505 * Return: 0 on success or -1 on failure. 1506 */ 1507 static int 1508 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1509 { 1510 struct i2c_adapter *adapter = data; 1511 unsigned char start = block * EDID_LENGTH; 1512 unsigned char segment = block >> 1; 1513 unsigned char xfers = segment ? 3 : 2; 1514 int ret, retries = 5; 1515 1516 /* 1517 * The core I2C driver will automatically retry the transfer if the 1518 * adapter reports EAGAIN. However, we find that bit-banging transfers 1519 * are susceptible to errors under a heavily loaded machine and 1520 * generate spurious NAKs and timeouts. Retrying the transfer 1521 * of the individual block a few times seems to overcome this. 1522 */ 1523 do { 1524 struct i2c_msg msgs[] = { 1525 { 1526 .addr = DDC_SEGMENT_ADDR, 1527 .flags = 0, 1528 .len = 1, 1529 .buf = &segment, 1530 }, { 1531 .addr = DDC_ADDR, 1532 .flags = 0, 1533 .len = 1, 1534 .buf = &start, 1535 }, { 1536 .addr = DDC_ADDR, 1537 .flags = I2C_M_RD, 1538 .len = len, 1539 .buf = buf, 1540 } 1541 }; 1542 1543 /* 1544 * Avoid sending the segment addr to not upset non-compliant 1545 * DDC monitors. 1546 */ 1547 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1548 1549 if (ret == -ENXIO) { 1550 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1551 adapter->name); 1552 break; 1553 } 1554 } while (ret != xfers && --retries); 1555 1556 return ret == xfers ? 0 : -1; 1557 } 1558 1559 static void connector_bad_edid(struct drm_connector *connector, 1560 u8 *edid, int num_blocks) 1561 { 1562 int i; 1563 1564 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS)) 1565 return; 1566 1567 dev_warn(connector->dev->dev, 1568 "%s: EDID is invalid:\n", 1569 connector->name); 1570 for (i = 0; i < num_blocks; i++) { 1571 u8 *block = edid + i * EDID_LENGTH; 1572 char prefix[20]; 1573 1574 if (drm_edid_is_zero(block, EDID_LENGTH)) 1575 snprintf(prefix, sizeof(prefix), "\t[%02x] ZERO ", i); 1576 else if (!drm_edid_block_valid(block, i, false, NULL)) 1577 snprintf(prefix, sizeof(prefix), "\t[%02x] BAD ", i); 1578 else 1579 snprintf(prefix, sizeof(prefix), "\t[%02x] GOOD ", i); 1580 1581 print_hex_dump(KERN_WARNING, 1582 prefix, DUMP_PREFIX_NONE, 16, 1, 1583 block, EDID_LENGTH, false); 1584 } 1585 } 1586 1587 /* Get override or firmware EDID */ 1588 static struct edid *drm_get_override_edid(struct drm_connector *connector) 1589 { 1590 struct edid *override = NULL; 1591 1592 if (connector->override_edid) 1593 override = drm_edid_duplicate(connector->edid_blob_ptr->data); 1594 1595 if (!override) 1596 override = drm_load_edid_firmware(connector); 1597 1598 return IS_ERR(override) ? NULL : override; 1599 } 1600 1601 /** 1602 * drm_add_override_edid_modes - add modes from override/firmware EDID 1603 * @connector: connector we're probing 1604 * 1605 * Add modes from the override/firmware EDID, if available. Only to be used from 1606 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 1607 * failed during drm_get_edid() and caused the override/firmware EDID to be 1608 * skipped. 1609 * 1610 * Return: The number of modes added or 0 if we couldn't find any. 1611 */ 1612 int drm_add_override_edid_modes(struct drm_connector *connector) 1613 { 1614 struct edid *override; 1615 int num_modes = 0; 1616 1617 override = drm_get_override_edid(connector); 1618 if (override) { 1619 drm_connector_update_edid_property(connector, override); 1620 num_modes = drm_add_edid_modes(connector, override); 1621 kfree(override); 1622 1623 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 1624 connector->base.id, connector->name, num_modes); 1625 } 1626 1627 return num_modes; 1628 } 1629 EXPORT_SYMBOL(drm_add_override_edid_modes); 1630 1631 /** 1632 * drm_do_get_edid - get EDID data using a custom EDID block read function 1633 * @connector: connector we're probing 1634 * @get_edid_block: EDID block read function 1635 * @data: private data passed to the block read function 1636 * 1637 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1638 * exposes a different interface to read EDID blocks this function can be used 1639 * to get EDID data using a custom block read function. 1640 * 1641 * As in the general case the DDC bus is accessible by the kernel at the I2C 1642 * level, drivers must make all reasonable efforts to expose it as an I2C 1643 * adapter and use drm_get_edid() instead of abusing this function. 1644 * 1645 * The EDID may be overridden using debugfs override_edid or firmare EDID 1646 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 1647 * order. Having either of them bypasses actual EDID reads. 1648 * 1649 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1650 */ 1651 struct edid *drm_do_get_edid(struct drm_connector *connector, 1652 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1653 size_t len), 1654 void *data) 1655 { 1656 int i, j = 0, valid_extensions = 0; 1657 u8 *edid, *new; 1658 struct edid *override; 1659 1660 override = drm_get_override_edid(connector); 1661 if (override) 1662 return override; 1663 1664 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1665 return NULL; 1666 1667 /* base block fetch */ 1668 for (i = 0; i < 4; i++) { 1669 if (get_edid_block(data, edid, 0, EDID_LENGTH)) 1670 goto out; 1671 if (drm_edid_block_valid(edid, 0, false, 1672 &connector->edid_corrupt)) 1673 break; 1674 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) { 1675 connector->null_edid_counter++; 1676 goto carp; 1677 } 1678 } 1679 if (i == 4) 1680 goto carp; 1681 1682 /* if there's no extensions, we're done */ 1683 valid_extensions = edid[0x7e]; 1684 if (valid_extensions == 0) 1685 return (struct edid *)edid; 1686 1687 new = kmalloc((valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1688 if (!new) 1689 goto out; 1690 memcpy(new, edid, EDID_LENGTH); 1691 kfree(edid); 1692 edid = new; 1693 1694 for (j = 1; j <= edid[0x7e]; j++) { 1695 u8 *block = edid + j * EDID_LENGTH; 1696 1697 for (i = 0; i < 4; i++) { 1698 if (get_edid_block(data, block, j, EDID_LENGTH)) 1699 goto out; 1700 if (drm_edid_block_valid(block, j, false, NULL)) 1701 break; 1702 } 1703 1704 if (i == 4) 1705 valid_extensions--; 1706 } 1707 1708 if (valid_extensions != edid[0x7e]) { 1709 u8 *base; 1710 1711 connector_bad_edid(connector, edid, edid[0x7e] + 1); 1712 1713 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions; 1714 edid[0x7e] = valid_extensions; 1715 1716 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH, 1717 GFP_KERNEL); 1718 if (!new) 1719 goto out; 1720 1721 base = new; 1722 for (i = 0; i <= edid[0x7e]; i++) { 1723 u8 *block = edid + i * EDID_LENGTH; 1724 1725 if (!drm_edid_block_valid(block, i, false, NULL)) 1726 continue; 1727 1728 memcpy(base, block, EDID_LENGTH); 1729 base += EDID_LENGTH; 1730 } 1731 1732 kfree(edid); 1733 edid = new; 1734 } 1735 1736 return (struct edid *)edid; 1737 1738 carp: 1739 connector_bad_edid(connector, edid, 1); 1740 out: 1741 kfree(edid); 1742 return NULL; 1743 } 1744 EXPORT_SYMBOL_GPL(drm_do_get_edid); 1745 1746 /** 1747 * drm_probe_ddc() - probe DDC presence 1748 * @adapter: I2C adapter to probe 1749 * 1750 * Return: True on success, false on failure. 1751 */ 1752 bool 1753 drm_probe_ddc(struct i2c_adapter *adapter) 1754 { 1755 unsigned char out; 1756 1757 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1758 } 1759 EXPORT_SYMBOL(drm_probe_ddc); 1760 1761 /** 1762 * drm_get_edid - get EDID data, if available 1763 * @connector: connector we're probing 1764 * @adapter: I2C adapter to use for DDC 1765 * 1766 * Poke the given I2C channel to grab EDID data if possible. If found, 1767 * attach it to the connector. 1768 * 1769 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1770 */ 1771 struct edid *drm_get_edid(struct drm_connector *connector, 1772 struct i2c_adapter *adapter) 1773 { 1774 struct edid *edid; 1775 1776 if (connector->force == DRM_FORCE_OFF) 1777 return NULL; 1778 1779 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 1780 return NULL; 1781 1782 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 1783 if (edid) 1784 drm_get_displayid(connector, edid); 1785 return edid; 1786 } 1787 EXPORT_SYMBOL(drm_get_edid); 1788 1789 /** 1790 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 1791 * @connector: connector we're probing 1792 * @adapter: I2C adapter to use for DDC 1793 * 1794 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 1795 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 1796 * switch DDC to the GPU which is retrieving EDID. 1797 * 1798 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 1799 */ 1800 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 1801 struct i2c_adapter *adapter) 1802 { 1803 #ifdef __linux__ 1804 struct pci_dev *pdev = connector->dev->pdev; 1805 #endif 1806 struct edid *edid; 1807 1808 vga_switcheroo_lock_ddc(pdev); 1809 edid = drm_get_edid(connector, adapter); 1810 vga_switcheroo_unlock_ddc(pdev); 1811 1812 return edid; 1813 } 1814 EXPORT_SYMBOL(drm_get_edid_switcheroo); 1815 1816 /** 1817 * drm_edid_duplicate - duplicate an EDID and the extensions 1818 * @edid: EDID to duplicate 1819 * 1820 * Return: Pointer to duplicated EDID or NULL on allocation failure. 1821 */ 1822 struct edid *drm_edid_duplicate(const struct edid *edid) 1823 { 1824 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1825 } 1826 EXPORT_SYMBOL(drm_edid_duplicate); 1827 1828 /*** EDID parsing ***/ 1829 1830 /** 1831 * edid_vendor - match a string against EDID's obfuscated vendor field 1832 * @edid: EDID to match 1833 * @vendor: vendor string 1834 * 1835 * Returns true if @vendor is in @edid, false otherwise 1836 */ 1837 static bool edid_vendor(const struct edid *edid, const char *vendor) 1838 { 1839 char edid_vendor[3]; 1840 1841 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1842 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1843 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1844 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1845 1846 return !strncmp(edid_vendor, vendor, 3); 1847 } 1848 1849 /** 1850 * edid_get_quirks - return quirk flags for a given EDID 1851 * @edid: EDID to process 1852 * 1853 * This tells subsequent routines what fixes they need to apply. 1854 */ 1855 static u32 edid_get_quirks(const struct edid *edid) 1856 { 1857 const struct edid_quirk *quirk; 1858 int i; 1859 1860 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1861 quirk = &edid_quirk_list[i]; 1862 1863 if (edid_vendor(edid, quirk->vendor) && 1864 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1865 return quirk->quirks; 1866 } 1867 1868 return 0; 1869 } 1870 1871 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1872 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 1873 1874 /** 1875 * edid_fixup_preferred - set preferred modes based on quirk list 1876 * @connector: has mode list to fix up 1877 * @quirks: quirks list 1878 * 1879 * Walk the mode list for @connector, clearing the preferred status 1880 * on existing modes and setting it anew for the right mode ala @quirks. 1881 */ 1882 static void edid_fixup_preferred(struct drm_connector *connector, 1883 u32 quirks) 1884 { 1885 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1886 int target_refresh = 0; 1887 int cur_vrefresh, preferred_vrefresh; 1888 1889 if (list_empty(&connector->probed_modes)) 1890 return; 1891 1892 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1893 target_refresh = 60; 1894 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1895 target_refresh = 75; 1896 1897 preferred_mode = list_first_entry(&connector->probed_modes, 1898 struct drm_display_mode, head); 1899 1900 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1901 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1902 1903 if (cur_mode == preferred_mode) 1904 continue; 1905 1906 /* Largest mode is preferred */ 1907 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1908 preferred_mode = cur_mode; 1909 1910 cur_vrefresh = cur_mode->vrefresh ? 1911 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 1912 preferred_vrefresh = preferred_mode->vrefresh ? 1913 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 1914 /* At a given size, try to get closest to target refresh */ 1915 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1916 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 1917 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 1918 preferred_mode = cur_mode; 1919 } 1920 } 1921 1922 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1923 } 1924 1925 static bool 1926 mode_is_rb(const struct drm_display_mode *mode) 1927 { 1928 return (mode->htotal - mode->hdisplay == 160) && 1929 (mode->hsync_end - mode->hdisplay == 80) && 1930 (mode->hsync_end - mode->hsync_start == 32) && 1931 (mode->vsync_start - mode->vdisplay == 3); 1932 } 1933 1934 /* 1935 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1936 * @dev: Device to duplicate against 1937 * @hsize: Mode width 1938 * @vsize: Mode height 1939 * @fresh: Mode refresh rate 1940 * @rb: Mode reduced-blanking-ness 1941 * 1942 * Walk the DMT mode list looking for a match for the given parameters. 1943 * 1944 * Return: A newly allocated copy of the mode, or NULL if not found. 1945 */ 1946 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1947 int hsize, int vsize, int fresh, 1948 bool rb) 1949 { 1950 int i; 1951 1952 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1953 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1954 if (hsize != ptr->hdisplay) 1955 continue; 1956 if (vsize != ptr->vdisplay) 1957 continue; 1958 if (fresh != drm_mode_vrefresh(ptr)) 1959 continue; 1960 if (rb != mode_is_rb(ptr)) 1961 continue; 1962 1963 return drm_mode_duplicate(dev, ptr); 1964 } 1965 1966 return NULL; 1967 } 1968 EXPORT_SYMBOL(drm_mode_find_dmt); 1969 1970 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1971 1972 static void 1973 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1974 { 1975 int i, n = 0; 1976 u8 d = ext[0x02]; 1977 u8 *det_base = ext + d; 1978 1979 n = (127 - d) / 18; 1980 for (i = 0; i < n; i++) 1981 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1982 } 1983 1984 static void 1985 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1986 { 1987 unsigned int i, n = min((int)ext[0x02], 6); 1988 u8 *det_base = ext + 5; 1989 1990 if (ext[0x01] != 1) 1991 return; /* unknown version */ 1992 1993 for (i = 0; i < n; i++) 1994 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1995 } 1996 1997 static void 1998 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1999 { 2000 int i; 2001 struct edid *edid = (struct edid *)raw_edid; 2002 2003 if (edid == NULL) 2004 return; 2005 2006 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 2007 cb(&(edid->detailed_timings[i]), closure); 2008 2009 for (i = 1; i <= raw_edid[0x7e]; i++) { 2010 u8 *ext = raw_edid + (i * EDID_LENGTH); 2011 switch (*ext) { 2012 case CEA_EXT: 2013 cea_for_each_detailed_block(ext, cb, closure); 2014 break; 2015 case VTB_EXT: 2016 vtb_for_each_detailed_block(ext, cb, closure); 2017 break; 2018 default: 2019 break; 2020 } 2021 } 2022 } 2023 2024 static void 2025 is_rb(struct detailed_timing *t, void *data) 2026 { 2027 u8 *r = (u8 *)t; 2028 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 2029 if (r[15] & 0x10) 2030 *(bool *)data = true; 2031 } 2032 2033 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 2034 static bool 2035 drm_monitor_supports_rb(struct edid *edid) 2036 { 2037 if (edid->revision >= 4) { 2038 bool ret = false; 2039 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 2040 return ret; 2041 } 2042 2043 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 2044 } 2045 2046 static void 2047 find_gtf2(struct detailed_timing *t, void *data) 2048 { 2049 u8 *r = (u8 *)t; 2050 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 2051 *(u8 **)data = r; 2052 } 2053 2054 /* Secondary GTF curve kicks in above some break frequency */ 2055 static int 2056 drm_gtf2_hbreak(struct edid *edid) 2057 { 2058 u8 *r = NULL; 2059 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2060 return r ? (r[12] * 2) : 0; 2061 } 2062 2063 static int 2064 drm_gtf2_2c(struct edid *edid) 2065 { 2066 u8 *r = NULL; 2067 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2068 return r ? r[13] : 0; 2069 } 2070 2071 static int 2072 drm_gtf2_m(struct edid *edid) 2073 { 2074 u8 *r = NULL; 2075 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2076 return r ? (r[15] << 8) + r[14] : 0; 2077 } 2078 2079 static int 2080 drm_gtf2_k(struct edid *edid) 2081 { 2082 u8 *r = NULL; 2083 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2084 return r ? r[16] : 0; 2085 } 2086 2087 static int 2088 drm_gtf2_2j(struct edid *edid) 2089 { 2090 u8 *r = NULL; 2091 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2092 return r ? r[17] : 0; 2093 } 2094 2095 /** 2096 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 2097 * @edid: EDID block to scan 2098 */ 2099 static int standard_timing_level(struct edid *edid) 2100 { 2101 if (edid->revision >= 2) { 2102 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 2103 return LEVEL_CVT; 2104 if (drm_gtf2_hbreak(edid)) 2105 return LEVEL_GTF2; 2106 return LEVEL_GTF; 2107 } 2108 return LEVEL_DMT; 2109 } 2110 2111 /* 2112 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 2113 * monitors fill with ascii space (0x20) instead. 2114 */ 2115 static int 2116 bad_std_timing(u8 a, u8 b) 2117 { 2118 return (a == 0x00 && b == 0x00) || 2119 (a == 0x01 && b == 0x01) || 2120 (a == 0x20 && b == 0x20); 2121 } 2122 2123 /** 2124 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 2125 * @connector: connector of for the EDID block 2126 * @edid: EDID block to scan 2127 * @t: standard timing params 2128 * 2129 * Take the standard timing params (in this case width, aspect, and refresh) 2130 * and convert them into a real mode using CVT/GTF/DMT. 2131 */ 2132 static struct drm_display_mode * 2133 drm_mode_std(struct drm_connector *connector, struct edid *edid, 2134 struct std_timing *t) 2135 { 2136 struct drm_device *dev = connector->dev; 2137 struct drm_display_mode *m, *mode = NULL; 2138 int hsize, vsize; 2139 int vrefresh_rate; 2140 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 2141 >> EDID_TIMING_ASPECT_SHIFT; 2142 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 2143 >> EDID_TIMING_VFREQ_SHIFT; 2144 int timing_level = standard_timing_level(edid); 2145 2146 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 2147 return NULL; 2148 2149 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 2150 hsize = t->hsize * 8 + 248; 2151 /* vrefresh_rate = vfreq + 60 */ 2152 vrefresh_rate = vfreq + 60; 2153 /* the vdisplay is calculated based on the aspect ratio */ 2154 if (aspect_ratio == 0) { 2155 if (edid->revision < 3) 2156 vsize = hsize; 2157 else 2158 vsize = (hsize * 10) / 16; 2159 } else if (aspect_ratio == 1) 2160 vsize = (hsize * 3) / 4; 2161 else if (aspect_ratio == 2) 2162 vsize = (hsize * 4) / 5; 2163 else 2164 vsize = (hsize * 9) / 16; 2165 2166 /* HDTV hack, part 1 */ 2167 if (vrefresh_rate == 60 && 2168 ((hsize == 1360 && vsize == 765) || 2169 (hsize == 1368 && vsize == 769))) { 2170 hsize = 1366; 2171 vsize = 768; 2172 } 2173 2174 /* 2175 * If this connector already has a mode for this size and refresh 2176 * rate (because it came from detailed or CVT info), use that 2177 * instead. This way we don't have to guess at interlace or 2178 * reduced blanking. 2179 */ 2180 list_for_each_entry(m, &connector->probed_modes, head) 2181 if (m->hdisplay == hsize && m->vdisplay == vsize && 2182 drm_mode_vrefresh(m) == vrefresh_rate) 2183 return NULL; 2184 2185 /* HDTV hack, part 2 */ 2186 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 2187 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 2188 false); 2189 if (!mode) 2190 return NULL; 2191 mode->hdisplay = 1366; 2192 mode->hsync_start = mode->hsync_start - 1; 2193 mode->hsync_end = mode->hsync_end - 1; 2194 return mode; 2195 } 2196 2197 /* check whether it can be found in default mode table */ 2198 if (drm_monitor_supports_rb(edid)) { 2199 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 2200 true); 2201 if (mode) 2202 return mode; 2203 } 2204 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 2205 if (mode) 2206 return mode; 2207 2208 /* okay, generate it */ 2209 switch (timing_level) { 2210 case LEVEL_DMT: 2211 break; 2212 case LEVEL_GTF: 2213 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2214 break; 2215 case LEVEL_GTF2: 2216 /* 2217 * This is potentially wrong if there's ever a monitor with 2218 * more than one ranges section, each claiming a different 2219 * secondary GTF curve. Please don't do that. 2220 */ 2221 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2222 if (!mode) 2223 return NULL; 2224 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 2225 drm_mode_destroy(dev, mode); 2226 mode = drm_gtf_mode_complex(dev, hsize, vsize, 2227 vrefresh_rate, 0, 0, 2228 drm_gtf2_m(edid), 2229 drm_gtf2_2c(edid), 2230 drm_gtf2_k(edid), 2231 drm_gtf2_2j(edid)); 2232 } 2233 break; 2234 case LEVEL_CVT: 2235 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 2236 false); 2237 break; 2238 } 2239 return mode; 2240 } 2241 2242 /* 2243 * EDID is delightfully ambiguous about how interlaced modes are to be 2244 * encoded. Our internal representation is of frame height, but some 2245 * HDTV detailed timings are encoded as field height. 2246 * 2247 * The format list here is from CEA, in frame size. Technically we 2248 * should be checking refresh rate too. Whatever. 2249 */ 2250 static void 2251 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 2252 struct detailed_pixel_timing *pt) 2253 { 2254 int i; 2255 static const struct { 2256 int w, h; 2257 } cea_interlaced[] = { 2258 { 1920, 1080 }, 2259 { 720, 480 }, 2260 { 1440, 480 }, 2261 { 2880, 480 }, 2262 { 720, 576 }, 2263 { 1440, 576 }, 2264 { 2880, 576 }, 2265 }; 2266 2267 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 2268 return; 2269 2270 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 2271 if ((mode->hdisplay == cea_interlaced[i].w) && 2272 (mode->vdisplay == cea_interlaced[i].h / 2)) { 2273 mode->vdisplay *= 2; 2274 mode->vsync_start *= 2; 2275 mode->vsync_end *= 2; 2276 mode->vtotal *= 2; 2277 mode->vtotal |= 1; 2278 } 2279 } 2280 2281 mode->flags |= DRM_MODE_FLAG_INTERLACE; 2282 } 2283 2284 /** 2285 * drm_mode_detailed - create a new mode from an EDID detailed timing section 2286 * @dev: DRM device (needed to create new mode) 2287 * @edid: EDID block 2288 * @timing: EDID detailed timing info 2289 * @quirks: quirks to apply 2290 * 2291 * An EDID detailed timing block contains enough info for us to create and 2292 * return a new struct drm_display_mode. 2293 */ 2294 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 2295 struct edid *edid, 2296 struct detailed_timing *timing, 2297 u32 quirks) 2298 { 2299 struct drm_display_mode *mode; 2300 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 2301 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 2302 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 2303 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 2304 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 2305 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 2306 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 2307 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 2308 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 2309 2310 /* ignore tiny modes */ 2311 if (hactive < 64 || vactive < 64) 2312 return NULL; 2313 2314 if (pt->misc & DRM_EDID_PT_STEREO) { 2315 DRM_DEBUG_KMS("stereo mode not supported\n"); 2316 return NULL; 2317 } 2318 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 2319 DRM_DEBUG_KMS("composite sync not supported\n"); 2320 } 2321 2322 /* it is incorrect if hsync/vsync width is zero */ 2323 if (!hsync_pulse_width || !vsync_pulse_width) { 2324 DRM_DEBUG_KMS("Incorrect Detailed timing. " 2325 "Wrong Hsync/Vsync pulse width\n"); 2326 return NULL; 2327 } 2328 2329 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 2330 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2331 if (!mode) 2332 return NULL; 2333 2334 goto set_size; 2335 } 2336 2337 mode = drm_mode_create(dev); 2338 if (!mode) 2339 return NULL; 2340 2341 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2342 timing->pixel_clock = cpu_to_le16(1088); 2343 2344 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2345 2346 mode->hdisplay = hactive; 2347 mode->hsync_start = mode->hdisplay + hsync_offset; 2348 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2349 mode->htotal = mode->hdisplay + hblank; 2350 2351 mode->vdisplay = vactive; 2352 mode->vsync_start = mode->vdisplay + vsync_offset; 2353 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2354 mode->vtotal = mode->vdisplay + vblank; 2355 2356 /* Some EDIDs have bogus h/vtotal values */ 2357 if (mode->hsync_end > mode->htotal) 2358 mode->htotal = mode->hsync_end + 1; 2359 if (mode->vsync_end > mode->vtotal) 2360 mode->vtotal = mode->vsync_end + 1; 2361 2362 drm_mode_do_interlace_quirk(mode, pt); 2363 2364 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2365 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 2366 } 2367 2368 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2369 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2370 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2371 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2372 2373 set_size: 2374 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2375 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2376 2377 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2378 mode->width_mm *= 10; 2379 mode->height_mm *= 10; 2380 } 2381 2382 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2383 mode->width_mm = edid->width_cm * 10; 2384 mode->height_mm = edid->height_cm * 10; 2385 } 2386 2387 mode->type = DRM_MODE_TYPE_DRIVER; 2388 mode->vrefresh = drm_mode_vrefresh(mode); 2389 drm_mode_set_name(mode); 2390 2391 return mode; 2392 } 2393 2394 static bool 2395 mode_in_hsync_range(const struct drm_display_mode *mode, 2396 struct edid *edid, u8 *t) 2397 { 2398 int hsync, hmin, hmax; 2399 2400 hmin = t[7]; 2401 if (edid->revision >= 4) 2402 hmin += ((t[4] & 0x04) ? 255 : 0); 2403 hmax = t[8]; 2404 if (edid->revision >= 4) 2405 hmax += ((t[4] & 0x08) ? 255 : 0); 2406 hsync = drm_mode_hsync(mode); 2407 2408 return (hsync <= hmax && hsync >= hmin); 2409 } 2410 2411 static bool 2412 mode_in_vsync_range(const struct drm_display_mode *mode, 2413 struct edid *edid, u8 *t) 2414 { 2415 int vsync, vmin, vmax; 2416 2417 vmin = t[5]; 2418 if (edid->revision >= 4) 2419 vmin += ((t[4] & 0x01) ? 255 : 0); 2420 vmax = t[6]; 2421 if (edid->revision >= 4) 2422 vmax += ((t[4] & 0x02) ? 255 : 0); 2423 vsync = drm_mode_vrefresh(mode); 2424 2425 return (vsync <= vmax && vsync >= vmin); 2426 } 2427 2428 static u32 2429 range_pixel_clock(struct edid *edid, u8 *t) 2430 { 2431 /* unspecified */ 2432 if (t[9] == 0 || t[9] == 255) 2433 return 0; 2434 2435 /* 1.4 with CVT support gives us real precision, yay */ 2436 if (edid->revision >= 4 && t[10] == 0x04) 2437 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2438 2439 /* 1.3 is pathetic, so fuzz up a bit */ 2440 return t[9] * 10000 + 5001; 2441 } 2442 2443 static bool 2444 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2445 struct detailed_timing *timing) 2446 { 2447 u32 max_clock; 2448 u8 *t = (u8 *)timing; 2449 2450 if (!mode_in_hsync_range(mode, edid, t)) 2451 return false; 2452 2453 if (!mode_in_vsync_range(mode, edid, t)) 2454 return false; 2455 2456 if ((max_clock = range_pixel_clock(edid, t))) 2457 if (mode->clock > max_clock) 2458 return false; 2459 2460 /* 1.4 max horizontal check */ 2461 if (edid->revision >= 4 && t[10] == 0x04) 2462 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2463 return false; 2464 2465 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2466 return false; 2467 2468 return true; 2469 } 2470 2471 static bool valid_inferred_mode(const struct drm_connector *connector, 2472 const struct drm_display_mode *mode) 2473 { 2474 const struct drm_display_mode *m; 2475 bool ok = false; 2476 2477 list_for_each_entry(m, &connector->probed_modes, head) { 2478 if (mode->hdisplay == m->hdisplay && 2479 mode->vdisplay == m->vdisplay && 2480 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2481 return false; /* duplicated */ 2482 if (mode->hdisplay <= m->hdisplay && 2483 mode->vdisplay <= m->vdisplay) 2484 ok = true; 2485 } 2486 return ok; 2487 } 2488 2489 static int 2490 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2491 struct detailed_timing *timing) 2492 { 2493 int i, modes = 0; 2494 struct drm_display_mode *newmode; 2495 struct drm_device *dev = connector->dev; 2496 2497 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2498 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2499 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2500 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2501 if (newmode) { 2502 drm_mode_probed_add(connector, newmode); 2503 modes++; 2504 } 2505 } 2506 } 2507 2508 return modes; 2509 } 2510 2511 /* fix up 1366x768 mode from 1368x768; 2512 * GFT/CVT can't express 1366 width which isn't dividable by 8 2513 */ 2514 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 2515 { 2516 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2517 mode->hdisplay = 1366; 2518 mode->hsync_start--; 2519 mode->hsync_end--; 2520 drm_mode_set_name(mode); 2521 } 2522 } 2523 2524 static int 2525 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2526 struct detailed_timing *timing) 2527 { 2528 int i, modes = 0; 2529 struct drm_display_mode *newmode; 2530 struct drm_device *dev = connector->dev; 2531 2532 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2533 const struct minimode *m = &extra_modes[i]; 2534 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2535 if (!newmode) 2536 return modes; 2537 2538 drm_mode_fixup_1366x768(newmode); 2539 if (!mode_in_range(newmode, edid, timing) || 2540 !valid_inferred_mode(connector, newmode)) { 2541 drm_mode_destroy(dev, newmode); 2542 continue; 2543 } 2544 2545 drm_mode_probed_add(connector, newmode); 2546 modes++; 2547 } 2548 2549 return modes; 2550 } 2551 2552 static int 2553 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2554 struct detailed_timing *timing) 2555 { 2556 int i, modes = 0; 2557 struct drm_display_mode *newmode; 2558 struct drm_device *dev = connector->dev; 2559 bool rb = drm_monitor_supports_rb(edid); 2560 2561 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2562 const struct minimode *m = &extra_modes[i]; 2563 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2564 if (!newmode) 2565 return modes; 2566 2567 drm_mode_fixup_1366x768(newmode); 2568 if (!mode_in_range(newmode, edid, timing) || 2569 !valid_inferred_mode(connector, newmode)) { 2570 drm_mode_destroy(dev, newmode); 2571 continue; 2572 } 2573 2574 drm_mode_probed_add(connector, newmode); 2575 modes++; 2576 } 2577 2578 return modes; 2579 } 2580 2581 static void 2582 do_inferred_modes(struct detailed_timing *timing, void *c) 2583 { 2584 struct detailed_mode_closure *closure = c; 2585 struct detailed_non_pixel *data = &timing->data.other_data; 2586 struct detailed_data_monitor_range *range = &data->data.range; 2587 2588 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2589 return; 2590 2591 closure->modes += drm_dmt_modes_for_range(closure->connector, 2592 closure->edid, 2593 timing); 2594 2595 if (!version_greater(closure->edid, 1, 1)) 2596 return; /* GTF not defined yet */ 2597 2598 switch (range->flags) { 2599 case 0x02: /* secondary gtf, XXX could do more */ 2600 case 0x00: /* default gtf */ 2601 closure->modes += drm_gtf_modes_for_range(closure->connector, 2602 closure->edid, 2603 timing); 2604 break; 2605 case 0x04: /* cvt, only in 1.4+ */ 2606 if (!version_greater(closure->edid, 1, 3)) 2607 break; 2608 2609 closure->modes += drm_cvt_modes_for_range(closure->connector, 2610 closure->edid, 2611 timing); 2612 break; 2613 case 0x01: /* just the ranges, no formula */ 2614 default: 2615 break; 2616 } 2617 } 2618 2619 static int 2620 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2621 { 2622 struct detailed_mode_closure closure = { 2623 .connector = connector, 2624 .edid = edid, 2625 }; 2626 2627 if (version_greater(edid, 1, 0)) 2628 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2629 &closure); 2630 2631 return closure.modes; 2632 } 2633 2634 static int 2635 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2636 { 2637 int i, j, m, modes = 0; 2638 struct drm_display_mode *mode; 2639 u8 *est = ((u8 *)timing) + 6; 2640 2641 for (i = 0; i < 6; i++) { 2642 for (j = 7; j >= 0; j--) { 2643 m = (i * 8) + (7 - j); 2644 if (m >= ARRAY_SIZE(est3_modes)) 2645 break; 2646 if (est[i] & (1 << j)) { 2647 mode = drm_mode_find_dmt(connector->dev, 2648 est3_modes[m].w, 2649 est3_modes[m].h, 2650 est3_modes[m].r, 2651 est3_modes[m].rb); 2652 if (mode) { 2653 drm_mode_probed_add(connector, mode); 2654 modes++; 2655 } 2656 } 2657 } 2658 } 2659 2660 return modes; 2661 } 2662 2663 static void 2664 do_established_modes(struct detailed_timing *timing, void *c) 2665 { 2666 struct detailed_mode_closure *closure = c; 2667 struct detailed_non_pixel *data = &timing->data.other_data; 2668 2669 if (data->type == EDID_DETAIL_EST_TIMINGS) 2670 closure->modes += drm_est3_modes(closure->connector, timing); 2671 } 2672 2673 /** 2674 * add_established_modes - get est. modes from EDID and add them 2675 * @connector: connector to add mode(s) to 2676 * @edid: EDID block to scan 2677 * 2678 * Each EDID block contains a bitmap of the supported "established modes" list 2679 * (defined above). Tease them out and add them to the global modes list. 2680 */ 2681 static int 2682 add_established_modes(struct drm_connector *connector, struct edid *edid) 2683 { 2684 struct drm_device *dev = connector->dev; 2685 unsigned long est_bits = edid->established_timings.t1 | 2686 (edid->established_timings.t2 << 8) | 2687 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2688 int i, modes = 0; 2689 struct detailed_mode_closure closure = { 2690 .connector = connector, 2691 .edid = edid, 2692 }; 2693 2694 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2695 if (est_bits & (1<<i)) { 2696 struct drm_display_mode *newmode; 2697 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2698 if (newmode) { 2699 drm_mode_probed_add(connector, newmode); 2700 modes++; 2701 } 2702 } 2703 } 2704 2705 if (version_greater(edid, 1, 0)) 2706 drm_for_each_detailed_block((u8 *)edid, 2707 do_established_modes, &closure); 2708 2709 return modes + closure.modes; 2710 } 2711 2712 static void 2713 do_standard_modes(struct detailed_timing *timing, void *c) 2714 { 2715 struct detailed_mode_closure *closure = c; 2716 struct detailed_non_pixel *data = &timing->data.other_data; 2717 struct drm_connector *connector = closure->connector; 2718 struct edid *edid = closure->edid; 2719 2720 if (data->type == EDID_DETAIL_STD_MODES) { 2721 int i; 2722 for (i = 0; i < 6; i++) { 2723 struct std_timing *std; 2724 struct drm_display_mode *newmode; 2725 2726 std = &data->data.timings[i]; 2727 newmode = drm_mode_std(connector, edid, std); 2728 if (newmode) { 2729 drm_mode_probed_add(connector, newmode); 2730 closure->modes++; 2731 } 2732 } 2733 } 2734 } 2735 2736 /** 2737 * add_standard_modes - get std. modes from EDID and add them 2738 * @connector: connector to add mode(s) to 2739 * @edid: EDID block to scan 2740 * 2741 * Standard modes can be calculated using the appropriate standard (DMT, 2742 * GTF or CVT. Grab them from @edid and add them to the list. 2743 */ 2744 static int 2745 add_standard_modes(struct drm_connector *connector, struct edid *edid) 2746 { 2747 int i, modes = 0; 2748 struct detailed_mode_closure closure = { 2749 .connector = connector, 2750 .edid = edid, 2751 }; 2752 2753 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2754 struct drm_display_mode *newmode; 2755 2756 newmode = drm_mode_std(connector, edid, 2757 &edid->standard_timings[i]); 2758 if (newmode) { 2759 drm_mode_probed_add(connector, newmode); 2760 modes++; 2761 } 2762 } 2763 2764 if (version_greater(edid, 1, 0)) 2765 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2766 &closure); 2767 2768 /* XXX should also look for standard codes in VTB blocks */ 2769 2770 return modes + closure.modes; 2771 } 2772 2773 static int drm_cvt_modes(struct drm_connector *connector, 2774 struct detailed_timing *timing) 2775 { 2776 int i, j, modes = 0; 2777 struct drm_display_mode *newmode; 2778 struct drm_device *dev = connector->dev; 2779 struct cvt_timing *cvt; 2780 const int rates[] = { 60, 85, 75, 60, 50 }; 2781 const u8 empty[3] = { 0, 0, 0 }; 2782 2783 for (i = 0; i < 4; i++) { 2784 int uninitialized_var(width), height; 2785 cvt = &(timing->data.other_data.data.cvt[i]); 2786 2787 if (!memcmp(cvt->code, empty, 3)) 2788 continue; 2789 2790 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2791 switch (cvt->code[1] & 0x0c) { 2792 case 0x00: 2793 width = height * 4 / 3; 2794 break; 2795 case 0x04: 2796 width = height * 16 / 9; 2797 break; 2798 case 0x08: 2799 width = height * 16 / 10; 2800 break; 2801 case 0x0c: 2802 width = height * 15 / 9; 2803 break; 2804 } 2805 2806 for (j = 1; j < 5; j++) { 2807 if (cvt->code[2] & (1 << j)) { 2808 newmode = drm_cvt_mode(dev, width, height, 2809 rates[j], j == 0, 2810 false, false); 2811 if (newmode) { 2812 drm_mode_probed_add(connector, newmode); 2813 modes++; 2814 } 2815 } 2816 } 2817 } 2818 2819 return modes; 2820 } 2821 2822 static void 2823 do_cvt_mode(struct detailed_timing *timing, void *c) 2824 { 2825 struct detailed_mode_closure *closure = c; 2826 struct detailed_non_pixel *data = &timing->data.other_data; 2827 2828 if (data->type == EDID_DETAIL_CVT_3BYTE) 2829 closure->modes += drm_cvt_modes(closure->connector, timing); 2830 } 2831 2832 static int 2833 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2834 { 2835 struct detailed_mode_closure closure = { 2836 .connector = connector, 2837 .edid = edid, 2838 }; 2839 2840 if (version_greater(edid, 1, 2)) 2841 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2842 2843 /* XXX should also look for CVT codes in VTB blocks */ 2844 2845 return closure.modes; 2846 } 2847 2848 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 2849 2850 static void 2851 do_detailed_mode(struct detailed_timing *timing, void *c) 2852 { 2853 struct detailed_mode_closure *closure = c; 2854 struct drm_display_mode *newmode; 2855 2856 if (timing->pixel_clock) { 2857 newmode = drm_mode_detailed(closure->connector->dev, 2858 closure->edid, timing, 2859 closure->quirks); 2860 if (!newmode) 2861 return; 2862 2863 if (closure->preferred) 2864 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2865 2866 /* 2867 * Detailed modes are limited to 10kHz pixel clock resolution, 2868 * so fix up anything that looks like CEA/HDMI mode, but the clock 2869 * is just slightly off. 2870 */ 2871 fixup_detailed_cea_mode_clock(newmode); 2872 2873 drm_mode_probed_add(closure->connector, newmode); 2874 closure->modes++; 2875 closure->preferred = false; 2876 } 2877 } 2878 2879 /* 2880 * add_detailed_modes - Add modes from detailed timings 2881 * @connector: attached connector 2882 * @edid: EDID block to scan 2883 * @quirks: quirks to apply 2884 */ 2885 static int 2886 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2887 u32 quirks) 2888 { 2889 struct detailed_mode_closure closure = { 2890 .connector = connector, 2891 .edid = edid, 2892 .preferred = true, 2893 .quirks = quirks, 2894 }; 2895 2896 if (closure.preferred && !version_greater(edid, 1, 3)) 2897 closure.preferred = 2898 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2899 2900 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2901 2902 return closure.modes; 2903 } 2904 2905 #define AUDIO_BLOCK 0x01 2906 #define VIDEO_BLOCK 0x02 2907 #define VENDOR_BLOCK 0x03 2908 #define SPEAKER_BLOCK 0x04 2909 #define USE_EXTENDED_TAG 0x07 2910 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00 2911 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 2912 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F 2913 #define EDID_BASIC_AUDIO (1 << 6) 2914 #define EDID_CEA_YCRCB444 (1 << 5) 2915 #define EDID_CEA_YCRCB422 (1 << 4) 2916 #define EDID_CEA_VCDB_QS (1 << 6) 2917 2918 /* 2919 * Search EDID for CEA extension block. 2920 */ 2921 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id) 2922 { 2923 u8 *edid_ext = NULL; 2924 int i; 2925 2926 /* No EDID or EDID extensions */ 2927 if (edid == NULL || edid->extensions == 0) 2928 return NULL; 2929 2930 /* Find CEA extension */ 2931 for (i = 0; i < edid->extensions; i++) { 2932 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2933 if (edid_ext[0] == ext_id) 2934 break; 2935 } 2936 2937 if (i == edid->extensions) 2938 return NULL; 2939 2940 return edid_ext; 2941 } 2942 2943 2944 static u8 *drm_find_displayid_extension(const struct edid *edid) 2945 { 2946 return drm_find_edid_extension(edid, DISPLAYID_EXT); 2947 } 2948 2949 static u8 *drm_find_cea_extension(const struct edid *edid) 2950 { 2951 int ret; 2952 int idx = 1; 2953 int length = EDID_LENGTH; 2954 struct displayid_block *block; 2955 u8 *cea; 2956 u8 *displayid; 2957 2958 /* Look for a top level CEA extension block */ 2959 cea = drm_find_edid_extension(edid, CEA_EXT); 2960 if (cea) 2961 return cea; 2962 2963 /* CEA blocks can also be found embedded in a DisplayID block */ 2964 displayid = drm_find_displayid_extension(edid); 2965 if (!displayid) 2966 return NULL; 2967 2968 ret = validate_displayid(displayid, length, idx); 2969 if (ret) 2970 return NULL; 2971 2972 idx += sizeof(struct displayid_hdr); 2973 for_each_displayid_db(displayid, block, idx, length) { 2974 if (block->tag == DATA_BLOCK_CTA) { 2975 cea = (u8 *)block; 2976 break; 2977 } 2978 } 2979 2980 return cea; 2981 } 2982 2983 /* 2984 * Calculate the alternate clock for the CEA mode 2985 * (60Hz vs. 59.94Hz etc.) 2986 */ 2987 static unsigned int 2988 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 2989 { 2990 unsigned int clock = cea_mode->clock; 2991 2992 if (cea_mode->vrefresh % 6 != 0) 2993 return clock; 2994 2995 /* 2996 * edid_cea_modes contains the 59.94Hz 2997 * variant for 240 and 480 line modes, 2998 * and the 60Hz variant otherwise. 2999 */ 3000 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3001 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3002 else 3003 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3004 3005 return clock; 3006 } 3007 3008 static bool 3009 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 3010 { 3011 /* 3012 * For certain VICs the spec allows the vertical 3013 * front porch to vary by one or two lines. 3014 * 3015 * cea_modes[] stores the variant with the shortest 3016 * vertical front porch. We can adjust the mode to 3017 * get the other variants by simply increasing the 3018 * vertical front porch length. 3019 */ 3020 #ifdef notyet 3021 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 || 3022 edid_cea_modes[9].vtotal != 262 || 3023 edid_cea_modes[12].vtotal != 262 || 3024 edid_cea_modes[13].vtotal != 262 || 3025 edid_cea_modes[23].vtotal != 312 || 3026 edid_cea_modes[24].vtotal != 312 || 3027 edid_cea_modes[27].vtotal != 312 || 3028 edid_cea_modes[28].vtotal != 312); 3029 #endif 3030 3031 if (((vic == 8 || vic == 9 || 3032 vic == 12 || vic == 13) && mode->vtotal < 263) || 3033 ((vic == 23 || vic == 24 || 3034 vic == 27 || vic == 28) && mode->vtotal < 314)) { 3035 mode->vsync_start++; 3036 mode->vsync_end++; 3037 mode->vtotal++; 3038 3039 return true; 3040 } 3041 3042 return false; 3043 } 3044 3045 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3046 unsigned int clock_tolerance) 3047 { 3048 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3049 u8 vic; 3050 3051 if (!to_match->clock) 3052 return 0; 3053 3054 if (to_match->picture_aspect_ratio) 3055 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3056 3057 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 3058 struct drm_display_mode cea_mode = edid_cea_modes[vic]; 3059 unsigned int clock1, clock2; 3060 3061 /* Check both 60Hz and 59.94Hz */ 3062 clock1 = cea_mode.clock; 3063 clock2 = cea_mode_alternate_clock(&cea_mode); 3064 3065 if (abs(to_match->clock - clock1) > clock_tolerance && 3066 abs(to_match->clock - clock2) > clock_tolerance) 3067 continue; 3068 3069 do { 3070 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3071 return vic; 3072 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3073 } 3074 3075 return 0; 3076 } 3077 3078 /** 3079 * drm_match_cea_mode - look for a CEA mode matching given mode 3080 * @to_match: display mode 3081 * 3082 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 3083 * mode. 3084 */ 3085 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 3086 { 3087 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3088 u8 vic; 3089 3090 if (!to_match->clock) 3091 return 0; 3092 3093 if (to_match->picture_aspect_ratio) 3094 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3095 3096 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 3097 struct drm_display_mode cea_mode = edid_cea_modes[vic]; 3098 unsigned int clock1, clock2; 3099 3100 /* Check both 60Hz and 59.94Hz */ 3101 clock1 = cea_mode.clock; 3102 clock2 = cea_mode_alternate_clock(&cea_mode); 3103 3104 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 3105 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 3106 continue; 3107 3108 do { 3109 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3110 return vic; 3111 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3112 } 3113 3114 return 0; 3115 } 3116 EXPORT_SYMBOL(drm_match_cea_mode); 3117 3118 static bool drm_valid_cea_vic(u8 vic) 3119 { 3120 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); 3121 } 3122 3123 /** 3124 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to 3125 * the input VIC from the CEA mode list 3126 * @video_code: ID given to each of the CEA modes 3127 * 3128 * Returns picture aspect ratio 3129 */ 3130 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 3131 { 3132 return edid_cea_modes[video_code].picture_aspect_ratio; 3133 } 3134 EXPORT_SYMBOL(drm_get_cea_aspect_ratio); 3135 3136 /* 3137 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 3138 * specific block). 3139 * 3140 * It's almost like cea_mode_alternate_clock(), we just need to add an 3141 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 3142 * one. 3143 */ 3144 static unsigned int 3145 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3146 { 3147 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 3148 return hdmi_mode->clock; 3149 3150 return cea_mode_alternate_clock(hdmi_mode); 3151 } 3152 3153 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3154 unsigned int clock_tolerance) 3155 { 3156 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3157 u8 vic; 3158 3159 if (!to_match->clock) 3160 return 0; 3161 3162 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3163 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3164 unsigned int clock1, clock2; 3165 3166 /* Make sure to also match alternate clocks */ 3167 clock1 = hdmi_mode->clock; 3168 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3169 3170 if (abs(to_match->clock - clock1) > clock_tolerance && 3171 abs(to_match->clock - clock2) > clock_tolerance) 3172 continue; 3173 3174 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 3175 return vic; 3176 } 3177 3178 return 0; 3179 } 3180 3181 /* 3182 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 3183 * @to_match: display mode 3184 * 3185 * An HDMI mode is one defined in the HDMI vendor specific block. 3186 * 3187 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 3188 */ 3189 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 3190 { 3191 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3192 u8 vic; 3193 3194 if (!to_match->clock) 3195 return 0; 3196 3197 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3198 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3199 unsigned int clock1, clock2; 3200 3201 /* Make sure to also match alternate clocks */ 3202 clock1 = hdmi_mode->clock; 3203 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3204 3205 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 3206 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 3207 drm_mode_match(to_match, hdmi_mode, match_flags)) 3208 return vic; 3209 } 3210 return 0; 3211 } 3212 3213 static bool drm_valid_hdmi_vic(u8 vic) 3214 { 3215 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 3216 } 3217 3218 static int 3219 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 3220 { 3221 struct drm_device *dev = connector->dev; 3222 struct drm_display_mode *mode, *tmp; 3223 DRM_LIST_HEAD(list); 3224 int modes = 0; 3225 3226 /* Don't add CEA modes if the CEA extension block is missing */ 3227 if (!drm_find_cea_extension(edid)) 3228 return 0; 3229 3230 /* 3231 * Go through all probed modes and create a new mode 3232 * with the alternate clock for certain CEA modes. 3233 */ 3234 list_for_each_entry(mode, &connector->probed_modes, head) { 3235 const struct drm_display_mode *cea_mode = NULL; 3236 struct drm_display_mode *newmode; 3237 u8 vic = drm_match_cea_mode(mode); 3238 unsigned int clock1, clock2; 3239 3240 if (drm_valid_cea_vic(vic)) { 3241 cea_mode = &edid_cea_modes[vic]; 3242 clock2 = cea_mode_alternate_clock(cea_mode); 3243 } else { 3244 vic = drm_match_hdmi_mode(mode); 3245 if (drm_valid_hdmi_vic(vic)) { 3246 cea_mode = &edid_4k_modes[vic]; 3247 clock2 = hdmi_mode_alternate_clock(cea_mode); 3248 } 3249 } 3250 3251 if (!cea_mode) 3252 continue; 3253 3254 clock1 = cea_mode->clock; 3255 3256 if (clock1 == clock2) 3257 continue; 3258 3259 if (mode->clock != clock1 && mode->clock != clock2) 3260 continue; 3261 3262 newmode = drm_mode_duplicate(dev, cea_mode); 3263 if (!newmode) 3264 continue; 3265 3266 /* Carry over the stereo flags */ 3267 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 3268 3269 /* 3270 * The current mode could be either variant. Make 3271 * sure to pick the "other" clock for the new mode. 3272 */ 3273 if (mode->clock != clock1) 3274 newmode->clock = clock1; 3275 else 3276 newmode->clock = clock2; 3277 3278 list_add_tail(&newmode->head, &list); 3279 } 3280 3281 list_for_each_entry_safe(mode, tmp, &list, head) { 3282 list_del(&mode->head); 3283 drm_mode_probed_add(connector, mode); 3284 modes++; 3285 } 3286 3287 return modes; 3288 } 3289 3290 static u8 svd_to_vic(u8 svd) 3291 { 3292 /* 0-6 bit vic, 7th bit native mode indicator */ 3293 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 3294 return svd & 127; 3295 3296 return svd; 3297 } 3298 3299 static struct drm_display_mode * 3300 drm_display_mode_from_vic_index(struct drm_connector *connector, 3301 const u8 *video_db, u8 video_len, 3302 u8 video_index) 3303 { 3304 struct drm_device *dev = connector->dev; 3305 struct drm_display_mode *newmode; 3306 u8 vic; 3307 3308 if (video_db == NULL || video_index >= video_len) 3309 return NULL; 3310 3311 /* CEA modes are numbered 1..127 */ 3312 vic = svd_to_vic(video_db[video_index]); 3313 if (!drm_valid_cea_vic(vic)) 3314 return NULL; 3315 3316 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 3317 if (!newmode) 3318 return NULL; 3319 3320 newmode->vrefresh = 0; 3321 3322 return newmode; 3323 } 3324 3325 /* 3326 * do_y420vdb_modes - Parse YCBCR 420 only modes 3327 * @connector: connector corresponding to the HDMI sink 3328 * @svds: start of the data block of CEA YCBCR 420 VDB 3329 * @len: length of the CEA YCBCR 420 VDB 3330 * 3331 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 3332 * which contains modes which can be supported in YCBCR 420 3333 * output format only. 3334 */ 3335 static int do_y420vdb_modes(struct drm_connector *connector, 3336 const u8 *svds, u8 svds_len) 3337 { 3338 int modes = 0, i; 3339 struct drm_device *dev = connector->dev; 3340 struct drm_display_info *info = &connector->display_info; 3341 struct drm_hdmi_info *hdmi = &info->hdmi; 3342 3343 for (i = 0; i < svds_len; i++) { 3344 u8 vic = svd_to_vic(svds[i]); 3345 struct drm_display_mode *newmode; 3346 3347 if (!drm_valid_cea_vic(vic)) 3348 continue; 3349 3350 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 3351 if (!newmode) 3352 break; 3353 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 3354 drm_mode_probed_add(connector, newmode); 3355 modes++; 3356 } 3357 3358 if (modes > 0) 3359 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3360 return modes; 3361 } 3362 3363 /* 3364 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 3365 * @connector: connector corresponding to the HDMI sink 3366 * @vic: CEA vic for the video mode to be added in the map 3367 * 3368 * Makes an entry for a videomode in the YCBCR 420 bitmap 3369 */ 3370 static void 3371 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 3372 { 3373 u8 vic = svd_to_vic(svd); 3374 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3375 3376 if (!drm_valid_cea_vic(vic)) 3377 return; 3378 3379 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 3380 } 3381 3382 static int 3383 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 3384 { 3385 int i, modes = 0; 3386 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3387 3388 for (i = 0; i < len; i++) { 3389 struct drm_display_mode *mode; 3390 mode = drm_display_mode_from_vic_index(connector, db, len, i); 3391 if (mode) { 3392 /* 3393 * YCBCR420 capability block contains a bitmap which 3394 * gives the index of CEA modes from CEA VDB, which 3395 * can support YCBCR 420 sampling output also (apart 3396 * from RGB/YCBCR444 etc). 3397 * For example, if the bit 0 in bitmap is set, 3398 * first mode in VDB can support YCBCR420 output too. 3399 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 3400 */ 3401 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 3402 drm_add_cmdb_modes(connector, db[i]); 3403 3404 drm_mode_probed_add(connector, mode); 3405 modes++; 3406 } 3407 } 3408 3409 return modes; 3410 } 3411 3412 struct stereo_mandatory_mode { 3413 int width, height, vrefresh; 3414 unsigned int flags; 3415 }; 3416 3417 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 3418 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3419 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3420 { 1920, 1080, 50, 3421 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3422 { 1920, 1080, 60, 3423 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3424 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3425 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3426 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3427 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 3428 }; 3429 3430 static bool 3431 stereo_match_mandatory(const struct drm_display_mode *mode, 3432 const struct stereo_mandatory_mode *stereo_mode) 3433 { 3434 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 3435 3436 return mode->hdisplay == stereo_mode->width && 3437 mode->vdisplay == stereo_mode->height && 3438 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 3439 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 3440 } 3441 3442 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 3443 { 3444 struct drm_device *dev = connector->dev; 3445 const struct drm_display_mode *mode; 3446 struct list_head stereo_modes; 3447 int modes = 0, i; 3448 3449 INIT_LIST_HEAD(&stereo_modes); 3450 3451 list_for_each_entry(mode, &connector->probed_modes, head) { 3452 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 3453 const struct stereo_mandatory_mode *mandatory; 3454 struct drm_display_mode *new_mode; 3455 3456 if (!stereo_match_mandatory(mode, 3457 &stereo_mandatory_modes[i])) 3458 continue; 3459 3460 mandatory = &stereo_mandatory_modes[i]; 3461 new_mode = drm_mode_duplicate(dev, mode); 3462 if (!new_mode) 3463 continue; 3464 3465 new_mode->flags |= mandatory->flags; 3466 list_add_tail(&new_mode->head, &stereo_modes); 3467 modes++; 3468 } 3469 } 3470 3471 list_splice_tail(&stereo_modes, &connector->probed_modes); 3472 3473 return modes; 3474 } 3475 3476 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 3477 { 3478 struct drm_device *dev = connector->dev; 3479 struct drm_display_mode *newmode; 3480 3481 if (!drm_valid_hdmi_vic(vic)) { 3482 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 3483 return 0; 3484 } 3485 3486 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 3487 if (!newmode) 3488 return 0; 3489 3490 drm_mode_probed_add(connector, newmode); 3491 3492 return 1; 3493 } 3494 3495 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 3496 const u8 *video_db, u8 video_len, u8 video_index) 3497 { 3498 struct drm_display_mode *newmode; 3499 int modes = 0; 3500 3501 if (structure & (1 << 0)) { 3502 newmode = drm_display_mode_from_vic_index(connector, video_db, 3503 video_len, 3504 video_index); 3505 if (newmode) { 3506 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 3507 drm_mode_probed_add(connector, newmode); 3508 modes++; 3509 } 3510 } 3511 if (structure & (1 << 6)) { 3512 newmode = drm_display_mode_from_vic_index(connector, video_db, 3513 video_len, 3514 video_index); 3515 if (newmode) { 3516 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3517 drm_mode_probed_add(connector, newmode); 3518 modes++; 3519 } 3520 } 3521 if (structure & (1 << 8)) { 3522 newmode = drm_display_mode_from_vic_index(connector, video_db, 3523 video_len, 3524 video_index); 3525 if (newmode) { 3526 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3527 drm_mode_probed_add(connector, newmode); 3528 modes++; 3529 } 3530 } 3531 3532 return modes; 3533 } 3534 3535 /* 3536 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 3537 * @connector: connector corresponding to the HDMI sink 3538 * @db: start of the CEA vendor specific block 3539 * @len: length of the CEA block payload, ie. one can access up to db[len] 3540 * 3541 * Parses the HDMI VSDB looking for modes to add to @connector. This function 3542 * also adds the stereo 3d modes when applicable. 3543 */ 3544 static int 3545 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 3546 const u8 *video_db, u8 video_len) 3547 { 3548 struct drm_display_info *info = &connector->display_info; 3549 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 3550 u8 vic_len, hdmi_3d_len = 0; 3551 u16 mask; 3552 u16 structure_all; 3553 3554 if (len < 8) 3555 goto out; 3556 3557 /* no HDMI_Video_Present */ 3558 if (!(db[8] & (1 << 5))) 3559 goto out; 3560 3561 /* Latency_Fields_Present */ 3562 if (db[8] & (1 << 7)) 3563 offset += 2; 3564 3565 /* I_Latency_Fields_Present */ 3566 if (db[8] & (1 << 6)) 3567 offset += 2; 3568 3569 /* the declared length is not long enough for the 2 first bytes 3570 * of additional video format capabilities */ 3571 if (len < (8 + offset + 2)) 3572 goto out; 3573 3574 /* 3D_Present */ 3575 offset++; 3576 if (db[8 + offset] & (1 << 7)) { 3577 modes += add_hdmi_mandatory_stereo_modes(connector); 3578 3579 /* 3D_Multi_present */ 3580 multi_present = (db[8 + offset] & 0x60) >> 5; 3581 } 3582 3583 offset++; 3584 vic_len = db[8 + offset] >> 5; 3585 hdmi_3d_len = db[8 + offset] & 0x1f; 3586 3587 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3588 u8 vic; 3589 3590 vic = db[9 + offset + i]; 3591 modes += add_hdmi_mode(connector, vic); 3592 } 3593 offset += 1 + vic_len; 3594 3595 if (multi_present == 1) 3596 multi_len = 2; 3597 else if (multi_present == 2) 3598 multi_len = 4; 3599 else 3600 multi_len = 0; 3601 3602 if (len < (8 + offset + hdmi_3d_len - 1)) 3603 goto out; 3604 3605 if (hdmi_3d_len < multi_len) 3606 goto out; 3607 3608 if (multi_present == 1 || multi_present == 2) { 3609 /* 3D_Structure_ALL */ 3610 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3611 3612 /* check if 3D_MASK is present */ 3613 if (multi_present == 2) 3614 mask = (db[10 + offset] << 8) | db[11 + offset]; 3615 else 3616 mask = 0xffff; 3617 3618 for (i = 0; i < 16; i++) { 3619 if (mask & (1 << i)) 3620 modes += add_3d_struct_modes(connector, 3621 structure_all, 3622 video_db, 3623 video_len, i); 3624 } 3625 } 3626 3627 offset += multi_len; 3628 3629 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3630 int vic_index; 3631 struct drm_display_mode *newmode = NULL; 3632 unsigned int newflag = 0; 3633 bool detail_present; 3634 3635 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3636 3637 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3638 break; 3639 3640 /* 2D_VIC_order_X */ 3641 vic_index = db[8 + offset + i] >> 4; 3642 3643 /* 3D_Structure_X */ 3644 switch (db[8 + offset + i] & 0x0f) { 3645 case 0: 3646 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3647 break; 3648 case 6: 3649 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3650 break; 3651 case 8: 3652 /* 3D_Detail_X */ 3653 if ((db[9 + offset + i] >> 4) == 1) 3654 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3655 break; 3656 } 3657 3658 if (newflag != 0) { 3659 newmode = drm_display_mode_from_vic_index(connector, 3660 video_db, 3661 video_len, 3662 vic_index); 3663 3664 if (newmode) { 3665 newmode->flags |= newflag; 3666 drm_mode_probed_add(connector, newmode); 3667 modes++; 3668 } 3669 } 3670 3671 if (detail_present) 3672 i++; 3673 } 3674 3675 out: 3676 if (modes > 0) 3677 info->has_hdmi_infoframe = true; 3678 return modes; 3679 } 3680 3681 static int 3682 cea_db_payload_len(const u8 *db) 3683 { 3684 return db[0] & 0x1f; 3685 } 3686 3687 static int 3688 cea_db_extended_tag(const u8 *db) 3689 { 3690 return db[1]; 3691 } 3692 3693 static int 3694 cea_db_tag(const u8 *db) 3695 { 3696 return db[0] >> 5; 3697 } 3698 3699 static int 3700 cea_revision(const u8 *cea) 3701 { 3702 return cea[1]; 3703 } 3704 3705 static int 3706 cea_db_offsets(const u8 *cea, int *start, int *end) 3707 { 3708 /* DisplayID CTA extension blocks and top-level CEA EDID 3709 * block header definitions differ in the following bytes: 3710 * 1) Byte 2 of the header specifies length differently, 3711 * 2) Byte 3 is only present in the CEA top level block. 3712 * 3713 * The different definitions for byte 2 follow. 3714 * 3715 * DisplayID CTA extension block defines byte 2 as: 3716 * Number of payload bytes 3717 * 3718 * CEA EDID block defines byte 2 as: 3719 * Byte number (decimal) within this block where the 18-byte 3720 * DTDs begin. If no non-DTD data is present in this extension 3721 * block, the value should be set to 04h (the byte after next). 3722 * If set to 00h, there are no DTDs present in this block and 3723 * no non-DTD data. 3724 */ 3725 if (cea[0] == DATA_BLOCK_CTA) { 3726 *start = 3; 3727 *end = *start + cea[2]; 3728 } else if (cea[0] == CEA_EXT) { 3729 /* Data block offset in CEA extension block */ 3730 *start = 4; 3731 *end = cea[2]; 3732 if (*end == 0) 3733 *end = 127; 3734 if (*end < 4 || *end > 127) 3735 return -ERANGE; 3736 } else { 3737 return -ENOTSUPP; 3738 } 3739 3740 return 0; 3741 } 3742 3743 static bool cea_db_is_hdmi_vsdb(const u8 *db) 3744 { 3745 int hdmi_id; 3746 3747 if (cea_db_tag(db) != VENDOR_BLOCK) 3748 return false; 3749 3750 if (cea_db_payload_len(db) < 5) 3751 return false; 3752 3753 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 3754 3755 return hdmi_id == HDMI_IEEE_OUI; 3756 } 3757 3758 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 3759 { 3760 unsigned int oui; 3761 3762 if (cea_db_tag(db) != VENDOR_BLOCK) 3763 return false; 3764 3765 if (cea_db_payload_len(db) < 7) 3766 return false; 3767 3768 oui = db[3] << 16 | db[2] << 8 | db[1]; 3769 3770 return oui == HDMI_FORUM_IEEE_OUI; 3771 } 3772 3773 static bool cea_db_is_y420cmdb(const u8 *db) 3774 { 3775 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3776 return false; 3777 3778 if (!cea_db_payload_len(db)) 3779 return false; 3780 3781 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 3782 return false; 3783 3784 return true; 3785 } 3786 3787 static bool cea_db_is_y420vdb(const u8 *db) 3788 { 3789 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3790 return false; 3791 3792 if (!cea_db_payload_len(db)) 3793 return false; 3794 3795 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 3796 return false; 3797 3798 return true; 3799 } 3800 3801 #define for_each_cea_db(cea, i, start, end) \ 3802 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 3803 3804 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 3805 const u8 *db) 3806 { 3807 struct drm_display_info *info = &connector->display_info; 3808 struct drm_hdmi_info *hdmi = &info->hdmi; 3809 u8 map_len = cea_db_payload_len(db) - 1; 3810 u8 count; 3811 u64 map = 0; 3812 3813 if (map_len == 0) { 3814 /* All CEA modes support ycbcr420 sampling also.*/ 3815 hdmi->y420_cmdb_map = U64_MAX; 3816 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3817 return; 3818 } 3819 3820 /* 3821 * This map indicates which of the existing CEA block modes 3822 * from VDB can support YCBCR420 output too. So if bit=0 is 3823 * set, first mode from VDB can support YCBCR420 output too. 3824 * We will parse and keep this map, before parsing VDB itself 3825 * to avoid going through the same block again and again. 3826 * 3827 * Spec is not clear about max possible size of this block. 3828 * Clamping max bitmap block size at 8 bytes. Every byte can 3829 * address 8 CEA modes, in this way this map can address 3830 * 8*8 = first 64 SVDs. 3831 */ 3832 if (WARN_ON_ONCE(map_len > 8)) 3833 map_len = 8; 3834 3835 for (count = 0; count < map_len; count++) 3836 map |= (u64)db[2 + count] << (8 * count); 3837 3838 if (map) 3839 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3840 3841 hdmi->y420_cmdb_map = map; 3842 } 3843 3844 static int 3845 add_cea_modes(struct drm_connector *connector, struct edid *edid) 3846 { 3847 const u8 *cea = drm_find_cea_extension(edid); 3848 const u8 *db, *hdmi = NULL, *video = NULL; 3849 u8 dbl, hdmi_len, video_len = 0; 3850 int modes = 0; 3851 3852 if (cea && cea_revision(cea) >= 3) { 3853 int i, start, end; 3854 3855 if (cea_db_offsets(cea, &start, &end)) 3856 return 0; 3857 3858 for_each_cea_db(cea, i, start, end) { 3859 db = &cea[i]; 3860 dbl = cea_db_payload_len(db); 3861 3862 if (cea_db_tag(db) == VIDEO_BLOCK) { 3863 video = db + 1; 3864 video_len = dbl; 3865 modes += do_cea_modes(connector, video, dbl); 3866 } else if (cea_db_is_hdmi_vsdb(db)) { 3867 hdmi = db; 3868 hdmi_len = dbl; 3869 } else if (cea_db_is_y420vdb(db)) { 3870 const u8 *vdb420 = &db[2]; 3871 3872 /* Add 4:2:0(only) modes present in EDID */ 3873 modes += do_y420vdb_modes(connector, 3874 vdb420, 3875 dbl - 1); 3876 } 3877 } 3878 } 3879 3880 /* 3881 * We parse the HDMI VSDB after having added the cea modes as we will 3882 * be patching their flags when the sink supports stereo 3D. 3883 */ 3884 if (hdmi) 3885 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 3886 video_len); 3887 3888 return modes; 3889 } 3890 3891 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3892 { 3893 const struct drm_display_mode *cea_mode; 3894 int clock1, clock2, clock; 3895 u8 vic; 3896 const char *type; 3897 3898 /* 3899 * allow 5kHz clock difference either way to account for 3900 * the 10kHz clock resolution limit of detailed timings. 3901 */ 3902 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 3903 if (drm_valid_cea_vic(vic)) { 3904 type = "CEA"; 3905 cea_mode = &edid_cea_modes[vic]; 3906 clock1 = cea_mode->clock; 3907 clock2 = cea_mode_alternate_clock(cea_mode); 3908 } else { 3909 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 3910 if (drm_valid_hdmi_vic(vic)) { 3911 type = "HDMI"; 3912 cea_mode = &edid_4k_modes[vic]; 3913 clock1 = cea_mode->clock; 3914 clock2 = hdmi_mode_alternate_clock(cea_mode); 3915 } else { 3916 return; 3917 } 3918 } 3919 3920 /* pick whichever is closest */ 3921 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3922 clock = clock1; 3923 else 3924 clock = clock2; 3925 3926 if (mode->clock == clock) 3927 return; 3928 3929 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3930 type, vic, mode->clock, clock); 3931 mode->clock = clock; 3932 } 3933 3934 static void 3935 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 3936 { 3937 u8 len = cea_db_payload_len(db); 3938 3939 if (len >= 6 && (db[6] & (1 << 7))) 3940 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 3941 if (len >= 8) { 3942 connector->latency_present[0] = db[8] >> 7; 3943 connector->latency_present[1] = (db[8] >> 6) & 1; 3944 } 3945 if (len >= 9) 3946 connector->video_latency[0] = db[9]; 3947 if (len >= 10) 3948 connector->audio_latency[0] = db[10]; 3949 if (len >= 11) 3950 connector->video_latency[1] = db[11]; 3951 if (len >= 12) 3952 connector->audio_latency[1] = db[12]; 3953 3954 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 3955 "video latency %d %d, " 3956 "audio latency %d %d\n", 3957 connector->latency_present[0], 3958 connector->latency_present[1], 3959 connector->video_latency[0], 3960 connector->video_latency[1], 3961 connector->audio_latency[0], 3962 connector->audio_latency[1]); 3963 } 3964 3965 static void 3966 monitor_name(struct detailed_timing *t, void *data) 3967 { 3968 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 3969 *(u8 **)data = t->data.other_data.data.str.str; 3970 } 3971 3972 static int get_monitor_name(struct edid *edid, char name[13]) 3973 { 3974 char *edid_name = NULL; 3975 int mnl; 3976 3977 if (!edid || !name) 3978 return 0; 3979 3980 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 3981 for (mnl = 0; edid_name && mnl < 13; mnl++) { 3982 if (edid_name[mnl] == 0x0a) 3983 break; 3984 3985 name[mnl] = edid_name[mnl]; 3986 } 3987 3988 return mnl; 3989 } 3990 3991 /** 3992 * drm_edid_get_monitor_name - fetch the monitor name from the edid 3993 * @edid: monitor EDID information 3994 * @name: pointer to a character array to hold the name of the monitor 3995 * @bufsize: The size of the name buffer (should be at least 14 chars.) 3996 * 3997 */ 3998 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 3999 { 4000 int name_length; 4001 char buf[13]; 4002 4003 if (bufsize <= 0) 4004 return; 4005 4006 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 4007 memcpy(name, buf, name_length); 4008 name[name_length] = '\0'; 4009 } 4010 EXPORT_SYMBOL(drm_edid_get_monitor_name); 4011 4012 static void clear_eld(struct drm_connector *connector) 4013 { 4014 memset(connector->eld, 0, sizeof(connector->eld)); 4015 4016 connector->latency_present[0] = false; 4017 connector->latency_present[1] = false; 4018 connector->video_latency[0] = 0; 4019 connector->audio_latency[0] = 0; 4020 connector->video_latency[1] = 0; 4021 connector->audio_latency[1] = 0; 4022 } 4023 4024 /* 4025 * drm_edid_to_eld - build ELD from EDID 4026 * @connector: connector corresponding to the HDMI/DP sink 4027 * @edid: EDID to parse 4028 * 4029 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 4030 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 4031 */ 4032 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 4033 { 4034 uint8_t *eld = connector->eld; 4035 u8 *cea; 4036 u8 *db; 4037 int total_sad_count = 0; 4038 int mnl; 4039 int dbl; 4040 4041 clear_eld(connector); 4042 4043 if (!edid) 4044 return; 4045 4046 cea = drm_find_cea_extension(edid); 4047 if (!cea) { 4048 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 4049 return; 4050 } 4051 4052 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 4053 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); 4054 4055 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT; 4056 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 4057 4058 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 4059 4060 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0]; 4061 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1]; 4062 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0]; 4063 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1]; 4064 4065 if (cea_revision(cea) >= 3) { 4066 int i, start, end; 4067 4068 if (cea_db_offsets(cea, &start, &end)) { 4069 start = 0; 4070 end = 0; 4071 } 4072 4073 for_each_cea_db(cea, i, start, end) { 4074 db = &cea[i]; 4075 dbl = cea_db_payload_len(db); 4076 4077 switch (cea_db_tag(db)) { 4078 int sad_count; 4079 4080 case AUDIO_BLOCK: 4081 /* Audio Data Block, contains SADs */ 4082 sad_count = min(dbl / 3, 15 - total_sad_count); 4083 if (sad_count >= 1) 4084 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 4085 &db[1], sad_count * 3); 4086 total_sad_count += sad_count; 4087 break; 4088 case SPEAKER_BLOCK: 4089 /* Speaker Allocation Data Block */ 4090 if (dbl >= 1) 4091 eld[DRM_ELD_SPEAKER] = db[1]; 4092 break; 4093 case VENDOR_BLOCK: 4094 /* HDMI Vendor-Specific Data Block */ 4095 if (cea_db_is_hdmi_vsdb(db)) 4096 drm_parse_hdmi_vsdb_audio(connector, db); 4097 break; 4098 default: 4099 break; 4100 } 4101 } 4102 } 4103 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 4104 4105 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 4106 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4107 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 4108 else 4109 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 4110 4111 eld[DRM_ELD_BASELINE_ELD_LEN] = 4112 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 4113 4114 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 4115 drm_eld_size(eld), total_sad_count); 4116 } 4117 4118 /** 4119 * drm_edid_to_sad - extracts SADs from EDID 4120 * @edid: EDID to parse 4121 * @sads: pointer that will be set to the extracted SADs 4122 * 4123 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 4124 * 4125 * Note: The returned pointer needs to be freed using kfree(). 4126 * 4127 * Return: The number of found SADs or negative number on error. 4128 */ 4129 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 4130 { 4131 int count = 0; 4132 int i, start, end, dbl; 4133 u8 *cea; 4134 4135 cea = drm_find_cea_extension(edid); 4136 if (!cea) { 4137 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4138 return -ENOENT; 4139 } 4140 4141 if (cea_revision(cea) < 3) { 4142 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4143 return -ENOTSUPP; 4144 } 4145 4146 if (cea_db_offsets(cea, &start, &end)) { 4147 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4148 return -EPROTO; 4149 } 4150 4151 for_each_cea_db(cea, i, start, end) { 4152 u8 *db = &cea[i]; 4153 4154 if (cea_db_tag(db) == AUDIO_BLOCK) { 4155 int j; 4156 dbl = cea_db_payload_len(db); 4157 4158 count = dbl / 3; /* SAD is 3B */ 4159 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 4160 if (!*sads) 4161 return -ENOMEM; 4162 for (j = 0; j < count; j++) { 4163 u8 *sad = &db[1 + j * 3]; 4164 4165 (*sads)[j].format = (sad[0] & 0x78) >> 3; 4166 (*sads)[j].channels = sad[0] & 0x7; 4167 (*sads)[j].freq = sad[1] & 0x7F; 4168 (*sads)[j].byte2 = sad[2]; 4169 } 4170 break; 4171 } 4172 } 4173 4174 return count; 4175 } 4176 EXPORT_SYMBOL(drm_edid_to_sad); 4177 4178 /** 4179 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 4180 * @edid: EDID to parse 4181 * @sadb: pointer to the speaker block 4182 * 4183 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 4184 * 4185 * Note: The returned pointer needs to be freed using kfree(). 4186 * 4187 * Return: The number of found Speaker Allocation Blocks or negative number on 4188 * error. 4189 */ 4190 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 4191 { 4192 int count = 0; 4193 int i, start, end, dbl; 4194 const u8 *cea; 4195 4196 cea = drm_find_cea_extension(edid); 4197 if (!cea) { 4198 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4199 return -ENOENT; 4200 } 4201 4202 if (cea_revision(cea) < 3) { 4203 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4204 return -ENOTSUPP; 4205 } 4206 4207 if (cea_db_offsets(cea, &start, &end)) { 4208 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4209 return -EPROTO; 4210 } 4211 4212 for_each_cea_db(cea, i, start, end) { 4213 const u8 *db = &cea[i]; 4214 4215 if (cea_db_tag(db) == SPEAKER_BLOCK) { 4216 dbl = cea_db_payload_len(db); 4217 4218 /* Speaker Allocation Data Block */ 4219 if (dbl == 3) { 4220 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 4221 if (!*sadb) 4222 return -ENOMEM; 4223 count = dbl; 4224 break; 4225 } 4226 } 4227 } 4228 4229 return count; 4230 } 4231 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 4232 4233 /** 4234 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 4235 * @connector: connector associated with the HDMI/DP sink 4236 * @mode: the display mode 4237 * 4238 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 4239 * the sink doesn't support audio or video. 4240 */ 4241 int drm_av_sync_delay(struct drm_connector *connector, 4242 const struct drm_display_mode *mode) 4243 { 4244 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 4245 int a, v; 4246 4247 if (!connector->latency_present[0]) 4248 return 0; 4249 if (!connector->latency_present[1]) 4250 i = 0; 4251 4252 a = connector->audio_latency[i]; 4253 v = connector->video_latency[i]; 4254 4255 /* 4256 * HDMI/DP sink doesn't support audio or video? 4257 */ 4258 if (a == 255 || v == 255) 4259 return 0; 4260 4261 /* 4262 * Convert raw EDID values to millisecond. 4263 * Treat unknown latency as 0ms. 4264 */ 4265 if (a) 4266 a = min(2 * (a - 1), 500); 4267 if (v) 4268 v = min(2 * (v - 1), 500); 4269 4270 return max(v - a, 0); 4271 } 4272 EXPORT_SYMBOL(drm_av_sync_delay); 4273 4274 /** 4275 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 4276 * @edid: monitor EDID information 4277 * 4278 * Parse the CEA extension according to CEA-861-B. 4279 * 4280 * Return: True if the monitor is HDMI, false if not or unknown. 4281 */ 4282 bool drm_detect_hdmi_monitor(struct edid *edid) 4283 { 4284 u8 *edid_ext; 4285 int i; 4286 int start_offset, end_offset; 4287 4288 edid_ext = drm_find_cea_extension(edid); 4289 if (!edid_ext) 4290 return false; 4291 4292 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4293 return false; 4294 4295 /* 4296 * Because HDMI identifier is in Vendor Specific Block, 4297 * search it from all data blocks of CEA extension. 4298 */ 4299 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4300 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 4301 return true; 4302 } 4303 4304 return false; 4305 } 4306 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 4307 4308 /** 4309 * drm_detect_monitor_audio - check monitor audio capability 4310 * @edid: EDID block to scan 4311 * 4312 * Monitor should have CEA extension block. 4313 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 4314 * audio' only. If there is any audio extension block and supported 4315 * audio format, assume at least 'basic audio' support, even if 'basic 4316 * audio' is not defined in EDID. 4317 * 4318 * Return: True if the monitor supports audio, false otherwise. 4319 */ 4320 bool drm_detect_monitor_audio(struct edid *edid) 4321 { 4322 u8 *edid_ext; 4323 int i, j; 4324 bool has_audio = false; 4325 int start_offset, end_offset; 4326 4327 edid_ext = drm_find_cea_extension(edid); 4328 if (!edid_ext) 4329 goto end; 4330 4331 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 4332 4333 if (has_audio) { 4334 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 4335 goto end; 4336 } 4337 4338 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4339 goto end; 4340 4341 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4342 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 4343 has_audio = true; 4344 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 4345 DRM_DEBUG_KMS("CEA audio format %d\n", 4346 (edid_ext[i + j] >> 3) & 0xf); 4347 goto end; 4348 } 4349 } 4350 end: 4351 return has_audio; 4352 } 4353 EXPORT_SYMBOL(drm_detect_monitor_audio); 4354 4355 /** 4356 * drm_rgb_quant_range_selectable - is RGB quantization range selectable? 4357 * @edid: EDID block to scan 4358 * 4359 * Check whether the monitor reports the RGB quantization range selection 4360 * as supported. The AVI infoframe can then be used to inform the monitor 4361 * which quantization range (full or limited) is used. 4362 * 4363 * Return: True if the RGB quantization range is selectable, false otherwise. 4364 */ 4365 bool drm_rgb_quant_range_selectable(struct edid *edid) 4366 { 4367 u8 *edid_ext; 4368 int i, start, end; 4369 4370 edid_ext = drm_find_cea_extension(edid); 4371 if (!edid_ext) 4372 return false; 4373 4374 if (cea_db_offsets(edid_ext, &start, &end)) 4375 return false; 4376 4377 for_each_cea_db(edid_ext, i, start, end) { 4378 if (cea_db_tag(&edid_ext[i]) == USE_EXTENDED_TAG && 4379 cea_db_payload_len(&edid_ext[i]) == 2 && 4380 cea_db_extended_tag(&edid_ext[i]) == 4381 EXT_VIDEO_CAPABILITY_BLOCK) { 4382 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); 4383 return edid_ext[i + 2] & EDID_CEA_VCDB_QS; 4384 } 4385 } 4386 4387 return false; 4388 } 4389 EXPORT_SYMBOL(drm_rgb_quant_range_selectable); 4390 4391 /** 4392 * drm_default_rgb_quant_range - default RGB quantization range 4393 * @mode: display mode 4394 * 4395 * Determine the default RGB quantization range for the mode, 4396 * as specified in CEA-861. 4397 * 4398 * Return: The default RGB quantization range for the mode 4399 */ 4400 enum hdmi_quantization_range 4401 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 4402 { 4403 /* All CEA modes other than VIC 1 use limited quantization range. */ 4404 return drm_match_cea_mode(mode) > 1 ? 4405 HDMI_QUANTIZATION_RANGE_LIMITED : 4406 HDMI_QUANTIZATION_RANGE_FULL; 4407 } 4408 EXPORT_SYMBOL(drm_default_rgb_quant_range); 4409 4410 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 4411 const u8 *db) 4412 { 4413 u8 dc_mask; 4414 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4415 4416 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 4417 hdmi->y420_dc_modes = dc_mask; 4418 } 4419 4420 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, 4421 const u8 *hf_vsdb) 4422 { 4423 struct drm_display_info *display = &connector->display_info; 4424 struct drm_hdmi_info *hdmi = &display->hdmi; 4425 4426 display->has_hdmi_infoframe = true; 4427 4428 if (hf_vsdb[6] & 0x80) { 4429 hdmi->scdc.supported = true; 4430 if (hf_vsdb[6] & 0x40) 4431 hdmi->scdc.read_request = true; 4432 } 4433 4434 /* 4435 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 4436 * And as per the spec, three factors confirm this: 4437 * * Availability of a HF-VSDB block in EDID (check) 4438 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 4439 * * SCDC support available (let's check) 4440 * Lets check it out. 4441 */ 4442 4443 if (hf_vsdb[5]) { 4444 /* max clock is 5000 KHz times block value */ 4445 u32 max_tmds_clock = hf_vsdb[5] * 5000; 4446 struct drm_scdc *scdc = &hdmi->scdc; 4447 4448 if (max_tmds_clock > 340000) { 4449 display->max_tmds_clock = max_tmds_clock; 4450 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 4451 display->max_tmds_clock); 4452 } 4453 4454 if (scdc->supported) { 4455 scdc->scrambling.supported = true; 4456 4457 /* Few sinks support scrambling for cloks < 340M */ 4458 if ((hf_vsdb[6] & 0x8)) 4459 scdc->scrambling.low_rates = true; 4460 } 4461 } 4462 4463 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb); 4464 } 4465 4466 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 4467 const u8 *hdmi) 4468 { 4469 struct drm_display_info *info = &connector->display_info; 4470 unsigned int dc_bpc = 0; 4471 4472 /* HDMI supports at least 8 bpc */ 4473 info->bpc = 8; 4474 4475 if (cea_db_payload_len(hdmi) < 6) 4476 return; 4477 4478 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 4479 dc_bpc = 10; 4480 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 4481 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 4482 connector->name); 4483 } 4484 4485 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 4486 dc_bpc = 12; 4487 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 4488 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 4489 connector->name); 4490 } 4491 4492 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 4493 dc_bpc = 16; 4494 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 4495 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 4496 connector->name); 4497 } 4498 4499 if (dc_bpc == 0) { 4500 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 4501 connector->name); 4502 return; 4503 } 4504 4505 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 4506 connector->name, dc_bpc); 4507 info->bpc = dc_bpc; 4508 4509 /* 4510 * Deep color support mandates RGB444 support for all video 4511 * modes and forbids YCRCB422 support for all video modes per 4512 * HDMI 1.3 spec. 4513 */ 4514 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4515 4516 /* YCRCB444 is optional according to spec. */ 4517 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 4518 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4519 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 4520 connector->name); 4521 } 4522 4523 /* 4524 * Spec says that if any deep color mode is supported at all, 4525 * then deep color 36 bit must be supported. 4526 */ 4527 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 4528 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 4529 connector->name); 4530 } 4531 } 4532 4533 static void 4534 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 4535 { 4536 struct drm_display_info *info = &connector->display_info; 4537 u8 len = cea_db_payload_len(db); 4538 4539 if (len >= 6) 4540 info->dvi_dual = db[6] & 1; 4541 if (len >= 7) 4542 info->max_tmds_clock = db[7] * 5000; 4543 4544 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 4545 "max TMDS clock %d kHz\n", 4546 info->dvi_dual, 4547 info->max_tmds_clock); 4548 4549 drm_parse_hdmi_deep_color_info(connector, db); 4550 } 4551 4552 static void drm_parse_cea_ext(struct drm_connector *connector, 4553 const struct edid *edid) 4554 { 4555 struct drm_display_info *info = &connector->display_info; 4556 const u8 *edid_ext; 4557 int i, start, end; 4558 4559 edid_ext = drm_find_cea_extension(edid); 4560 if (!edid_ext) 4561 return; 4562 4563 info->cea_rev = edid_ext[1]; 4564 4565 /* The existence of a CEA block should imply RGB support */ 4566 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4567 if (edid_ext[3] & EDID_CEA_YCRCB444) 4568 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4569 if (edid_ext[3] & EDID_CEA_YCRCB422) 4570 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4571 4572 if (cea_db_offsets(edid_ext, &start, &end)) 4573 return; 4574 4575 for_each_cea_db(edid_ext, i, start, end) { 4576 const u8 *db = &edid_ext[i]; 4577 4578 if (cea_db_is_hdmi_vsdb(db)) 4579 drm_parse_hdmi_vsdb_video(connector, db); 4580 if (cea_db_is_hdmi_forum_vsdb(db)) 4581 drm_parse_hdmi_forum_vsdb(connector, db); 4582 if (cea_db_is_y420cmdb(db)) 4583 drm_parse_y420cmdb_bitmap(connector, db); 4584 } 4585 } 4586 4587 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 4588 * all of the values which would have been set from EDID 4589 */ 4590 void 4591 drm_reset_display_info(struct drm_connector *connector) 4592 { 4593 struct drm_display_info *info = &connector->display_info; 4594 4595 info->width_mm = 0; 4596 info->height_mm = 0; 4597 4598 info->bpc = 0; 4599 info->color_formats = 0; 4600 info->cea_rev = 0; 4601 info->max_tmds_clock = 0; 4602 info->dvi_dual = false; 4603 info->has_hdmi_infoframe = false; 4604 memset(&info->hdmi, 0, sizeof(info->hdmi)); 4605 4606 info->non_desktop = 0; 4607 } 4608 4609 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) 4610 { 4611 struct drm_display_info *info = &connector->display_info; 4612 4613 u32 quirks = edid_get_quirks(edid); 4614 4615 drm_reset_display_info(connector); 4616 4617 info->width_mm = edid->width_cm * 10; 4618 info->height_mm = edid->height_cm * 10; 4619 4620 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); 4621 4622 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); 4623 4624 if (edid->revision < 3) 4625 return quirks; 4626 4627 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 4628 return quirks; 4629 4630 drm_parse_cea_ext(connector, edid); 4631 4632 /* 4633 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 4634 * 4635 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 4636 * tells us to assume 8 bpc color depth if the EDID doesn't have 4637 * extensions which tell otherwise. 4638 */ 4639 if ((info->bpc == 0) && (edid->revision < 4) && 4640 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) { 4641 info->bpc = 8; 4642 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 4643 connector->name, info->bpc); 4644 } 4645 4646 /* Only defined for 1.4 with digital displays */ 4647 if (edid->revision < 4) 4648 return quirks; 4649 4650 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 4651 case DRM_EDID_DIGITAL_DEPTH_6: 4652 info->bpc = 6; 4653 break; 4654 case DRM_EDID_DIGITAL_DEPTH_8: 4655 info->bpc = 8; 4656 break; 4657 case DRM_EDID_DIGITAL_DEPTH_10: 4658 info->bpc = 10; 4659 break; 4660 case DRM_EDID_DIGITAL_DEPTH_12: 4661 info->bpc = 12; 4662 break; 4663 case DRM_EDID_DIGITAL_DEPTH_14: 4664 info->bpc = 14; 4665 break; 4666 case DRM_EDID_DIGITAL_DEPTH_16: 4667 info->bpc = 16; 4668 break; 4669 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 4670 default: 4671 info->bpc = 0; 4672 break; 4673 } 4674 4675 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 4676 connector->name, info->bpc); 4677 4678 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 4679 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 4680 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4681 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 4682 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4683 return quirks; 4684 } 4685 4686 static int validate_displayid(u8 *displayid, int length, int idx) 4687 { 4688 int i; 4689 u8 csum = 0; 4690 struct displayid_hdr *base; 4691 4692 base = (struct displayid_hdr *)&displayid[idx]; 4693 4694 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 4695 base->rev, base->bytes, base->prod_id, base->ext_count); 4696 4697 if (base->bytes + 5 > length - idx) 4698 return -EINVAL; 4699 for (i = idx; i <= base->bytes + 5; i++) { 4700 csum += displayid[i]; 4701 } 4702 if (csum) { 4703 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum); 4704 return -EINVAL; 4705 } 4706 return 0; 4707 } 4708 4709 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 4710 struct displayid_detailed_timings_1 *timings) 4711 { 4712 struct drm_display_mode *mode; 4713 unsigned pixel_clock = (timings->pixel_clock[0] | 4714 (timings->pixel_clock[1] << 8) | 4715 (timings->pixel_clock[2] << 16)); 4716 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 4717 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 4718 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 4719 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 4720 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 4721 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 4722 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 4723 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 4724 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 4725 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 4726 mode = drm_mode_create(dev); 4727 if (!mode) 4728 return NULL; 4729 4730 mode->clock = pixel_clock * 10; 4731 mode->hdisplay = hactive; 4732 mode->hsync_start = mode->hdisplay + hsync; 4733 mode->hsync_end = mode->hsync_start + hsync_width; 4734 mode->htotal = mode->hdisplay + hblank; 4735 4736 mode->vdisplay = vactive; 4737 mode->vsync_start = mode->vdisplay + vsync; 4738 mode->vsync_end = mode->vsync_start + vsync_width; 4739 mode->vtotal = mode->vdisplay + vblank; 4740 4741 mode->flags = 0; 4742 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4743 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4744 mode->type = DRM_MODE_TYPE_DRIVER; 4745 4746 if (timings->flags & 0x80) 4747 mode->type |= DRM_MODE_TYPE_PREFERRED; 4748 mode->vrefresh = drm_mode_vrefresh(mode); 4749 drm_mode_set_name(mode); 4750 4751 return mode; 4752 } 4753 4754 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 4755 struct displayid_block *block) 4756 { 4757 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 4758 int i; 4759 int num_timings; 4760 struct drm_display_mode *newmode; 4761 int num_modes = 0; 4762 /* blocks must be multiple of 20 bytes length */ 4763 if (block->num_bytes % 20) 4764 return 0; 4765 4766 num_timings = block->num_bytes / 20; 4767 for (i = 0; i < num_timings; i++) { 4768 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 4769 4770 newmode = drm_mode_displayid_detailed(connector->dev, timings); 4771 if (!newmode) 4772 continue; 4773 4774 drm_mode_probed_add(connector, newmode); 4775 num_modes++; 4776 } 4777 return num_modes; 4778 } 4779 4780 static int add_displayid_detailed_modes(struct drm_connector *connector, 4781 struct edid *edid) 4782 { 4783 u8 *displayid; 4784 int ret; 4785 int idx = 1; 4786 int length = EDID_LENGTH; 4787 struct displayid_block *block; 4788 int num_modes = 0; 4789 4790 displayid = drm_find_displayid_extension(edid); 4791 if (!displayid) 4792 return 0; 4793 4794 ret = validate_displayid(displayid, length, idx); 4795 if (ret) 4796 return 0; 4797 4798 idx += sizeof(struct displayid_hdr); 4799 while (block = (struct displayid_block *)&displayid[idx], 4800 idx + sizeof(struct displayid_block) <= length && 4801 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 4802 block->num_bytes > 0) { 4803 idx += block->num_bytes + sizeof(struct displayid_block); 4804 switch (block->tag) { 4805 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4806 num_modes += add_displayid_detailed_1_modes(connector, block); 4807 break; 4808 } 4809 } 4810 return num_modes; 4811 } 4812 4813 /** 4814 * drm_add_edid_modes - add modes from EDID data, if available 4815 * @connector: connector we're probing 4816 * @edid: EDID data 4817 * 4818 * Add the specified modes to the connector's mode list. Also fills out the 4819 * &drm_display_info structure and ELD in @connector with any information which 4820 * can be derived from the edid. 4821 * 4822 * Return: The number of modes added or 0 if we couldn't find any. 4823 */ 4824 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 4825 { 4826 int num_modes = 0; 4827 u32 quirks; 4828 4829 if (edid == NULL) { 4830 clear_eld(connector); 4831 return 0; 4832 } 4833 if (!drm_edid_is_valid(edid)) { 4834 clear_eld(connector); 4835 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 4836 connector->name); 4837 return 0; 4838 } 4839 4840 drm_edid_to_eld(connector, edid); 4841 4842 /* 4843 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 4844 * To avoid multiple parsing of same block, lets parse that map 4845 * from sink info, before parsing CEA modes. 4846 */ 4847 quirks = drm_add_display_info(connector, edid); 4848 4849 /* 4850 * EDID spec says modes should be preferred in this order: 4851 * - preferred detailed mode 4852 * - other detailed modes from base block 4853 * - detailed modes from extension blocks 4854 * - CVT 3-byte code modes 4855 * - standard timing codes 4856 * - established timing codes 4857 * - modes inferred from GTF or CVT range information 4858 * 4859 * We get this pretty much right. 4860 * 4861 * XXX order for additional mode types in extension blocks? 4862 */ 4863 num_modes += add_detailed_modes(connector, edid, quirks); 4864 num_modes += add_cvt_modes(connector, edid); 4865 num_modes += add_standard_modes(connector, edid); 4866 num_modes += add_established_modes(connector, edid); 4867 num_modes += add_cea_modes(connector, edid); 4868 num_modes += add_alternate_cea_modes(connector, edid); 4869 num_modes += add_displayid_detailed_modes(connector, edid); 4870 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 4871 num_modes += add_inferred_modes(connector, edid); 4872 4873 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 4874 edid_fixup_preferred(connector, quirks); 4875 4876 if (quirks & EDID_QUIRK_FORCE_6BPC) 4877 connector->display_info.bpc = 6; 4878 4879 if (quirks & EDID_QUIRK_FORCE_8BPC) 4880 connector->display_info.bpc = 8; 4881 4882 if (quirks & EDID_QUIRK_FORCE_10BPC) 4883 connector->display_info.bpc = 10; 4884 4885 if (quirks & EDID_QUIRK_FORCE_12BPC) 4886 connector->display_info.bpc = 12; 4887 4888 return num_modes; 4889 } 4890 EXPORT_SYMBOL(drm_add_edid_modes); 4891 4892 /** 4893 * drm_add_modes_noedid - add modes for the connectors without EDID 4894 * @connector: connector we're probing 4895 * @hdisplay: the horizontal display limit 4896 * @vdisplay: the vertical display limit 4897 * 4898 * Add the specified modes to the connector's mode list. Only when the 4899 * hdisplay/vdisplay is not beyond the given limit, it will be added. 4900 * 4901 * Return: The number of modes added or 0 if we couldn't find any. 4902 */ 4903 int drm_add_modes_noedid(struct drm_connector *connector, 4904 int hdisplay, int vdisplay) 4905 { 4906 int i, count, num_modes = 0; 4907 struct drm_display_mode *mode; 4908 struct drm_device *dev = connector->dev; 4909 4910 count = ARRAY_SIZE(drm_dmt_modes); 4911 if (hdisplay < 0) 4912 hdisplay = 0; 4913 if (vdisplay < 0) 4914 vdisplay = 0; 4915 4916 for (i = 0; i < count; i++) { 4917 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 4918 if (hdisplay && vdisplay) { 4919 /* 4920 * Only when two are valid, they will be used to check 4921 * whether the mode should be added to the mode list of 4922 * the connector. 4923 */ 4924 if (ptr->hdisplay > hdisplay || 4925 ptr->vdisplay > vdisplay) 4926 continue; 4927 } 4928 if (drm_mode_vrefresh(ptr) > 61) 4929 continue; 4930 mode = drm_mode_duplicate(dev, ptr); 4931 if (mode) { 4932 drm_mode_probed_add(connector, mode); 4933 num_modes++; 4934 } 4935 } 4936 return num_modes; 4937 } 4938 EXPORT_SYMBOL(drm_add_modes_noedid); 4939 4940 /** 4941 * drm_set_preferred_mode - Sets the preferred mode of a connector 4942 * @connector: connector whose mode list should be processed 4943 * @hpref: horizontal resolution of preferred mode 4944 * @vpref: vertical resolution of preferred mode 4945 * 4946 * Marks a mode as preferred if it matches the resolution specified by @hpref 4947 * and @vpref. 4948 */ 4949 void drm_set_preferred_mode(struct drm_connector *connector, 4950 int hpref, int vpref) 4951 { 4952 struct drm_display_mode *mode; 4953 4954 list_for_each_entry(mode, &connector->probed_modes, head) { 4955 if (mode->hdisplay == hpref && 4956 mode->vdisplay == vpref) 4957 mode->type |= DRM_MODE_TYPE_PREFERRED; 4958 } 4959 } 4960 EXPORT_SYMBOL(drm_set_preferred_mode); 4961 4962 /** 4963 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 4964 * data from a DRM display mode 4965 * @frame: HDMI AVI infoframe 4966 * @mode: DRM display mode 4967 * @is_hdmi2_sink: Sink is HDMI 2.0 compliant 4968 * 4969 * Return: 0 on success or a negative error code on failure. 4970 */ 4971 int 4972 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 4973 const struct drm_display_mode *mode, 4974 bool is_hdmi2_sink) 4975 { 4976 enum hdmi_picture_aspect picture_aspect; 4977 int err; 4978 4979 if (!frame || !mode) 4980 return -EINVAL; 4981 4982 err = hdmi_avi_infoframe_init(frame); 4983 if (err < 0) 4984 return err; 4985 4986 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 4987 frame->pixel_repeat = 1; 4988 4989 frame->video_code = drm_match_cea_mode(mode); 4990 4991 /* 4992 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 4993 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 4994 * have to make sure we dont break HDMI 1.4 sinks. 4995 */ 4996 if (!is_hdmi2_sink && frame->video_code > 64) 4997 frame->video_code = 0; 4998 4999 /* 5000 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5001 * we should send its VIC in vendor infoframes, else send the 5002 * VIC in AVI infoframes. Lets check if this mode is present in 5003 * HDMI 1.4b 4K modes 5004 */ 5005 if (frame->video_code) { 5006 u8 vendor_if_vic = drm_match_hdmi_mode(mode); 5007 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK; 5008 5009 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d) 5010 frame->video_code = 0; 5011 } 5012 5013 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5014 5015 /* 5016 * As some drivers don't support atomic, we can't use connector state. 5017 * So just initialize the frame with default values, just the same way 5018 * as it's done with other properties here. 5019 */ 5020 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 5021 frame->itc = 0; 5022 5023 /* 5024 * Populate picture aspect ratio from either 5025 * user input (if specified) or from the CEA mode list. 5026 */ 5027 picture_aspect = mode->picture_aspect_ratio; 5028 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) 5029 picture_aspect = drm_get_cea_aspect_ratio(frame->video_code); 5030 5031 /* 5032 * The infoframe can't convey anything but none, 4:3 5033 * and 16:9, so if the user has asked for anything else 5034 * we can only satisfy it by specifying the right VIC. 5035 */ 5036 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 5037 if (picture_aspect != 5038 drm_get_cea_aspect_ratio(frame->video_code)) 5039 return -EINVAL; 5040 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5041 } 5042 5043 frame->picture_aspect = picture_aspect; 5044 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5045 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5046 5047 return 0; 5048 } 5049 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 5050 5051 /** 5052 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 5053 * quantization range information 5054 * @frame: HDMI AVI infoframe 5055 * @mode: DRM display mode 5056 * @rgb_quant_range: RGB quantization range (Q) 5057 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS) 5058 * @is_hdmi2_sink: HDMI 2.0 sink, which has different default recommendations 5059 * 5060 * Note that @is_hdmi2_sink can be derived by looking at the 5061 * &drm_scdc.supported flag stored in &drm_hdmi_info.scdc, 5062 * &drm_display_info.hdmi, which can be found in &drm_connector.display_info. 5063 */ 5064 void 5065 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 5066 const struct drm_display_mode *mode, 5067 enum hdmi_quantization_range rgb_quant_range, 5068 bool rgb_quant_range_selectable, 5069 bool is_hdmi2_sink) 5070 { 5071 /* 5072 * CEA-861: 5073 * "A Source shall not send a non-zero Q value that does not correspond 5074 * to the default RGB Quantization Range for the transmitted Picture 5075 * unless the Sink indicates support for the Q bit in a Video 5076 * Capabilities Data Block." 5077 * 5078 * HDMI 2.0 recommends sending non-zero Q when it does match the 5079 * default RGB quantization range for the mode, even when QS=0. 5080 */ 5081 if (rgb_quant_range_selectable || 5082 rgb_quant_range == drm_default_rgb_quant_range(mode)) 5083 frame->quantization_range = rgb_quant_range; 5084 else 5085 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 5086 5087 /* 5088 * CEA-861-F: 5089 * "When transmitting any RGB colorimetry, the Source should set the 5090 * YQ-field to match the RGB Quantization Range being transmitted 5091 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 5092 * set YQ=1) and the Sink shall ignore the YQ-field." 5093 * 5094 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 5095 * by non-zero YQ when receiving RGB. There doesn't seem to be any 5096 * good way to tell which version of CEA-861 the sink supports, so 5097 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 5098 * on on CEA-861-F. 5099 */ 5100 if (!is_hdmi2_sink || 5101 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 5102 frame->ycc_quantization_range = 5103 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 5104 else 5105 frame->ycc_quantization_range = 5106 HDMI_YCC_QUANTIZATION_RANGE_FULL; 5107 } 5108 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 5109 5110 static enum hdmi_3d_structure 5111 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5112 { 5113 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5114 5115 switch (layout) { 5116 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5117 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5118 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5119 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5120 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5121 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5122 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5123 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5124 case DRM_MODE_FLAG_3D_L_DEPTH: 5125 return HDMI_3D_STRUCTURE_L_DEPTH; 5126 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5127 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5128 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5129 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5130 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5131 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5132 default: 5133 return HDMI_3D_STRUCTURE_INVALID; 5134 } 5135 } 5136 5137 /** 5138 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 5139 * data from a DRM display mode 5140 * @frame: HDMI vendor infoframe 5141 * @connector: the connector 5142 * @mode: DRM display mode 5143 * 5144 * Note that there's is a need to send HDMI vendor infoframes only when using a 5145 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 5146 * function will return -EINVAL, error that can be safely ignored. 5147 * 5148 * Return: 0 on success or a negative error code on failure. 5149 */ 5150 int 5151 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5152 struct drm_connector *connector, 5153 const struct drm_display_mode *mode) 5154 { 5155 /* 5156 * FIXME: sil-sii8620 doesn't have a connector around when 5157 * we need one, so we have to be prepared for a NULL connector. 5158 */ 5159 bool has_hdmi_infoframe = connector ? 5160 connector->display_info.has_hdmi_infoframe : false; 5161 int err; 5162 u32 s3d_flags; 5163 u8 vic; 5164 5165 if (!frame || !mode) 5166 return -EINVAL; 5167 5168 if (!has_hdmi_infoframe) 5169 return -EINVAL; 5170 5171 vic = drm_match_hdmi_mode(mode); 5172 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 5173 5174 /* 5175 * Even if it's not absolutely necessary to send the infoframe 5176 * (ie.vic==0 and s3d_struct==0) we will still send it if we 5177 * know that the sink can handle it. This is based on a 5178 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 5179 * have trouble realizing that they shuld switch from 3D to 2D 5180 * mode if the source simply stops sending the infoframe when 5181 * it wants to switch from 3D to 2D. 5182 */ 5183 5184 if (vic && s3d_flags) 5185 return -EINVAL; 5186 5187 err = hdmi_vendor_infoframe_init(frame); 5188 if (err < 0) 5189 return err; 5190 5191 frame->vic = vic; 5192 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5193 5194 return 0; 5195 } 5196 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 5197 5198 static int drm_parse_tiled_block(struct drm_connector *connector, 5199 struct displayid_block *block) 5200 { 5201 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 5202 u16 w, h; 5203 u8 tile_v_loc, tile_h_loc; 5204 u8 num_v_tile, num_h_tile; 5205 struct drm_tile_group *tg; 5206 5207 w = tile->tile_size[0] | tile->tile_size[1] << 8; 5208 h = tile->tile_size[2] | tile->tile_size[3] << 8; 5209 5210 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 5211 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 5212 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 5213 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 5214 5215 connector->has_tile = true; 5216 if (tile->tile_cap & 0x80) 5217 connector->tile_is_single_monitor = true; 5218 5219 connector->num_h_tile = num_h_tile + 1; 5220 connector->num_v_tile = num_v_tile + 1; 5221 connector->tile_h_loc = tile_h_loc; 5222 connector->tile_v_loc = tile_v_loc; 5223 connector->tile_h_size = w + 1; 5224 connector->tile_v_size = h + 1; 5225 5226 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 5227 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 5228 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 5229 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 5230 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 5231 5232 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 5233 if (!tg) { 5234 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 5235 } 5236 if (!tg) 5237 return -ENOMEM; 5238 5239 if (connector->tile_group != tg) { 5240 /* if we haven't got a pointer, 5241 take the reference, drop ref to old tile group */ 5242 if (connector->tile_group) { 5243 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5244 } 5245 connector->tile_group = tg; 5246 } else 5247 /* if same tile group, then release the ref we just took. */ 5248 drm_mode_put_tile_group(connector->dev, tg); 5249 return 0; 5250 } 5251 5252 static int drm_parse_display_id(struct drm_connector *connector, 5253 u8 *displayid, int length, 5254 bool is_edid_extension) 5255 { 5256 /* if this is an EDID extension the first byte will be 0x70 */ 5257 int idx = 0; 5258 struct displayid_block *block; 5259 int ret; 5260 5261 if (is_edid_extension) 5262 idx = 1; 5263 5264 ret = validate_displayid(displayid, length, idx); 5265 if (ret) 5266 return ret; 5267 5268 idx += sizeof(struct displayid_hdr); 5269 while (block = (struct displayid_block *)&displayid[idx], 5270 idx + sizeof(struct displayid_block) <= length && 5271 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 5272 block->num_bytes > 0) { 5273 idx += block->num_bytes + sizeof(struct displayid_block); 5274 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", 5275 block->tag, block->rev, block->num_bytes); 5276 5277 switch (block->tag) { 5278 case DATA_BLOCK_TILED_DISPLAY: 5279 ret = drm_parse_tiled_block(connector, block); 5280 if (ret) 5281 return ret; 5282 break; 5283 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5284 /* handled in mode gathering code. */ 5285 break; 5286 case DATA_BLOCK_CTA: 5287 /* handled in the cea parser code. */ 5288 break; 5289 default: 5290 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); 5291 break; 5292 } 5293 } 5294 return 0; 5295 } 5296 5297 static void drm_get_displayid(struct drm_connector *connector, 5298 struct edid *edid) 5299 { 5300 void *displayid = NULL; 5301 int ret; 5302 connector->has_tile = false; 5303 displayid = drm_find_displayid_extension(edid); 5304 if (!displayid) { 5305 /* drop reference to any tile group we had */ 5306 goto out_drop_ref; 5307 } 5308 5309 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true); 5310 if (ret < 0) 5311 goto out_drop_ref; 5312 if (!connector->has_tile) 5313 goto out_drop_ref; 5314 return; 5315 out_drop_ref: 5316 if (connector->tile_group) { 5317 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5318 connector->tile_group = NULL; 5319 } 5320 return; 5321 } 5322