1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/hdmi.h> 32 #include <linux/i2c.h> 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/slab.h> 36 #include <linux/vga_switcheroo.h> 37 38 #include <drm/drm_displayid.h> 39 #include <drm/drm_drv.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_encoder.h> 42 #include <drm/drm_print.h> 43 #include <drm/drm_scdc_helper.h> 44 45 #include "drm_crtc_internal.h" 46 47 #define version_greater(edid, maj, min) \ 48 (((edid)->version > (maj)) || \ 49 ((edid)->version == (maj) && (edid)->revision > (min))) 50 51 #define EDID_EST_TIMINGS 16 52 #define EDID_STD_TIMINGS 8 53 #define EDID_DETAILED_TIMINGS 4 54 55 /* 56 * EDID blocks out in the wild have a variety of bugs, try to collect 57 * them here (note that userspace may work around broken monitors first, 58 * but fixes should make their way here so that the kernel "just works" 59 * on as many displays as possible). 60 */ 61 62 /* First detailed mode wrong, use largest 60Hz mode */ 63 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 64 /* Reported 135MHz pixel clock is too high, needs adjustment */ 65 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 66 /* Prefer the largest mode at 75 Hz */ 67 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 68 /* Detail timing is in cm not mm */ 69 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 70 /* Detailed timing descriptors have bogus size values, so just take the 71 * maximum size and use that. 72 */ 73 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 74 /* use +hsync +vsync for detailed mode */ 75 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 76 /* Force reduced-blanking timings for detailed modes */ 77 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 78 /* Force 8bpc */ 79 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 80 /* Force 12bpc */ 81 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 82 /* Force 6bpc */ 83 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 84 /* Force 10bpc */ 85 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 86 /* Non desktop display (i.e. HMD) */ 87 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 88 89 struct detailed_mode_closure { 90 struct drm_connector *connector; 91 struct edid *edid; 92 bool preferred; 93 u32 quirks; 94 int modes; 95 }; 96 97 #define LEVEL_DMT 0 98 #define LEVEL_GTF 1 99 #define LEVEL_GTF2 2 100 #define LEVEL_CVT 3 101 102 static const struct edid_quirk { 103 char vendor[4]; 104 int product_id; 105 u32 quirks; 106 } edid_quirk_list[] = { 107 /* Acer AL1706 */ 108 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 109 /* Acer F51 */ 110 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 111 112 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 113 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 114 115 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 116 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC }, 117 118 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 119 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC }, 120 121 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 122 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC }, 123 124 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 125 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC }, 126 127 /* Belinea 10 15 55 */ 128 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 129 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 130 131 /* Envision Peripherals, Inc. EN-7100e */ 132 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 133 /* Envision EN2028 */ 134 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 135 136 /* Funai Electronics PM36B */ 137 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 138 EDID_QUIRK_DETAILED_IN_CM }, 139 140 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 141 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 142 143 /* LG Philips LCD LP154W01-A5 */ 144 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 145 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 146 147 /* Samsung SyncMaster 205BW. Note: irony */ 148 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 149 /* Samsung SyncMaster 22[5-6]BW */ 150 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 151 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 152 153 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 154 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 155 156 /* ViewSonic VA2026w */ 157 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 158 159 /* Medion MD 30217 PG */ 160 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 161 162 /* Lenovo G50 */ 163 { "SDC", 18514, EDID_QUIRK_FORCE_6BPC }, 164 165 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 166 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 167 168 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 169 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 170 171 /* Valve Index Headset */ 172 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP }, 173 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP }, 174 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP }, 175 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP }, 176 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP }, 177 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP }, 178 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP }, 179 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP }, 180 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP }, 181 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP }, 182 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP }, 183 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP }, 184 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP }, 185 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP }, 186 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP }, 187 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP }, 188 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP }, 189 190 /* HTC Vive and Vive Pro VR Headsets */ 191 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP }, 192 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP }, 193 194 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 195 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP }, 196 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP }, 197 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP }, 198 { "OVR", 0x0012, EDID_QUIRK_NON_DESKTOP }, 199 200 /* Windows Mixed Reality Headsets */ 201 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 202 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP }, 203 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP }, 204 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP }, 205 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP }, 206 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 207 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP }, 208 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP }, 209 210 /* Sony PlayStation VR Headset */ 211 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP }, 212 213 /* Sensics VR Headsets */ 214 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP }, 215 216 /* OSVR HDK and HDK2 VR Headsets */ 217 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP }, 218 }; 219 220 /* 221 * Autogenerated from the DMT spec. 222 * This table is copied from xfree86/modes/xf86EdidModes.c. 223 */ 224 static const struct drm_display_mode drm_dmt_modes[] = { 225 /* 0x01 - 640x350@85Hz */ 226 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 227 736, 832, 0, 350, 382, 385, 445, 0, 228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 229 /* 0x02 - 640x400@85Hz */ 230 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 231 736, 832, 0, 400, 401, 404, 445, 0, 232 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 233 /* 0x03 - 720x400@85Hz */ 234 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 235 828, 936, 0, 400, 401, 404, 446, 0, 236 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 237 /* 0x04 - 640x480@60Hz */ 238 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 239 752, 800, 0, 480, 490, 492, 525, 0, 240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 241 /* 0x05 - 640x480@72Hz */ 242 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 243 704, 832, 0, 480, 489, 492, 520, 0, 244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 245 /* 0x06 - 640x480@75Hz */ 246 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 247 720, 840, 0, 480, 481, 484, 500, 0, 248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 249 /* 0x07 - 640x480@85Hz */ 250 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 251 752, 832, 0, 480, 481, 484, 509, 0, 252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 253 /* 0x08 - 800x600@56Hz */ 254 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 255 896, 1024, 0, 600, 601, 603, 625, 0, 256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 257 /* 0x09 - 800x600@60Hz */ 258 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 259 968, 1056, 0, 600, 601, 605, 628, 0, 260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 261 /* 0x0a - 800x600@72Hz */ 262 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 263 976, 1040, 0, 600, 637, 643, 666, 0, 264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 265 /* 0x0b - 800x600@75Hz */ 266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 267 896, 1056, 0, 600, 601, 604, 625, 0, 268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 269 /* 0x0c - 800x600@85Hz */ 270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 271 896, 1048, 0, 600, 601, 604, 631, 0, 272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 273 /* 0x0d - 800x600@120Hz RB */ 274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 275 880, 960, 0, 600, 603, 607, 636, 0, 276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 277 /* 0x0e - 848x480@60Hz */ 278 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 279 976, 1088, 0, 480, 486, 494, 517, 0, 280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 281 /* 0x0f - 1024x768@43Hz, interlace */ 282 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 283 1208, 1264, 0, 768, 768, 776, 817, 0, 284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 285 DRM_MODE_FLAG_INTERLACE) }, 286 /* 0x10 - 1024x768@60Hz */ 287 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 288 1184, 1344, 0, 768, 771, 777, 806, 0, 289 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 290 /* 0x11 - 1024x768@70Hz */ 291 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 292 1184, 1328, 0, 768, 771, 777, 806, 0, 293 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 294 /* 0x12 - 1024x768@75Hz */ 295 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 296 1136, 1312, 0, 768, 769, 772, 800, 0, 297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 298 /* 0x13 - 1024x768@85Hz */ 299 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 300 1168, 1376, 0, 768, 769, 772, 808, 0, 301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 302 /* 0x14 - 1024x768@120Hz RB */ 303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 304 1104, 1184, 0, 768, 771, 775, 813, 0, 305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 306 /* 0x15 - 1152x864@75Hz */ 307 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 308 1344, 1600, 0, 864, 865, 868, 900, 0, 309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 310 /* 0x55 - 1280x720@60Hz */ 311 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 312 1430, 1650, 0, 720, 725, 730, 750, 0, 313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 314 /* 0x16 - 1280x768@60Hz RB */ 315 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 316 1360, 1440, 0, 768, 771, 778, 790, 0, 317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 318 /* 0x17 - 1280x768@60Hz */ 319 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 320 1472, 1664, 0, 768, 771, 778, 798, 0, 321 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 322 /* 0x18 - 1280x768@75Hz */ 323 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 324 1488, 1696, 0, 768, 771, 778, 805, 0, 325 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 326 /* 0x19 - 1280x768@85Hz */ 327 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 328 1496, 1712, 0, 768, 771, 778, 809, 0, 329 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 330 /* 0x1a - 1280x768@120Hz RB */ 331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 332 1360, 1440, 0, 768, 771, 778, 813, 0, 333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 334 /* 0x1b - 1280x800@60Hz RB */ 335 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 336 1360, 1440, 0, 800, 803, 809, 823, 0, 337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 338 /* 0x1c - 1280x800@60Hz */ 339 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 340 1480, 1680, 0, 800, 803, 809, 831, 0, 341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 342 /* 0x1d - 1280x800@75Hz */ 343 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 344 1488, 1696, 0, 800, 803, 809, 838, 0, 345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 346 /* 0x1e - 1280x800@85Hz */ 347 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 348 1496, 1712, 0, 800, 803, 809, 843, 0, 349 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 350 /* 0x1f - 1280x800@120Hz RB */ 351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 352 1360, 1440, 0, 800, 803, 809, 847, 0, 353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 354 /* 0x20 - 1280x960@60Hz */ 355 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 356 1488, 1800, 0, 960, 961, 964, 1000, 0, 357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 358 /* 0x21 - 1280x960@85Hz */ 359 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 360 1504, 1728, 0, 960, 961, 964, 1011, 0, 361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 362 /* 0x22 - 1280x960@120Hz RB */ 363 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 364 1360, 1440, 0, 960, 963, 967, 1017, 0, 365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 366 /* 0x23 - 1280x1024@60Hz */ 367 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 368 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 370 /* 0x24 - 1280x1024@75Hz */ 371 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 372 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 374 /* 0x25 - 1280x1024@85Hz */ 375 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 376 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 378 /* 0x26 - 1280x1024@120Hz RB */ 379 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 380 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 382 /* 0x27 - 1360x768@60Hz */ 383 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 384 1536, 1792, 0, 768, 771, 777, 795, 0, 385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 386 /* 0x28 - 1360x768@120Hz RB */ 387 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 388 1440, 1520, 0, 768, 771, 776, 813, 0, 389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 390 /* 0x51 - 1366x768@60Hz */ 391 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 392 1579, 1792, 0, 768, 771, 774, 798, 0, 393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 394 /* 0x56 - 1366x768@60Hz */ 395 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 396 1436, 1500, 0, 768, 769, 772, 800, 0, 397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 398 /* 0x29 - 1400x1050@60Hz RB */ 399 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 400 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 402 /* 0x2a - 1400x1050@60Hz */ 403 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 404 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 405 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 406 /* 0x2b - 1400x1050@75Hz */ 407 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 408 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 409 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 410 /* 0x2c - 1400x1050@85Hz */ 411 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 412 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 414 /* 0x2d - 1400x1050@120Hz RB */ 415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 416 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 418 /* 0x2e - 1440x900@60Hz RB */ 419 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 420 1520, 1600, 0, 900, 903, 909, 926, 0, 421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 422 /* 0x2f - 1440x900@60Hz */ 423 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 424 1672, 1904, 0, 900, 903, 909, 934, 0, 425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 426 /* 0x30 - 1440x900@75Hz */ 427 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 428 1688, 1936, 0, 900, 903, 909, 942, 0, 429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 430 /* 0x31 - 1440x900@85Hz */ 431 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 432 1696, 1952, 0, 900, 903, 909, 948, 0, 433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 434 /* 0x32 - 1440x900@120Hz RB */ 435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 436 1520, 1600, 0, 900, 903, 909, 953, 0, 437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 438 /* 0x53 - 1600x900@60Hz */ 439 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 440 1704, 1800, 0, 900, 901, 904, 1000, 0, 441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 442 /* 0x33 - 1600x1200@60Hz */ 443 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 444 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 446 /* 0x34 - 1600x1200@65Hz */ 447 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 448 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 450 /* 0x35 - 1600x1200@70Hz */ 451 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 452 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 454 /* 0x36 - 1600x1200@75Hz */ 455 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 456 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 458 /* 0x37 - 1600x1200@85Hz */ 459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 462 /* 0x38 - 1600x1200@120Hz RB */ 463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 464 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 466 /* 0x39 - 1680x1050@60Hz RB */ 467 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 468 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 470 /* 0x3a - 1680x1050@60Hz */ 471 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 472 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 474 /* 0x3b - 1680x1050@75Hz */ 475 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 476 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 477 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 478 /* 0x3c - 1680x1050@85Hz */ 479 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 480 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 482 /* 0x3d - 1680x1050@120Hz RB */ 483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 484 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 486 /* 0x3e - 1792x1344@60Hz */ 487 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 488 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 490 /* 0x3f - 1792x1344@75Hz */ 491 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 492 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 494 /* 0x40 - 1792x1344@120Hz RB */ 495 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 496 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 498 /* 0x41 - 1856x1392@60Hz */ 499 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 500 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 502 /* 0x42 - 1856x1392@75Hz */ 503 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 504 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 506 /* 0x43 - 1856x1392@120Hz RB */ 507 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 508 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 510 /* 0x52 - 1920x1080@60Hz */ 511 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 512 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 514 /* 0x44 - 1920x1200@60Hz RB */ 515 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 516 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 518 /* 0x45 - 1920x1200@60Hz */ 519 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 520 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 522 /* 0x46 - 1920x1200@75Hz */ 523 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 524 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 526 /* 0x47 - 1920x1200@85Hz */ 527 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 528 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 530 /* 0x48 - 1920x1200@120Hz RB */ 531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 532 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 534 /* 0x49 - 1920x1440@60Hz */ 535 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 536 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 538 /* 0x4a - 1920x1440@75Hz */ 539 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 540 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 541 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 542 /* 0x4b - 1920x1440@120Hz RB */ 543 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 544 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 546 /* 0x54 - 2048x1152@60Hz */ 547 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 548 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 550 /* 0x4c - 2560x1600@60Hz RB */ 551 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 552 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 554 /* 0x4d - 2560x1600@60Hz */ 555 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 556 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 558 /* 0x4e - 2560x1600@75Hz */ 559 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 560 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 561 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 562 /* 0x4f - 2560x1600@85Hz */ 563 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 564 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 565 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 566 /* 0x50 - 2560x1600@120Hz RB */ 567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 568 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 570 /* 0x57 - 4096x2160@60Hz RB */ 571 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 572 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 574 /* 0x58 - 4096x2160@59.94Hz RB */ 575 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 576 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 578 }; 579 580 /* 581 * These more or less come from the DMT spec. The 720x400 modes are 582 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 583 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 584 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 585 * mode. 586 * 587 * The DMT modes have been fact-checked; the rest are mild guesses. 588 */ 589 static const struct drm_display_mode edid_est_modes[] = { 590 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 591 968, 1056, 0, 600, 601, 605, 628, 0, 592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 593 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 594 896, 1024, 0, 600, 601, 603, 625, 0, 595 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 596 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 597 720, 840, 0, 480, 481, 484, 500, 0, 598 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 599 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 600 704, 832, 0, 480, 489, 492, 520, 0, 601 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 602 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 603 768, 864, 0, 480, 483, 486, 525, 0, 604 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 605 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 606 752, 800, 0, 480, 490, 492, 525, 0, 607 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 608 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 609 846, 900, 0, 400, 421, 423, 449, 0, 610 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 611 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 612 846, 900, 0, 400, 412, 414, 449, 0, 613 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 614 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 615 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 616 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 617 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 618 1136, 1312, 0, 768, 769, 772, 800, 0, 619 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 620 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 621 1184, 1328, 0, 768, 771, 777, 806, 0, 622 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 623 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 624 1184, 1344, 0, 768, 771, 777, 806, 0, 625 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 626 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 627 1208, 1264, 0, 768, 768, 776, 817, 0, 628 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 629 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 630 928, 1152, 0, 624, 625, 628, 667, 0, 631 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 632 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 633 896, 1056, 0, 600, 601, 604, 625, 0, 634 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 635 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 636 976, 1040, 0, 600, 637, 643, 666, 0, 637 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 638 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 639 1344, 1600, 0, 864, 865, 868, 900, 0, 640 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 641 }; 642 643 struct minimode { 644 short w; 645 short h; 646 short r; 647 short rb; 648 }; 649 650 static const struct minimode est3_modes[] = { 651 /* byte 6 */ 652 { 640, 350, 85, 0 }, 653 { 640, 400, 85, 0 }, 654 { 720, 400, 85, 0 }, 655 { 640, 480, 85, 0 }, 656 { 848, 480, 60, 0 }, 657 { 800, 600, 85, 0 }, 658 { 1024, 768, 85, 0 }, 659 { 1152, 864, 75, 0 }, 660 /* byte 7 */ 661 { 1280, 768, 60, 1 }, 662 { 1280, 768, 60, 0 }, 663 { 1280, 768, 75, 0 }, 664 { 1280, 768, 85, 0 }, 665 { 1280, 960, 60, 0 }, 666 { 1280, 960, 85, 0 }, 667 { 1280, 1024, 60, 0 }, 668 { 1280, 1024, 85, 0 }, 669 /* byte 8 */ 670 { 1360, 768, 60, 0 }, 671 { 1440, 900, 60, 1 }, 672 { 1440, 900, 60, 0 }, 673 { 1440, 900, 75, 0 }, 674 { 1440, 900, 85, 0 }, 675 { 1400, 1050, 60, 1 }, 676 { 1400, 1050, 60, 0 }, 677 { 1400, 1050, 75, 0 }, 678 /* byte 9 */ 679 { 1400, 1050, 85, 0 }, 680 { 1680, 1050, 60, 1 }, 681 { 1680, 1050, 60, 0 }, 682 { 1680, 1050, 75, 0 }, 683 { 1680, 1050, 85, 0 }, 684 { 1600, 1200, 60, 0 }, 685 { 1600, 1200, 65, 0 }, 686 { 1600, 1200, 70, 0 }, 687 /* byte 10 */ 688 { 1600, 1200, 75, 0 }, 689 { 1600, 1200, 85, 0 }, 690 { 1792, 1344, 60, 0 }, 691 { 1792, 1344, 75, 0 }, 692 { 1856, 1392, 60, 0 }, 693 { 1856, 1392, 75, 0 }, 694 { 1920, 1200, 60, 1 }, 695 { 1920, 1200, 60, 0 }, 696 /* byte 11 */ 697 { 1920, 1200, 75, 0 }, 698 { 1920, 1200, 85, 0 }, 699 { 1920, 1440, 60, 0 }, 700 { 1920, 1440, 75, 0 }, 701 }; 702 703 static const struct minimode extra_modes[] = { 704 { 1024, 576, 60, 0 }, 705 { 1366, 768, 60, 0 }, 706 { 1600, 900, 60, 0 }, 707 { 1680, 945, 60, 0 }, 708 { 1920, 1080, 60, 0 }, 709 { 2048, 1152, 60, 0 }, 710 { 2048, 1536, 60, 0 }, 711 }; 712 713 /* 714 * From CEA/CTA-861 spec. 715 * 716 * Do not access directly, instead always use cea_mode_for_vic(). 717 */ 718 static const struct drm_display_mode edid_cea_modes_1[] = { 719 /* 1 - 640x480@60Hz 4:3 */ 720 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 721 752, 800, 0, 480, 490, 492, 525, 0, 722 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 723 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 724 /* 2 - 720x480@60Hz 4:3 */ 725 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 726 798, 858, 0, 480, 489, 495, 525, 0, 727 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 728 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 729 /* 3 - 720x480@60Hz 16:9 */ 730 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 731 798, 858, 0, 480, 489, 495, 525, 0, 732 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 733 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 734 /* 4 - 1280x720@60Hz 16:9 */ 735 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 736 1430, 1650, 0, 720, 725, 730, 750, 0, 737 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 738 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 739 /* 5 - 1920x1080i@60Hz 16:9 */ 740 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 741 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 742 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 743 DRM_MODE_FLAG_INTERLACE), 744 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 745 /* 6 - 720(1440)x480i@60Hz 4:3 */ 746 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 747 801, 858, 0, 480, 488, 494, 525, 0, 748 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 749 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 750 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 751 /* 7 - 720(1440)x480i@60Hz 16:9 */ 752 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 753 801, 858, 0, 480, 488, 494, 525, 0, 754 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 755 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 756 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 757 /* 8 - 720(1440)x240@60Hz 4:3 */ 758 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 759 801, 858, 0, 240, 244, 247, 262, 0, 760 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 761 DRM_MODE_FLAG_DBLCLK), 762 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 763 /* 9 - 720(1440)x240@60Hz 16:9 */ 764 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 765 801, 858, 0, 240, 244, 247, 262, 0, 766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 767 DRM_MODE_FLAG_DBLCLK), 768 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 769 /* 10 - 2880x480i@60Hz 4:3 */ 770 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 771 3204, 3432, 0, 480, 488, 494, 525, 0, 772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 773 DRM_MODE_FLAG_INTERLACE), 774 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 775 /* 11 - 2880x480i@60Hz 16:9 */ 776 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 777 3204, 3432, 0, 480, 488, 494, 525, 0, 778 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 779 DRM_MODE_FLAG_INTERLACE), 780 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 781 /* 12 - 2880x240@60Hz 4:3 */ 782 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 783 3204, 3432, 0, 240, 244, 247, 262, 0, 784 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 785 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 786 /* 13 - 2880x240@60Hz 16:9 */ 787 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 788 3204, 3432, 0, 240, 244, 247, 262, 0, 789 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 790 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 791 /* 14 - 1440x480@60Hz 4:3 */ 792 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 793 1596, 1716, 0, 480, 489, 495, 525, 0, 794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 795 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 796 /* 15 - 1440x480@60Hz 16:9 */ 797 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 798 1596, 1716, 0, 480, 489, 495, 525, 0, 799 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 800 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 801 /* 16 - 1920x1080@60Hz 16:9 */ 802 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 803 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 804 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 805 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 806 /* 17 - 720x576@50Hz 4:3 */ 807 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 808 796, 864, 0, 576, 581, 586, 625, 0, 809 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 810 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 811 /* 18 - 720x576@50Hz 16:9 */ 812 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 813 796, 864, 0, 576, 581, 586, 625, 0, 814 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 815 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 816 /* 19 - 1280x720@50Hz 16:9 */ 817 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 818 1760, 1980, 0, 720, 725, 730, 750, 0, 819 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 820 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 821 /* 20 - 1920x1080i@50Hz 16:9 */ 822 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 823 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 824 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 825 DRM_MODE_FLAG_INTERLACE), 826 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 827 /* 21 - 720(1440)x576i@50Hz 4:3 */ 828 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 829 795, 864, 0, 576, 580, 586, 625, 0, 830 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 831 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 832 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 833 /* 22 - 720(1440)x576i@50Hz 16:9 */ 834 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 835 795, 864, 0, 576, 580, 586, 625, 0, 836 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 837 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 838 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 839 /* 23 - 720(1440)x288@50Hz 4:3 */ 840 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 841 795, 864, 0, 288, 290, 293, 312, 0, 842 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 843 DRM_MODE_FLAG_DBLCLK), 844 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 845 /* 24 - 720(1440)x288@50Hz 16:9 */ 846 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 847 795, 864, 0, 288, 290, 293, 312, 0, 848 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 849 DRM_MODE_FLAG_DBLCLK), 850 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 851 /* 25 - 2880x576i@50Hz 4:3 */ 852 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 853 3180, 3456, 0, 576, 580, 586, 625, 0, 854 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 855 DRM_MODE_FLAG_INTERLACE), 856 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 857 /* 26 - 2880x576i@50Hz 16:9 */ 858 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 859 3180, 3456, 0, 576, 580, 586, 625, 0, 860 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 861 DRM_MODE_FLAG_INTERLACE), 862 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 863 /* 27 - 2880x288@50Hz 4:3 */ 864 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 865 3180, 3456, 0, 288, 290, 293, 312, 0, 866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 867 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 868 /* 28 - 2880x288@50Hz 16:9 */ 869 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 870 3180, 3456, 0, 288, 290, 293, 312, 0, 871 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 872 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 873 /* 29 - 1440x576@50Hz 4:3 */ 874 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 875 1592, 1728, 0, 576, 581, 586, 625, 0, 876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 877 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 878 /* 30 - 1440x576@50Hz 16:9 */ 879 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 880 1592, 1728, 0, 576, 581, 586, 625, 0, 881 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 882 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 883 /* 31 - 1920x1080@50Hz 16:9 */ 884 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 885 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 886 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 887 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 888 /* 32 - 1920x1080@24Hz 16:9 */ 889 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 890 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 891 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 892 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 893 /* 33 - 1920x1080@25Hz 16:9 */ 894 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 895 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 896 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 897 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 898 /* 34 - 1920x1080@30Hz 16:9 */ 899 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 900 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 901 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 902 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 903 /* 35 - 2880x480@60Hz 4:3 */ 904 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 905 3192, 3432, 0, 480, 489, 495, 525, 0, 906 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 907 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 908 /* 36 - 2880x480@60Hz 16:9 */ 909 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 910 3192, 3432, 0, 480, 489, 495, 525, 0, 911 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 912 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 913 /* 37 - 2880x576@50Hz 4:3 */ 914 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 915 3184, 3456, 0, 576, 581, 586, 625, 0, 916 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 917 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 918 /* 38 - 2880x576@50Hz 16:9 */ 919 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 920 3184, 3456, 0, 576, 581, 586, 625, 0, 921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 922 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 923 /* 39 - 1920x1080i@50Hz 16:9 */ 924 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 925 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 926 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 927 DRM_MODE_FLAG_INTERLACE), 928 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 929 /* 40 - 1920x1080i@100Hz 16:9 */ 930 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 931 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 933 DRM_MODE_FLAG_INTERLACE), 934 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 935 /* 41 - 1280x720@100Hz 16:9 */ 936 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 937 1760, 1980, 0, 720, 725, 730, 750, 0, 938 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 939 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 940 /* 42 - 720x576@100Hz 4:3 */ 941 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 942 796, 864, 0, 576, 581, 586, 625, 0, 943 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 944 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 945 /* 43 - 720x576@100Hz 16:9 */ 946 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 947 796, 864, 0, 576, 581, 586, 625, 0, 948 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 949 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 950 /* 44 - 720(1440)x576i@100Hz 4:3 */ 951 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 952 795, 864, 0, 576, 580, 586, 625, 0, 953 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 954 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 955 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 956 /* 45 - 720(1440)x576i@100Hz 16:9 */ 957 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 958 795, 864, 0, 576, 580, 586, 625, 0, 959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 960 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 961 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 962 /* 46 - 1920x1080i@120Hz 16:9 */ 963 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 964 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 965 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 966 DRM_MODE_FLAG_INTERLACE), 967 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 968 /* 47 - 1280x720@120Hz 16:9 */ 969 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 970 1430, 1650, 0, 720, 725, 730, 750, 0, 971 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 972 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 973 /* 48 - 720x480@120Hz 4:3 */ 974 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 975 798, 858, 0, 480, 489, 495, 525, 0, 976 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 977 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 978 /* 49 - 720x480@120Hz 16:9 */ 979 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 980 798, 858, 0, 480, 489, 495, 525, 0, 981 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 982 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 983 /* 50 - 720(1440)x480i@120Hz 4:3 */ 984 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 985 801, 858, 0, 480, 488, 494, 525, 0, 986 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 987 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 988 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 989 /* 51 - 720(1440)x480i@120Hz 16:9 */ 990 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 991 801, 858, 0, 480, 488, 494, 525, 0, 992 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 993 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 994 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 995 /* 52 - 720x576@200Hz 4:3 */ 996 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 997 796, 864, 0, 576, 581, 586, 625, 0, 998 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 999 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1000 /* 53 - 720x576@200Hz 16:9 */ 1001 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1002 796, 864, 0, 576, 581, 586, 625, 0, 1003 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1004 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1005 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1006 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1007 795, 864, 0, 576, 580, 586, 625, 0, 1008 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1009 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1010 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1011 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1012 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1013 795, 864, 0, 576, 580, 586, 625, 0, 1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1015 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1016 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1017 /* 56 - 720x480@240Hz 4:3 */ 1018 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1019 798, 858, 0, 480, 489, 495, 525, 0, 1020 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1021 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1022 /* 57 - 720x480@240Hz 16:9 */ 1023 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1024 798, 858, 0, 480, 489, 495, 525, 0, 1025 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1026 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1027 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1028 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1029 801, 858, 0, 480, 488, 494, 525, 0, 1030 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1031 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1032 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1033 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1034 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1035 801, 858, 0, 480, 488, 494, 525, 0, 1036 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1037 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1038 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1039 /* 60 - 1280x720@24Hz 16:9 */ 1040 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1041 3080, 3300, 0, 720, 725, 730, 750, 0, 1042 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1043 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1044 /* 61 - 1280x720@25Hz 16:9 */ 1045 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1046 3740, 3960, 0, 720, 725, 730, 750, 0, 1047 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1048 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1049 /* 62 - 1280x720@30Hz 16:9 */ 1050 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1051 3080, 3300, 0, 720, 725, 730, 750, 0, 1052 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1053 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1054 /* 63 - 1920x1080@120Hz 16:9 */ 1055 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1056 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1058 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1059 /* 64 - 1920x1080@100Hz 16:9 */ 1060 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1061 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1062 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1063 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1064 /* 65 - 1280x720@24Hz 64:27 */ 1065 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1066 3080, 3300, 0, 720, 725, 730, 750, 0, 1067 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1068 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1069 /* 66 - 1280x720@25Hz 64:27 */ 1070 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1071 3740, 3960, 0, 720, 725, 730, 750, 0, 1072 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1073 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1074 /* 67 - 1280x720@30Hz 64:27 */ 1075 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1076 3080, 3300, 0, 720, 725, 730, 750, 0, 1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1078 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1079 /* 68 - 1280x720@50Hz 64:27 */ 1080 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1081 1760, 1980, 0, 720, 725, 730, 750, 0, 1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1083 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1084 /* 69 - 1280x720@60Hz 64:27 */ 1085 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1086 1430, 1650, 0, 720, 725, 730, 750, 0, 1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1088 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1089 /* 70 - 1280x720@100Hz 64:27 */ 1090 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1091 1760, 1980, 0, 720, 725, 730, 750, 0, 1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1093 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1094 /* 71 - 1280x720@120Hz 64:27 */ 1095 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1096 1430, 1650, 0, 720, 725, 730, 750, 0, 1097 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1098 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1099 /* 72 - 1920x1080@24Hz 64:27 */ 1100 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1101 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1103 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1104 /* 73 - 1920x1080@25Hz 64:27 */ 1105 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1106 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1108 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1109 /* 74 - 1920x1080@30Hz 64:27 */ 1110 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1111 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1113 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1114 /* 75 - 1920x1080@50Hz 64:27 */ 1115 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1116 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1117 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1118 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1119 /* 76 - 1920x1080@60Hz 64:27 */ 1120 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1121 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1123 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1124 /* 77 - 1920x1080@100Hz 64:27 */ 1125 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1126 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1127 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1128 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1129 /* 78 - 1920x1080@120Hz 64:27 */ 1130 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1131 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1133 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1134 /* 79 - 1680x720@24Hz 64:27 */ 1135 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1136 3080, 3300, 0, 720, 725, 730, 750, 0, 1137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1138 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1139 /* 80 - 1680x720@25Hz 64:27 */ 1140 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1141 2948, 3168, 0, 720, 725, 730, 750, 0, 1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1143 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1144 /* 81 - 1680x720@30Hz 64:27 */ 1145 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1146 2420, 2640, 0, 720, 725, 730, 750, 0, 1147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1148 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1149 /* 82 - 1680x720@50Hz 64:27 */ 1150 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1151 1980, 2200, 0, 720, 725, 730, 750, 0, 1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1153 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1154 /* 83 - 1680x720@60Hz 64:27 */ 1155 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1156 1980, 2200, 0, 720, 725, 730, 750, 0, 1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1158 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1159 /* 84 - 1680x720@100Hz 64:27 */ 1160 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1161 1780, 2000, 0, 720, 725, 730, 825, 0, 1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1163 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1164 /* 85 - 1680x720@120Hz 64:27 */ 1165 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1166 1780, 2000, 0, 720, 725, 730, 825, 0, 1167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1168 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1169 /* 86 - 2560x1080@24Hz 64:27 */ 1170 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1171 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1173 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1174 /* 87 - 2560x1080@25Hz 64:27 */ 1175 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1176 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1178 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1179 /* 88 - 2560x1080@30Hz 64:27 */ 1180 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1181 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1183 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1184 /* 89 - 2560x1080@50Hz 64:27 */ 1185 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1186 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1188 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1189 /* 90 - 2560x1080@60Hz 64:27 */ 1190 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1191 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1193 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1194 /* 91 - 2560x1080@100Hz 64:27 */ 1195 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1196 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1198 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1199 /* 92 - 2560x1080@120Hz 64:27 */ 1200 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1201 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1203 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1204 /* 93 - 3840x2160@24Hz 16:9 */ 1205 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1206 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1208 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1209 /* 94 - 3840x2160@25Hz 16:9 */ 1210 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1211 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1213 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1214 /* 95 - 3840x2160@30Hz 16:9 */ 1215 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1216 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1218 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1219 /* 96 - 3840x2160@50Hz 16:9 */ 1220 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1221 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1223 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1224 /* 97 - 3840x2160@60Hz 16:9 */ 1225 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1226 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1228 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1229 /* 98 - 4096x2160@24Hz 256:135 */ 1230 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1231 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1233 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1234 /* 99 - 4096x2160@25Hz 256:135 */ 1235 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1236 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1238 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1239 /* 100 - 4096x2160@30Hz 256:135 */ 1240 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1241 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1243 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1244 /* 101 - 4096x2160@50Hz 256:135 */ 1245 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1246 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1248 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1249 /* 102 - 4096x2160@60Hz 256:135 */ 1250 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1251 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1253 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1254 /* 103 - 3840x2160@24Hz 64:27 */ 1255 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1256 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1258 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1259 /* 104 - 3840x2160@25Hz 64:27 */ 1260 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1261 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1263 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1264 /* 105 - 3840x2160@30Hz 64:27 */ 1265 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1266 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1268 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1269 /* 106 - 3840x2160@50Hz 64:27 */ 1270 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1271 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1273 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1274 /* 107 - 3840x2160@60Hz 64:27 */ 1275 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1276 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1278 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1279 /* 108 - 1280x720@48Hz 16:9 */ 1280 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1281 2280, 2500, 0, 720, 725, 730, 750, 0, 1282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1283 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1284 /* 109 - 1280x720@48Hz 64:27 */ 1285 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1286 2280, 2500, 0, 720, 725, 730, 750, 0, 1287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1288 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1289 /* 110 - 1680x720@48Hz 64:27 */ 1290 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1291 2530, 2750, 0, 720, 725, 730, 750, 0, 1292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1293 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1294 /* 111 - 1920x1080@48Hz 16:9 */ 1295 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1296 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1298 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1299 /* 112 - 1920x1080@48Hz 64:27 */ 1300 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1301 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1303 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1304 /* 113 - 2560x1080@48Hz 64:27 */ 1305 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1306 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1308 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1309 /* 114 - 3840x2160@48Hz 16:9 */ 1310 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1311 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1313 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1314 /* 115 - 4096x2160@48Hz 256:135 */ 1315 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1316 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1318 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1319 /* 116 - 3840x2160@48Hz 64:27 */ 1320 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1321 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1323 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1324 /* 117 - 3840x2160@100Hz 16:9 */ 1325 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1326 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1328 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1329 /* 118 - 3840x2160@120Hz 16:9 */ 1330 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1331 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1333 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1334 /* 119 - 3840x2160@100Hz 64:27 */ 1335 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1336 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1338 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1339 /* 120 - 3840x2160@120Hz 64:27 */ 1340 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1341 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1343 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1344 /* 121 - 5120x2160@24Hz 64:27 */ 1345 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1346 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1348 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1349 /* 122 - 5120x2160@25Hz 64:27 */ 1350 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1351 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1353 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1354 /* 123 - 5120x2160@30Hz 64:27 */ 1355 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1356 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1358 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1359 /* 124 - 5120x2160@48Hz 64:27 */ 1360 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1361 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1363 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1364 /* 125 - 5120x2160@50Hz 64:27 */ 1365 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1366 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1368 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1369 /* 126 - 5120x2160@60Hz 64:27 */ 1370 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1371 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1373 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1374 /* 127 - 5120x2160@100Hz 64:27 */ 1375 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1376 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1378 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1379 }; 1380 1381 /* 1382 * From CEA/CTA-861 spec. 1383 * 1384 * Do not access directly, instead always use cea_mode_for_vic(). 1385 */ 1386 static const struct drm_display_mode edid_cea_modes_193[] = { 1387 /* 193 - 5120x2160@120Hz 64:27 */ 1388 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1389 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1391 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1392 /* 194 - 7680x4320@24Hz 16:9 */ 1393 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1394 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1396 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1397 /* 195 - 7680x4320@25Hz 16:9 */ 1398 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1399 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1401 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1402 /* 196 - 7680x4320@30Hz 16:9 */ 1403 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1404 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1406 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1407 /* 197 - 7680x4320@48Hz 16:9 */ 1408 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1409 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1411 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1412 /* 198 - 7680x4320@50Hz 16:9 */ 1413 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1414 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1416 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1417 /* 199 - 7680x4320@60Hz 16:9 */ 1418 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1419 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1421 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1422 /* 200 - 7680x4320@100Hz 16:9 */ 1423 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1424 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1426 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1427 /* 201 - 7680x4320@120Hz 16:9 */ 1428 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1429 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1431 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1432 /* 202 - 7680x4320@24Hz 64:27 */ 1433 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1434 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1436 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1437 /* 203 - 7680x4320@25Hz 64:27 */ 1438 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1439 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1441 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1442 /* 204 - 7680x4320@30Hz 64:27 */ 1443 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1444 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1446 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1447 /* 205 - 7680x4320@48Hz 64:27 */ 1448 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1449 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1451 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1452 /* 206 - 7680x4320@50Hz 64:27 */ 1453 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1454 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1455 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1456 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1457 /* 207 - 7680x4320@60Hz 64:27 */ 1458 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1459 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1461 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1462 /* 208 - 7680x4320@100Hz 64:27 */ 1463 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1464 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1466 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1467 /* 209 - 7680x4320@120Hz 64:27 */ 1468 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1469 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1471 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1472 /* 210 - 10240x4320@24Hz 64:27 */ 1473 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1474 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1476 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1477 /* 211 - 10240x4320@25Hz 64:27 */ 1478 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1479 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1481 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1482 /* 212 - 10240x4320@30Hz 64:27 */ 1483 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1484 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1486 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1487 /* 213 - 10240x4320@48Hz 64:27 */ 1488 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1489 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1491 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1492 /* 214 - 10240x4320@50Hz 64:27 */ 1493 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1494 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1496 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1497 /* 215 - 10240x4320@60Hz 64:27 */ 1498 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1499 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1501 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1502 /* 216 - 10240x4320@100Hz 64:27 */ 1503 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1504 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1506 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1507 /* 217 - 10240x4320@120Hz 64:27 */ 1508 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1509 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1511 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1512 /* 218 - 4096x2160@100Hz 256:135 */ 1513 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1514 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1516 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1517 /* 219 - 4096x2160@120Hz 256:135 */ 1518 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1519 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1521 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1522 }; 1523 1524 /* 1525 * HDMI 1.4 4k modes. Index using the VIC. 1526 */ 1527 static const struct drm_display_mode edid_4k_modes[] = { 1528 /* 0 - dummy, VICs start at 1 */ 1529 { }, 1530 /* 1 - 3840x2160@30Hz */ 1531 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1532 3840, 4016, 4104, 4400, 0, 1533 2160, 2168, 2178, 2250, 0, 1534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1535 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1536 /* 2 - 3840x2160@25Hz */ 1537 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1538 3840, 4896, 4984, 5280, 0, 1539 2160, 2168, 2178, 2250, 0, 1540 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1541 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1542 /* 3 - 3840x2160@24Hz */ 1543 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1544 3840, 5116, 5204, 5500, 0, 1545 2160, 2168, 2178, 2250, 0, 1546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1547 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1548 /* 4 - 4096x2160@24Hz (SMPTE) */ 1549 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1550 4096, 5116, 5204, 5500, 0, 1551 2160, 2168, 2178, 2250, 0, 1552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1553 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1554 }; 1555 1556 /*** DDC fetch and block validation ***/ 1557 1558 static const u8 edid_header[] = { 1559 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1560 }; 1561 1562 /** 1563 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1564 * @raw_edid: pointer to raw base EDID block 1565 * 1566 * Sanity check the header of the base EDID block. 1567 * 1568 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1569 */ 1570 int drm_edid_header_is_valid(const u8 *raw_edid) 1571 { 1572 int i, score = 0; 1573 1574 for (i = 0; i < sizeof(edid_header); i++) 1575 if (raw_edid[i] == edid_header[i]) 1576 score++; 1577 1578 return score; 1579 } 1580 EXPORT_SYMBOL(drm_edid_header_is_valid); 1581 1582 static int edid_fixup __read_mostly = 6; 1583 module_param_named(edid_fixup, edid_fixup, int, 0400); 1584 MODULE_PARM_DESC(edid_fixup, 1585 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1586 1587 static int validate_displayid(u8 *displayid, int length, int idx); 1588 1589 static int drm_edid_block_checksum(const u8 *raw_edid) 1590 { 1591 int i; 1592 u8 csum = 0, crc = 0; 1593 1594 for (i = 0; i < EDID_LENGTH - 1; i++) 1595 csum += raw_edid[i]; 1596 1597 crc = 0x100 - csum; 1598 1599 return crc; 1600 } 1601 1602 static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum) 1603 { 1604 if (raw_edid[EDID_LENGTH - 1] != real_checksum) 1605 return true; 1606 else 1607 return false; 1608 } 1609 1610 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1611 { 1612 if (memchr_inv(in_edid, 0, length)) 1613 return false; 1614 1615 return true; 1616 } 1617 1618 /** 1619 * drm_edid_are_equal - compare two edid blobs. 1620 * @edid1: pointer to first blob 1621 * @edid2: pointer to second blob 1622 * This helper can be used during probing to determine if 1623 * edid had changed. 1624 */ 1625 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2) 1626 { 1627 int edid1_len, edid2_len; 1628 bool edid1_present = edid1 != NULL; 1629 bool edid2_present = edid2 != NULL; 1630 1631 if (edid1_present != edid2_present) 1632 return false; 1633 1634 if (edid1) { 1635 edid1_len = EDID_LENGTH * (1 + edid1->extensions); 1636 edid2_len = EDID_LENGTH * (1 + edid2->extensions); 1637 1638 if (edid1_len != edid2_len) 1639 return false; 1640 1641 if (memcmp(edid1, edid2, edid1_len)) 1642 return false; 1643 } 1644 1645 return true; 1646 } 1647 EXPORT_SYMBOL(drm_edid_are_equal); 1648 1649 /** 1650 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1651 * @raw_edid: pointer to raw EDID block 1652 * @block: type of block to validate (0 for base, extension otherwise) 1653 * @print_bad_edid: if true, dump bad EDID blocks to the console 1654 * @edid_corrupt: if true, the header or checksum is invalid 1655 * 1656 * Validate a base or extension EDID block and optionally dump bad blocks to 1657 * the console. 1658 * 1659 * Return: True if the block is valid, false otherwise. 1660 */ 1661 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1662 bool *edid_corrupt) 1663 { 1664 u8 csum; 1665 struct edid *edid = (struct edid *)raw_edid; 1666 1667 if (WARN_ON(!raw_edid)) 1668 return false; 1669 1670 if (edid_fixup > 8 || edid_fixup < 0) 1671 edid_fixup = 6; 1672 1673 if (block == 0) { 1674 int score = drm_edid_header_is_valid(raw_edid); 1675 1676 if (score == 8) { 1677 if (edid_corrupt) 1678 *edid_corrupt = false; 1679 } else if (score >= edid_fixup) { 1680 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1681 * The corrupt flag needs to be set here otherwise, the 1682 * fix-up code here will correct the problem, the 1683 * checksum is correct and the test fails 1684 */ 1685 if (edid_corrupt) 1686 *edid_corrupt = true; 1687 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1688 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1689 } else { 1690 if (edid_corrupt) 1691 *edid_corrupt = true; 1692 goto bad; 1693 } 1694 } 1695 1696 csum = drm_edid_block_checksum(raw_edid); 1697 if (drm_edid_block_checksum_diff(raw_edid, csum)) { 1698 if (edid_corrupt) 1699 *edid_corrupt = true; 1700 1701 /* allow CEA to slide through, switches mangle this */ 1702 if (raw_edid[0] == CEA_EXT) { 1703 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum); 1704 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n"); 1705 } else { 1706 if (print_bad_edid) 1707 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum); 1708 1709 goto bad; 1710 } 1711 } 1712 1713 /* per-block-type checks */ 1714 switch (raw_edid[0]) { 1715 case 0: /* base */ 1716 if (edid->version != 1) { 1717 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version); 1718 goto bad; 1719 } 1720 1721 if (edid->revision > 4) 1722 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1723 break; 1724 1725 default: 1726 break; 1727 } 1728 1729 return true; 1730 1731 bad: 1732 if (print_bad_edid) { 1733 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1734 pr_notice("EDID block is all zeroes\n"); 1735 } else { 1736 pr_notice("Raw EDID:\n"); 1737 print_hex_dump(KERN_NOTICE, 1738 " \t", DUMP_PREFIX_NONE, 16, 1, 1739 raw_edid, EDID_LENGTH, false); 1740 } 1741 } 1742 return false; 1743 } 1744 EXPORT_SYMBOL(drm_edid_block_valid); 1745 1746 /** 1747 * drm_edid_is_valid - sanity check EDID data 1748 * @edid: EDID data 1749 * 1750 * Sanity-check an entire EDID record (including extensions) 1751 * 1752 * Return: True if the EDID data is valid, false otherwise. 1753 */ 1754 bool drm_edid_is_valid(struct edid *edid) 1755 { 1756 int i; 1757 u8 *raw = (u8 *)edid; 1758 1759 if (!edid) 1760 return false; 1761 1762 for (i = 0; i <= edid->extensions; i++) 1763 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1764 return false; 1765 1766 return true; 1767 } 1768 EXPORT_SYMBOL(drm_edid_is_valid); 1769 1770 #define DDC_SEGMENT_ADDR 0x30 1771 /** 1772 * drm_do_probe_ddc_edid() - get EDID information via I2C 1773 * @data: I2C device adapter 1774 * @buf: EDID data buffer to be filled 1775 * @block: 128 byte EDID block to start fetching from 1776 * @len: EDID data buffer length to fetch 1777 * 1778 * Try to fetch EDID information by calling I2C driver functions. 1779 * 1780 * Return: 0 on success or -1 on failure. 1781 */ 1782 static int 1783 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1784 { 1785 struct i2c_adapter *adapter = data; 1786 unsigned char start = block * EDID_LENGTH; 1787 unsigned char segment = block >> 1; 1788 unsigned char xfers = segment ? 3 : 2; 1789 int ret, retries = 5; 1790 1791 /* 1792 * The core I2C driver will automatically retry the transfer if the 1793 * adapter reports EAGAIN. However, we find that bit-banging transfers 1794 * are susceptible to errors under a heavily loaded machine and 1795 * generate spurious NAKs and timeouts. Retrying the transfer 1796 * of the individual block a few times seems to overcome this. 1797 */ 1798 do { 1799 struct i2c_msg msgs[] = { 1800 { 1801 .addr = DDC_SEGMENT_ADDR, 1802 .flags = 0, 1803 .len = 1, 1804 .buf = &segment, 1805 }, { 1806 .addr = DDC_ADDR, 1807 .flags = 0, 1808 .len = 1, 1809 .buf = &start, 1810 }, { 1811 .addr = DDC_ADDR, 1812 .flags = I2C_M_RD, 1813 .len = len, 1814 .buf = buf, 1815 } 1816 }; 1817 1818 /* 1819 * Avoid sending the segment addr to not upset non-compliant 1820 * DDC monitors. 1821 */ 1822 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1823 1824 if (ret == -ENXIO) { 1825 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1826 adapter->name); 1827 break; 1828 } 1829 } while (ret != xfers && --retries); 1830 1831 return ret == xfers ? 0 : -1; 1832 } 1833 1834 static void connector_bad_edid(struct drm_connector *connector, 1835 u8 *edid, int num_blocks) 1836 { 1837 int i; 1838 u8 num_of_ext = edid[0x7e]; 1839 1840 if (num_of_ext > num_blocks) 1841 num_of_ext = num_blocks; 1842 1843 /* Calculate real checksum for the last edid extension block data */ 1844 connector->real_edid_checksum = 1845 drm_edid_block_checksum(edid + num_of_ext * EDID_LENGTH); 1846 1847 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 1848 return; 1849 1850 drm_warn(connector->dev, "%s: EDID is invalid:\n", connector->name); 1851 for (i = 0; i < num_blocks; i++) { 1852 u8 *block = edid + i * EDID_LENGTH; 1853 char prefix[20]; 1854 1855 if (drm_edid_is_zero(block, EDID_LENGTH)) 1856 snprintf(prefix, sizeof(prefix), "\t[%02x] ZERO ", i); 1857 else if (!drm_edid_block_valid(block, i, false, NULL)) 1858 snprintf(prefix, sizeof(prefix), "\t[%02x] BAD ", i); 1859 else 1860 snprintf(prefix, sizeof(prefix), "\t[%02x] GOOD ", i); 1861 1862 print_hex_dump(KERN_WARNING, 1863 prefix, DUMP_PREFIX_NONE, 16, 1, 1864 block, EDID_LENGTH, false); 1865 } 1866 } 1867 1868 /* Get override or firmware EDID */ 1869 static struct edid *drm_get_override_edid(struct drm_connector *connector) 1870 { 1871 struct edid *override = NULL; 1872 1873 if (connector->override_edid) 1874 override = drm_edid_duplicate(connector->edid_blob_ptr->data); 1875 1876 if (!override) 1877 override = drm_load_edid_firmware(connector); 1878 1879 return IS_ERR(override) ? NULL : override; 1880 } 1881 1882 /** 1883 * drm_add_override_edid_modes - add modes from override/firmware EDID 1884 * @connector: connector we're probing 1885 * 1886 * Add modes from the override/firmware EDID, if available. Only to be used from 1887 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 1888 * failed during drm_get_edid() and caused the override/firmware EDID to be 1889 * skipped. 1890 * 1891 * Return: The number of modes added or 0 if we couldn't find any. 1892 */ 1893 int drm_add_override_edid_modes(struct drm_connector *connector) 1894 { 1895 struct edid *override; 1896 int num_modes = 0; 1897 1898 override = drm_get_override_edid(connector); 1899 if (override) { 1900 drm_connector_update_edid_property(connector, override); 1901 num_modes = drm_add_edid_modes(connector, override); 1902 kfree(override); 1903 1904 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 1905 connector->base.id, connector->name, num_modes); 1906 } 1907 1908 return num_modes; 1909 } 1910 EXPORT_SYMBOL(drm_add_override_edid_modes); 1911 1912 /** 1913 * drm_do_get_edid - get EDID data using a custom EDID block read function 1914 * @connector: connector we're probing 1915 * @get_edid_block: EDID block read function 1916 * @data: private data passed to the block read function 1917 * 1918 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1919 * exposes a different interface to read EDID blocks this function can be used 1920 * to get EDID data using a custom block read function. 1921 * 1922 * As in the general case the DDC bus is accessible by the kernel at the I2C 1923 * level, drivers must make all reasonable efforts to expose it as an I2C 1924 * adapter and use drm_get_edid() instead of abusing this function. 1925 * 1926 * The EDID may be overridden using debugfs override_edid or firmare EDID 1927 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 1928 * order. Having either of them bypasses actual EDID reads. 1929 * 1930 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1931 */ 1932 struct edid *drm_do_get_edid(struct drm_connector *connector, 1933 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1934 size_t len), 1935 void *data) 1936 { 1937 int i, j = 0, valid_extensions = 0; 1938 u8 *edid, *new; 1939 struct edid *override; 1940 1941 override = drm_get_override_edid(connector); 1942 if (override) 1943 return override; 1944 1945 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1946 return NULL; 1947 1948 /* base block fetch */ 1949 for (i = 0; i < 4; i++) { 1950 if (get_edid_block(data, edid, 0, EDID_LENGTH)) 1951 goto out; 1952 if (drm_edid_block_valid(edid, 0, false, 1953 &connector->edid_corrupt)) 1954 break; 1955 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) { 1956 connector->null_edid_counter++; 1957 goto carp; 1958 } 1959 } 1960 if (i == 4) 1961 goto carp; 1962 1963 /* if there's no extensions, we're done */ 1964 valid_extensions = edid[0x7e]; 1965 if (valid_extensions == 0) 1966 return (struct edid *)edid; 1967 1968 #ifdef __linux__ 1969 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1970 if (!new) 1971 goto out; 1972 #else 1973 new = kmalloc((valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1974 if (!new) 1975 goto out; 1976 memcpy(new, edid, EDID_LENGTH); 1977 kfree(edid); 1978 #endif 1979 edid = new; 1980 1981 for (j = 1; j <= edid[0x7e]; j++) { 1982 u8 *block = edid + j * EDID_LENGTH; 1983 1984 for (i = 0; i < 4; i++) { 1985 if (get_edid_block(data, block, j, EDID_LENGTH)) 1986 goto out; 1987 if (drm_edid_block_valid(block, j, false, NULL)) 1988 break; 1989 } 1990 1991 if (i == 4) 1992 valid_extensions--; 1993 } 1994 1995 if (valid_extensions != edid[0x7e]) { 1996 u8 *base; 1997 1998 connector_bad_edid(connector, edid, edid[0x7e] + 1); 1999 2000 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions; 2001 edid[0x7e] = valid_extensions; 2002 2003 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH, 2004 GFP_KERNEL); 2005 if (!new) 2006 goto out; 2007 2008 base = new; 2009 for (i = 0; i <= edid[0x7e]; i++) { 2010 u8 *block = edid + i * EDID_LENGTH; 2011 2012 if (!drm_edid_block_valid(block, i, false, NULL)) 2013 continue; 2014 2015 memcpy(base, block, EDID_LENGTH); 2016 base += EDID_LENGTH; 2017 } 2018 2019 kfree(edid); 2020 edid = new; 2021 } 2022 2023 return (struct edid *)edid; 2024 2025 carp: 2026 connector_bad_edid(connector, edid, 1); 2027 out: 2028 kfree(edid); 2029 return NULL; 2030 } 2031 EXPORT_SYMBOL_GPL(drm_do_get_edid); 2032 2033 /** 2034 * drm_probe_ddc() - probe DDC presence 2035 * @adapter: I2C adapter to probe 2036 * 2037 * Return: True on success, false on failure. 2038 */ 2039 bool 2040 drm_probe_ddc(struct i2c_adapter *adapter) 2041 { 2042 unsigned char out; 2043 2044 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2045 } 2046 EXPORT_SYMBOL(drm_probe_ddc); 2047 2048 /** 2049 * drm_get_edid - get EDID data, if available 2050 * @connector: connector we're probing 2051 * @adapter: I2C adapter to use for DDC 2052 * 2053 * Poke the given I2C channel to grab EDID data if possible. If found, 2054 * attach it to the connector. 2055 * 2056 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2057 */ 2058 struct edid *drm_get_edid(struct drm_connector *connector, 2059 struct i2c_adapter *adapter) 2060 { 2061 struct edid *edid; 2062 2063 if (connector->force == DRM_FORCE_OFF) 2064 return NULL; 2065 2066 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2067 return NULL; 2068 2069 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 2070 drm_connector_update_edid_property(connector, edid); 2071 return edid; 2072 } 2073 EXPORT_SYMBOL(drm_get_edid); 2074 2075 /** 2076 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2077 * @connector: connector we're probing 2078 * @adapter: I2C adapter to use for DDC 2079 * 2080 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2081 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2082 * switch DDC to the GPU which is retrieving EDID. 2083 * 2084 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2085 */ 2086 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2087 struct i2c_adapter *adapter) 2088 { 2089 struct pci_dev *pdev = connector->dev->pdev; 2090 struct edid *edid; 2091 2092 vga_switcheroo_lock_ddc(pdev); 2093 edid = drm_get_edid(connector, adapter); 2094 vga_switcheroo_unlock_ddc(pdev); 2095 2096 return edid; 2097 } 2098 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2099 2100 /** 2101 * drm_edid_duplicate - duplicate an EDID and the extensions 2102 * @edid: EDID to duplicate 2103 * 2104 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2105 */ 2106 struct edid *drm_edid_duplicate(const struct edid *edid) 2107 { 2108 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 2109 } 2110 EXPORT_SYMBOL(drm_edid_duplicate); 2111 2112 /*** EDID parsing ***/ 2113 2114 /** 2115 * edid_vendor - match a string against EDID's obfuscated vendor field 2116 * @edid: EDID to match 2117 * @vendor: vendor string 2118 * 2119 * Returns true if @vendor is in @edid, false otherwise 2120 */ 2121 static bool edid_vendor(const struct edid *edid, const char *vendor) 2122 { 2123 char edid_vendor[3]; 2124 2125 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 2126 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 2127 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 2128 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 2129 2130 return !strncmp(edid_vendor, vendor, 3); 2131 } 2132 2133 /** 2134 * edid_get_quirks - return quirk flags for a given EDID 2135 * @edid: EDID to process 2136 * 2137 * This tells subsequent routines what fixes they need to apply. 2138 */ 2139 static u32 edid_get_quirks(const struct edid *edid) 2140 { 2141 const struct edid_quirk *quirk; 2142 int i; 2143 2144 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2145 quirk = &edid_quirk_list[i]; 2146 2147 if (edid_vendor(edid, quirk->vendor) && 2148 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 2149 return quirk->quirks; 2150 } 2151 2152 return 0; 2153 } 2154 2155 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2156 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2157 2158 /** 2159 * edid_fixup_preferred - set preferred modes based on quirk list 2160 * @connector: has mode list to fix up 2161 * @quirks: quirks list 2162 * 2163 * Walk the mode list for @connector, clearing the preferred status 2164 * on existing modes and setting it anew for the right mode ala @quirks. 2165 */ 2166 static void edid_fixup_preferred(struct drm_connector *connector, 2167 u32 quirks) 2168 { 2169 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2170 int target_refresh = 0; 2171 int cur_vrefresh, preferred_vrefresh; 2172 2173 if (list_empty(&connector->probed_modes)) 2174 return; 2175 2176 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 2177 target_refresh = 60; 2178 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 2179 target_refresh = 75; 2180 2181 preferred_mode = list_first_entry(&connector->probed_modes, 2182 struct drm_display_mode, head); 2183 2184 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 2185 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2186 2187 if (cur_mode == preferred_mode) 2188 continue; 2189 2190 /* Largest mode is preferred */ 2191 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 2192 preferred_mode = cur_mode; 2193 2194 cur_vrefresh = drm_mode_vrefresh(cur_mode); 2195 preferred_vrefresh = drm_mode_vrefresh(preferred_mode); 2196 /* At a given size, try to get closest to target refresh */ 2197 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2198 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2199 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2200 preferred_mode = cur_mode; 2201 } 2202 } 2203 2204 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 2205 } 2206 2207 static bool 2208 mode_is_rb(const struct drm_display_mode *mode) 2209 { 2210 return (mode->htotal - mode->hdisplay == 160) && 2211 (mode->hsync_end - mode->hdisplay == 80) && 2212 (mode->hsync_end - mode->hsync_start == 32) && 2213 (mode->vsync_start - mode->vdisplay == 3); 2214 } 2215 2216 /* 2217 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 2218 * @dev: Device to duplicate against 2219 * @hsize: Mode width 2220 * @vsize: Mode height 2221 * @fresh: Mode refresh rate 2222 * @rb: Mode reduced-blanking-ness 2223 * 2224 * Walk the DMT mode list looking for a match for the given parameters. 2225 * 2226 * Return: A newly allocated copy of the mode, or NULL if not found. 2227 */ 2228 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 2229 int hsize, int vsize, int fresh, 2230 bool rb) 2231 { 2232 int i; 2233 2234 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2235 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 2236 2237 if (hsize != ptr->hdisplay) 2238 continue; 2239 if (vsize != ptr->vdisplay) 2240 continue; 2241 if (fresh != drm_mode_vrefresh(ptr)) 2242 continue; 2243 if (rb != mode_is_rb(ptr)) 2244 continue; 2245 2246 return drm_mode_duplicate(dev, ptr); 2247 } 2248 2249 return NULL; 2250 } 2251 EXPORT_SYMBOL(drm_mode_find_dmt); 2252 2253 static bool is_display_descriptor(const u8 d[18], u8 tag) 2254 { 2255 return d[0] == 0x00 && d[1] == 0x00 && 2256 d[2] == 0x00 && d[3] == tag; 2257 } 2258 2259 static bool is_detailed_timing_descriptor(const u8 d[18]) 2260 { 2261 return d[0] != 0x00 || d[1] != 0x00; 2262 } 2263 2264 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 2265 2266 static void 2267 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 2268 { 2269 int i, n; 2270 u8 d = ext[0x02]; 2271 u8 *det_base = ext + d; 2272 2273 if (d < 4 || d > 127) 2274 return; 2275 2276 n = (127 - d) / 18; 2277 for (i = 0; i < n; i++) 2278 cb((struct detailed_timing *)(det_base + 18 * i), closure); 2279 } 2280 2281 static void 2282 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 2283 { 2284 unsigned int i, n = min((int)ext[0x02], 6); 2285 u8 *det_base = ext + 5; 2286 2287 if (ext[0x01] != 1) 2288 return; /* unknown version */ 2289 2290 for (i = 0; i < n; i++) 2291 cb((struct detailed_timing *)(det_base + 18 * i), closure); 2292 } 2293 2294 static void 2295 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 2296 { 2297 int i; 2298 struct edid *edid = (struct edid *)raw_edid; 2299 2300 if (edid == NULL) 2301 return; 2302 2303 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 2304 cb(&(edid->detailed_timings[i]), closure); 2305 2306 for (i = 1; i <= raw_edid[0x7e]; i++) { 2307 u8 *ext = raw_edid + (i * EDID_LENGTH); 2308 2309 switch (*ext) { 2310 case CEA_EXT: 2311 cea_for_each_detailed_block(ext, cb, closure); 2312 break; 2313 case VTB_EXT: 2314 vtb_for_each_detailed_block(ext, cb, closure); 2315 break; 2316 default: 2317 break; 2318 } 2319 } 2320 } 2321 2322 static void 2323 is_rb(struct detailed_timing *t, void *data) 2324 { 2325 u8 *r = (u8 *)t; 2326 2327 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE)) 2328 return; 2329 2330 if (r[15] & 0x10) 2331 *(bool *)data = true; 2332 } 2333 2334 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 2335 static bool 2336 drm_monitor_supports_rb(struct edid *edid) 2337 { 2338 if (edid->revision >= 4) { 2339 bool ret = false; 2340 2341 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 2342 return ret; 2343 } 2344 2345 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 2346 } 2347 2348 static void 2349 find_gtf2(struct detailed_timing *t, void *data) 2350 { 2351 u8 *r = (u8 *)t; 2352 2353 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE)) 2354 return; 2355 2356 if (r[10] == 0x02) 2357 *(u8 **)data = r; 2358 } 2359 2360 /* Secondary GTF curve kicks in above some break frequency */ 2361 static int 2362 drm_gtf2_hbreak(struct edid *edid) 2363 { 2364 u8 *r = NULL; 2365 2366 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2367 return r ? (r[12] * 2) : 0; 2368 } 2369 2370 static int 2371 drm_gtf2_2c(struct edid *edid) 2372 { 2373 u8 *r = NULL; 2374 2375 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2376 return r ? r[13] : 0; 2377 } 2378 2379 static int 2380 drm_gtf2_m(struct edid *edid) 2381 { 2382 u8 *r = NULL; 2383 2384 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2385 return r ? (r[15] << 8) + r[14] : 0; 2386 } 2387 2388 static int 2389 drm_gtf2_k(struct edid *edid) 2390 { 2391 u8 *r = NULL; 2392 2393 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2394 return r ? r[16] : 0; 2395 } 2396 2397 static int 2398 drm_gtf2_2j(struct edid *edid) 2399 { 2400 u8 *r = NULL; 2401 2402 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2403 return r ? r[17] : 0; 2404 } 2405 2406 /** 2407 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 2408 * @edid: EDID block to scan 2409 */ 2410 static int standard_timing_level(struct edid *edid) 2411 { 2412 if (edid->revision >= 2) { 2413 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 2414 return LEVEL_CVT; 2415 if (drm_gtf2_hbreak(edid)) 2416 return LEVEL_GTF2; 2417 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 2418 return LEVEL_GTF; 2419 } 2420 return LEVEL_DMT; 2421 } 2422 2423 /* 2424 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 2425 * monitors fill with ascii space (0x20) instead. 2426 */ 2427 static int 2428 bad_std_timing(u8 a, u8 b) 2429 { 2430 return (a == 0x00 && b == 0x00) || 2431 (a == 0x01 && b == 0x01) || 2432 (a == 0x20 && b == 0x20); 2433 } 2434 2435 static int drm_mode_hsync(const struct drm_display_mode *mode) 2436 { 2437 if (mode->htotal <= 0) 2438 return 0; 2439 2440 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 2441 } 2442 2443 /** 2444 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 2445 * @connector: connector of for the EDID block 2446 * @edid: EDID block to scan 2447 * @t: standard timing params 2448 * 2449 * Take the standard timing params (in this case width, aspect, and refresh) 2450 * and convert them into a real mode using CVT/GTF/DMT. 2451 */ 2452 static struct drm_display_mode * 2453 drm_mode_std(struct drm_connector *connector, struct edid *edid, 2454 struct std_timing *t) 2455 { 2456 struct drm_device *dev = connector->dev; 2457 struct drm_display_mode *m, *mode = NULL; 2458 int hsize, vsize; 2459 int vrefresh_rate; 2460 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 2461 >> EDID_TIMING_ASPECT_SHIFT; 2462 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 2463 >> EDID_TIMING_VFREQ_SHIFT; 2464 int timing_level = standard_timing_level(edid); 2465 2466 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 2467 return NULL; 2468 2469 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 2470 hsize = t->hsize * 8 + 248; 2471 /* vrefresh_rate = vfreq + 60 */ 2472 vrefresh_rate = vfreq + 60; 2473 /* the vdisplay is calculated based on the aspect ratio */ 2474 if (aspect_ratio == 0) { 2475 if (edid->revision < 3) 2476 vsize = hsize; 2477 else 2478 vsize = (hsize * 10) / 16; 2479 } else if (aspect_ratio == 1) 2480 vsize = (hsize * 3) / 4; 2481 else if (aspect_ratio == 2) 2482 vsize = (hsize * 4) / 5; 2483 else 2484 vsize = (hsize * 9) / 16; 2485 2486 /* HDTV hack, part 1 */ 2487 if (vrefresh_rate == 60 && 2488 ((hsize == 1360 && vsize == 765) || 2489 (hsize == 1368 && vsize == 769))) { 2490 hsize = 1366; 2491 vsize = 768; 2492 } 2493 2494 /* 2495 * If this connector already has a mode for this size and refresh 2496 * rate (because it came from detailed or CVT info), use that 2497 * instead. This way we don't have to guess at interlace or 2498 * reduced blanking. 2499 */ 2500 list_for_each_entry(m, &connector->probed_modes, head) 2501 if (m->hdisplay == hsize && m->vdisplay == vsize && 2502 drm_mode_vrefresh(m) == vrefresh_rate) 2503 return NULL; 2504 2505 /* HDTV hack, part 2 */ 2506 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 2507 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 2508 false); 2509 if (!mode) 2510 return NULL; 2511 mode->hdisplay = 1366; 2512 mode->hsync_start = mode->hsync_start - 1; 2513 mode->hsync_end = mode->hsync_end - 1; 2514 return mode; 2515 } 2516 2517 /* check whether it can be found in default mode table */ 2518 if (drm_monitor_supports_rb(edid)) { 2519 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 2520 true); 2521 if (mode) 2522 return mode; 2523 } 2524 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 2525 if (mode) 2526 return mode; 2527 2528 /* okay, generate it */ 2529 switch (timing_level) { 2530 case LEVEL_DMT: 2531 break; 2532 case LEVEL_GTF: 2533 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2534 break; 2535 case LEVEL_GTF2: 2536 /* 2537 * This is potentially wrong if there's ever a monitor with 2538 * more than one ranges section, each claiming a different 2539 * secondary GTF curve. Please don't do that. 2540 */ 2541 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2542 if (!mode) 2543 return NULL; 2544 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 2545 drm_mode_destroy(dev, mode); 2546 mode = drm_gtf_mode_complex(dev, hsize, vsize, 2547 vrefresh_rate, 0, 0, 2548 drm_gtf2_m(edid), 2549 drm_gtf2_2c(edid), 2550 drm_gtf2_k(edid), 2551 drm_gtf2_2j(edid)); 2552 } 2553 break; 2554 case LEVEL_CVT: 2555 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 2556 false); 2557 break; 2558 } 2559 return mode; 2560 } 2561 2562 /* 2563 * EDID is delightfully ambiguous about how interlaced modes are to be 2564 * encoded. Our internal representation is of frame height, but some 2565 * HDTV detailed timings are encoded as field height. 2566 * 2567 * The format list here is from CEA, in frame size. Technically we 2568 * should be checking refresh rate too. Whatever. 2569 */ 2570 static void 2571 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 2572 struct detailed_pixel_timing *pt) 2573 { 2574 int i; 2575 static const struct { 2576 int w, h; 2577 } cea_interlaced[] = { 2578 { 1920, 1080 }, 2579 { 720, 480 }, 2580 { 1440, 480 }, 2581 { 2880, 480 }, 2582 { 720, 576 }, 2583 { 1440, 576 }, 2584 { 2880, 576 }, 2585 }; 2586 2587 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 2588 return; 2589 2590 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 2591 if ((mode->hdisplay == cea_interlaced[i].w) && 2592 (mode->vdisplay == cea_interlaced[i].h / 2)) { 2593 mode->vdisplay *= 2; 2594 mode->vsync_start *= 2; 2595 mode->vsync_end *= 2; 2596 mode->vtotal *= 2; 2597 mode->vtotal |= 1; 2598 } 2599 } 2600 2601 mode->flags |= DRM_MODE_FLAG_INTERLACE; 2602 } 2603 2604 /** 2605 * drm_mode_detailed - create a new mode from an EDID detailed timing section 2606 * @dev: DRM device (needed to create new mode) 2607 * @edid: EDID block 2608 * @timing: EDID detailed timing info 2609 * @quirks: quirks to apply 2610 * 2611 * An EDID detailed timing block contains enough info for us to create and 2612 * return a new struct drm_display_mode. 2613 */ 2614 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 2615 struct edid *edid, 2616 struct detailed_timing *timing, 2617 u32 quirks) 2618 { 2619 struct drm_display_mode *mode; 2620 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 2621 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 2622 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 2623 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 2624 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 2625 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 2626 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 2627 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 2628 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 2629 2630 /* ignore tiny modes */ 2631 if (hactive < 64 || vactive < 64) 2632 return NULL; 2633 2634 if (pt->misc & DRM_EDID_PT_STEREO) { 2635 DRM_DEBUG_KMS("stereo mode not supported\n"); 2636 return NULL; 2637 } 2638 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 2639 DRM_DEBUG_KMS("composite sync not supported\n"); 2640 } 2641 2642 /* it is incorrect if hsync/vsync width is zero */ 2643 if (!hsync_pulse_width || !vsync_pulse_width) { 2644 DRM_DEBUG_KMS("Incorrect Detailed timing. " 2645 "Wrong Hsync/Vsync pulse width\n"); 2646 return NULL; 2647 } 2648 2649 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 2650 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2651 if (!mode) 2652 return NULL; 2653 2654 goto set_size; 2655 } 2656 2657 mode = drm_mode_create(dev); 2658 if (!mode) 2659 return NULL; 2660 2661 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2662 timing->pixel_clock = cpu_to_le16(1088); 2663 2664 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2665 2666 mode->hdisplay = hactive; 2667 mode->hsync_start = mode->hdisplay + hsync_offset; 2668 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2669 mode->htotal = mode->hdisplay + hblank; 2670 2671 mode->vdisplay = vactive; 2672 mode->vsync_start = mode->vdisplay + vsync_offset; 2673 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2674 mode->vtotal = mode->vdisplay + vblank; 2675 2676 /* Some EDIDs have bogus h/vtotal values */ 2677 if (mode->hsync_end > mode->htotal) 2678 mode->htotal = mode->hsync_end + 1; 2679 if (mode->vsync_end > mode->vtotal) 2680 mode->vtotal = mode->vsync_end + 1; 2681 2682 drm_mode_do_interlace_quirk(mode, pt); 2683 2684 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2685 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 2686 } 2687 2688 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2689 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2690 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2691 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2692 2693 set_size: 2694 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2695 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2696 2697 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2698 mode->width_mm *= 10; 2699 mode->height_mm *= 10; 2700 } 2701 2702 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2703 mode->width_mm = edid->width_cm * 10; 2704 mode->height_mm = edid->height_cm * 10; 2705 } 2706 2707 mode->type = DRM_MODE_TYPE_DRIVER; 2708 drm_mode_set_name(mode); 2709 2710 return mode; 2711 } 2712 2713 static bool 2714 mode_in_hsync_range(const struct drm_display_mode *mode, 2715 struct edid *edid, u8 *t) 2716 { 2717 int hsync, hmin, hmax; 2718 2719 hmin = t[7]; 2720 if (edid->revision >= 4) 2721 hmin += ((t[4] & 0x04) ? 255 : 0); 2722 hmax = t[8]; 2723 if (edid->revision >= 4) 2724 hmax += ((t[4] & 0x08) ? 255 : 0); 2725 hsync = drm_mode_hsync(mode); 2726 2727 return (hsync <= hmax && hsync >= hmin); 2728 } 2729 2730 static bool 2731 mode_in_vsync_range(const struct drm_display_mode *mode, 2732 struct edid *edid, u8 *t) 2733 { 2734 int vsync, vmin, vmax; 2735 2736 vmin = t[5]; 2737 if (edid->revision >= 4) 2738 vmin += ((t[4] & 0x01) ? 255 : 0); 2739 vmax = t[6]; 2740 if (edid->revision >= 4) 2741 vmax += ((t[4] & 0x02) ? 255 : 0); 2742 vsync = drm_mode_vrefresh(mode); 2743 2744 return (vsync <= vmax && vsync >= vmin); 2745 } 2746 2747 static u32 2748 range_pixel_clock(struct edid *edid, u8 *t) 2749 { 2750 /* unspecified */ 2751 if (t[9] == 0 || t[9] == 255) 2752 return 0; 2753 2754 /* 1.4 with CVT support gives us real precision, yay */ 2755 if (edid->revision >= 4 && t[10] == 0x04) 2756 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2757 2758 /* 1.3 is pathetic, so fuzz up a bit */ 2759 return t[9] * 10000 + 5001; 2760 } 2761 2762 static bool 2763 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2764 struct detailed_timing *timing) 2765 { 2766 u32 max_clock; 2767 u8 *t = (u8 *)timing; 2768 2769 if (!mode_in_hsync_range(mode, edid, t)) 2770 return false; 2771 2772 if (!mode_in_vsync_range(mode, edid, t)) 2773 return false; 2774 2775 if ((max_clock = range_pixel_clock(edid, t))) 2776 if (mode->clock > max_clock) 2777 return false; 2778 2779 /* 1.4 max horizontal check */ 2780 if (edid->revision >= 4 && t[10] == 0x04) 2781 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2782 return false; 2783 2784 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2785 return false; 2786 2787 return true; 2788 } 2789 2790 static bool valid_inferred_mode(const struct drm_connector *connector, 2791 const struct drm_display_mode *mode) 2792 { 2793 const struct drm_display_mode *m; 2794 bool ok = false; 2795 2796 list_for_each_entry(m, &connector->probed_modes, head) { 2797 if (mode->hdisplay == m->hdisplay && 2798 mode->vdisplay == m->vdisplay && 2799 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2800 return false; /* duplicated */ 2801 if (mode->hdisplay <= m->hdisplay && 2802 mode->vdisplay <= m->vdisplay) 2803 ok = true; 2804 } 2805 return ok; 2806 } 2807 2808 static int 2809 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2810 struct detailed_timing *timing) 2811 { 2812 int i, modes = 0; 2813 struct drm_display_mode *newmode; 2814 struct drm_device *dev = connector->dev; 2815 2816 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2817 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2818 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2819 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2820 if (newmode) { 2821 drm_mode_probed_add(connector, newmode); 2822 modes++; 2823 } 2824 } 2825 } 2826 2827 return modes; 2828 } 2829 2830 /* fix up 1366x768 mode from 1368x768; 2831 * GFT/CVT can't express 1366 width which isn't dividable by 8 2832 */ 2833 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 2834 { 2835 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2836 mode->hdisplay = 1366; 2837 mode->hsync_start--; 2838 mode->hsync_end--; 2839 drm_mode_set_name(mode); 2840 } 2841 } 2842 2843 static int 2844 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2845 struct detailed_timing *timing) 2846 { 2847 int i, modes = 0; 2848 struct drm_display_mode *newmode; 2849 struct drm_device *dev = connector->dev; 2850 2851 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2852 const struct minimode *m = &extra_modes[i]; 2853 2854 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2855 if (!newmode) 2856 return modes; 2857 2858 drm_mode_fixup_1366x768(newmode); 2859 if (!mode_in_range(newmode, edid, timing) || 2860 !valid_inferred_mode(connector, newmode)) { 2861 drm_mode_destroy(dev, newmode); 2862 continue; 2863 } 2864 2865 drm_mode_probed_add(connector, newmode); 2866 modes++; 2867 } 2868 2869 return modes; 2870 } 2871 2872 static int 2873 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2874 struct detailed_timing *timing) 2875 { 2876 int i, modes = 0; 2877 struct drm_display_mode *newmode; 2878 struct drm_device *dev = connector->dev; 2879 bool rb = drm_monitor_supports_rb(edid); 2880 2881 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2882 const struct minimode *m = &extra_modes[i]; 2883 2884 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2885 if (!newmode) 2886 return modes; 2887 2888 drm_mode_fixup_1366x768(newmode); 2889 if (!mode_in_range(newmode, edid, timing) || 2890 !valid_inferred_mode(connector, newmode)) { 2891 drm_mode_destroy(dev, newmode); 2892 continue; 2893 } 2894 2895 drm_mode_probed_add(connector, newmode); 2896 modes++; 2897 } 2898 2899 return modes; 2900 } 2901 2902 static void 2903 do_inferred_modes(struct detailed_timing *timing, void *c) 2904 { 2905 struct detailed_mode_closure *closure = c; 2906 struct detailed_non_pixel *data = &timing->data.other_data; 2907 struct detailed_data_monitor_range *range = &data->data.range; 2908 2909 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE)) 2910 return; 2911 2912 closure->modes += drm_dmt_modes_for_range(closure->connector, 2913 closure->edid, 2914 timing); 2915 2916 if (!version_greater(closure->edid, 1, 1)) 2917 return; /* GTF not defined yet */ 2918 2919 switch (range->flags) { 2920 case 0x02: /* secondary gtf, XXX could do more */ 2921 case 0x00: /* default gtf */ 2922 closure->modes += drm_gtf_modes_for_range(closure->connector, 2923 closure->edid, 2924 timing); 2925 break; 2926 case 0x04: /* cvt, only in 1.4+ */ 2927 if (!version_greater(closure->edid, 1, 3)) 2928 break; 2929 2930 closure->modes += drm_cvt_modes_for_range(closure->connector, 2931 closure->edid, 2932 timing); 2933 break; 2934 case 0x01: /* just the ranges, no formula */ 2935 default: 2936 break; 2937 } 2938 } 2939 2940 static int 2941 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2942 { 2943 struct detailed_mode_closure closure = { 2944 .connector = connector, 2945 .edid = edid, 2946 }; 2947 2948 if (version_greater(edid, 1, 0)) 2949 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2950 &closure); 2951 2952 return closure.modes; 2953 } 2954 2955 static int 2956 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2957 { 2958 int i, j, m, modes = 0; 2959 struct drm_display_mode *mode; 2960 u8 *est = ((u8 *)timing) + 6; 2961 2962 for (i = 0; i < 6; i++) { 2963 for (j = 7; j >= 0; j--) { 2964 m = (i * 8) + (7 - j); 2965 if (m >= ARRAY_SIZE(est3_modes)) 2966 break; 2967 if (est[i] & (1 << j)) { 2968 mode = drm_mode_find_dmt(connector->dev, 2969 est3_modes[m].w, 2970 est3_modes[m].h, 2971 est3_modes[m].r, 2972 est3_modes[m].rb); 2973 if (mode) { 2974 drm_mode_probed_add(connector, mode); 2975 modes++; 2976 } 2977 } 2978 } 2979 } 2980 2981 return modes; 2982 } 2983 2984 static void 2985 do_established_modes(struct detailed_timing *timing, void *c) 2986 { 2987 struct detailed_mode_closure *closure = c; 2988 2989 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS)) 2990 return; 2991 2992 closure->modes += drm_est3_modes(closure->connector, timing); 2993 } 2994 2995 /** 2996 * add_established_modes - get est. modes from EDID and add them 2997 * @connector: connector to add mode(s) to 2998 * @edid: EDID block to scan 2999 * 3000 * Each EDID block contains a bitmap of the supported "established modes" list 3001 * (defined above). Tease them out and add them to the global modes list. 3002 */ 3003 static int 3004 add_established_modes(struct drm_connector *connector, struct edid *edid) 3005 { 3006 struct drm_device *dev = connector->dev; 3007 unsigned long est_bits = edid->established_timings.t1 | 3008 (edid->established_timings.t2 << 8) | 3009 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 3010 int i, modes = 0; 3011 struct detailed_mode_closure closure = { 3012 .connector = connector, 3013 .edid = edid, 3014 }; 3015 3016 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 3017 if (est_bits & (1<<i)) { 3018 struct drm_display_mode *newmode; 3019 3020 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 3021 if (newmode) { 3022 drm_mode_probed_add(connector, newmode); 3023 modes++; 3024 } 3025 } 3026 } 3027 3028 if (version_greater(edid, 1, 0)) 3029 drm_for_each_detailed_block((u8 *)edid, 3030 do_established_modes, &closure); 3031 3032 return modes + closure.modes; 3033 } 3034 3035 static void 3036 do_standard_modes(struct detailed_timing *timing, void *c) 3037 { 3038 struct detailed_mode_closure *closure = c; 3039 struct detailed_non_pixel *data = &timing->data.other_data; 3040 struct drm_connector *connector = closure->connector; 3041 struct edid *edid = closure->edid; 3042 int i; 3043 3044 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES)) 3045 return; 3046 3047 for (i = 0; i < 6; i++) { 3048 struct std_timing *std = &data->data.timings[i]; 3049 struct drm_display_mode *newmode; 3050 3051 newmode = drm_mode_std(connector, edid, std); 3052 if (newmode) { 3053 drm_mode_probed_add(connector, newmode); 3054 closure->modes++; 3055 } 3056 } 3057 } 3058 3059 /** 3060 * add_standard_modes - get std. modes from EDID and add them 3061 * @connector: connector to add mode(s) to 3062 * @edid: EDID block to scan 3063 * 3064 * Standard modes can be calculated using the appropriate standard (DMT, 3065 * GTF or CVT. Grab them from @edid and add them to the list. 3066 */ 3067 static int 3068 add_standard_modes(struct drm_connector *connector, struct edid *edid) 3069 { 3070 int i, modes = 0; 3071 struct detailed_mode_closure closure = { 3072 .connector = connector, 3073 .edid = edid, 3074 }; 3075 3076 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3077 struct drm_display_mode *newmode; 3078 3079 newmode = drm_mode_std(connector, edid, 3080 &edid->standard_timings[i]); 3081 if (newmode) { 3082 drm_mode_probed_add(connector, newmode); 3083 modes++; 3084 } 3085 } 3086 3087 if (version_greater(edid, 1, 0)) 3088 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 3089 &closure); 3090 3091 /* XXX should also look for standard codes in VTB blocks */ 3092 3093 return modes + closure.modes; 3094 } 3095 3096 static int drm_cvt_modes(struct drm_connector *connector, 3097 struct detailed_timing *timing) 3098 { 3099 int i, j, modes = 0; 3100 struct drm_display_mode *newmode; 3101 struct drm_device *dev = connector->dev; 3102 struct cvt_timing *cvt; 3103 const int rates[] = { 60, 85, 75, 60, 50 }; 3104 const u8 empty[3] = { 0, 0, 0 }; 3105 3106 for (i = 0; i < 4; i++) { 3107 int width, height; 3108 3109 cvt = &(timing->data.other_data.data.cvt[i]); 3110 3111 if (!memcmp(cvt->code, empty, 3)) 3112 continue; 3113 3114 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3115 switch (cvt->code[1] & 0x0c) { 3116 /* default - because compiler doesn't see that we've enumerated all cases */ 3117 default: 3118 case 0x00: 3119 width = height * 4 / 3; 3120 break; 3121 case 0x04: 3122 width = height * 16 / 9; 3123 break; 3124 case 0x08: 3125 width = height * 16 / 10; 3126 break; 3127 case 0x0c: 3128 width = height * 15 / 9; 3129 break; 3130 } 3131 3132 for (j = 1; j < 5; j++) { 3133 if (cvt->code[2] & (1 << j)) { 3134 newmode = drm_cvt_mode(dev, width, height, 3135 rates[j], j == 0, 3136 false, false); 3137 if (newmode) { 3138 drm_mode_probed_add(connector, newmode); 3139 modes++; 3140 } 3141 } 3142 } 3143 } 3144 3145 return modes; 3146 } 3147 3148 static void 3149 do_cvt_mode(struct detailed_timing *timing, void *c) 3150 { 3151 struct detailed_mode_closure *closure = c; 3152 3153 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE)) 3154 return; 3155 3156 closure->modes += drm_cvt_modes(closure->connector, timing); 3157 } 3158 3159 static int 3160 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 3161 { 3162 struct detailed_mode_closure closure = { 3163 .connector = connector, 3164 .edid = edid, 3165 }; 3166 3167 if (version_greater(edid, 1, 2)) 3168 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 3169 3170 /* XXX should also look for CVT codes in VTB blocks */ 3171 3172 return closure.modes; 3173 } 3174 3175 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 3176 3177 static void 3178 do_detailed_mode(struct detailed_timing *timing, void *c) 3179 { 3180 struct detailed_mode_closure *closure = c; 3181 struct drm_display_mode *newmode; 3182 3183 if (!is_detailed_timing_descriptor((const u8 *)timing)) 3184 return; 3185 3186 newmode = drm_mode_detailed(closure->connector->dev, 3187 closure->edid, timing, 3188 closure->quirks); 3189 if (!newmode) 3190 return; 3191 3192 if (closure->preferred) 3193 newmode->type |= DRM_MODE_TYPE_PREFERRED; 3194 3195 /* 3196 * Detailed modes are limited to 10kHz pixel clock resolution, 3197 * so fix up anything that looks like CEA/HDMI mode, but the clock 3198 * is just slightly off. 3199 */ 3200 fixup_detailed_cea_mode_clock(newmode); 3201 3202 drm_mode_probed_add(closure->connector, newmode); 3203 closure->modes++; 3204 closure->preferred = false; 3205 } 3206 3207 /* 3208 * add_detailed_modes - Add modes from detailed timings 3209 * @connector: attached connector 3210 * @edid: EDID block to scan 3211 * @quirks: quirks to apply 3212 */ 3213 static int 3214 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 3215 u32 quirks) 3216 { 3217 struct detailed_mode_closure closure = { 3218 .connector = connector, 3219 .edid = edid, 3220 .preferred = true, 3221 .quirks = quirks, 3222 }; 3223 3224 if (closure.preferred && !version_greater(edid, 1, 3)) 3225 closure.preferred = 3226 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 3227 3228 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 3229 3230 return closure.modes; 3231 } 3232 3233 #define AUDIO_BLOCK 0x01 3234 #define VIDEO_BLOCK 0x02 3235 #define VENDOR_BLOCK 0x03 3236 #define SPEAKER_BLOCK 0x04 3237 #define HDR_STATIC_METADATA_BLOCK 0x6 3238 #define USE_EXTENDED_TAG 0x07 3239 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00 3240 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 3241 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F 3242 #define EDID_BASIC_AUDIO (1 << 6) 3243 #define EDID_CEA_YCRCB444 (1 << 5) 3244 #define EDID_CEA_YCRCB422 (1 << 4) 3245 #define EDID_CEA_VCDB_QS (1 << 6) 3246 3247 /* 3248 * Search EDID for CEA extension block. 3249 */ 3250 static u8 *drm_find_edid_extension(const struct edid *edid, 3251 int ext_id, int *ext_index) 3252 { 3253 u8 *edid_ext = NULL; 3254 int i; 3255 3256 /* No EDID or EDID extensions */ 3257 if (edid == NULL || edid->extensions == 0) 3258 return NULL; 3259 3260 /* Find CEA extension */ 3261 for (i = *ext_index; i < edid->extensions; i++) { 3262 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 3263 if (edid_ext[0] == ext_id) 3264 break; 3265 } 3266 3267 if (i >= edid->extensions) 3268 return NULL; 3269 3270 *ext_index = i + 1; 3271 3272 return edid_ext; 3273 } 3274 3275 3276 static u8 *drm_find_displayid_extension(const struct edid *edid, 3277 int *length, int *idx, 3278 int *ext_index) 3279 { 3280 u8 *displayid = drm_find_edid_extension(edid, DISPLAYID_EXT, ext_index); 3281 struct displayid_hdr *base; 3282 int ret; 3283 3284 if (!displayid) 3285 return NULL; 3286 3287 /* EDID extensions block checksum isn't for us */ 3288 *length = EDID_LENGTH - 1; 3289 *idx = 1; 3290 3291 ret = validate_displayid(displayid, *length, *idx); 3292 if (ret) 3293 return NULL; 3294 3295 base = (struct displayid_hdr *)&displayid[*idx]; 3296 *length = *idx + sizeof(*base) + base->bytes; 3297 3298 return displayid; 3299 } 3300 3301 static u8 *drm_find_cea_extension(const struct edid *edid) 3302 { 3303 int length, idx; 3304 struct displayid_block *block; 3305 u8 *cea; 3306 u8 *displayid; 3307 int ext_index; 3308 3309 /* Look for a top level CEA extension block */ 3310 /* FIXME: make callers iterate through multiple CEA ext blocks? */ 3311 ext_index = 0; 3312 cea = drm_find_edid_extension(edid, CEA_EXT, &ext_index); 3313 if (cea) 3314 return cea; 3315 3316 /* CEA blocks can also be found embedded in a DisplayID block */ 3317 ext_index = 0; 3318 for (;;) { 3319 displayid = drm_find_displayid_extension(edid, &length, &idx, 3320 &ext_index); 3321 if (!displayid) 3322 return NULL; 3323 3324 idx += sizeof(struct displayid_hdr); 3325 for_each_displayid_db(displayid, block, idx, length) { 3326 if (block->tag == DATA_BLOCK_CTA) 3327 return (u8 *)block; 3328 } 3329 } 3330 3331 return NULL; 3332 } 3333 3334 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 3335 { 3336 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 3337 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 3338 3339 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 3340 return &edid_cea_modes_1[vic - 1]; 3341 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 3342 return &edid_cea_modes_193[vic - 193]; 3343 return NULL; 3344 } 3345 3346 static u8 cea_num_vics(void) 3347 { 3348 return 193 + ARRAY_SIZE(edid_cea_modes_193); 3349 } 3350 3351 static u8 cea_next_vic(u8 vic) 3352 { 3353 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 3354 vic = 193; 3355 return vic; 3356 } 3357 3358 /* 3359 * Calculate the alternate clock for the CEA mode 3360 * (60Hz vs. 59.94Hz etc.) 3361 */ 3362 static unsigned int 3363 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3364 { 3365 unsigned int clock = cea_mode->clock; 3366 3367 if (drm_mode_vrefresh(cea_mode) % 6 != 0) 3368 return clock; 3369 3370 /* 3371 * edid_cea_modes contains the 59.94Hz 3372 * variant for 240 and 480 line modes, 3373 * and the 60Hz variant otherwise. 3374 */ 3375 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3376 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3377 else 3378 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3379 3380 return clock; 3381 } 3382 3383 static bool 3384 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 3385 { 3386 /* 3387 * For certain VICs the spec allows the vertical 3388 * front porch to vary by one or two lines. 3389 * 3390 * cea_modes[] stores the variant with the shortest 3391 * vertical front porch. We can adjust the mode to 3392 * get the other variants by simply increasing the 3393 * vertical front porch length. 3394 */ 3395 #ifdef notyet 3396 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 3397 cea_mode_for_vic(9)->vtotal != 262 || 3398 cea_mode_for_vic(12)->vtotal != 262 || 3399 cea_mode_for_vic(13)->vtotal != 262 || 3400 cea_mode_for_vic(23)->vtotal != 312 || 3401 cea_mode_for_vic(24)->vtotal != 312 || 3402 cea_mode_for_vic(27)->vtotal != 312 || 3403 cea_mode_for_vic(28)->vtotal != 312); 3404 #endif 3405 3406 if (((vic == 8 || vic == 9 || 3407 vic == 12 || vic == 13) && mode->vtotal < 263) || 3408 ((vic == 23 || vic == 24 || 3409 vic == 27 || vic == 28) && mode->vtotal < 314)) { 3410 mode->vsync_start++; 3411 mode->vsync_end++; 3412 mode->vtotal++; 3413 3414 return true; 3415 } 3416 3417 return false; 3418 } 3419 3420 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3421 unsigned int clock_tolerance) 3422 { 3423 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3424 u8 vic; 3425 3426 if (!to_match->clock) 3427 return 0; 3428 3429 if (to_match->picture_aspect_ratio) 3430 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3431 3432 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3433 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); 3434 unsigned int clock1, clock2; 3435 3436 /* Check both 60Hz and 59.94Hz */ 3437 clock1 = cea_mode.clock; 3438 clock2 = cea_mode_alternate_clock(&cea_mode); 3439 3440 if (abs(to_match->clock - clock1) > clock_tolerance && 3441 abs(to_match->clock - clock2) > clock_tolerance) 3442 continue; 3443 3444 do { 3445 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3446 return vic; 3447 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3448 } 3449 3450 return 0; 3451 } 3452 3453 /** 3454 * drm_match_cea_mode - look for a CEA mode matching given mode 3455 * @to_match: display mode 3456 * 3457 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 3458 * mode. 3459 */ 3460 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 3461 { 3462 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3463 u8 vic; 3464 3465 if (!to_match->clock) 3466 return 0; 3467 3468 if (to_match->picture_aspect_ratio) 3469 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3470 3471 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3472 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); 3473 unsigned int clock1, clock2; 3474 3475 /* Check both 60Hz and 59.94Hz */ 3476 clock1 = cea_mode.clock; 3477 clock2 = cea_mode_alternate_clock(&cea_mode); 3478 3479 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 3480 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 3481 continue; 3482 3483 do { 3484 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3485 return vic; 3486 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3487 } 3488 3489 return 0; 3490 } 3491 EXPORT_SYMBOL(drm_match_cea_mode); 3492 3493 static bool drm_valid_cea_vic(u8 vic) 3494 { 3495 return cea_mode_for_vic(vic) != NULL; 3496 } 3497 3498 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 3499 { 3500 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 3501 3502 if (mode) 3503 return mode->picture_aspect_ratio; 3504 3505 return HDMI_PICTURE_ASPECT_NONE; 3506 } 3507 3508 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 3509 { 3510 return edid_4k_modes[video_code].picture_aspect_ratio; 3511 } 3512 3513 /* 3514 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 3515 * specific block). 3516 */ 3517 static unsigned int 3518 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3519 { 3520 return cea_mode_alternate_clock(hdmi_mode); 3521 } 3522 3523 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3524 unsigned int clock_tolerance) 3525 { 3526 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3527 u8 vic; 3528 3529 if (!to_match->clock) 3530 return 0; 3531 3532 if (to_match->picture_aspect_ratio) 3533 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3534 3535 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3536 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3537 unsigned int clock1, clock2; 3538 3539 /* Make sure to also match alternate clocks */ 3540 clock1 = hdmi_mode->clock; 3541 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3542 3543 if (abs(to_match->clock - clock1) > clock_tolerance && 3544 abs(to_match->clock - clock2) > clock_tolerance) 3545 continue; 3546 3547 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 3548 return vic; 3549 } 3550 3551 return 0; 3552 } 3553 3554 /* 3555 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 3556 * @to_match: display mode 3557 * 3558 * An HDMI mode is one defined in the HDMI vendor specific block. 3559 * 3560 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 3561 */ 3562 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 3563 { 3564 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3565 u8 vic; 3566 3567 if (!to_match->clock) 3568 return 0; 3569 3570 if (to_match->picture_aspect_ratio) 3571 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3572 3573 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3574 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3575 unsigned int clock1, clock2; 3576 3577 /* Make sure to also match alternate clocks */ 3578 clock1 = hdmi_mode->clock; 3579 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3580 3581 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 3582 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 3583 drm_mode_match(to_match, hdmi_mode, match_flags)) 3584 return vic; 3585 } 3586 return 0; 3587 } 3588 3589 static bool drm_valid_hdmi_vic(u8 vic) 3590 { 3591 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 3592 } 3593 3594 static int 3595 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 3596 { 3597 struct drm_device *dev = connector->dev; 3598 struct drm_display_mode *mode, *tmp; 3599 DRM_LIST_HEAD(list); 3600 int modes = 0; 3601 3602 /* Don't add CEA modes if the CEA extension block is missing */ 3603 if (!drm_find_cea_extension(edid)) 3604 return 0; 3605 3606 /* 3607 * Go through all probed modes and create a new mode 3608 * with the alternate clock for certain CEA modes. 3609 */ 3610 list_for_each_entry(mode, &connector->probed_modes, head) { 3611 const struct drm_display_mode *cea_mode = NULL; 3612 struct drm_display_mode *newmode; 3613 u8 vic = drm_match_cea_mode(mode); 3614 unsigned int clock1, clock2; 3615 3616 if (drm_valid_cea_vic(vic)) { 3617 cea_mode = cea_mode_for_vic(vic); 3618 clock2 = cea_mode_alternate_clock(cea_mode); 3619 } else { 3620 vic = drm_match_hdmi_mode(mode); 3621 if (drm_valid_hdmi_vic(vic)) { 3622 cea_mode = &edid_4k_modes[vic]; 3623 clock2 = hdmi_mode_alternate_clock(cea_mode); 3624 } 3625 } 3626 3627 if (!cea_mode) 3628 continue; 3629 3630 clock1 = cea_mode->clock; 3631 3632 if (clock1 == clock2) 3633 continue; 3634 3635 if (mode->clock != clock1 && mode->clock != clock2) 3636 continue; 3637 3638 newmode = drm_mode_duplicate(dev, cea_mode); 3639 if (!newmode) 3640 continue; 3641 3642 /* Carry over the stereo flags */ 3643 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 3644 3645 /* 3646 * The current mode could be either variant. Make 3647 * sure to pick the "other" clock for the new mode. 3648 */ 3649 if (mode->clock != clock1) 3650 newmode->clock = clock1; 3651 else 3652 newmode->clock = clock2; 3653 3654 list_add_tail(&newmode->head, &list); 3655 } 3656 3657 list_for_each_entry_safe(mode, tmp, &list, head) { 3658 list_del(&mode->head); 3659 drm_mode_probed_add(connector, mode); 3660 modes++; 3661 } 3662 3663 return modes; 3664 } 3665 3666 static u8 svd_to_vic(u8 svd) 3667 { 3668 /* 0-6 bit vic, 7th bit native mode indicator */ 3669 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 3670 return svd & 127; 3671 3672 return svd; 3673 } 3674 3675 static struct drm_display_mode * 3676 drm_display_mode_from_vic_index(struct drm_connector *connector, 3677 const u8 *video_db, u8 video_len, 3678 u8 video_index) 3679 { 3680 struct drm_device *dev = connector->dev; 3681 struct drm_display_mode *newmode; 3682 u8 vic; 3683 3684 if (video_db == NULL || video_index >= video_len) 3685 return NULL; 3686 3687 /* CEA modes are numbered 1..127 */ 3688 vic = svd_to_vic(video_db[video_index]); 3689 if (!drm_valid_cea_vic(vic)) 3690 return NULL; 3691 3692 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3693 if (!newmode) 3694 return NULL; 3695 3696 return newmode; 3697 } 3698 3699 /* 3700 * do_y420vdb_modes - Parse YCBCR 420 only modes 3701 * @connector: connector corresponding to the HDMI sink 3702 * @svds: start of the data block of CEA YCBCR 420 VDB 3703 * @len: length of the CEA YCBCR 420 VDB 3704 * 3705 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 3706 * which contains modes which can be supported in YCBCR 420 3707 * output format only. 3708 */ 3709 static int do_y420vdb_modes(struct drm_connector *connector, 3710 const u8 *svds, u8 svds_len) 3711 { 3712 int modes = 0, i; 3713 struct drm_device *dev = connector->dev; 3714 struct drm_display_info *info = &connector->display_info; 3715 struct drm_hdmi_info *hdmi = &info->hdmi; 3716 3717 for (i = 0; i < svds_len; i++) { 3718 u8 vic = svd_to_vic(svds[i]); 3719 struct drm_display_mode *newmode; 3720 3721 if (!drm_valid_cea_vic(vic)) 3722 continue; 3723 3724 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3725 if (!newmode) 3726 break; 3727 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 3728 drm_mode_probed_add(connector, newmode); 3729 modes++; 3730 } 3731 3732 if (modes > 0) 3733 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3734 return modes; 3735 } 3736 3737 /* 3738 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 3739 * @connector: connector corresponding to the HDMI sink 3740 * @vic: CEA vic for the video mode to be added in the map 3741 * 3742 * Makes an entry for a videomode in the YCBCR 420 bitmap 3743 */ 3744 static void 3745 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 3746 { 3747 u8 vic = svd_to_vic(svd); 3748 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3749 3750 if (!drm_valid_cea_vic(vic)) 3751 return; 3752 3753 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 3754 } 3755 3756 /** 3757 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC 3758 * @dev: DRM device 3759 * @video_code: CEA VIC of the mode 3760 * 3761 * Creates a new mode matching the specified CEA VIC. 3762 * 3763 * Returns: A new drm_display_mode on success or NULL on failure 3764 */ 3765 struct drm_display_mode * 3766 drm_display_mode_from_cea_vic(struct drm_device *dev, 3767 u8 video_code) 3768 { 3769 const struct drm_display_mode *cea_mode; 3770 struct drm_display_mode *newmode; 3771 3772 cea_mode = cea_mode_for_vic(video_code); 3773 if (!cea_mode) 3774 return NULL; 3775 3776 newmode = drm_mode_duplicate(dev, cea_mode); 3777 if (!newmode) 3778 return NULL; 3779 3780 return newmode; 3781 } 3782 EXPORT_SYMBOL(drm_display_mode_from_cea_vic); 3783 3784 static int 3785 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 3786 { 3787 int i, modes = 0; 3788 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3789 3790 for (i = 0; i < len; i++) { 3791 struct drm_display_mode *mode; 3792 3793 mode = drm_display_mode_from_vic_index(connector, db, len, i); 3794 if (mode) { 3795 /* 3796 * YCBCR420 capability block contains a bitmap which 3797 * gives the index of CEA modes from CEA VDB, which 3798 * can support YCBCR 420 sampling output also (apart 3799 * from RGB/YCBCR444 etc). 3800 * For example, if the bit 0 in bitmap is set, 3801 * first mode in VDB can support YCBCR420 output too. 3802 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 3803 */ 3804 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 3805 drm_add_cmdb_modes(connector, db[i]); 3806 3807 drm_mode_probed_add(connector, mode); 3808 modes++; 3809 } 3810 } 3811 3812 return modes; 3813 } 3814 3815 struct stereo_mandatory_mode { 3816 int width, height, vrefresh; 3817 unsigned int flags; 3818 }; 3819 3820 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 3821 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3822 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3823 { 1920, 1080, 50, 3824 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3825 { 1920, 1080, 60, 3826 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3827 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3828 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3829 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3830 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 3831 }; 3832 3833 static bool 3834 stereo_match_mandatory(const struct drm_display_mode *mode, 3835 const struct stereo_mandatory_mode *stereo_mode) 3836 { 3837 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 3838 3839 return mode->hdisplay == stereo_mode->width && 3840 mode->vdisplay == stereo_mode->height && 3841 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 3842 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 3843 } 3844 3845 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 3846 { 3847 struct drm_device *dev = connector->dev; 3848 const struct drm_display_mode *mode; 3849 struct list_head stereo_modes; 3850 int modes = 0, i; 3851 3852 INIT_LIST_HEAD(&stereo_modes); 3853 3854 list_for_each_entry(mode, &connector->probed_modes, head) { 3855 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 3856 const struct stereo_mandatory_mode *mandatory; 3857 struct drm_display_mode *new_mode; 3858 3859 if (!stereo_match_mandatory(mode, 3860 &stereo_mandatory_modes[i])) 3861 continue; 3862 3863 mandatory = &stereo_mandatory_modes[i]; 3864 new_mode = drm_mode_duplicate(dev, mode); 3865 if (!new_mode) 3866 continue; 3867 3868 new_mode->flags |= mandatory->flags; 3869 list_add_tail(&new_mode->head, &stereo_modes); 3870 modes++; 3871 } 3872 } 3873 3874 list_splice_tail(&stereo_modes, &connector->probed_modes); 3875 3876 return modes; 3877 } 3878 3879 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 3880 { 3881 struct drm_device *dev = connector->dev; 3882 struct drm_display_mode *newmode; 3883 3884 if (!drm_valid_hdmi_vic(vic)) { 3885 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 3886 return 0; 3887 } 3888 3889 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 3890 if (!newmode) 3891 return 0; 3892 3893 drm_mode_probed_add(connector, newmode); 3894 3895 return 1; 3896 } 3897 3898 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 3899 const u8 *video_db, u8 video_len, u8 video_index) 3900 { 3901 struct drm_display_mode *newmode; 3902 int modes = 0; 3903 3904 if (structure & (1 << 0)) { 3905 newmode = drm_display_mode_from_vic_index(connector, video_db, 3906 video_len, 3907 video_index); 3908 if (newmode) { 3909 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 3910 drm_mode_probed_add(connector, newmode); 3911 modes++; 3912 } 3913 } 3914 if (structure & (1 << 6)) { 3915 newmode = drm_display_mode_from_vic_index(connector, video_db, 3916 video_len, 3917 video_index); 3918 if (newmode) { 3919 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3920 drm_mode_probed_add(connector, newmode); 3921 modes++; 3922 } 3923 } 3924 if (structure & (1 << 8)) { 3925 newmode = drm_display_mode_from_vic_index(connector, video_db, 3926 video_len, 3927 video_index); 3928 if (newmode) { 3929 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3930 drm_mode_probed_add(connector, newmode); 3931 modes++; 3932 } 3933 } 3934 3935 return modes; 3936 } 3937 3938 /* 3939 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 3940 * @connector: connector corresponding to the HDMI sink 3941 * @db: start of the CEA vendor specific block 3942 * @len: length of the CEA block payload, ie. one can access up to db[len] 3943 * 3944 * Parses the HDMI VSDB looking for modes to add to @connector. This function 3945 * also adds the stereo 3d modes when applicable. 3946 */ 3947 static int 3948 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 3949 const u8 *video_db, u8 video_len) 3950 { 3951 struct drm_display_info *info = &connector->display_info; 3952 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 3953 u8 vic_len, hdmi_3d_len = 0; 3954 u16 mask; 3955 u16 structure_all; 3956 3957 if (len < 8) 3958 goto out; 3959 3960 /* no HDMI_Video_Present */ 3961 if (!(db[8] & (1 << 5))) 3962 goto out; 3963 3964 /* Latency_Fields_Present */ 3965 if (db[8] & (1 << 7)) 3966 offset += 2; 3967 3968 /* I_Latency_Fields_Present */ 3969 if (db[8] & (1 << 6)) 3970 offset += 2; 3971 3972 /* the declared length is not long enough for the 2 first bytes 3973 * of additional video format capabilities */ 3974 if (len < (8 + offset + 2)) 3975 goto out; 3976 3977 /* 3D_Present */ 3978 offset++; 3979 if (db[8 + offset] & (1 << 7)) { 3980 modes += add_hdmi_mandatory_stereo_modes(connector); 3981 3982 /* 3D_Multi_present */ 3983 multi_present = (db[8 + offset] & 0x60) >> 5; 3984 } 3985 3986 offset++; 3987 vic_len = db[8 + offset] >> 5; 3988 hdmi_3d_len = db[8 + offset] & 0x1f; 3989 3990 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3991 u8 vic; 3992 3993 vic = db[9 + offset + i]; 3994 modes += add_hdmi_mode(connector, vic); 3995 } 3996 offset += 1 + vic_len; 3997 3998 if (multi_present == 1) 3999 multi_len = 2; 4000 else if (multi_present == 2) 4001 multi_len = 4; 4002 else 4003 multi_len = 0; 4004 4005 if (len < (8 + offset + hdmi_3d_len - 1)) 4006 goto out; 4007 4008 if (hdmi_3d_len < multi_len) 4009 goto out; 4010 4011 if (multi_present == 1 || multi_present == 2) { 4012 /* 3D_Structure_ALL */ 4013 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 4014 4015 /* check if 3D_MASK is present */ 4016 if (multi_present == 2) 4017 mask = (db[10 + offset] << 8) | db[11 + offset]; 4018 else 4019 mask = 0xffff; 4020 4021 for (i = 0; i < 16; i++) { 4022 if (mask & (1 << i)) 4023 modes += add_3d_struct_modes(connector, 4024 structure_all, 4025 video_db, 4026 video_len, i); 4027 } 4028 } 4029 4030 offset += multi_len; 4031 4032 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 4033 int vic_index; 4034 struct drm_display_mode *newmode = NULL; 4035 unsigned int newflag = 0; 4036 bool detail_present; 4037 4038 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 4039 4040 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 4041 break; 4042 4043 /* 2D_VIC_order_X */ 4044 vic_index = db[8 + offset + i] >> 4; 4045 4046 /* 3D_Structure_X */ 4047 switch (db[8 + offset + i] & 0x0f) { 4048 case 0: 4049 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 4050 break; 4051 case 6: 4052 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4053 break; 4054 case 8: 4055 /* 3D_Detail_X */ 4056 if ((db[9 + offset + i] >> 4) == 1) 4057 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4058 break; 4059 } 4060 4061 if (newflag != 0) { 4062 newmode = drm_display_mode_from_vic_index(connector, 4063 video_db, 4064 video_len, 4065 vic_index); 4066 4067 if (newmode) { 4068 newmode->flags |= newflag; 4069 drm_mode_probed_add(connector, newmode); 4070 modes++; 4071 } 4072 } 4073 4074 if (detail_present) 4075 i++; 4076 } 4077 4078 out: 4079 if (modes > 0) 4080 info->has_hdmi_infoframe = true; 4081 return modes; 4082 } 4083 4084 static int 4085 cea_db_payload_len(const u8 *db) 4086 { 4087 return db[0] & 0x1f; 4088 } 4089 4090 static int 4091 cea_db_extended_tag(const u8 *db) 4092 { 4093 return db[1]; 4094 } 4095 4096 static int 4097 cea_db_tag(const u8 *db) 4098 { 4099 return db[0] >> 5; 4100 } 4101 4102 static int 4103 cea_revision(const u8 *cea) 4104 { 4105 /* 4106 * FIXME is this correct for the DispID variant? 4107 * The DispID spec doesn't really specify whether 4108 * this is the revision of the CEA extension or 4109 * the DispID CEA data block. And the only value 4110 * given as an example is 0. 4111 */ 4112 return cea[1]; 4113 } 4114 4115 static int 4116 cea_db_offsets(const u8 *cea, int *start, int *end) 4117 { 4118 /* DisplayID CTA extension blocks and top-level CEA EDID 4119 * block header definitions differ in the following bytes: 4120 * 1) Byte 2 of the header specifies length differently, 4121 * 2) Byte 3 is only present in the CEA top level block. 4122 * 4123 * The different definitions for byte 2 follow. 4124 * 4125 * DisplayID CTA extension block defines byte 2 as: 4126 * Number of payload bytes 4127 * 4128 * CEA EDID block defines byte 2 as: 4129 * Byte number (decimal) within this block where the 18-byte 4130 * DTDs begin. If no non-DTD data is present in this extension 4131 * block, the value should be set to 04h (the byte after next). 4132 * If set to 00h, there are no DTDs present in this block and 4133 * no non-DTD data. 4134 */ 4135 if (cea[0] == DATA_BLOCK_CTA) { 4136 /* 4137 * for_each_displayid_db() has already verified 4138 * that these stay within expected bounds. 4139 */ 4140 *start = 3; 4141 *end = *start + cea[2]; 4142 } else if (cea[0] == CEA_EXT) { 4143 /* Data block offset in CEA extension block */ 4144 *start = 4; 4145 *end = cea[2]; 4146 if (*end == 0) 4147 *end = 127; 4148 if (*end < 4 || *end > 127) 4149 return -ERANGE; 4150 } else { 4151 return -EOPNOTSUPP; 4152 } 4153 4154 return 0; 4155 } 4156 4157 static bool cea_db_is_hdmi_vsdb(const u8 *db) 4158 { 4159 int hdmi_id; 4160 4161 if (cea_db_tag(db) != VENDOR_BLOCK) 4162 return false; 4163 4164 if (cea_db_payload_len(db) < 5) 4165 return false; 4166 4167 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 4168 4169 return hdmi_id == HDMI_IEEE_OUI; 4170 } 4171 4172 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 4173 { 4174 unsigned int oui; 4175 4176 if (cea_db_tag(db) != VENDOR_BLOCK) 4177 return false; 4178 4179 if (cea_db_payload_len(db) < 7) 4180 return false; 4181 4182 oui = db[3] << 16 | db[2] << 8 | db[1]; 4183 4184 return oui == HDMI_FORUM_IEEE_OUI; 4185 } 4186 4187 static bool cea_db_is_vcdb(const u8 *db) 4188 { 4189 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4190 return false; 4191 4192 if (cea_db_payload_len(db) != 2) 4193 return false; 4194 4195 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK) 4196 return false; 4197 4198 return true; 4199 } 4200 4201 static bool cea_db_is_y420cmdb(const u8 *db) 4202 { 4203 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4204 return false; 4205 4206 if (!cea_db_payload_len(db)) 4207 return false; 4208 4209 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 4210 return false; 4211 4212 return true; 4213 } 4214 4215 static bool cea_db_is_y420vdb(const u8 *db) 4216 { 4217 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4218 return false; 4219 4220 if (!cea_db_payload_len(db)) 4221 return false; 4222 4223 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 4224 return false; 4225 4226 return true; 4227 } 4228 4229 #define for_each_cea_db(cea, i, start, end) \ 4230 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 4231 4232 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 4233 const u8 *db) 4234 { 4235 struct drm_display_info *info = &connector->display_info; 4236 struct drm_hdmi_info *hdmi = &info->hdmi; 4237 u8 map_len = cea_db_payload_len(db) - 1; 4238 u8 count; 4239 u64 map = 0; 4240 4241 if (map_len == 0) { 4242 /* All CEA modes support ycbcr420 sampling also.*/ 4243 hdmi->y420_cmdb_map = U64_MAX; 4244 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 4245 return; 4246 } 4247 4248 /* 4249 * This map indicates which of the existing CEA block modes 4250 * from VDB can support YCBCR420 output too. So if bit=0 is 4251 * set, first mode from VDB can support YCBCR420 output too. 4252 * We will parse and keep this map, before parsing VDB itself 4253 * to avoid going through the same block again and again. 4254 * 4255 * Spec is not clear about max possible size of this block. 4256 * Clamping max bitmap block size at 8 bytes. Every byte can 4257 * address 8 CEA modes, in this way this map can address 4258 * 8*8 = first 64 SVDs. 4259 */ 4260 if (WARN_ON_ONCE(map_len > 8)) 4261 map_len = 8; 4262 4263 for (count = 0; count < map_len; count++) 4264 map |= (u64)db[2 + count] << (8 * count); 4265 4266 if (map) 4267 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 4268 4269 hdmi->y420_cmdb_map = map; 4270 } 4271 4272 static int 4273 add_cea_modes(struct drm_connector *connector, struct edid *edid) 4274 { 4275 const u8 *cea = drm_find_cea_extension(edid); 4276 const u8 *db, *hdmi = NULL, *video = NULL; 4277 u8 dbl, hdmi_len, video_len = 0; 4278 int modes = 0; 4279 4280 if (cea && cea_revision(cea) >= 3) { 4281 int i, start, end; 4282 4283 if (cea_db_offsets(cea, &start, &end)) 4284 return 0; 4285 4286 for_each_cea_db(cea, i, start, end) { 4287 db = &cea[i]; 4288 dbl = cea_db_payload_len(db); 4289 4290 if (cea_db_tag(db) == VIDEO_BLOCK) { 4291 video = db + 1; 4292 video_len = dbl; 4293 modes += do_cea_modes(connector, video, dbl); 4294 } else if (cea_db_is_hdmi_vsdb(db)) { 4295 hdmi = db; 4296 hdmi_len = dbl; 4297 } else if (cea_db_is_y420vdb(db)) { 4298 const u8 *vdb420 = &db[2]; 4299 4300 /* Add 4:2:0(only) modes present in EDID */ 4301 modes += do_y420vdb_modes(connector, 4302 vdb420, 4303 dbl - 1); 4304 } 4305 } 4306 } 4307 4308 /* 4309 * We parse the HDMI VSDB after having added the cea modes as we will 4310 * be patching their flags when the sink supports stereo 3D. 4311 */ 4312 if (hdmi) 4313 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 4314 video_len); 4315 4316 return modes; 4317 } 4318 4319 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 4320 { 4321 const struct drm_display_mode *cea_mode; 4322 int clock1, clock2, clock; 4323 u8 vic; 4324 const char *type; 4325 4326 /* 4327 * allow 5kHz clock difference either way to account for 4328 * the 10kHz clock resolution limit of detailed timings. 4329 */ 4330 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 4331 if (drm_valid_cea_vic(vic)) { 4332 type = "CEA"; 4333 cea_mode = cea_mode_for_vic(vic); 4334 clock1 = cea_mode->clock; 4335 clock2 = cea_mode_alternate_clock(cea_mode); 4336 } else { 4337 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 4338 if (drm_valid_hdmi_vic(vic)) { 4339 type = "HDMI"; 4340 cea_mode = &edid_4k_modes[vic]; 4341 clock1 = cea_mode->clock; 4342 clock2 = hdmi_mode_alternate_clock(cea_mode); 4343 } else { 4344 return; 4345 } 4346 } 4347 4348 /* pick whichever is closest */ 4349 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 4350 clock = clock1; 4351 else 4352 clock = clock2; 4353 4354 if (mode->clock == clock) 4355 return; 4356 4357 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 4358 type, vic, mode->clock, clock); 4359 mode->clock = clock; 4360 } 4361 4362 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db) 4363 { 4364 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4365 return false; 4366 4367 if (db[1] != HDR_STATIC_METADATA_BLOCK) 4368 return false; 4369 4370 if (cea_db_payload_len(db) < 3) 4371 return false; 4372 4373 return true; 4374 } 4375 4376 static uint8_t eotf_supported(const u8 *edid_ext) 4377 { 4378 return edid_ext[2] & 4379 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 4380 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 4381 BIT(HDMI_EOTF_SMPTE_ST2084) | 4382 BIT(HDMI_EOTF_BT_2100_HLG)); 4383 } 4384 4385 static uint8_t hdr_metadata_type(const u8 *edid_ext) 4386 { 4387 return edid_ext[3] & 4388 BIT(HDMI_STATIC_METADATA_TYPE1); 4389 } 4390 4391 static void 4392 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 4393 { 4394 u16 len; 4395 4396 len = cea_db_payload_len(db); 4397 4398 connector->hdr_sink_metadata.hdmi_type1.eotf = 4399 eotf_supported(db); 4400 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 4401 hdr_metadata_type(db); 4402 4403 if (len >= 4) 4404 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 4405 if (len >= 5) 4406 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 4407 if (len >= 6) 4408 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 4409 } 4410 4411 static void 4412 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 4413 { 4414 u8 len = cea_db_payload_len(db); 4415 4416 if (len >= 6 && (db[6] & (1 << 7))) 4417 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 4418 if (len >= 8) { 4419 connector->latency_present[0] = db[8] >> 7; 4420 connector->latency_present[1] = (db[8] >> 6) & 1; 4421 } 4422 if (len >= 9) 4423 connector->video_latency[0] = db[9]; 4424 if (len >= 10) 4425 connector->audio_latency[0] = db[10]; 4426 if (len >= 11) 4427 connector->video_latency[1] = db[11]; 4428 if (len >= 12) 4429 connector->audio_latency[1] = db[12]; 4430 4431 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 4432 "video latency %d %d, " 4433 "audio latency %d %d\n", 4434 connector->latency_present[0], 4435 connector->latency_present[1], 4436 connector->video_latency[0], 4437 connector->video_latency[1], 4438 connector->audio_latency[0], 4439 connector->audio_latency[1]); 4440 } 4441 4442 static void 4443 monitor_name(struct detailed_timing *t, void *data) 4444 { 4445 if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME)) 4446 return; 4447 4448 *(u8 **)data = t->data.other_data.data.str.str; 4449 } 4450 4451 static int get_monitor_name(struct edid *edid, char name[13]) 4452 { 4453 char *edid_name = NULL; 4454 int mnl; 4455 4456 if (!edid || !name) 4457 return 0; 4458 4459 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 4460 for (mnl = 0; edid_name && mnl < 13; mnl++) { 4461 if (edid_name[mnl] == 0x0a) 4462 break; 4463 4464 name[mnl] = edid_name[mnl]; 4465 } 4466 4467 return mnl; 4468 } 4469 4470 /** 4471 * drm_edid_get_monitor_name - fetch the monitor name from the edid 4472 * @edid: monitor EDID information 4473 * @name: pointer to a character array to hold the name of the monitor 4474 * @bufsize: The size of the name buffer (should be at least 14 chars.) 4475 * 4476 */ 4477 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 4478 { 4479 int name_length; 4480 char buf[13]; 4481 4482 if (bufsize <= 0) 4483 return; 4484 4485 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 4486 memcpy(name, buf, name_length); 4487 name[name_length] = '\0'; 4488 } 4489 EXPORT_SYMBOL(drm_edid_get_monitor_name); 4490 4491 static void clear_eld(struct drm_connector *connector) 4492 { 4493 memset(connector->eld, 0, sizeof(connector->eld)); 4494 4495 connector->latency_present[0] = false; 4496 connector->latency_present[1] = false; 4497 connector->video_latency[0] = 0; 4498 connector->audio_latency[0] = 0; 4499 connector->video_latency[1] = 0; 4500 connector->audio_latency[1] = 0; 4501 } 4502 4503 /* 4504 * drm_edid_to_eld - build ELD from EDID 4505 * @connector: connector corresponding to the HDMI/DP sink 4506 * @edid: EDID to parse 4507 * 4508 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 4509 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 4510 */ 4511 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 4512 { 4513 uint8_t *eld = connector->eld; 4514 u8 *cea; 4515 u8 *db; 4516 int total_sad_count = 0; 4517 int mnl; 4518 int dbl; 4519 4520 clear_eld(connector); 4521 4522 if (!edid) 4523 return; 4524 4525 cea = drm_find_cea_extension(edid); 4526 if (!cea) { 4527 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 4528 return; 4529 } 4530 4531 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 4532 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); 4533 4534 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT; 4535 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 4536 4537 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 4538 4539 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0]; 4540 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1]; 4541 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0]; 4542 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1]; 4543 4544 if (cea_revision(cea) >= 3) { 4545 int i, start, end; 4546 int sad_count; 4547 4548 if (cea_db_offsets(cea, &start, &end)) { 4549 start = 0; 4550 end = 0; 4551 } 4552 4553 for_each_cea_db(cea, i, start, end) { 4554 db = &cea[i]; 4555 dbl = cea_db_payload_len(db); 4556 4557 switch (cea_db_tag(db)) { 4558 case AUDIO_BLOCK: 4559 /* Audio Data Block, contains SADs */ 4560 sad_count = min(dbl / 3, 15 - total_sad_count); 4561 if (sad_count >= 1) 4562 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 4563 &db[1], sad_count * 3); 4564 total_sad_count += sad_count; 4565 break; 4566 case SPEAKER_BLOCK: 4567 /* Speaker Allocation Data Block */ 4568 if (dbl >= 1) 4569 eld[DRM_ELD_SPEAKER] = db[1]; 4570 break; 4571 case VENDOR_BLOCK: 4572 /* HDMI Vendor-Specific Data Block */ 4573 if (cea_db_is_hdmi_vsdb(db)) 4574 drm_parse_hdmi_vsdb_audio(connector, db); 4575 break; 4576 default: 4577 break; 4578 } 4579 } 4580 } 4581 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 4582 4583 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 4584 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4585 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 4586 else 4587 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 4588 4589 eld[DRM_ELD_BASELINE_ELD_LEN] = 4590 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 4591 4592 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 4593 drm_eld_size(eld), total_sad_count); 4594 } 4595 4596 /** 4597 * drm_edid_to_sad - extracts SADs from EDID 4598 * @edid: EDID to parse 4599 * @sads: pointer that will be set to the extracted SADs 4600 * 4601 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 4602 * 4603 * Note: The returned pointer needs to be freed using kfree(). 4604 * 4605 * Return: The number of found SADs or negative number on error. 4606 */ 4607 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 4608 { 4609 int count = 0; 4610 int i, start, end, dbl; 4611 u8 *cea; 4612 4613 cea = drm_find_cea_extension(edid); 4614 if (!cea) { 4615 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4616 return 0; 4617 } 4618 4619 if (cea_revision(cea) < 3) { 4620 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4621 return 0; 4622 } 4623 4624 if (cea_db_offsets(cea, &start, &end)) { 4625 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4626 return -EPROTO; 4627 } 4628 4629 for_each_cea_db(cea, i, start, end) { 4630 u8 *db = &cea[i]; 4631 4632 if (cea_db_tag(db) == AUDIO_BLOCK) { 4633 int j; 4634 4635 dbl = cea_db_payload_len(db); 4636 4637 count = dbl / 3; /* SAD is 3B */ 4638 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 4639 if (!*sads) 4640 return -ENOMEM; 4641 for (j = 0; j < count; j++) { 4642 u8 *sad = &db[1 + j * 3]; 4643 4644 (*sads)[j].format = (sad[0] & 0x78) >> 3; 4645 (*sads)[j].channels = sad[0] & 0x7; 4646 (*sads)[j].freq = sad[1] & 0x7F; 4647 (*sads)[j].byte2 = sad[2]; 4648 } 4649 break; 4650 } 4651 } 4652 4653 return count; 4654 } 4655 EXPORT_SYMBOL(drm_edid_to_sad); 4656 4657 /** 4658 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 4659 * @edid: EDID to parse 4660 * @sadb: pointer to the speaker block 4661 * 4662 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 4663 * 4664 * Note: The returned pointer needs to be freed using kfree(). 4665 * 4666 * Return: The number of found Speaker Allocation Blocks or negative number on 4667 * error. 4668 */ 4669 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 4670 { 4671 int count = 0; 4672 int i, start, end, dbl; 4673 const u8 *cea; 4674 4675 cea = drm_find_cea_extension(edid); 4676 if (!cea) { 4677 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4678 return 0; 4679 } 4680 4681 if (cea_revision(cea) < 3) { 4682 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4683 return 0; 4684 } 4685 4686 if (cea_db_offsets(cea, &start, &end)) { 4687 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4688 return -EPROTO; 4689 } 4690 4691 for_each_cea_db(cea, i, start, end) { 4692 const u8 *db = &cea[i]; 4693 4694 if (cea_db_tag(db) == SPEAKER_BLOCK) { 4695 dbl = cea_db_payload_len(db); 4696 4697 /* Speaker Allocation Data Block */ 4698 if (dbl == 3) { 4699 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 4700 if (!*sadb) 4701 return -ENOMEM; 4702 count = dbl; 4703 break; 4704 } 4705 } 4706 } 4707 4708 return count; 4709 } 4710 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 4711 4712 /** 4713 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 4714 * @connector: connector associated with the HDMI/DP sink 4715 * @mode: the display mode 4716 * 4717 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 4718 * the sink doesn't support audio or video. 4719 */ 4720 int drm_av_sync_delay(struct drm_connector *connector, 4721 const struct drm_display_mode *mode) 4722 { 4723 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 4724 int a, v; 4725 4726 if (!connector->latency_present[0]) 4727 return 0; 4728 if (!connector->latency_present[1]) 4729 i = 0; 4730 4731 a = connector->audio_latency[i]; 4732 v = connector->video_latency[i]; 4733 4734 /* 4735 * HDMI/DP sink doesn't support audio or video? 4736 */ 4737 if (a == 255 || v == 255) 4738 return 0; 4739 4740 /* 4741 * Convert raw EDID values to millisecond. 4742 * Treat unknown latency as 0ms. 4743 */ 4744 if (a) 4745 a = min(2 * (a - 1), 500); 4746 if (v) 4747 v = min(2 * (v - 1), 500); 4748 4749 return max(v - a, 0); 4750 } 4751 EXPORT_SYMBOL(drm_av_sync_delay); 4752 4753 /** 4754 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 4755 * @edid: monitor EDID information 4756 * 4757 * Parse the CEA extension according to CEA-861-B. 4758 * 4759 * Drivers that have added the modes parsed from EDID to drm_display_info 4760 * should use &drm_display_info.is_hdmi instead of calling this function. 4761 * 4762 * Return: True if the monitor is HDMI, false if not or unknown. 4763 */ 4764 bool drm_detect_hdmi_monitor(struct edid *edid) 4765 { 4766 u8 *edid_ext; 4767 int i; 4768 int start_offset, end_offset; 4769 4770 edid_ext = drm_find_cea_extension(edid); 4771 if (!edid_ext) 4772 return false; 4773 4774 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4775 return false; 4776 4777 /* 4778 * Because HDMI identifier is in Vendor Specific Block, 4779 * search it from all data blocks of CEA extension. 4780 */ 4781 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4782 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 4783 return true; 4784 } 4785 4786 return false; 4787 } 4788 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 4789 4790 /** 4791 * drm_detect_monitor_audio - check monitor audio capability 4792 * @edid: EDID block to scan 4793 * 4794 * Monitor should have CEA extension block. 4795 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 4796 * audio' only. If there is any audio extension block and supported 4797 * audio format, assume at least 'basic audio' support, even if 'basic 4798 * audio' is not defined in EDID. 4799 * 4800 * Return: True if the monitor supports audio, false otherwise. 4801 */ 4802 bool drm_detect_monitor_audio(struct edid *edid) 4803 { 4804 u8 *edid_ext; 4805 int i, j; 4806 bool has_audio = false; 4807 int start_offset, end_offset; 4808 4809 edid_ext = drm_find_cea_extension(edid); 4810 if (!edid_ext) 4811 goto end; 4812 4813 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 4814 4815 if (has_audio) { 4816 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 4817 goto end; 4818 } 4819 4820 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4821 goto end; 4822 4823 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4824 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 4825 has_audio = true; 4826 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 4827 DRM_DEBUG_KMS("CEA audio format %d\n", 4828 (edid_ext[i + j] >> 3) & 0xf); 4829 goto end; 4830 } 4831 } 4832 end: 4833 return has_audio; 4834 } 4835 EXPORT_SYMBOL(drm_detect_monitor_audio); 4836 4837 4838 /** 4839 * drm_default_rgb_quant_range - default RGB quantization range 4840 * @mode: display mode 4841 * 4842 * Determine the default RGB quantization range for the mode, 4843 * as specified in CEA-861. 4844 * 4845 * Return: The default RGB quantization range for the mode 4846 */ 4847 enum hdmi_quantization_range 4848 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 4849 { 4850 /* All CEA modes other than VIC 1 use limited quantization range. */ 4851 return drm_match_cea_mode(mode) > 1 ? 4852 HDMI_QUANTIZATION_RANGE_LIMITED : 4853 HDMI_QUANTIZATION_RANGE_FULL; 4854 } 4855 EXPORT_SYMBOL(drm_default_rgb_quant_range); 4856 4857 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 4858 { 4859 struct drm_display_info *info = &connector->display_info; 4860 4861 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]); 4862 4863 if (db[2] & EDID_CEA_VCDB_QS) 4864 info->rgb_quant_range_selectable = true; 4865 } 4866 4867 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 4868 const u8 *db) 4869 { 4870 u8 dc_mask; 4871 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4872 4873 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 4874 hdmi->y420_dc_modes = dc_mask; 4875 } 4876 4877 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, 4878 const u8 *hf_vsdb) 4879 { 4880 struct drm_display_info *display = &connector->display_info; 4881 struct drm_hdmi_info *hdmi = &display->hdmi; 4882 4883 display->has_hdmi_infoframe = true; 4884 4885 if (hf_vsdb[6] & 0x80) { 4886 hdmi->scdc.supported = true; 4887 if (hf_vsdb[6] & 0x40) 4888 hdmi->scdc.read_request = true; 4889 } 4890 4891 /* 4892 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 4893 * And as per the spec, three factors confirm this: 4894 * * Availability of a HF-VSDB block in EDID (check) 4895 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 4896 * * SCDC support available (let's check) 4897 * Lets check it out. 4898 */ 4899 4900 if (hf_vsdb[5]) { 4901 /* max clock is 5000 KHz times block value */ 4902 u32 max_tmds_clock = hf_vsdb[5] * 5000; 4903 struct drm_scdc *scdc = &hdmi->scdc; 4904 4905 if (max_tmds_clock > 340000) { 4906 display->max_tmds_clock = max_tmds_clock; 4907 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 4908 display->max_tmds_clock); 4909 } 4910 4911 if (scdc->supported) { 4912 scdc->scrambling.supported = true; 4913 4914 /* Few sinks support scrambling for clocks < 340M */ 4915 if ((hf_vsdb[6] & 0x8)) 4916 scdc->scrambling.low_rates = true; 4917 } 4918 } 4919 4920 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb); 4921 } 4922 4923 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 4924 const u8 *hdmi) 4925 { 4926 struct drm_display_info *info = &connector->display_info; 4927 unsigned int dc_bpc = 0; 4928 4929 /* HDMI supports at least 8 bpc */ 4930 info->bpc = 8; 4931 4932 if (cea_db_payload_len(hdmi) < 6) 4933 return; 4934 4935 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 4936 dc_bpc = 10; 4937 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 4938 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 4939 connector->name); 4940 } 4941 4942 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 4943 dc_bpc = 12; 4944 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 4945 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 4946 connector->name); 4947 } 4948 4949 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 4950 dc_bpc = 16; 4951 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 4952 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 4953 connector->name); 4954 } 4955 4956 if (dc_bpc == 0) { 4957 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 4958 connector->name); 4959 return; 4960 } 4961 4962 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 4963 connector->name, dc_bpc); 4964 info->bpc = dc_bpc; 4965 4966 /* 4967 * Deep color support mandates RGB444 support for all video 4968 * modes and forbids YCRCB422 support for all video modes per 4969 * HDMI 1.3 spec. 4970 */ 4971 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4972 4973 /* YCRCB444 is optional according to spec. */ 4974 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 4975 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4976 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 4977 connector->name); 4978 } 4979 4980 /* 4981 * Spec says that if any deep color mode is supported at all, 4982 * then deep color 36 bit must be supported. 4983 */ 4984 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 4985 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 4986 connector->name); 4987 } 4988 } 4989 4990 static void 4991 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 4992 { 4993 struct drm_display_info *info = &connector->display_info; 4994 u8 len = cea_db_payload_len(db); 4995 4996 info->is_hdmi = true; 4997 4998 if (len >= 6) 4999 info->dvi_dual = db[6] & 1; 5000 if (len >= 7) 5001 info->max_tmds_clock = db[7] * 5000; 5002 5003 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 5004 "max TMDS clock %d kHz\n", 5005 info->dvi_dual, 5006 info->max_tmds_clock); 5007 5008 drm_parse_hdmi_deep_color_info(connector, db); 5009 } 5010 5011 static void drm_parse_cea_ext(struct drm_connector *connector, 5012 const struct edid *edid) 5013 { 5014 struct drm_display_info *info = &connector->display_info; 5015 const u8 *edid_ext; 5016 int i, start, end; 5017 5018 edid_ext = drm_find_cea_extension(edid); 5019 if (!edid_ext) 5020 return; 5021 5022 info->cea_rev = edid_ext[1]; 5023 5024 /* The existence of a CEA block should imply RGB support */ 5025 info->color_formats = DRM_COLOR_FORMAT_RGB444; 5026 if (edid_ext[3] & EDID_CEA_YCRCB444) 5027 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 5028 if (edid_ext[3] & EDID_CEA_YCRCB422) 5029 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 5030 5031 if (cea_db_offsets(edid_ext, &start, &end)) 5032 return; 5033 5034 for_each_cea_db(edid_ext, i, start, end) { 5035 const u8 *db = &edid_ext[i]; 5036 5037 if (cea_db_is_hdmi_vsdb(db)) 5038 drm_parse_hdmi_vsdb_video(connector, db); 5039 if (cea_db_is_hdmi_forum_vsdb(db)) 5040 drm_parse_hdmi_forum_vsdb(connector, db); 5041 if (cea_db_is_y420cmdb(db)) 5042 drm_parse_y420cmdb_bitmap(connector, db); 5043 if (cea_db_is_vcdb(db)) 5044 drm_parse_vcdb(connector, db); 5045 if (cea_db_is_hdmi_hdr_metadata_block(db)) 5046 drm_parse_hdr_metadata_block(connector, db); 5047 } 5048 } 5049 5050 static 5051 void get_monitor_range(struct detailed_timing *timing, 5052 void *info_monitor_range) 5053 { 5054 struct drm_monitor_range_info *monitor_range = info_monitor_range; 5055 const struct detailed_non_pixel *data = &timing->data.other_data; 5056 const struct detailed_data_monitor_range *range = &data->data.range; 5057 5058 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE)) 5059 return; 5060 5061 /* 5062 * Check for flag range limits only. If flag == 1 then 5063 * no additional timing information provided. 5064 * Default GTF, GTF Secondary curve and CVT are not 5065 * supported 5066 */ 5067 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 5068 return; 5069 5070 monitor_range->min_vfreq = range->min_vfreq; 5071 monitor_range->max_vfreq = range->max_vfreq; 5072 } 5073 5074 static 5075 void drm_get_monitor_range(struct drm_connector *connector, 5076 const struct edid *edid) 5077 { 5078 struct drm_display_info *info = &connector->display_info; 5079 5080 if (!version_greater(edid, 1, 1)) 5081 return; 5082 5083 drm_for_each_detailed_block((u8 *)edid, get_monitor_range, 5084 &info->monitor_range); 5085 5086 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 5087 info->monitor_range.min_vfreq, 5088 info->monitor_range.max_vfreq); 5089 } 5090 5091 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 5092 * all of the values which would have been set from EDID 5093 */ 5094 void 5095 drm_reset_display_info(struct drm_connector *connector) 5096 { 5097 struct drm_display_info *info = &connector->display_info; 5098 5099 info->width_mm = 0; 5100 info->height_mm = 0; 5101 5102 info->bpc = 0; 5103 info->color_formats = 0; 5104 info->cea_rev = 0; 5105 info->max_tmds_clock = 0; 5106 info->dvi_dual = false; 5107 info->is_hdmi = false; 5108 info->has_hdmi_infoframe = false; 5109 info->rgb_quant_range_selectable = false; 5110 memset(&info->hdmi, 0, sizeof(info->hdmi)); 5111 5112 info->non_desktop = 0; 5113 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 5114 } 5115 5116 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) 5117 { 5118 struct drm_display_info *info = &connector->display_info; 5119 5120 u32 quirks = edid_get_quirks(edid); 5121 5122 drm_reset_display_info(connector); 5123 5124 info->width_mm = edid->width_cm * 10; 5125 info->height_mm = edid->height_cm * 10; 5126 5127 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); 5128 5129 drm_get_monitor_range(connector, edid); 5130 5131 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); 5132 5133 if (edid->revision < 3) 5134 return quirks; 5135 5136 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 5137 return quirks; 5138 5139 drm_parse_cea_ext(connector, edid); 5140 5141 /* 5142 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 5143 * 5144 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 5145 * tells us to assume 8 bpc color depth if the EDID doesn't have 5146 * extensions which tell otherwise. 5147 */ 5148 if (info->bpc == 0 && edid->revision == 3 && 5149 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 5150 info->bpc = 8; 5151 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 5152 connector->name, info->bpc); 5153 } 5154 5155 /* Only defined for 1.4 with digital displays */ 5156 if (edid->revision < 4) 5157 return quirks; 5158 5159 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 5160 case DRM_EDID_DIGITAL_DEPTH_6: 5161 info->bpc = 6; 5162 break; 5163 case DRM_EDID_DIGITAL_DEPTH_8: 5164 info->bpc = 8; 5165 break; 5166 case DRM_EDID_DIGITAL_DEPTH_10: 5167 info->bpc = 10; 5168 break; 5169 case DRM_EDID_DIGITAL_DEPTH_12: 5170 info->bpc = 12; 5171 break; 5172 case DRM_EDID_DIGITAL_DEPTH_14: 5173 info->bpc = 14; 5174 break; 5175 case DRM_EDID_DIGITAL_DEPTH_16: 5176 info->bpc = 16; 5177 break; 5178 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 5179 default: 5180 info->bpc = 0; 5181 break; 5182 } 5183 5184 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 5185 connector->name, info->bpc); 5186 5187 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 5188 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 5189 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 5190 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 5191 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 5192 return quirks; 5193 } 5194 5195 static int validate_displayid(u8 *displayid, int length, int idx) 5196 { 5197 int i, dispid_length; 5198 u8 csum = 0; 5199 struct displayid_hdr *base; 5200 5201 base = (struct displayid_hdr *)&displayid[idx]; 5202 5203 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 5204 base->rev, base->bytes, base->prod_id, base->ext_count); 5205 5206 /* +1 for DispID checksum */ 5207 dispid_length = sizeof(*base) + base->bytes + 1; 5208 if (dispid_length > length - idx) 5209 return -EINVAL; 5210 5211 for (i = 0; i < dispid_length; i++) 5212 csum += displayid[idx + i]; 5213 if (csum) { 5214 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum); 5215 return -EINVAL; 5216 } 5217 5218 return 0; 5219 } 5220 5221 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 5222 struct displayid_detailed_timings_1 *timings) 5223 { 5224 struct drm_display_mode *mode; 5225 unsigned pixel_clock = (timings->pixel_clock[0] | 5226 (timings->pixel_clock[1] << 8) | 5227 (timings->pixel_clock[2] << 16)) + 1; 5228 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 5229 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 5230 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 5231 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 5232 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 5233 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 5234 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 5235 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 5236 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 5237 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 5238 5239 mode = drm_mode_create(dev); 5240 if (!mode) 5241 return NULL; 5242 5243 mode->clock = pixel_clock * 10; 5244 mode->hdisplay = hactive; 5245 mode->hsync_start = mode->hdisplay + hsync; 5246 mode->hsync_end = mode->hsync_start + hsync_width; 5247 mode->htotal = mode->hdisplay + hblank; 5248 5249 mode->vdisplay = vactive; 5250 mode->vsync_start = mode->vdisplay + vsync; 5251 mode->vsync_end = mode->vsync_start + vsync_width; 5252 mode->vtotal = mode->vdisplay + vblank; 5253 5254 mode->flags = 0; 5255 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 5256 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 5257 mode->type = DRM_MODE_TYPE_DRIVER; 5258 5259 if (timings->flags & 0x80) 5260 mode->type |= DRM_MODE_TYPE_PREFERRED; 5261 drm_mode_set_name(mode); 5262 5263 return mode; 5264 } 5265 5266 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 5267 struct displayid_block *block) 5268 { 5269 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 5270 int i; 5271 int num_timings; 5272 struct drm_display_mode *newmode; 5273 int num_modes = 0; 5274 /* blocks must be multiple of 20 bytes length */ 5275 if (block->num_bytes % 20) 5276 return 0; 5277 5278 num_timings = block->num_bytes / 20; 5279 for (i = 0; i < num_timings; i++) { 5280 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 5281 5282 newmode = drm_mode_displayid_detailed(connector->dev, timings); 5283 if (!newmode) 5284 continue; 5285 5286 drm_mode_probed_add(connector, newmode); 5287 num_modes++; 5288 } 5289 return num_modes; 5290 } 5291 5292 static int add_displayid_detailed_modes(struct drm_connector *connector, 5293 struct edid *edid) 5294 { 5295 u8 *displayid; 5296 int length, idx; 5297 struct displayid_block *block; 5298 int num_modes = 0; 5299 int ext_index = 0; 5300 5301 for (;;) { 5302 displayid = drm_find_displayid_extension(edid, &length, &idx, 5303 &ext_index); 5304 if (!displayid) 5305 break; 5306 5307 idx += sizeof(struct displayid_hdr); 5308 for_each_displayid_db(displayid, block, idx, length) { 5309 switch (block->tag) { 5310 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5311 num_modes += add_displayid_detailed_1_modes(connector, block); 5312 break; 5313 } 5314 } 5315 } 5316 5317 return num_modes; 5318 } 5319 5320 /** 5321 * drm_add_edid_modes - add modes from EDID data, if available 5322 * @connector: connector we're probing 5323 * @edid: EDID data 5324 * 5325 * Add the specified modes to the connector's mode list. Also fills out the 5326 * &drm_display_info structure and ELD in @connector with any information which 5327 * can be derived from the edid. 5328 * 5329 * Return: The number of modes added or 0 if we couldn't find any. 5330 */ 5331 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 5332 { 5333 int num_modes = 0; 5334 u32 quirks; 5335 5336 if (edid == NULL) { 5337 clear_eld(connector); 5338 return 0; 5339 } 5340 if (!drm_edid_is_valid(edid)) { 5341 clear_eld(connector); 5342 drm_warn(connector->dev, "%s: EDID invalid.\n", 5343 connector->name); 5344 return 0; 5345 } 5346 5347 drm_edid_to_eld(connector, edid); 5348 5349 /* 5350 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 5351 * To avoid multiple parsing of same block, lets parse that map 5352 * from sink info, before parsing CEA modes. 5353 */ 5354 quirks = drm_add_display_info(connector, edid); 5355 5356 /* 5357 * EDID spec says modes should be preferred in this order: 5358 * - preferred detailed mode 5359 * - other detailed modes from base block 5360 * - detailed modes from extension blocks 5361 * - CVT 3-byte code modes 5362 * - standard timing codes 5363 * - established timing codes 5364 * - modes inferred from GTF or CVT range information 5365 * 5366 * We get this pretty much right. 5367 * 5368 * XXX order for additional mode types in extension blocks? 5369 */ 5370 num_modes += add_detailed_modes(connector, edid, quirks); 5371 num_modes += add_cvt_modes(connector, edid); 5372 num_modes += add_standard_modes(connector, edid); 5373 num_modes += add_established_modes(connector, edid); 5374 num_modes += add_cea_modes(connector, edid); 5375 num_modes += add_alternate_cea_modes(connector, edid); 5376 num_modes += add_displayid_detailed_modes(connector, edid); 5377 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 5378 num_modes += add_inferred_modes(connector, edid); 5379 5380 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 5381 edid_fixup_preferred(connector, quirks); 5382 5383 if (quirks & EDID_QUIRK_FORCE_6BPC) 5384 connector->display_info.bpc = 6; 5385 5386 if (quirks & EDID_QUIRK_FORCE_8BPC) 5387 connector->display_info.bpc = 8; 5388 5389 if (quirks & EDID_QUIRK_FORCE_10BPC) 5390 connector->display_info.bpc = 10; 5391 5392 if (quirks & EDID_QUIRK_FORCE_12BPC) 5393 connector->display_info.bpc = 12; 5394 5395 return num_modes; 5396 } 5397 EXPORT_SYMBOL(drm_add_edid_modes); 5398 5399 /** 5400 * drm_add_modes_noedid - add modes for the connectors without EDID 5401 * @connector: connector we're probing 5402 * @hdisplay: the horizontal display limit 5403 * @vdisplay: the vertical display limit 5404 * 5405 * Add the specified modes to the connector's mode list. Only when the 5406 * hdisplay/vdisplay is not beyond the given limit, it will be added. 5407 * 5408 * Return: The number of modes added or 0 if we couldn't find any. 5409 */ 5410 int drm_add_modes_noedid(struct drm_connector *connector, 5411 int hdisplay, int vdisplay) 5412 { 5413 int i, count, num_modes = 0; 5414 struct drm_display_mode *mode; 5415 struct drm_device *dev = connector->dev; 5416 5417 count = ARRAY_SIZE(drm_dmt_modes); 5418 if (hdisplay < 0) 5419 hdisplay = 0; 5420 if (vdisplay < 0) 5421 vdisplay = 0; 5422 5423 for (i = 0; i < count; i++) { 5424 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 5425 5426 if (hdisplay && vdisplay) { 5427 /* 5428 * Only when two are valid, they will be used to check 5429 * whether the mode should be added to the mode list of 5430 * the connector. 5431 */ 5432 if (ptr->hdisplay > hdisplay || 5433 ptr->vdisplay > vdisplay) 5434 continue; 5435 } 5436 if (drm_mode_vrefresh(ptr) > 61) 5437 continue; 5438 mode = drm_mode_duplicate(dev, ptr); 5439 if (mode) { 5440 drm_mode_probed_add(connector, mode); 5441 num_modes++; 5442 } 5443 } 5444 return num_modes; 5445 } 5446 EXPORT_SYMBOL(drm_add_modes_noedid); 5447 5448 /** 5449 * drm_set_preferred_mode - Sets the preferred mode of a connector 5450 * @connector: connector whose mode list should be processed 5451 * @hpref: horizontal resolution of preferred mode 5452 * @vpref: vertical resolution of preferred mode 5453 * 5454 * Marks a mode as preferred if it matches the resolution specified by @hpref 5455 * and @vpref. 5456 */ 5457 void drm_set_preferred_mode(struct drm_connector *connector, 5458 int hpref, int vpref) 5459 { 5460 struct drm_display_mode *mode; 5461 5462 list_for_each_entry(mode, &connector->probed_modes, head) { 5463 if (mode->hdisplay == hpref && 5464 mode->vdisplay == vpref) 5465 mode->type |= DRM_MODE_TYPE_PREFERRED; 5466 } 5467 } 5468 EXPORT_SYMBOL(drm_set_preferred_mode); 5469 5470 static bool is_hdmi2_sink(const struct drm_connector *connector) 5471 { 5472 /* 5473 * FIXME: sil-sii8620 doesn't have a connector around when 5474 * we need one, so we have to be prepared for a NULL connector. 5475 */ 5476 if (!connector) 5477 return true; 5478 5479 return connector->display_info.hdmi.scdc.supported || 5480 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420; 5481 } 5482 5483 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf) 5484 { 5485 return sink_eotf & BIT(output_eotf); 5486 } 5487 5488 /** 5489 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with 5490 * HDR metadata from userspace 5491 * @frame: HDMI DRM infoframe 5492 * @conn_state: Connector state containing HDR metadata 5493 * 5494 * Return: 0 on success or a negative error code on failure. 5495 */ 5496 int 5497 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame, 5498 const struct drm_connector_state *conn_state) 5499 { 5500 struct drm_connector *connector; 5501 struct hdr_output_metadata *hdr_metadata; 5502 int err; 5503 5504 if (!frame || !conn_state) 5505 return -EINVAL; 5506 5507 connector = conn_state->connector; 5508 5509 if (!conn_state->hdr_output_metadata) 5510 return -EINVAL; 5511 5512 hdr_metadata = conn_state->hdr_output_metadata->data; 5513 5514 if (!hdr_metadata || !connector) 5515 return -EINVAL; 5516 5517 /* Sink EOTF is Bit map while infoframe is absolute values */ 5518 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf, 5519 connector->hdr_sink_metadata.hdmi_type1.eotf)) { 5520 DRM_DEBUG_KMS("EOTF Not Supported\n"); 5521 return -EINVAL; 5522 } 5523 5524 err = hdmi_drm_infoframe_init(frame); 5525 if (err < 0) 5526 return err; 5527 5528 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf; 5529 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type; 5530 5531 BUILD_BUG_ON(sizeof(frame->display_primaries) != 5532 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries)); 5533 BUILD_BUG_ON(sizeof(frame->white_point) != 5534 sizeof(hdr_metadata->hdmi_metadata_type1.white_point)); 5535 5536 memcpy(&frame->display_primaries, 5537 &hdr_metadata->hdmi_metadata_type1.display_primaries, 5538 sizeof(frame->display_primaries)); 5539 5540 memcpy(&frame->white_point, 5541 &hdr_metadata->hdmi_metadata_type1.white_point, 5542 sizeof(frame->white_point)); 5543 5544 frame->max_display_mastering_luminance = 5545 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance; 5546 frame->min_display_mastering_luminance = 5547 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance; 5548 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall; 5549 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll; 5550 5551 return 0; 5552 } 5553 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata); 5554 5555 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, 5556 const struct drm_display_mode *mode) 5557 { 5558 bool has_hdmi_infoframe = connector ? 5559 connector->display_info.has_hdmi_infoframe : false; 5560 5561 if (!has_hdmi_infoframe) 5562 return 0; 5563 5564 /* No HDMI VIC when signalling 3D video format */ 5565 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 5566 return 0; 5567 5568 return drm_match_hdmi_mode(mode); 5569 } 5570 5571 static u8 drm_mode_cea_vic(const struct drm_connector *connector, 5572 const struct drm_display_mode *mode) 5573 { 5574 u8 vic; 5575 5576 /* 5577 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5578 * we should send its VIC in vendor infoframes, else send the 5579 * VIC in AVI infoframes. Lets check if this mode is present in 5580 * HDMI 1.4b 4K modes 5581 */ 5582 if (drm_mode_hdmi_vic(connector, mode)) 5583 return 0; 5584 5585 vic = drm_match_cea_mode(mode); 5586 5587 /* 5588 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5589 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5590 * have to make sure we dont break HDMI 1.4 sinks. 5591 */ 5592 if (!is_hdmi2_sink(connector) && vic > 64) 5593 return 0; 5594 5595 return vic; 5596 } 5597 5598 /** 5599 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 5600 * data from a DRM display mode 5601 * @frame: HDMI AVI infoframe 5602 * @connector: the connector 5603 * @mode: DRM display mode 5604 * 5605 * Return: 0 on success or a negative error code on failure. 5606 */ 5607 int 5608 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5609 const struct drm_connector *connector, 5610 const struct drm_display_mode *mode) 5611 { 5612 enum hdmi_picture_aspect picture_aspect; 5613 u8 vic, hdmi_vic; 5614 5615 if (!frame || !mode) 5616 return -EINVAL; 5617 5618 hdmi_avi_infoframe_init(frame); 5619 5620 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5621 frame->pixel_repeat = 1; 5622 5623 vic = drm_mode_cea_vic(connector, mode); 5624 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 5625 5626 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5627 5628 /* 5629 * As some drivers don't support atomic, we can't use connector state. 5630 * So just initialize the frame with default values, just the same way 5631 * as it's done with other properties here. 5632 */ 5633 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 5634 frame->itc = 0; 5635 5636 /* 5637 * Populate picture aspect ratio from either 5638 * user input (if specified) or from the CEA/HDMI mode lists. 5639 */ 5640 picture_aspect = mode->picture_aspect_ratio; 5641 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 5642 if (vic) 5643 picture_aspect = drm_get_cea_aspect_ratio(vic); 5644 else if (hdmi_vic) 5645 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 5646 } 5647 5648 /* 5649 * The infoframe can't convey anything but none, 4:3 5650 * and 16:9, so if the user has asked for anything else 5651 * we can only satisfy it by specifying the right VIC. 5652 */ 5653 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 5654 if (vic) { 5655 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 5656 return -EINVAL; 5657 } else if (hdmi_vic) { 5658 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 5659 return -EINVAL; 5660 } else { 5661 return -EINVAL; 5662 } 5663 5664 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5665 } 5666 5667 frame->video_code = vic; 5668 frame->picture_aspect = picture_aspect; 5669 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5670 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5671 5672 return 0; 5673 } 5674 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 5675 5676 /* HDMI Colorspace Spec Definitions */ 5677 #define FULL_COLORIMETRY_MASK 0x1FF 5678 #define NORMAL_COLORIMETRY_MASK 0x3 5679 #define EXTENDED_COLORIMETRY_MASK 0x7 5680 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF 5681 5682 #define C(x) ((x) << 0) 5683 #define EC(x) ((x) << 2) 5684 #define ACE(x) ((x) << 5) 5685 5686 #define HDMI_COLORIMETRY_NO_DATA 0x0 5687 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0)) 5688 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0)) 5689 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0)) 5690 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0)) 5691 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0)) 5692 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0)) 5693 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0)) 5694 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0)) 5695 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0)) 5696 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0)) 5697 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0)) 5698 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1)) 5699 5700 static const u32 hdmi_colorimetry_val[] = { 5701 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA, 5702 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC, 5703 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC, 5704 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601, 5705 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709, 5706 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601, 5707 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601, 5708 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB, 5709 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC, 5710 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB, 5711 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC, 5712 }; 5713 5714 #undef C 5715 #undef EC 5716 #undef ACE 5717 5718 /** 5719 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe 5720 * colorspace information 5721 * @frame: HDMI AVI infoframe 5722 * @conn_state: connector state 5723 */ 5724 void 5725 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 5726 const struct drm_connector_state *conn_state) 5727 { 5728 u32 colorimetry_val; 5729 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK; 5730 5731 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val)) 5732 colorimetry_val = HDMI_COLORIMETRY_NO_DATA; 5733 else 5734 colorimetry_val = hdmi_colorimetry_val[colorimetry_index]; 5735 5736 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK; 5737 /* 5738 * ToDo: Extend it for ACE formats as well. Modify the infoframe 5739 * structure and extend it in drivers/video/hdmi 5740 */ 5741 frame->extended_colorimetry = (colorimetry_val >> 2) & 5742 EXTENDED_COLORIMETRY_MASK; 5743 } 5744 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace); 5745 5746 /** 5747 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 5748 * quantization range information 5749 * @frame: HDMI AVI infoframe 5750 * @connector: the connector 5751 * @mode: DRM display mode 5752 * @rgb_quant_range: RGB quantization range (Q) 5753 */ 5754 void 5755 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 5756 const struct drm_connector *connector, 5757 const struct drm_display_mode *mode, 5758 enum hdmi_quantization_range rgb_quant_range) 5759 { 5760 const struct drm_display_info *info = &connector->display_info; 5761 5762 /* 5763 * CEA-861: 5764 * "A Source shall not send a non-zero Q value that does not correspond 5765 * to the default RGB Quantization Range for the transmitted Picture 5766 * unless the Sink indicates support for the Q bit in a Video 5767 * Capabilities Data Block." 5768 * 5769 * HDMI 2.0 recommends sending non-zero Q when it does match the 5770 * default RGB quantization range for the mode, even when QS=0. 5771 */ 5772 if (info->rgb_quant_range_selectable || 5773 rgb_quant_range == drm_default_rgb_quant_range(mode)) 5774 frame->quantization_range = rgb_quant_range; 5775 else 5776 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 5777 5778 /* 5779 * CEA-861-F: 5780 * "When transmitting any RGB colorimetry, the Source should set the 5781 * YQ-field to match the RGB Quantization Range being transmitted 5782 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 5783 * set YQ=1) and the Sink shall ignore the YQ-field." 5784 * 5785 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 5786 * by non-zero YQ when receiving RGB. There doesn't seem to be any 5787 * good way to tell which version of CEA-861 the sink supports, so 5788 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 5789 * on on CEA-861-F. 5790 */ 5791 if (!is_hdmi2_sink(connector) || 5792 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 5793 frame->ycc_quantization_range = 5794 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 5795 else 5796 frame->ycc_quantization_range = 5797 HDMI_YCC_QUANTIZATION_RANGE_FULL; 5798 } 5799 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 5800 5801 /** 5802 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe 5803 * bar information 5804 * @frame: HDMI AVI infoframe 5805 * @conn_state: connector state 5806 */ 5807 void 5808 drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame, 5809 const struct drm_connector_state *conn_state) 5810 { 5811 frame->right_bar = conn_state->tv.margins.right; 5812 frame->left_bar = conn_state->tv.margins.left; 5813 frame->top_bar = conn_state->tv.margins.top; 5814 frame->bottom_bar = conn_state->tv.margins.bottom; 5815 } 5816 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars); 5817 5818 static enum hdmi_3d_structure 5819 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5820 { 5821 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5822 5823 switch (layout) { 5824 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5825 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5826 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5827 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5828 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5829 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5830 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5831 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5832 case DRM_MODE_FLAG_3D_L_DEPTH: 5833 return HDMI_3D_STRUCTURE_L_DEPTH; 5834 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5835 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5836 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5837 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5838 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5839 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5840 default: 5841 return HDMI_3D_STRUCTURE_INVALID; 5842 } 5843 } 5844 5845 /** 5846 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 5847 * data from a DRM display mode 5848 * @frame: HDMI vendor infoframe 5849 * @connector: the connector 5850 * @mode: DRM display mode 5851 * 5852 * Note that there's is a need to send HDMI vendor infoframes only when using a 5853 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 5854 * function will return -EINVAL, error that can be safely ignored. 5855 * 5856 * Return: 0 on success or a negative error code on failure. 5857 */ 5858 int 5859 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5860 const struct drm_connector *connector, 5861 const struct drm_display_mode *mode) 5862 { 5863 /* 5864 * FIXME: sil-sii8620 doesn't have a connector around when 5865 * we need one, so we have to be prepared for a NULL connector. 5866 */ 5867 bool has_hdmi_infoframe = connector ? 5868 connector->display_info.has_hdmi_infoframe : false; 5869 int err; 5870 5871 if (!frame || !mode) 5872 return -EINVAL; 5873 5874 if (!has_hdmi_infoframe) 5875 return -EINVAL; 5876 5877 err = hdmi_vendor_infoframe_init(frame); 5878 if (err < 0) 5879 return err; 5880 5881 /* 5882 * Even if it's not absolutely necessary to send the infoframe 5883 * (ie.vic==0 and s3d_struct==0) we will still send it if we 5884 * know that the sink can handle it. This is based on a 5885 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 5886 * have trouble realizing that they shuld switch from 3D to 2D 5887 * mode if the source simply stops sending the infoframe when 5888 * it wants to switch from 3D to 2D. 5889 */ 5890 frame->vic = drm_mode_hdmi_vic(connector, mode); 5891 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5892 5893 return 0; 5894 } 5895 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 5896 5897 static void drm_parse_tiled_block(struct drm_connector *connector, 5898 const struct displayid_block *block) 5899 { 5900 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 5901 u16 w, h; 5902 u8 tile_v_loc, tile_h_loc; 5903 u8 num_v_tile, num_h_tile; 5904 struct drm_tile_group *tg; 5905 5906 w = tile->tile_size[0] | tile->tile_size[1] << 8; 5907 h = tile->tile_size[2] | tile->tile_size[3] << 8; 5908 5909 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 5910 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 5911 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 5912 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 5913 5914 connector->has_tile = true; 5915 if (tile->tile_cap & 0x80) 5916 connector->tile_is_single_monitor = true; 5917 5918 connector->num_h_tile = num_h_tile + 1; 5919 connector->num_v_tile = num_v_tile + 1; 5920 connector->tile_h_loc = tile_h_loc; 5921 connector->tile_v_loc = tile_v_loc; 5922 connector->tile_h_size = w + 1; 5923 connector->tile_v_size = h + 1; 5924 5925 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 5926 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 5927 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 5928 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 5929 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 5930 5931 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 5932 if (!tg) 5933 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 5934 if (!tg) 5935 return; 5936 5937 if (connector->tile_group != tg) { 5938 /* if we haven't got a pointer, 5939 take the reference, drop ref to old tile group */ 5940 if (connector->tile_group) 5941 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5942 connector->tile_group = tg; 5943 } else { 5944 /* if same tile group, then release the ref we just took. */ 5945 drm_mode_put_tile_group(connector->dev, tg); 5946 } 5947 } 5948 5949 static void drm_displayid_parse_tiled(struct drm_connector *connector, 5950 const u8 *displayid, int length, int idx) 5951 { 5952 const struct displayid_block *block; 5953 5954 idx += sizeof(struct displayid_hdr); 5955 for_each_displayid_db(displayid, block, idx, length) { 5956 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", 5957 block->tag, block->rev, block->num_bytes); 5958 5959 switch (block->tag) { 5960 case DATA_BLOCK_TILED_DISPLAY: 5961 drm_parse_tiled_block(connector, block); 5962 break; 5963 default: 5964 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); 5965 break; 5966 } 5967 } 5968 } 5969 5970 void drm_update_tile_info(struct drm_connector *connector, 5971 const struct edid *edid) 5972 { 5973 const void *displayid = NULL; 5974 int ext_index = 0; 5975 int length, idx; 5976 5977 connector->has_tile = false; 5978 for (;;) { 5979 displayid = drm_find_displayid_extension(edid, &length, &idx, 5980 &ext_index); 5981 if (!displayid) 5982 break; 5983 5984 drm_displayid_parse_tiled(connector, displayid, length, idx); 5985 } 5986 5987 if (!connector->has_tile && connector->tile_group) { 5988 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5989 connector->tile_group = NULL; 5990 } 5991 } 5992