1 /* 2 * Copyright © 2009 Keith Packard 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that copyright 7 * notice and this permission notice appear in supporting documentation, and 8 * that the name of the copyright holders not be used in advertising or 9 * publicity pertaining to distribution of the software without specific, 10 * written prior permission. The copyright holders make no representations 11 * about the suitability of this software for any purpose. It is provided "as 12 * is" without express or implied warranty. 13 * 14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20 * OF THIS SOFTWARE. 21 */ 22 23 #include <linux/backlight.h> 24 #include <linux/delay.h> 25 #include <linux/errno.h> 26 #include <linux/i2c.h> 27 #include <linux/init.h> 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/sched.h> 31 #include <linux/seq_file.h> 32 #include <linux/string_helpers.h> 33 #include <linux/dynamic_debug.h> 34 35 #include <drm/display/drm_dp_helper.h> 36 #include <drm/display/drm_dp_mst_helper.h> 37 #include <drm/drm_edid.h> 38 #include <drm/drm_print.h> 39 #include <drm/drm_vblank.h> 40 #include <drm/drm_panel.h> 41 42 #include "drm_dp_helper_internal.h" 43 44 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 45 "DRM_UT_CORE", 46 "DRM_UT_DRIVER", 47 "DRM_UT_KMS", 48 "DRM_UT_PRIME", 49 "DRM_UT_ATOMIC", 50 "DRM_UT_VBL", 51 "DRM_UT_STATE", 52 "DRM_UT_LEASE", 53 "DRM_UT_DP", 54 "DRM_UT_DRMRES"); 55 56 struct dp_aux_backlight { 57 struct backlight_device *base; 58 struct drm_dp_aux *aux; 59 struct drm_edp_backlight_info info; 60 bool enabled; 61 }; 62 63 /** 64 * DOC: dp helpers 65 * 66 * These functions contain some common logic and helpers at various abstraction 67 * levels to deal with Display Port sink devices and related things like DP aux 68 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD 69 * blocks, ... 70 */ 71 72 /* Helpers for DP link training */ 73 static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r) 74 { 75 return link_status[r - DP_LANE0_1_STATUS]; 76 } 77 78 static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE], 79 int lane) 80 { 81 int i = DP_LANE0_1_STATUS + (lane >> 1); 82 int s = (lane & 1) * 4; 83 u8 l = dp_link_status(link_status, i); 84 85 return (l >> s) & 0xf; 86 } 87 88 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 89 int lane_count) 90 { 91 u8 lane_align; 92 u8 lane_status; 93 int lane; 94 95 lane_align = dp_link_status(link_status, 96 DP_LANE_ALIGN_STATUS_UPDATED); 97 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) 98 return false; 99 for (lane = 0; lane < lane_count; lane++) { 100 lane_status = dp_get_lane_status(link_status, lane); 101 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS) 102 return false; 103 } 104 return true; 105 } 106 EXPORT_SYMBOL(drm_dp_channel_eq_ok); 107 108 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 109 int lane_count) 110 { 111 int lane; 112 u8 lane_status; 113 114 for (lane = 0; lane < lane_count; lane++) { 115 lane_status = dp_get_lane_status(link_status, lane); 116 if ((lane_status & DP_LANE_CR_DONE) == 0) 117 return false; 118 } 119 return true; 120 } 121 EXPORT_SYMBOL(drm_dp_clock_recovery_ok); 122 123 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], 124 int lane) 125 { 126 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 127 int s = ((lane & 1) ? 128 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 129 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); 130 u8 l = dp_link_status(link_status, i); 131 132 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; 133 } 134 EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage); 135 136 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], 137 int lane) 138 { 139 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 140 int s = ((lane & 1) ? 141 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : 142 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); 143 u8 l = dp_link_status(link_status, i); 144 145 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; 146 } 147 EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis); 148 149 /* DP 2.0 128b/132b */ 150 u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], 151 int lane) 152 { 153 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 154 int s = ((lane & 1) ? 155 DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT : 156 DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT); 157 u8 l = dp_link_status(link_status, i); 158 159 return (l >> s) & 0xf; 160 } 161 EXPORT_SYMBOL(drm_dp_get_adjust_tx_ffe_preset); 162 163 /* DP 2.0 errata for 128b/132b */ 164 bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE], 165 int lane_count) 166 { 167 u8 lane_align, lane_status; 168 int lane; 169 170 lane_align = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED); 171 if (!(lane_align & DP_INTERLANE_ALIGN_DONE)) 172 return false; 173 174 for (lane = 0; lane < lane_count; lane++) { 175 lane_status = dp_get_lane_status(link_status, lane); 176 if (!(lane_status & DP_LANE_CHANNEL_EQ_DONE)) 177 return false; 178 } 179 return true; 180 } 181 EXPORT_SYMBOL(drm_dp_128b132b_lane_channel_eq_done); 182 183 /* DP 2.0 errata for 128b/132b */ 184 bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE], 185 int lane_count) 186 { 187 u8 lane_status; 188 int lane; 189 190 for (lane = 0; lane < lane_count; lane++) { 191 lane_status = dp_get_lane_status(link_status, lane); 192 if (!(lane_status & DP_LANE_SYMBOL_LOCKED)) 193 return false; 194 } 195 return true; 196 } 197 EXPORT_SYMBOL(drm_dp_128b132b_lane_symbol_locked); 198 199 /* DP 2.0 errata for 128b/132b */ 200 bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]) 201 { 202 u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED); 203 204 return status & DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE; 205 } 206 EXPORT_SYMBOL(drm_dp_128b132b_eq_interlane_align_done); 207 208 /* DP 2.0 errata for 128b/132b */ 209 bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]) 210 { 211 u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED); 212 213 return status & DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE; 214 } 215 EXPORT_SYMBOL(drm_dp_128b132b_cds_interlane_align_done); 216 217 /* DP 2.0 errata for 128b/132b */ 218 bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]) 219 { 220 u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED); 221 222 return status & DP_128B132B_LT_FAILED; 223 } 224 EXPORT_SYMBOL(drm_dp_128b132b_link_training_failed); 225 226 static int __8b10b_clock_recovery_delay_us(const struct drm_dp_aux *aux, u8 rd_interval) 227 { 228 if (rd_interval > 4) 229 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n", 230 aux->name, rd_interval); 231 232 if (rd_interval == 0) 233 return 100; 234 235 return rd_interval * 4 * USEC_PER_MSEC; 236 } 237 238 static int __8b10b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval) 239 { 240 if (rd_interval > 4) 241 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n", 242 aux->name, rd_interval); 243 244 if (rd_interval == 0) 245 return 400; 246 247 return rd_interval * 4 * USEC_PER_MSEC; 248 } 249 250 static int __128b132b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval) 251 { 252 switch (rd_interval) { 253 default: 254 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x\n", 255 aux->name, rd_interval); 256 fallthrough; 257 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US: 258 return 400; 259 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS: 260 return 4000; 261 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_8_MS: 262 return 8000; 263 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_12_MS: 264 return 12000; 265 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_16_MS: 266 return 16000; 267 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_32_MS: 268 return 32000; 269 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_64_MS: 270 return 64000; 271 } 272 } 273 274 /* 275 * The link training delays are different for: 276 * 277 * - Clock recovery vs. channel equalization 278 * - DPRX vs. LTTPR 279 * - 128b/132b vs. 8b/10b 280 * - DPCD rev 1.3 vs. later 281 * 282 * Get the correct delay in us, reading DPCD if necessary. 283 */ 284 static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 285 enum drm_dp_phy dp_phy, bool uhbr, bool cr) 286 { 287 int (*parse)(const struct drm_dp_aux *aux, u8 rd_interval); 288 unsigned int offset; 289 u8 rd_interval, mask; 290 291 if (dp_phy == DP_PHY_DPRX) { 292 if (uhbr) { 293 if (cr) 294 return 100; 295 296 offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL; 297 mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK; 298 parse = __128b132b_channel_eq_delay_us; 299 } else { 300 if (cr && dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 301 return 100; 302 303 offset = DP_TRAINING_AUX_RD_INTERVAL; 304 mask = DP_TRAINING_AUX_RD_MASK; 305 if (cr) 306 parse = __8b10b_clock_recovery_delay_us; 307 else 308 parse = __8b10b_channel_eq_delay_us; 309 } 310 } else { 311 if (uhbr) { 312 offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy); 313 mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK; 314 parse = __128b132b_channel_eq_delay_us; 315 } else { 316 if (cr) 317 return 100; 318 319 offset = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy); 320 mask = DP_TRAINING_AUX_RD_MASK; 321 parse = __8b10b_channel_eq_delay_us; 322 } 323 } 324 325 if (offset < DP_RECEIVER_CAP_SIZE) { 326 rd_interval = dpcd[offset]; 327 } else { 328 if (drm_dp_dpcd_readb(aux, offset, &rd_interval) != 1) { 329 drm_dbg_kms(aux->drm_dev, "%s: failed rd interval read\n", 330 aux->name); 331 /* arbitrary default delay */ 332 return 400; 333 } 334 } 335 336 return parse(aux, rd_interval & mask); 337 } 338 339 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 340 enum drm_dp_phy dp_phy, bool uhbr) 341 { 342 return __read_delay(aux, dpcd, dp_phy, uhbr, true); 343 } 344 EXPORT_SYMBOL(drm_dp_read_clock_recovery_delay); 345 346 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 347 enum drm_dp_phy dp_phy, bool uhbr) 348 { 349 return __read_delay(aux, dpcd, dp_phy, uhbr, false); 350 } 351 EXPORT_SYMBOL(drm_dp_read_channel_eq_delay); 352 353 /* Per DP 2.0 Errata */ 354 int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux) 355 { 356 int unit; 357 u8 val; 358 359 if (drm_dp_dpcd_readb(aux, DP_128B132B_TRAINING_AUX_RD_INTERVAL, &val) != 1) { 360 drm_err(aux->drm_dev, "%s: failed rd interval read\n", 361 aux->name); 362 /* default to max */ 363 val = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK; 364 } 365 366 unit = (val & DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT) ? 1 : 2; 367 val &= DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK; 368 369 return (val + 1) * unit * 1000; 370 } 371 EXPORT_SYMBOL(drm_dp_128b132b_read_aux_rd_interval); 372 373 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, 374 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 375 { 376 u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 377 DP_TRAINING_AUX_RD_MASK; 378 int delay_us; 379 380 if (dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 381 delay_us = 100; 382 else 383 delay_us = __8b10b_clock_recovery_delay_us(aux, rd_interval); 384 385 usleep_range(delay_us, delay_us * 2); 386 } 387 EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay); 388 389 static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 390 u8 rd_interval) 391 { 392 int delay_us = __8b10b_channel_eq_delay_us(aux, rd_interval); 393 394 usleep_range(delay_us, delay_us * 2); 395 } 396 397 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 398 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 399 { 400 __drm_dp_link_train_channel_eq_delay(aux, 401 dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 402 DP_TRAINING_AUX_RD_MASK); 403 } 404 EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay); 405 406 /** 407 * drm_dp_phy_name() - Get the name of the given DP PHY 408 * @dp_phy: The DP PHY identifier 409 * 410 * Given the @dp_phy, get a user friendly name of the DP PHY, either "DPRX" or 411 * "LTTPR <N>", or "<INVALID DP PHY>" on errors. The returned string is always 412 * non-NULL and valid. 413 * 414 * Returns: Name of the DP PHY. 415 */ 416 const char *drm_dp_phy_name(enum drm_dp_phy dp_phy) 417 { 418 static const char * const phy_names[] = { 419 [DP_PHY_DPRX] = "DPRX", 420 [DP_PHY_LTTPR1] = "LTTPR 1", 421 [DP_PHY_LTTPR2] = "LTTPR 2", 422 [DP_PHY_LTTPR3] = "LTTPR 3", 423 [DP_PHY_LTTPR4] = "LTTPR 4", 424 [DP_PHY_LTTPR5] = "LTTPR 5", 425 [DP_PHY_LTTPR6] = "LTTPR 6", 426 [DP_PHY_LTTPR7] = "LTTPR 7", 427 [DP_PHY_LTTPR8] = "LTTPR 8", 428 }; 429 430 if (dp_phy < 0 || dp_phy >= ARRAY_SIZE(phy_names) || 431 WARN_ON(!phy_names[dp_phy])) 432 return "<INVALID DP PHY>"; 433 434 return phy_names[dp_phy]; 435 } 436 EXPORT_SYMBOL(drm_dp_phy_name); 437 438 void drm_dp_lttpr_link_train_clock_recovery_delay(void) 439 { 440 usleep_range(100, 200); 441 } 442 EXPORT_SYMBOL(drm_dp_lttpr_link_train_clock_recovery_delay); 443 444 static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r) 445 { 446 return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1]; 447 } 448 449 void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 450 const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE]) 451 { 452 u8 interval = dp_lttpr_phy_cap(phy_cap, 453 DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) & 454 DP_TRAINING_AUX_RD_MASK; 455 456 __drm_dp_link_train_channel_eq_delay(aux, interval); 457 } 458 EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay); 459 460 u8 drm_dp_link_rate_to_bw_code(int link_rate) 461 { 462 switch (link_rate) { 463 case 1000000: 464 return DP_LINK_BW_10; 465 case 1350000: 466 return DP_LINK_BW_13_5; 467 case 2000000: 468 return DP_LINK_BW_20; 469 default: 470 /* Spec says link_bw = link_rate / 0.27Gbps */ 471 return link_rate / 27000; 472 } 473 } 474 EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code); 475 476 int drm_dp_bw_code_to_link_rate(u8 link_bw) 477 { 478 switch (link_bw) { 479 case DP_LINK_BW_10: 480 return 1000000; 481 case DP_LINK_BW_13_5: 482 return 1350000; 483 case DP_LINK_BW_20: 484 return 2000000; 485 default: 486 /* Spec says link_rate = link_bw * 0.27Gbps */ 487 return link_bw * 27000; 488 } 489 } 490 EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate); 491 492 #define AUX_RETRY_INTERVAL 500 /* us */ 493 494 static inline void 495 drm_dp_dump_access(const struct drm_dp_aux *aux, 496 u8 request, uint offset, void *buffer, int ret) 497 { 498 const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-"; 499 500 if (ret > 0) 501 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d) %*ph\n", 502 aux->name, offset, arrow, ret, min(ret, 20), buffer); 503 else 504 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d)\n", 505 aux->name, offset, arrow, ret); 506 } 507 508 /** 509 * DOC: dp helpers 510 * 511 * The DisplayPort AUX channel is an abstraction to allow generic, driver- 512 * independent access to AUX functionality. Drivers can take advantage of 513 * this by filling in the fields of the drm_dp_aux structure. 514 * 515 * Transactions are described using a hardware-independent drm_dp_aux_msg 516 * structure, which is passed into a driver's .transfer() implementation. 517 * Both native and I2C-over-AUX transactions are supported. 518 */ 519 520 static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request, 521 unsigned int offset, void *buffer, size_t size) 522 { 523 struct drm_dp_aux_msg msg; 524 unsigned int retry, native_reply; 525 int err = 0, ret = 0; 526 527 memset(&msg, 0, sizeof(msg)); 528 msg.address = offset; 529 msg.request = request; 530 msg.buffer = buffer; 531 msg.size = size; 532 533 mutex_lock(&aux->hw_mutex); 534 535 /* 536 * If the device attached to the aux bus is powered down then there's 537 * no reason to attempt a transfer. Error out immediately. 538 */ 539 if (aux->powered_down) { 540 ret = -EBUSY; 541 goto unlock; 542 } 543 544 /* 545 * The specification doesn't give any recommendation on how often to 546 * retry native transactions. We used to retry 7 times like for 547 * aux i2c transactions but real world devices this wasn't 548 * sufficient, bump to 32 which makes Dell 4k monitors happier. 549 */ 550 for (retry = 0; retry < 32; retry++) { 551 if (ret != 0 && ret != -ETIMEDOUT) { 552 usleep_range(AUX_RETRY_INTERVAL, 553 AUX_RETRY_INTERVAL + 100); 554 } 555 556 ret = aux->transfer(aux, &msg); 557 if (ret >= 0) { 558 native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK; 559 if (native_reply == DP_AUX_NATIVE_REPLY_ACK) { 560 if (ret == size) 561 goto unlock; 562 563 ret = -EPROTO; 564 } else 565 ret = -EIO; 566 } 567 568 /* 569 * We want the error we return to be the error we received on 570 * the first transaction, since we may get a different error the 571 * next time we retry 572 */ 573 if (!err) 574 err = ret; 575 } 576 577 drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up. First error: %d\n", 578 aux->name, err); 579 ret = err; 580 581 unlock: 582 mutex_unlock(&aux->hw_mutex); 583 return ret; 584 } 585 586 /** 587 * drm_dp_dpcd_probe() - probe a given DPCD address with a 1-byte read access 588 * @aux: DisplayPort AUX channel (SST) 589 * @offset: address of the register to probe 590 * 591 * Probe the provided DPCD address by reading 1 byte from it. The function can 592 * be used to trigger some side-effect the read access has, like waking up the 593 * sink, without the need for the read-out value. 594 * 595 * Returns 0 if the read access suceeded, or a negative error code on failure. 596 */ 597 int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset) 598 { 599 u8 buffer; 600 int ret; 601 602 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, &buffer, 1); 603 WARN_ON(ret == 0); 604 605 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, &buffer, ret); 606 607 return ret < 0 ? ret : 0; 608 } 609 EXPORT_SYMBOL(drm_dp_dpcd_probe); 610 611 /** 612 * drm_dp_dpcd_set_powered() - Set whether the DP device is powered 613 * @aux: DisplayPort AUX channel; for convenience it's OK to pass NULL here 614 * and the function will be a no-op. 615 * @powered: true if powered; false if not 616 * 617 * If the endpoint device on the DP AUX bus is known to be powered down 618 * then this function can be called to make future transfers fail immediately 619 * instead of needing to time out. 620 * 621 * If this function is never called then a device defaults to being powered. 622 */ 623 void drm_dp_dpcd_set_powered(struct drm_dp_aux *aux, bool powered) 624 { 625 if (!aux) 626 return; 627 628 mutex_lock(&aux->hw_mutex); 629 aux->powered_down = !powered; 630 mutex_unlock(&aux->hw_mutex); 631 } 632 EXPORT_SYMBOL(drm_dp_dpcd_set_powered); 633 634 /** 635 * drm_dp_dpcd_read() - read a series of bytes from the DPCD 636 * @aux: DisplayPort AUX channel (SST or MST) 637 * @offset: address of the (first) register to read 638 * @buffer: buffer to store the register values 639 * @size: number of bytes in @buffer 640 * 641 * Returns the number of bytes transferred on success, or a negative error 642 * code on failure. -EIO is returned if the request was NAKed by the sink or 643 * if the retry count was exceeded. If not all bytes were transferred, this 644 * function returns -EPROTO. Errors from the underlying AUX channel transfer 645 * function, with the exception of -EBUSY (which causes the transaction to 646 * be retried), are propagated to the caller. 647 */ 648 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, 649 void *buffer, size_t size) 650 { 651 int ret; 652 653 /* 654 * HP ZR24w corrupts the first DPCD access after entering power save 655 * mode. Eg. on a read, the entire buffer will be filled with the same 656 * byte. Do a throw away read to avoid corrupting anything we care 657 * about. Afterwards things will work correctly until the monitor 658 * gets woken up and subsequently re-enters power save mode. 659 * 660 * The user pressing any button on the monitor is enough to wake it 661 * up, so there is no particularly good place to do the workaround. 662 * We just have to do it before any DPCD access and hope that the 663 * monitor doesn't power down exactly after the throw away read. 664 */ 665 if (!aux->is_remote) { 666 ret = drm_dp_dpcd_probe(aux, DP_DPCD_REV); 667 if (ret < 0) 668 return ret; 669 } 670 671 if (aux->is_remote) 672 ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size); 673 else 674 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, 675 buffer, size); 676 677 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret); 678 return ret; 679 } 680 EXPORT_SYMBOL(drm_dp_dpcd_read); 681 682 /** 683 * drm_dp_dpcd_write() - write a series of bytes to the DPCD 684 * @aux: DisplayPort AUX channel (SST or MST) 685 * @offset: address of the (first) register to write 686 * @buffer: buffer containing the values to write 687 * @size: number of bytes in @buffer 688 * 689 * Returns the number of bytes transferred on success, or a negative error 690 * code on failure. -EIO is returned if the request was NAKed by the sink or 691 * if the retry count was exceeded. If not all bytes were transferred, this 692 * function returns -EPROTO. Errors from the underlying AUX channel transfer 693 * function, with the exception of -EBUSY (which causes the transaction to 694 * be retried), are propagated to the caller. 695 */ 696 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, 697 void *buffer, size_t size) 698 { 699 int ret; 700 701 if (aux->is_remote) 702 ret = drm_dp_mst_dpcd_write(aux, offset, buffer, size); 703 else 704 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, 705 buffer, size); 706 707 drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret); 708 return ret; 709 } 710 EXPORT_SYMBOL(drm_dp_dpcd_write); 711 712 /** 713 * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207) 714 * @aux: DisplayPort AUX channel 715 * @status: buffer to store the link status in (must be at least 6 bytes) 716 * 717 * Returns the number of bytes transferred on success or a negative error 718 * code on failure. 719 */ 720 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, 721 u8 status[DP_LINK_STATUS_SIZE]) 722 { 723 return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status, 724 DP_LINK_STATUS_SIZE); 725 } 726 EXPORT_SYMBOL(drm_dp_dpcd_read_link_status); 727 728 /** 729 * drm_dp_dpcd_read_phy_link_status - get the link status information for a DP PHY 730 * @aux: DisplayPort AUX channel 731 * @dp_phy: the DP PHY to get the link status for 732 * @link_status: buffer to return the status in 733 * 734 * Fetch the AUX DPCD registers for the DPRX or an LTTPR PHY link status. The 735 * layout of the returned @link_status matches the DPCD register layout of the 736 * DPRX PHY link status. 737 * 738 * Returns 0 if the information was read successfully or a negative error code 739 * on failure. 740 */ 741 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux, 742 enum drm_dp_phy dp_phy, 743 u8 link_status[DP_LINK_STATUS_SIZE]) 744 { 745 int ret; 746 747 if (dp_phy == DP_PHY_DPRX) { 748 ret = drm_dp_dpcd_read(aux, 749 DP_LANE0_1_STATUS, 750 link_status, 751 DP_LINK_STATUS_SIZE); 752 753 if (ret < 0) 754 return ret; 755 756 WARN_ON(ret != DP_LINK_STATUS_SIZE); 757 758 return 0; 759 } 760 761 ret = drm_dp_dpcd_read(aux, 762 DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy), 763 link_status, 764 DP_LINK_STATUS_SIZE - 1); 765 766 if (ret < 0) 767 return ret; 768 769 WARN_ON(ret != DP_LINK_STATUS_SIZE - 1); 770 771 /* Convert the LTTPR to the sink PHY link status layout */ 772 memmove(&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS + 1], 773 &link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS], 774 DP_LINK_STATUS_SIZE - (DP_SINK_STATUS - DP_LANE0_1_STATUS) - 1); 775 link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS] = 0; 776 777 return 0; 778 } 779 EXPORT_SYMBOL(drm_dp_dpcd_read_phy_link_status); 780 781 static bool is_edid_digital_input_dp(const struct edid *edid) 782 { 783 return edid && edid->revision >= 4 && 784 edid->input & DRM_EDID_INPUT_DIGITAL && 785 (edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_DP; 786 } 787 788 /** 789 * drm_dp_downstream_is_type() - is the downstream facing port of certain type? 790 * @dpcd: DisplayPort configuration data 791 * @port_cap: port capabilities 792 * @type: port type to be checked. Can be: 793 * %DP_DS_PORT_TYPE_DP, %DP_DS_PORT_TYPE_VGA, %DP_DS_PORT_TYPE_DVI, 794 * %DP_DS_PORT_TYPE_HDMI, %DP_DS_PORT_TYPE_NON_EDID, 795 * %DP_DS_PORT_TYPE_DP_DUALMODE or %DP_DS_PORT_TYPE_WIRELESS. 796 * 797 * Caveat: Only works with DPCD 1.1+ port caps. 798 * 799 * Returns: whether the downstream facing port matches the type. 800 */ 801 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 802 const u8 port_cap[4], u8 type) 803 { 804 return drm_dp_is_branch(dpcd) && 805 dpcd[DP_DPCD_REV] >= 0x11 && 806 (port_cap[0] & DP_DS_PORT_TYPE_MASK) == type; 807 } 808 EXPORT_SYMBOL(drm_dp_downstream_is_type); 809 810 /** 811 * drm_dp_downstream_is_tmds() - is the downstream facing port TMDS? 812 * @dpcd: DisplayPort configuration data 813 * @port_cap: port capabilities 814 * @edid: EDID 815 * 816 * Returns: whether the downstream facing port is TMDS (HDMI/DVI). 817 */ 818 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 819 const u8 port_cap[4], 820 const struct edid *edid) 821 { 822 if (dpcd[DP_DPCD_REV] < 0x11) { 823 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { 824 case DP_DWN_STRM_PORT_TYPE_TMDS: 825 return true; 826 default: 827 return false; 828 } 829 } 830 831 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 832 case DP_DS_PORT_TYPE_DP_DUALMODE: 833 if (is_edid_digital_input_dp(edid)) 834 return false; 835 fallthrough; 836 case DP_DS_PORT_TYPE_DVI: 837 case DP_DS_PORT_TYPE_HDMI: 838 return true; 839 default: 840 return false; 841 } 842 } 843 EXPORT_SYMBOL(drm_dp_downstream_is_tmds); 844 845 /** 846 * drm_dp_send_real_edid_checksum() - send back real edid checksum value 847 * @aux: DisplayPort AUX channel 848 * @real_edid_checksum: real edid checksum for the last block 849 * 850 * Returns: 851 * True on success 852 */ 853 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux, 854 u8 real_edid_checksum) 855 { 856 u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0; 857 858 if (drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR, 859 &auto_test_req, 1) < 1) { 860 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n", 861 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR); 862 return false; 863 } 864 auto_test_req &= DP_AUTOMATED_TEST_REQUEST; 865 866 if (drm_dp_dpcd_read(aux, DP_TEST_REQUEST, &link_edid_read, 1) < 1) { 867 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n", 868 aux->name, DP_TEST_REQUEST); 869 return false; 870 } 871 link_edid_read &= DP_TEST_LINK_EDID_READ; 872 873 if (!auto_test_req || !link_edid_read) { 874 drm_dbg_kms(aux->drm_dev, "%s: Source DUT does not support TEST_EDID_READ\n", 875 aux->name); 876 return false; 877 } 878 879 if (drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR, 880 &auto_test_req, 1) < 1) { 881 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n", 882 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR); 883 return false; 884 } 885 886 /* send back checksum for the last edid extension block data */ 887 if (drm_dp_dpcd_write(aux, DP_TEST_EDID_CHECKSUM, 888 &real_edid_checksum, 1) < 1) { 889 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n", 890 aux->name, DP_TEST_EDID_CHECKSUM); 891 return false; 892 } 893 894 test_resp |= DP_TEST_EDID_CHECKSUM_WRITE; 895 if (drm_dp_dpcd_write(aux, DP_TEST_RESPONSE, &test_resp, 1) < 1) { 896 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n", 897 aux->name, DP_TEST_RESPONSE); 898 return false; 899 } 900 901 return true; 902 } 903 EXPORT_SYMBOL(drm_dp_send_real_edid_checksum); 904 905 static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 906 { 907 u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK; 908 909 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE && port_count > 4) 910 port_count = 4; 911 912 return port_count; 913 } 914 915 static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux, 916 u8 dpcd[DP_RECEIVER_CAP_SIZE]) 917 { 918 u8 dpcd_ext[DP_RECEIVER_CAP_SIZE]; 919 int ret; 920 921 /* 922 * Prior to DP1.3 the bit represented by 923 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved. 924 * If it is set DP_DPCD_REV at 0000h could be at a value less than 925 * the true capability of the panel. The only way to check is to 926 * then compare 0000h and 2200h. 927 */ 928 if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 929 DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT)) 930 return 0; 931 932 ret = drm_dp_dpcd_read(aux, DP_DP13_DPCD_REV, &dpcd_ext, 933 sizeof(dpcd_ext)); 934 if (ret < 0) 935 return ret; 936 if (ret != sizeof(dpcd_ext)) 937 return -EIO; 938 939 if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) { 940 drm_dbg_kms(aux->drm_dev, 941 "%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n", 942 aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]); 943 return 0; 944 } 945 946 if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext))) 947 return 0; 948 949 drm_dbg_kms(aux->drm_dev, "%s: Base DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd); 950 951 memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext)); 952 953 return 0; 954 } 955 956 /** 957 * drm_dp_read_dpcd_caps() - read DPCD caps and extended DPCD caps if 958 * available 959 * @aux: DisplayPort AUX channel 960 * @dpcd: Buffer to store the resulting DPCD in 961 * 962 * Attempts to read the base DPCD caps for @aux. Additionally, this function 963 * checks for and reads the extended DPRX caps (%DP_DP13_DPCD_REV) if 964 * present. 965 * 966 * Returns: %0 if the DPCD was read successfully, negative error code 967 * otherwise. 968 */ 969 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, 970 u8 dpcd[DP_RECEIVER_CAP_SIZE]) 971 { 972 int ret; 973 974 ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE); 975 if (ret < 0) 976 return ret; 977 if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0) 978 return -EIO; 979 980 ret = drm_dp_read_extended_dpcd_caps(aux, dpcd); 981 if (ret < 0) 982 return ret; 983 984 drm_dbg_kms(aux->drm_dev, "%s: DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd); 985 986 return ret; 987 } 988 EXPORT_SYMBOL(drm_dp_read_dpcd_caps); 989 990 /** 991 * drm_dp_read_downstream_info() - read DPCD downstream port info if available 992 * @aux: DisplayPort AUX channel 993 * @dpcd: A cached copy of the port's DPCD 994 * @downstream_ports: buffer to store the downstream port info in 995 * 996 * See also: 997 * drm_dp_downstream_max_clock() 998 * drm_dp_downstream_max_bpc() 999 * 1000 * Returns: 0 if either the downstream port info was read successfully or 1001 * there was no downstream info to read, or a negative error code otherwise. 1002 */ 1003 int drm_dp_read_downstream_info(struct drm_dp_aux *aux, 1004 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1005 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]) 1006 { 1007 int ret; 1008 u8 len; 1009 1010 memset(downstream_ports, 0, DP_MAX_DOWNSTREAM_PORTS); 1011 1012 /* No downstream info to read */ 1013 if (!drm_dp_is_branch(dpcd) || dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) 1014 return 0; 1015 1016 /* Some branches advertise having 0 downstream ports, despite also advertising they have a 1017 * downstream port present. The DP spec isn't clear on if this is allowed or not, but since 1018 * some branches do it we need to handle it regardless. 1019 */ 1020 len = drm_dp_downstream_port_count(dpcd); 1021 if (!len) 1022 return 0; 1023 1024 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) 1025 len *= 4; 1026 1027 ret = drm_dp_dpcd_read(aux, DP_DOWNSTREAM_PORT_0, downstream_ports, len); 1028 if (ret < 0) 1029 return ret; 1030 if (ret != len) 1031 return -EIO; 1032 1033 drm_dbg_kms(aux->drm_dev, "%s: DPCD DFP: %*ph\n", aux->name, len, downstream_ports); 1034 1035 return 0; 1036 } 1037 EXPORT_SYMBOL(drm_dp_read_downstream_info); 1038 1039 /** 1040 * drm_dp_downstream_max_dotclock() - extract downstream facing port max dot clock 1041 * @dpcd: DisplayPort configuration data 1042 * @port_cap: port capabilities 1043 * 1044 * Returns: Downstream facing port max dot clock in kHz on success, 1045 * or 0 if max clock not defined 1046 */ 1047 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1048 const u8 port_cap[4]) 1049 { 1050 if (!drm_dp_is_branch(dpcd)) 1051 return 0; 1052 1053 if (dpcd[DP_DPCD_REV] < 0x11) 1054 return 0; 1055 1056 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1057 case DP_DS_PORT_TYPE_VGA: 1058 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1059 return 0; 1060 return port_cap[1] * 8000; 1061 default: 1062 return 0; 1063 } 1064 } 1065 EXPORT_SYMBOL(drm_dp_downstream_max_dotclock); 1066 1067 /** 1068 * drm_dp_downstream_max_tmds_clock() - extract downstream facing port max TMDS clock 1069 * @dpcd: DisplayPort configuration data 1070 * @port_cap: port capabilities 1071 * @edid: EDID 1072 * 1073 * Returns: HDMI/DVI downstream facing port max TMDS clock in kHz on success, 1074 * or 0 if max TMDS clock not defined 1075 */ 1076 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1077 const u8 port_cap[4], 1078 const struct edid *edid) 1079 { 1080 if (!drm_dp_is_branch(dpcd)) 1081 return 0; 1082 1083 if (dpcd[DP_DPCD_REV] < 0x11) { 1084 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { 1085 case DP_DWN_STRM_PORT_TYPE_TMDS: 1086 return 165000; 1087 default: 1088 return 0; 1089 } 1090 } 1091 1092 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1093 case DP_DS_PORT_TYPE_DP_DUALMODE: 1094 if (is_edid_digital_input_dp(edid)) 1095 return 0; 1096 /* 1097 * It's left up to the driver to check the 1098 * DP dual mode adapter's max TMDS clock. 1099 * 1100 * Unfortunately it looks like branch devices 1101 * may not fordward that the DP dual mode i2c 1102 * access so we just usually get i2c nak :( 1103 */ 1104 fallthrough; 1105 case DP_DS_PORT_TYPE_HDMI: 1106 /* 1107 * We should perhaps assume 165 MHz when detailed cap 1108 * info is not available. But looks like many typical 1109 * branch devices fall into that category and so we'd 1110 * probably end up with users complaining that they can't 1111 * get high resolution modes with their favorite dongle. 1112 * 1113 * So let's limit to 300 MHz instead since DPCD 1.4 1114 * HDMI 2.0 DFPs are required to have the detailed cap 1115 * info. So it's more likely we're dealing with a HDMI 1.4 1116 * compatible* device here. 1117 */ 1118 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1119 return 300000; 1120 return port_cap[1] * 2500; 1121 case DP_DS_PORT_TYPE_DVI: 1122 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1123 return 165000; 1124 /* FIXME what to do about DVI dual link? */ 1125 return port_cap[1] * 2500; 1126 default: 1127 return 0; 1128 } 1129 } 1130 EXPORT_SYMBOL(drm_dp_downstream_max_tmds_clock); 1131 1132 /** 1133 * drm_dp_downstream_min_tmds_clock() - extract downstream facing port min TMDS clock 1134 * @dpcd: DisplayPort configuration data 1135 * @port_cap: port capabilities 1136 * @edid: EDID 1137 * 1138 * Returns: HDMI/DVI downstream facing port min TMDS clock in kHz on success, 1139 * or 0 if max TMDS clock not defined 1140 */ 1141 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1142 const u8 port_cap[4], 1143 const struct edid *edid) 1144 { 1145 if (!drm_dp_is_branch(dpcd)) 1146 return 0; 1147 1148 if (dpcd[DP_DPCD_REV] < 0x11) { 1149 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { 1150 case DP_DWN_STRM_PORT_TYPE_TMDS: 1151 return 25000; 1152 default: 1153 return 0; 1154 } 1155 } 1156 1157 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1158 case DP_DS_PORT_TYPE_DP_DUALMODE: 1159 if (is_edid_digital_input_dp(edid)) 1160 return 0; 1161 fallthrough; 1162 case DP_DS_PORT_TYPE_DVI: 1163 case DP_DS_PORT_TYPE_HDMI: 1164 /* 1165 * Unclear whether the protocol converter could 1166 * utilize pixel replication. Assume it won't. 1167 */ 1168 return 25000; 1169 default: 1170 return 0; 1171 } 1172 } 1173 EXPORT_SYMBOL(drm_dp_downstream_min_tmds_clock); 1174 1175 /** 1176 * drm_dp_downstream_max_bpc() - extract downstream facing port max 1177 * bits per component 1178 * @dpcd: DisplayPort configuration data 1179 * @port_cap: downstream facing port capabilities 1180 * @edid: EDID 1181 * 1182 * Returns: Max bpc on success or 0 if max bpc not defined 1183 */ 1184 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1185 const u8 port_cap[4], 1186 const struct edid *edid) 1187 { 1188 if (!drm_dp_is_branch(dpcd)) 1189 return 0; 1190 1191 if (dpcd[DP_DPCD_REV] < 0x11) { 1192 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { 1193 case DP_DWN_STRM_PORT_TYPE_DP: 1194 return 0; 1195 default: 1196 return 8; 1197 } 1198 } 1199 1200 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1201 case DP_DS_PORT_TYPE_DP: 1202 return 0; 1203 case DP_DS_PORT_TYPE_DP_DUALMODE: 1204 if (is_edid_digital_input_dp(edid)) 1205 return 0; 1206 fallthrough; 1207 case DP_DS_PORT_TYPE_HDMI: 1208 case DP_DS_PORT_TYPE_DVI: 1209 case DP_DS_PORT_TYPE_VGA: 1210 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1211 return 8; 1212 1213 switch (port_cap[2] & DP_DS_MAX_BPC_MASK) { 1214 case DP_DS_8BPC: 1215 return 8; 1216 case DP_DS_10BPC: 1217 return 10; 1218 case DP_DS_12BPC: 1219 return 12; 1220 case DP_DS_16BPC: 1221 return 16; 1222 default: 1223 return 8; 1224 } 1225 break; 1226 default: 1227 return 8; 1228 } 1229 } 1230 EXPORT_SYMBOL(drm_dp_downstream_max_bpc); 1231 1232 /** 1233 * drm_dp_downstream_420_passthrough() - determine downstream facing port 1234 * YCbCr 4:2:0 pass-through capability 1235 * @dpcd: DisplayPort configuration data 1236 * @port_cap: downstream facing port capabilities 1237 * 1238 * Returns: whether the downstream facing port can pass through YCbCr 4:2:0 1239 */ 1240 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1241 const u8 port_cap[4]) 1242 { 1243 if (!drm_dp_is_branch(dpcd)) 1244 return false; 1245 1246 if (dpcd[DP_DPCD_REV] < 0x13) 1247 return false; 1248 1249 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1250 case DP_DS_PORT_TYPE_DP: 1251 return true; 1252 case DP_DS_PORT_TYPE_HDMI: 1253 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1254 return false; 1255 1256 return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH; 1257 default: 1258 return false; 1259 } 1260 } 1261 EXPORT_SYMBOL(drm_dp_downstream_420_passthrough); 1262 1263 /** 1264 * drm_dp_downstream_444_to_420_conversion() - determine downstream facing port 1265 * YCbCr 4:4:4->4:2:0 conversion capability 1266 * @dpcd: DisplayPort configuration data 1267 * @port_cap: downstream facing port capabilities 1268 * 1269 * Returns: whether the downstream facing port can convert YCbCr 4:4:4 to 4:2:0 1270 */ 1271 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1272 const u8 port_cap[4]) 1273 { 1274 if (!drm_dp_is_branch(dpcd)) 1275 return false; 1276 1277 if (dpcd[DP_DPCD_REV] < 0x13) 1278 return false; 1279 1280 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1281 case DP_DS_PORT_TYPE_HDMI: 1282 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1283 return false; 1284 1285 return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV; 1286 default: 1287 return false; 1288 } 1289 } 1290 EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion); 1291 1292 /** 1293 * drm_dp_downstream_rgb_to_ycbcr_conversion() - determine downstream facing port 1294 * RGB->YCbCr conversion capability 1295 * @dpcd: DisplayPort configuration data 1296 * @port_cap: downstream facing port capabilities 1297 * @color_spc: Colorspace for which conversion cap is sought 1298 * 1299 * Returns: whether the downstream facing port can convert RGB->YCbCr for a given 1300 * colorspace. 1301 */ 1302 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1303 const u8 port_cap[4], 1304 u8 color_spc) 1305 { 1306 if (!drm_dp_is_branch(dpcd)) 1307 return false; 1308 1309 if (dpcd[DP_DPCD_REV] < 0x13) 1310 return false; 1311 1312 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1313 case DP_DS_PORT_TYPE_HDMI: 1314 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1315 return false; 1316 1317 return port_cap[3] & color_spc; 1318 default: 1319 return false; 1320 } 1321 } 1322 EXPORT_SYMBOL(drm_dp_downstream_rgb_to_ycbcr_conversion); 1323 1324 /** 1325 * drm_dp_downstream_mode() - return a mode for downstream facing port 1326 * @dev: DRM device 1327 * @dpcd: DisplayPort configuration data 1328 * @port_cap: port capabilities 1329 * 1330 * Provides a suitable mode for downstream facing ports without EDID. 1331 * 1332 * Returns: A new drm_display_mode on success or NULL on failure 1333 */ 1334 struct drm_display_mode * 1335 drm_dp_downstream_mode(struct drm_device *dev, 1336 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1337 const u8 port_cap[4]) 1338 1339 { 1340 u8 vic; 1341 1342 if (!drm_dp_is_branch(dpcd)) 1343 return NULL; 1344 1345 if (dpcd[DP_DPCD_REV] < 0x11) 1346 return NULL; 1347 1348 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1349 case DP_DS_PORT_TYPE_NON_EDID: 1350 switch (port_cap[0] & DP_DS_NON_EDID_MASK) { 1351 case DP_DS_NON_EDID_720x480i_60: 1352 vic = 6; 1353 break; 1354 case DP_DS_NON_EDID_720x480i_50: 1355 vic = 21; 1356 break; 1357 case DP_DS_NON_EDID_1920x1080i_60: 1358 vic = 5; 1359 break; 1360 case DP_DS_NON_EDID_1920x1080i_50: 1361 vic = 20; 1362 break; 1363 case DP_DS_NON_EDID_1280x720_60: 1364 vic = 4; 1365 break; 1366 case DP_DS_NON_EDID_1280x720_50: 1367 vic = 19; 1368 break; 1369 default: 1370 return NULL; 1371 } 1372 return drm_display_mode_from_cea_vic(dev, vic); 1373 default: 1374 return NULL; 1375 } 1376 } 1377 EXPORT_SYMBOL(drm_dp_downstream_mode); 1378 1379 /** 1380 * drm_dp_downstream_id() - identify branch device 1381 * @aux: DisplayPort AUX channel 1382 * @id: DisplayPort branch device id 1383 * 1384 * Returns branch device id on success or NULL on failure 1385 */ 1386 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]) 1387 { 1388 return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6); 1389 } 1390 EXPORT_SYMBOL(drm_dp_downstream_id); 1391 1392 /** 1393 * drm_dp_downstream_debug() - debug DP branch devices 1394 * @m: pointer for debugfs file 1395 * @dpcd: DisplayPort configuration data 1396 * @port_cap: port capabilities 1397 * @edid: EDID 1398 * @aux: DisplayPort AUX channel 1399 * 1400 */ 1401 void drm_dp_downstream_debug(struct seq_file *m, 1402 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1403 const u8 port_cap[4], 1404 const struct edid *edid, 1405 struct drm_dp_aux *aux) 1406 { 1407 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & 1408 DP_DETAILED_CAP_INFO_AVAILABLE; 1409 int clk; 1410 int bpc; 1411 char id[7]; 1412 int len; 1413 uint8_t rev[2]; 1414 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK; 1415 bool branch_device = drm_dp_is_branch(dpcd); 1416 1417 seq_printf(m, "\tDP branch device present: %s\n", 1418 str_yes_no(branch_device)); 1419 1420 if (!branch_device) 1421 return; 1422 1423 switch (type) { 1424 case DP_DS_PORT_TYPE_DP: 1425 seq_puts(m, "\t\tType: DisplayPort\n"); 1426 break; 1427 case DP_DS_PORT_TYPE_VGA: 1428 seq_puts(m, "\t\tType: VGA\n"); 1429 break; 1430 case DP_DS_PORT_TYPE_DVI: 1431 seq_puts(m, "\t\tType: DVI\n"); 1432 break; 1433 case DP_DS_PORT_TYPE_HDMI: 1434 seq_puts(m, "\t\tType: HDMI\n"); 1435 break; 1436 case DP_DS_PORT_TYPE_NON_EDID: 1437 seq_puts(m, "\t\tType: others without EDID support\n"); 1438 break; 1439 case DP_DS_PORT_TYPE_DP_DUALMODE: 1440 seq_puts(m, "\t\tType: DP++\n"); 1441 break; 1442 case DP_DS_PORT_TYPE_WIRELESS: 1443 seq_puts(m, "\t\tType: Wireless\n"); 1444 break; 1445 default: 1446 seq_puts(m, "\t\tType: N/A\n"); 1447 } 1448 1449 memset(id, 0, sizeof(id)); 1450 drm_dp_downstream_id(aux, id); 1451 seq_printf(m, "\t\tID: %s\n", id); 1452 1453 len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1); 1454 if (len > 0) 1455 seq_printf(m, "\t\tHW: %d.%d\n", 1456 (rev[0] & 0xf0) >> 4, rev[0] & 0xf); 1457 1458 len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, rev, 2); 1459 if (len > 0) 1460 seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]); 1461 1462 if (detailed_cap_info) { 1463 clk = drm_dp_downstream_max_dotclock(dpcd, port_cap); 1464 if (clk > 0) 1465 seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk); 1466 1467 clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, edid); 1468 if (clk > 0) 1469 seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk); 1470 1471 clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, edid); 1472 if (clk > 0) 1473 seq_printf(m, "\t\tMin TMDS clock: %d kHz\n", clk); 1474 1475 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, edid); 1476 1477 if (bpc > 0) 1478 seq_printf(m, "\t\tMax bpc: %d\n", bpc); 1479 } 1480 } 1481 EXPORT_SYMBOL(drm_dp_downstream_debug); 1482 1483 /** 1484 * drm_dp_subconnector_type() - get DP branch device type 1485 * @dpcd: DisplayPort configuration data 1486 * @port_cap: port capabilities 1487 */ 1488 enum drm_mode_subconnector 1489 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1490 const u8 port_cap[4]) 1491 { 1492 int type; 1493 if (!drm_dp_is_branch(dpcd)) 1494 return DRM_MODE_SUBCONNECTOR_Native; 1495 /* DP 1.0 approach */ 1496 if (dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) { 1497 type = dpcd[DP_DOWNSTREAMPORT_PRESENT] & 1498 DP_DWN_STRM_PORT_TYPE_MASK; 1499 1500 switch (type) { 1501 case DP_DWN_STRM_PORT_TYPE_TMDS: 1502 /* Can be HDMI or DVI-D, DVI-D is a safer option */ 1503 return DRM_MODE_SUBCONNECTOR_DVID; 1504 case DP_DWN_STRM_PORT_TYPE_ANALOG: 1505 /* Can be VGA or DVI-A, VGA is more popular */ 1506 return DRM_MODE_SUBCONNECTOR_VGA; 1507 case DP_DWN_STRM_PORT_TYPE_DP: 1508 return DRM_MODE_SUBCONNECTOR_DisplayPort; 1509 case DP_DWN_STRM_PORT_TYPE_OTHER: 1510 default: 1511 return DRM_MODE_SUBCONNECTOR_Unknown; 1512 } 1513 } 1514 type = port_cap[0] & DP_DS_PORT_TYPE_MASK; 1515 1516 switch (type) { 1517 case DP_DS_PORT_TYPE_DP: 1518 case DP_DS_PORT_TYPE_DP_DUALMODE: 1519 return DRM_MODE_SUBCONNECTOR_DisplayPort; 1520 case DP_DS_PORT_TYPE_VGA: 1521 return DRM_MODE_SUBCONNECTOR_VGA; 1522 case DP_DS_PORT_TYPE_DVI: 1523 return DRM_MODE_SUBCONNECTOR_DVID; 1524 case DP_DS_PORT_TYPE_HDMI: 1525 return DRM_MODE_SUBCONNECTOR_HDMIA; 1526 case DP_DS_PORT_TYPE_WIRELESS: 1527 return DRM_MODE_SUBCONNECTOR_Wireless; 1528 case DP_DS_PORT_TYPE_NON_EDID: 1529 default: 1530 return DRM_MODE_SUBCONNECTOR_Unknown; 1531 } 1532 } 1533 EXPORT_SYMBOL(drm_dp_subconnector_type); 1534 1535 /** 1536 * drm_dp_set_subconnector_property - set subconnector for DP connector 1537 * @connector: connector to set property on 1538 * @status: connector status 1539 * @dpcd: DisplayPort configuration data 1540 * @port_cap: port capabilities 1541 * 1542 * Called by a driver on every detect event. 1543 */ 1544 void drm_dp_set_subconnector_property(struct drm_connector *connector, 1545 enum drm_connector_status status, 1546 const u8 *dpcd, 1547 const u8 port_cap[4]) 1548 { 1549 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown; 1550 1551 if (status == connector_status_connected) 1552 subconnector = drm_dp_subconnector_type(dpcd, port_cap); 1553 drm_object_property_set_value(&connector->base, 1554 connector->dev->mode_config.dp_subconnector_property, 1555 subconnector); 1556 } 1557 EXPORT_SYMBOL(drm_dp_set_subconnector_property); 1558 1559 /** 1560 * drm_dp_read_sink_count_cap() - Check whether a given connector has a valid sink 1561 * count 1562 * @connector: The DRM connector to check 1563 * @dpcd: A cached copy of the connector's DPCD RX capabilities 1564 * @desc: A cached copy of the connector's DP descriptor 1565 * 1566 * See also: drm_dp_read_sink_count() 1567 * 1568 * Returns: %True if the (e)DP connector has a valid sink count that should 1569 * be probed, %false otherwise. 1570 */ 1571 bool drm_dp_read_sink_count_cap(struct drm_connector *connector, 1572 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1573 const struct drm_dp_desc *desc) 1574 { 1575 /* Some eDP panels don't set a valid value for the sink count */ 1576 return connector->connector_type != DRM_MODE_CONNECTOR_eDP && 1577 dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 && 1578 dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT && 1579 !drm_dp_has_quirk(desc, DP_DPCD_QUIRK_NO_SINK_COUNT); 1580 } 1581 EXPORT_SYMBOL(drm_dp_read_sink_count_cap); 1582 1583 /** 1584 * drm_dp_read_sink_count() - Retrieve the sink count for a given sink 1585 * @aux: The DP AUX channel to use 1586 * 1587 * See also: drm_dp_read_sink_count_cap() 1588 * 1589 * Returns: The current sink count reported by @aux, or a negative error code 1590 * otherwise. 1591 */ 1592 int drm_dp_read_sink_count(struct drm_dp_aux *aux) 1593 { 1594 u8 count; 1595 int ret; 1596 1597 ret = drm_dp_dpcd_readb(aux, DP_SINK_COUNT, &count); 1598 if (ret < 0) 1599 return ret; 1600 if (ret != 1) 1601 return -EIO; 1602 1603 return DP_GET_SINK_COUNT(count); 1604 } 1605 EXPORT_SYMBOL(drm_dp_read_sink_count); 1606 1607 /* 1608 * I2C-over-AUX implementation 1609 */ 1610 1611 static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter) 1612 { 1613 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 1614 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 1615 I2C_FUNC_SMBUS_BLOCK_PROC_CALL | 1616 I2C_FUNC_10BIT_ADDR; 1617 } 1618 1619 static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg) 1620 { 1621 /* 1622 * In case of i2c defer or short i2c ack reply to a write, 1623 * we need to switch to WRITE_STATUS_UPDATE to drain the 1624 * rest of the message 1625 */ 1626 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) { 1627 msg->request &= DP_AUX_I2C_MOT; 1628 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE; 1629 } 1630 } 1631 1632 #define AUX_PRECHARGE_LEN 10 /* 10 to 16 */ 1633 #define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */ 1634 #define AUX_STOP_LEN 4 1635 #define AUX_CMD_LEN 4 1636 #define AUX_ADDRESS_LEN 20 1637 #define AUX_REPLY_PAD_LEN 4 1638 #define AUX_LENGTH_LEN 8 1639 1640 /* 1641 * Calculate the duration of the AUX request/reply in usec. Gives the 1642 * "best" case estimate, ie. successful while as short as possible. 1643 */ 1644 static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg) 1645 { 1646 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN + 1647 AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN; 1648 1649 if ((msg->request & DP_AUX_I2C_READ) == 0) 1650 len += msg->size * 8; 1651 1652 return len; 1653 } 1654 1655 static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg) 1656 { 1657 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN + 1658 AUX_CMD_LEN + AUX_REPLY_PAD_LEN; 1659 1660 /* 1661 * For read we expect what was asked. For writes there will 1662 * be 0 or 1 data bytes. Assume 0 for the "best" case. 1663 */ 1664 if (msg->request & DP_AUX_I2C_READ) 1665 len += msg->size * 8; 1666 1667 return len; 1668 } 1669 1670 #define I2C_START_LEN 1 1671 #define I2C_STOP_LEN 1 1672 #define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */ 1673 #define I2C_DATA_LEN 9 /* DATA + ACK/NACK */ 1674 1675 /* 1676 * Calculate the length of the i2c transfer in usec, assuming 1677 * the i2c bus speed is as specified. Gives the "worst" 1678 * case estimate, ie. successful while as long as possible. 1679 * Doesn't account the "MOT" bit, and instead assumes each 1680 * message includes a START, ADDRESS and STOP. Neither does it 1681 * account for additional random variables such as clock stretching. 1682 */ 1683 static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg, 1684 int i2c_speed_khz) 1685 { 1686 /* AUX bitrate is 1MHz, i2c bitrate as specified */ 1687 return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN + 1688 msg->size * I2C_DATA_LEN + 1689 I2C_STOP_LEN) * 1000, i2c_speed_khz); 1690 } 1691 1692 /* 1693 * Determine how many retries should be attempted to successfully transfer 1694 * the specified message, based on the estimated durations of the 1695 * i2c and AUX transfers. 1696 */ 1697 static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg, 1698 int i2c_speed_khz) 1699 { 1700 int aux_time_us = drm_dp_aux_req_duration(msg) + 1701 drm_dp_aux_reply_duration(msg); 1702 int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz); 1703 1704 return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL); 1705 } 1706 1707 /* 1708 * FIXME currently assumes 10 kHz as some real world devices seem 1709 * to require it. We should query/set the speed via DPCD if supported. 1710 */ 1711 static int dp_aux_i2c_speed_khz __read_mostly = 10; 1712 module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644); 1713 MODULE_PARM_DESC(dp_aux_i2c_speed_khz, 1714 "Assumed speed of the i2c bus in kHz, (1-400, default 10)"); 1715 1716 /* 1717 * Transfer a single I2C-over-AUX message and handle various error conditions, 1718 * retrying the transaction as appropriate. It is assumed that the 1719 * &drm_dp_aux.transfer function does not modify anything in the msg other than the 1720 * reply field. 1721 * 1722 * Returns bytes transferred on success, or a negative error code on failure. 1723 */ 1724 static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 1725 { 1726 unsigned int retry, defer_i2c; 1727 int ret; 1728 /* 1729 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device 1730 * is required to retry at least seven times upon receiving AUX_DEFER 1731 * before giving up the AUX transaction. 1732 * 1733 * We also try to account for the i2c bus speed. 1734 */ 1735 int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz)); 1736 1737 for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) { 1738 ret = aux->transfer(aux, msg); 1739 if (ret < 0) { 1740 if (ret == -EBUSY) 1741 continue; 1742 1743 /* 1744 * While timeouts can be errors, they're usually normal 1745 * behavior (for instance, when a driver tries to 1746 * communicate with a non-existent DisplayPort device). 1747 * Avoid spamming the kernel log with timeout errors. 1748 */ 1749 if (ret == -ETIMEDOUT) 1750 drm_dbg_kms_ratelimited(aux->drm_dev, "%s: transaction timed out\n", 1751 aux->name); 1752 else 1753 drm_dbg_kms(aux->drm_dev, "%s: transaction failed: %d\n", 1754 aux->name, ret); 1755 return ret; 1756 } 1757 1758 1759 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) { 1760 case DP_AUX_NATIVE_REPLY_ACK: 1761 /* 1762 * For I2C-over-AUX transactions this isn't enough, we 1763 * need to check for the I2C ACK reply. 1764 */ 1765 break; 1766 1767 case DP_AUX_NATIVE_REPLY_NACK: 1768 drm_dbg_kms(aux->drm_dev, "%s: native nack (result=%d, size=%zu)\n", 1769 aux->name, ret, msg->size); 1770 return -EREMOTEIO; 1771 1772 case DP_AUX_NATIVE_REPLY_DEFER: 1773 drm_dbg_kms(aux->drm_dev, "%s: native defer\n", aux->name); 1774 /* 1775 * We could check for I2C bit rate capabilities and if 1776 * available adjust this interval. We could also be 1777 * more careful with DP-to-legacy adapters where a 1778 * long legacy cable may force very low I2C bit rates. 1779 * 1780 * For now just defer for long enough to hopefully be 1781 * safe for all use-cases. 1782 */ 1783 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100); 1784 continue; 1785 1786 default: 1787 drm_err(aux->drm_dev, "%s: invalid native reply %#04x\n", 1788 aux->name, msg->reply); 1789 return -EREMOTEIO; 1790 } 1791 1792 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) { 1793 case DP_AUX_I2C_REPLY_ACK: 1794 /* 1795 * Both native ACK and I2C ACK replies received. We 1796 * can assume the transfer was successful. 1797 */ 1798 if (ret != msg->size) 1799 drm_dp_i2c_msg_write_status_update(msg); 1800 return ret; 1801 1802 case DP_AUX_I2C_REPLY_NACK: 1803 drm_dbg_kms(aux->drm_dev, "%s: I2C nack (result=%d, size=%zu)\n", 1804 aux->name, ret, msg->size); 1805 aux->i2c_nack_count++; 1806 return -EREMOTEIO; 1807 1808 case DP_AUX_I2C_REPLY_DEFER: 1809 drm_dbg_kms(aux->drm_dev, "%s: I2C defer\n", aux->name); 1810 /* DP Compliance Test 4.2.2.5 Requirement: 1811 * Must have at least 7 retries for I2C defers on the 1812 * transaction to pass this test 1813 */ 1814 aux->i2c_defer_count++; 1815 if (defer_i2c < 7) 1816 defer_i2c++; 1817 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100); 1818 drm_dp_i2c_msg_write_status_update(msg); 1819 1820 continue; 1821 1822 default: 1823 drm_err(aux->drm_dev, "%s: invalid I2C reply %#04x\n", 1824 aux->name, msg->reply); 1825 return -EREMOTEIO; 1826 } 1827 } 1828 1829 drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up\n", aux->name); 1830 return -EREMOTEIO; 1831 } 1832 1833 static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg, 1834 const struct i2c_msg *i2c_msg) 1835 { 1836 msg->request = (i2c_msg->flags & I2C_M_RD) ? 1837 DP_AUX_I2C_READ : DP_AUX_I2C_WRITE; 1838 if (!(i2c_msg->flags & I2C_M_STOP)) 1839 msg->request |= DP_AUX_I2C_MOT; 1840 } 1841 1842 /* 1843 * Keep retrying drm_dp_i2c_do_msg until all data has been transferred. 1844 * 1845 * Returns an error code on failure, or a recommended transfer size on success. 1846 */ 1847 static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg) 1848 { 1849 int err, ret = orig_msg->size; 1850 struct drm_dp_aux_msg msg = *orig_msg; 1851 1852 while (msg.size > 0) { 1853 err = drm_dp_i2c_do_msg(aux, &msg); 1854 if (err <= 0) 1855 return err == 0 ? -EPROTO : err; 1856 1857 if (err < msg.size && err < ret) { 1858 drm_dbg_kms(aux->drm_dev, 1859 "%s: Partial I2C reply: requested %zu bytes got %d bytes\n", 1860 aux->name, msg.size, err); 1861 ret = err; 1862 } 1863 1864 msg.size -= err; 1865 msg.buffer += err; 1866 } 1867 1868 return ret; 1869 } 1870 1871 /* 1872 * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX 1873 * packets to be as large as possible. If not, the I2C transactions never 1874 * succeed. Hence the default is maximum. 1875 */ 1876 static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES; 1877 module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644); 1878 MODULE_PARM_DESC(dp_aux_i2c_transfer_size, 1879 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)"); 1880 1881 static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, 1882 int num) 1883 { 1884 struct drm_dp_aux *aux = adapter->algo_data; 1885 unsigned int i, j; 1886 unsigned transfer_size; 1887 struct drm_dp_aux_msg msg; 1888 int err = 0; 1889 1890 if (aux->powered_down) 1891 return -EBUSY; 1892 1893 dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES); 1894 1895 memset(&msg, 0, sizeof(msg)); 1896 1897 for (i = 0; i < num; i++) { 1898 msg.address = msgs[i].addr; 1899 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 1900 /* Send a bare address packet to start the transaction. 1901 * Zero sized messages specify an address only (bare 1902 * address) transaction. 1903 */ 1904 msg.buffer = NULL; 1905 msg.size = 0; 1906 err = drm_dp_i2c_do_msg(aux, &msg); 1907 1908 /* 1909 * Reset msg.request in case in case it got 1910 * changed into a WRITE_STATUS_UPDATE. 1911 */ 1912 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 1913 1914 if (err < 0) 1915 break; 1916 /* We want each transaction to be as large as possible, but 1917 * we'll go to smaller sizes if the hardware gives us a 1918 * short reply. 1919 */ 1920 transfer_size = dp_aux_i2c_transfer_size; 1921 for (j = 0; j < msgs[i].len; j += msg.size) { 1922 msg.buffer = msgs[i].buf + j; 1923 msg.size = min(transfer_size, msgs[i].len - j); 1924 1925 err = drm_dp_i2c_drain_msg(aux, &msg); 1926 1927 /* 1928 * Reset msg.request in case in case it got 1929 * changed into a WRITE_STATUS_UPDATE. 1930 */ 1931 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 1932 1933 if (err < 0) 1934 break; 1935 transfer_size = err; 1936 } 1937 if (err < 0) 1938 break; 1939 } 1940 if (err >= 0) 1941 err = num; 1942 /* Send a bare address packet to close out the transaction. 1943 * Zero sized messages specify an address only (bare 1944 * address) transaction. 1945 */ 1946 msg.request &= ~DP_AUX_I2C_MOT; 1947 msg.buffer = NULL; 1948 msg.size = 0; 1949 (void)drm_dp_i2c_do_msg(aux, &msg); 1950 1951 return err; 1952 } 1953 1954 static const struct i2c_algorithm drm_dp_i2c_algo = { 1955 .functionality = drm_dp_i2c_functionality, 1956 .master_xfer = drm_dp_i2c_xfer, 1957 }; 1958 1959 static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c) 1960 { 1961 return container_of(i2c, struct drm_dp_aux, ddc); 1962 } 1963 1964 static void lock_bus(struct i2c_adapter *i2c, unsigned int flags) 1965 { 1966 mutex_lock(&i2c_to_aux(i2c)->hw_mutex); 1967 } 1968 1969 static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags) 1970 { 1971 return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex); 1972 } 1973 1974 static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags) 1975 { 1976 mutex_unlock(&i2c_to_aux(i2c)->hw_mutex); 1977 } 1978 1979 static const struct i2c_lock_operations drm_dp_i2c_lock_ops = { 1980 .lock_bus = lock_bus, 1981 .trylock_bus = trylock_bus, 1982 .unlock_bus = unlock_bus, 1983 }; 1984 1985 static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc) 1986 { 1987 u8 buf, count; 1988 int ret; 1989 1990 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); 1991 if (ret < 0) 1992 return ret; 1993 1994 WARN_ON(!(buf & DP_TEST_SINK_START)); 1995 1996 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf); 1997 if (ret < 0) 1998 return ret; 1999 2000 count = buf & DP_TEST_COUNT_MASK; 2001 if (count == aux->crc_count) 2002 return -EAGAIN; /* No CRC yet */ 2003 2004 aux->crc_count = count; 2005 2006 /* 2007 * At DP_TEST_CRC_R_CR, there's 6 bytes containing CRC data, 2 bytes 2008 * per component (RGB or CrYCb). 2009 */ 2010 ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR, crc, 6); 2011 if (ret < 0) 2012 return ret; 2013 2014 return 0; 2015 } 2016 2017 static void drm_dp_aux_crc_work(struct work_struct *work) 2018 { 2019 struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux, 2020 crc_work); 2021 struct drm_crtc *crtc; 2022 u8 crc_bytes[6]; 2023 uint32_t crcs[3]; 2024 int ret; 2025 2026 if (WARN_ON(!aux->crtc)) 2027 return; 2028 2029 crtc = aux->crtc; 2030 while (crtc->crc.opened) { 2031 drm_crtc_wait_one_vblank(crtc); 2032 if (!crtc->crc.opened) 2033 break; 2034 2035 ret = drm_dp_aux_get_crc(aux, crc_bytes); 2036 if (ret == -EAGAIN) { 2037 usleep_range(1000, 2000); 2038 ret = drm_dp_aux_get_crc(aux, crc_bytes); 2039 } 2040 2041 if (ret == -EAGAIN) { 2042 drm_dbg_kms(aux->drm_dev, "%s: Get CRC failed after retrying: %d\n", 2043 aux->name, ret); 2044 continue; 2045 } else if (ret) { 2046 drm_dbg_kms(aux->drm_dev, "%s: Failed to get a CRC: %d\n", aux->name, ret); 2047 continue; 2048 } 2049 2050 crcs[0] = crc_bytes[0] | crc_bytes[1] << 8; 2051 crcs[1] = crc_bytes[2] | crc_bytes[3] << 8; 2052 crcs[2] = crc_bytes[4] | crc_bytes[5] << 8; 2053 drm_crtc_add_crc_entry(crtc, false, 0, crcs); 2054 } 2055 } 2056 2057 /** 2058 * drm_dp_remote_aux_init() - minimally initialise a remote aux channel 2059 * @aux: DisplayPort AUX channel 2060 * 2061 * Used for remote aux channel in general. Merely initialize the crc work 2062 * struct. 2063 */ 2064 void drm_dp_remote_aux_init(struct drm_dp_aux *aux) 2065 { 2066 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work); 2067 } 2068 EXPORT_SYMBOL(drm_dp_remote_aux_init); 2069 2070 /** 2071 * drm_dp_aux_init() - minimally initialise an aux channel 2072 * @aux: DisplayPort AUX channel 2073 * 2074 * If you need to use the drm_dp_aux's i2c adapter prior to registering it with 2075 * the outside world, call drm_dp_aux_init() first. For drivers which are 2076 * grandparents to their AUX adapters (e.g. the AUX adapter is parented by a 2077 * &drm_connector), you must still call drm_dp_aux_register() once the connector 2078 * has been registered to allow userspace access to the auxiliary DP channel. 2079 * Likewise, for such drivers you should also assign &drm_dp_aux.drm_dev as 2080 * early as possible so that the &drm_device that corresponds to the AUX adapter 2081 * may be mentioned in debugging output from the DRM DP helpers. 2082 * 2083 * For devices which use a separate platform device for their AUX adapters, this 2084 * may be called as early as required by the driver. 2085 * 2086 */ 2087 void drm_dp_aux_init(struct drm_dp_aux *aux) 2088 { 2089 /* 2090 * witness does not understand mutex_lock_nest_lock() 2091 * order reversal in i915 with this lock 2092 */ 2093 rw_init_flags(&aux->hw_mutex, "drmdp", RWL_NOWITNESS); 2094 rw_init(&aux->cec.lock, "drmcec"); 2095 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work); 2096 2097 aux->ddc.algo = &drm_dp_i2c_algo; 2098 aux->ddc.algo_data = aux; 2099 aux->ddc.retries = 3; 2100 2101 aux->ddc.lock_ops = &drm_dp_i2c_lock_ops; 2102 } 2103 EXPORT_SYMBOL(drm_dp_aux_init); 2104 2105 /** 2106 * drm_dp_aux_register() - initialise and register aux channel 2107 * @aux: DisplayPort AUX channel 2108 * 2109 * Automatically calls drm_dp_aux_init() if this hasn't been done yet. This 2110 * should only be called once the parent of @aux, &drm_dp_aux.dev, is 2111 * initialized. For devices which are grandparents of their AUX channels, 2112 * &drm_dp_aux.dev will typically be the &drm_connector &device which 2113 * corresponds to @aux. For these devices, it's advised to call 2114 * drm_dp_aux_register() in &drm_connector_funcs.late_register, and likewise to 2115 * call drm_dp_aux_unregister() in &drm_connector_funcs.early_unregister. 2116 * Functions which don't follow this will likely Oops when 2117 * %CONFIG_DRM_DP_AUX_CHARDEV is enabled. 2118 * 2119 * For devices where the AUX channel is a device that exists independently of 2120 * the &drm_device that uses it, such as SoCs and bridge devices, it is 2121 * recommended to call drm_dp_aux_register() after a &drm_device has been 2122 * assigned to &drm_dp_aux.drm_dev, and likewise to call 2123 * drm_dp_aux_unregister() once the &drm_device should no longer be associated 2124 * with the AUX channel (e.g. on bridge detach). 2125 * 2126 * Drivers which need to use the aux channel before either of the two points 2127 * mentioned above need to call drm_dp_aux_init() in order to use the AUX 2128 * channel before registration. 2129 * 2130 * Returns 0 on success or a negative error code on failure. 2131 */ 2132 int drm_dp_aux_register(struct drm_dp_aux *aux) 2133 { 2134 int ret; 2135 2136 WARN_ON_ONCE(!aux->drm_dev); 2137 2138 if (!aux->ddc.algo) 2139 drm_dp_aux_init(aux); 2140 2141 #ifdef __linux__ 2142 aux->ddc.class = I2C_CLASS_DDC; 2143 aux->ddc.owner = THIS_MODULE; 2144 aux->ddc.dev.parent = aux->dev; 2145 #endif 2146 2147 strscpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev), 2148 sizeof(aux->ddc.name)); 2149 2150 ret = drm_dp_aux_register_devnode(aux); 2151 if (ret) 2152 return ret; 2153 2154 ret = i2c_add_adapter(&aux->ddc); 2155 if (ret) { 2156 drm_dp_aux_unregister_devnode(aux); 2157 return ret; 2158 } 2159 2160 return 0; 2161 } 2162 EXPORT_SYMBOL(drm_dp_aux_register); 2163 2164 /** 2165 * drm_dp_aux_unregister() - unregister an AUX adapter 2166 * @aux: DisplayPort AUX channel 2167 */ 2168 void drm_dp_aux_unregister(struct drm_dp_aux *aux) 2169 { 2170 drm_dp_aux_unregister_devnode(aux); 2171 i2c_del_adapter(&aux->ddc); 2172 } 2173 EXPORT_SYMBOL(drm_dp_aux_unregister); 2174 2175 #define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x) 2176 2177 /** 2178 * drm_dp_psr_setup_time() - PSR setup in time usec 2179 * @psr_cap: PSR capabilities from DPCD 2180 * 2181 * Returns: 2182 * PSR setup time for the panel in microseconds, negative 2183 * error code on failure. 2184 */ 2185 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]) 2186 { 2187 static const u16 psr_setup_time_us[] = { 2188 PSR_SETUP_TIME(330), 2189 PSR_SETUP_TIME(275), 2190 PSR_SETUP_TIME(220), 2191 PSR_SETUP_TIME(165), 2192 PSR_SETUP_TIME(110), 2193 PSR_SETUP_TIME(55), 2194 PSR_SETUP_TIME(0), 2195 }; 2196 int i; 2197 2198 i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT; 2199 if (i >= ARRAY_SIZE(psr_setup_time_us)) 2200 return -EINVAL; 2201 2202 return psr_setup_time_us[i]; 2203 } 2204 EXPORT_SYMBOL(drm_dp_psr_setup_time); 2205 2206 #undef PSR_SETUP_TIME 2207 2208 /** 2209 * drm_dp_start_crc() - start capture of frame CRCs 2210 * @aux: DisplayPort AUX channel 2211 * @crtc: CRTC displaying the frames whose CRCs are to be captured 2212 * 2213 * Returns 0 on success or a negative error code on failure. 2214 */ 2215 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc) 2216 { 2217 u8 buf; 2218 int ret; 2219 2220 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); 2221 if (ret < 0) 2222 return ret; 2223 2224 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START); 2225 if (ret < 0) 2226 return ret; 2227 2228 aux->crc_count = 0; 2229 aux->crtc = crtc; 2230 schedule_work(&aux->crc_work); 2231 2232 return 0; 2233 } 2234 EXPORT_SYMBOL(drm_dp_start_crc); 2235 2236 /** 2237 * drm_dp_stop_crc() - stop capture of frame CRCs 2238 * @aux: DisplayPort AUX channel 2239 * 2240 * Returns 0 on success or a negative error code on failure. 2241 */ 2242 int drm_dp_stop_crc(struct drm_dp_aux *aux) 2243 { 2244 u8 buf; 2245 int ret; 2246 2247 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); 2248 if (ret < 0) 2249 return ret; 2250 2251 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf & ~DP_TEST_SINK_START); 2252 if (ret < 0) 2253 return ret; 2254 2255 flush_work(&aux->crc_work); 2256 aux->crtc = NULL; 2257 2258 return 0; 2259 } 2260 EXPORT_SYMBOL(drm_dp_stop_crc); 2261 2262 struct dpcd_quirk { 2263 u8 oui[3]; 2264 u8 device_id[6]; 2265 bool is_branch; 2266 u32 quirks; 2267 }; 2268 2269 #define OUI(first, second, third) { (first), (second), (third) } 2270 #define DEVICE_ID(first, second, third, fourth, fifth, sixth) \ 2271 { (first), (second), (third), (fourth), (fifth), (sixth) } 2272 2273 #define DEVICE_ID_ANY DEVICE_ID(0, 0, 0, 0, 0, 0) 2274 2275 static const struct dpcd_quirk dpcd_quirk_list[] = { 2276 /* Analogix 7737 needs reduced M and N at HBR2 link rates */ 2277 { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) }, 2278 /* LG LP140WF6-SPM1 eDP panel */ 2279 { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) }, 2280 /* Apple panels need some additional handling to support PSR */ 2281 { OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) }, 2282 /* CH7511 seems to leave SINK_COUNT zeroed */ 2283 { OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) }, 2284 /* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */ 2285 { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) }, 2286 /* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */ 2287 { OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) }, 2288 }; 2289 2290 #undef OUI 2291 2292 /* 2293 * Get a bit mask of DPCD quirks for the sink/branch device identified by 2294 * ident. The quirk data is shared but it's up to the drivers to act on the 2295 * data. 2296 * 2297 * For now, only the OUI (first three bytes) is used, but this may be extended 2298 * to device identification string and hardware/firmware revisions later. 2299 */ 2300 static u32 2301 drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch) 2302 { 2303 const struct dpcd_quirk *quirk; 2304 u32 quirks = 0; 2305 int i; 2306 u8 any_device[] = DEVICE_ID_ANY; 2307 2308 for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) { 2309 quirk = &dpcd_quirk_list[i]; 2310 2311 if (quirk->is_branch != is_branch) 2312 continue; 2313 2314 if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0) 2315 continue; 2316 2317 if (memcmp(quirk->device_id, any_device, sizeof(any_device)) != 0 && 2318 memcmp(quirk->device_id, ident->device_id, sizeof(ident->device_id)) != 0) 2319 continue; 2320 2321 quirks |= quirk->quirks; 2322 } 2323 2324 return quirks; 2325 } 2326 2327 #undef DEVICE_ID_ANY 2328 #undef DEVICE_ID 2329 2330 /** 2331 * drm_dp_read_desc - read sink/branch descriptor from DPCD 2332 * @aux: DisplayPort AUX channel 2333 * @desc: Device descriptor to fill from DPCD 2334 * @is_branch: true for branch devices, false for sink devices 2335 * 2336 * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the 2337 * identification. 2338 * 2339 * Returns 0 on success or a negative error code on failure. 2340 */ 2341 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, 2342 bool is_branch) 2343 { 2344 struct drm_dp_dpcd_ident *ident = &desc->ident; 2345 unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI; 2346 int ret, dev_id_len; 2347 2348 ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident)); 2349 if (ret < 0) 2350 return ret; 2351 2352 desc->quirks = drm_dp_get_quirks(ident, is_branch); 2353 2354 dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id)); 2355 2356 drm_dbg_kms(aux->drm_dev, 2357 "%s: DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n", 2358 aux->name, is_branch ? "branch" : "sink", 2359 (int)sizeof(ident->oui), ident->oui, dev_id_len, 2360 ident->device_id, ident->hw_rev >> 4, ident->hw_rev & 0xf, 2361 ident->sw_major_rev, ident->sw_minor_rev, desc->quirks); 2362 2363 return 0; 2364 } 2365 EXPORT_SYMBOL(drm_dp_read_desc); 2366 2367 /** 2368 * drm_dp_dsc_sink_max_slice_count() - Get the max slice count 2369 * supported by the DSC sink. 2370 * @dsc_dpcd: DSC capabilities from DPCD 2371 * @is_edp: true if its eDP, false for DP 2372 * 2373 * Read the slice capabilities DPCD register from DSC sink to get 2374 * the maximum slice count supported. This is used to populate 2375 * the DSC parameters in the &struct drm_dsc_config by the driver. 2376 * Driver creates an infoframe using these parameters to populate 2377 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC 2378 * infoframe using the helper function drm_dsc_pps_infoframe_pack() 2379 * 2380 * Returns: 2381 * Maximum slice count supported by DSC sink or 0 its invalid 2382 */ 2383 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 2384 bool is_edp) 2385 { 2386 u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT]; 2387 2388 if (is_edp) { 2389 /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */ 2390 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) 2391 return 4; 2392 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) 2393 return 2; 2394 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) 2395 return 1; 2396 } else { 2397 /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */ 2398 u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT]; 2399 2400 if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK) 2401 return 24; 2402 if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK) 2403 return 20; 2404 if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK) 2405 return 16; 2406 if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK) 2407 return 12; 2408 if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK) 2409 return 10; 2410 if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK) 2411 return 8; 2412 if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK) 2413 return 6; 2414 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) 2415 return 4; 2416 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) 2417 return 2; 2418 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) 2419 return 1; 2420 } 2421 2422 return 0; 2423 } 2424 EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count); 2425 2426 /** 2427 * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits 2428 * @dsc_dpcd: DSC capabilities from DPCD 2429 * 2430 * Read the DSC DPCD register to parse the line buffer depth in bits which is 2431 * number of bits of precision within the decoder line buffer supported by 2432 * the DSC sink. This is used to populate the DSC parameters in the 2433 * &struct drm_dsc_config by the driver. 2434 * Driver creates an infoframe using these parameters to populate 2435 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC 2436 * infoframe using the helper function drm_dsc_pps_infoframe_pack() 2437 * 2438 * Returns: 2439 * Line buffer depth supported by DSC panel or 0 its invalid 2440 */ 2441 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 2442 { 2443 u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT]; 2444 2445 switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) { 2446 case DP_DSC_LINE_BUF_BIT_DEPTH_9: 2447 return 9; 2448 case DP_DSC_LINE_BUF_BIT_DEPTH_10: 2449 return 10; 2450 case DP_DSC_LINE_BUF_BIT_DEPTH_11: 2451 return 11; 2452 case DP_DSC_LINE_BUF_BIT_DEPTH_12: 2453 return 12; 2454 case DP_DSC_LINE_BUF_BIT_DEPTH_13: 2455 return 13; 2456 case DP_DSC_LINE_BUF_BIT_DEPTH_14: 2457 return 14; 2458 case DP_DSC_LINE_BUF_BIT_DEPTH_15: 2459 return 15; 2460 case DP_DSC_LINE_BUF_BIT_DEPTH_16: 2461 return 16; 2462 case DP_DSC_LINE_BUF_BIT_DEPTH_8: 2463 return 8; 2464 } 2465 2466 return 0; 2467 } 2468 EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth); 2469 2470 /** 2471 * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component 2472 * values supported by the DSC sink. 2473 * @dsc_dpcd: DSC capabilities from DPCD 2474 * @dsc_bpc: An array to be filled by this helper with supported 2475 * input bpcs. 2476 * 2477 * Read the DSC DPCD from the sink device to parse the supported bits per 2478 * component values. This is used to populate the DSC parameters 2479 * in the &struct drm_dsc_config by the driver. 2480 * Driver creates an infoframe using these parameters to populate 2481 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC 2482 * infoframe using the helper function drm_dsc_pps_infoframe_pack() 2483 * 2484 * Returns: 2485 * Number of input BPC values parsed from the DPCD 2486 */ 2487 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 2488 u8 dsc_bpc[3]) 2489 { 2490 int num_bpc = 0; 2491 u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT]; 2492 2493 if (color_depth & DP_DSC_12_BPC) 2494 dsc_bpc[num_bpc++] = 12; 2495 if (color_depth & DP_DSC_10_BPC) 2496 dsc_bpc[num_bpc++] = 10; 2497 if (color_depth & DP_DSC_8_BPC) 2498 dsc_bpc[num_bpc++] = 8; 2499 2500 return num_bpc; 2501 } 2502 EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs); 2503 2504 static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux, 2505 const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address, 2506 u8 *buf, int buf_size) 2507 { 2508 /* 2509 * At least the DELL P2715Q monitor with a DPCD_REV < 0x14 returns 2510 * corrupted values when reading from the 0xF0000- range with a block 2511 * size bigger than 1. 2512 */ 2513 int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size; 2514 int offset; 2515 int ret; 2516 2517 for (offset = 0; offset < buf_size; offset += block_size) { 2518 ret = drm_dp_dpcd_read(aux, 2519 address + offset, 2520 &buf[offset], block_size); 2521 if (ret < 0) 2522 return ret; 2523 2524 WARN_ON(ret != block_size); 2525 } 2526 2527 return 0; 2528 } 2529 2530 /** 2531 * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities 2532 * @aux: DisplayPort AUX channel 2533 * @dpcd: DisplayPort configuration data 2534 * @caps: buffer to return the capability info in 2535 * 2536 * Read capabilities common to all LTTPRs. 2537 * 2538 * Returns 0 on success or a negative error code on failure. 2539 */ 2540 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux, 2541 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 2542 u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) 2543 { 2544 return drm_dp_read_lttpr_regs(aux, dpcd, 2545 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV, 2546 caps, DP_LTTPR_COMMON_CAP_SIZE); 2547 } 2548 EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps); 2549 2550 /** 2551 * drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY 2552 * @aux: DisplayPort AUX channel 2553 * @dpcd: DisplayPort configuration data 2554 * @dp_phy: LTTPR PHY to read the capabilities for 2555 * @caps: buffer to return the capability info in 2556 * 2557 * Read the capabilities for the given LTTPR PHY. 2558 * 2559 * Returns 0 on success or a negative error code on failure. 2560 */ 2561 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux, 2562 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 2563 enum drm_dp_phy dp_phy, 2564 u8 caps[DP_LTTPR_PHY_CAP_SIZE]) 2565 { 2566 return drm_dp_read_lttpr_regs(aux, dpcd, 2567 DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy), 2568 caps, DP_LTTPR_PHY_CAP_SIZE); 2569 } 2570 EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps); 2571 2572 static u8 dp_lttpr_common_cap(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE], int r) 2573 { 2574 return caps[r - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 2575 } 2576 2577 /** 2578 * drm_dp_lttpr_count - get the number of detected LTTPRs 2579 * @caps: LTTPR common capabilities 2580 * 2581 * Get the number of detected LTTPRs from the LTTPR common capabilities info. 2582 * 2583 * Returns: 2584 * -ERANGE if more than supported number (8) of LTTPRs are detected 2585 * -EINVAL if the DP_PHY_REPEATER_CNT register contains an invalid value 2586 * otherwise the number of detected LTTPRs 2587 */ 2588 int drm_dp_lttpr_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) 2589 { 2590 u8 count = dp_lttpr_common_cap(caps, DP_PHY_REPEATER_CNT); 2591 2592 switch (hweight8(count)) { 2593 case 0: 2594 return 0; 2595 case 1: 2596 return 8 - ilog2(count); 2597 case 8: 2598 return -ERANGE; 2599 default: 2600 return -EINVAL; 2601 } 2602 } 2603 EXPORT_SYMBOL(drm_dp_lttpr_count); 2604 2605 /** 2606 * drm_dp_lttpr_max_link_rate - get the maximum link rate supported by all LTTPRs 2607 * @caps: LTTPR common capabilities 2608 * 2609 * Returns the maximum link rate supported by all detected LTTPRs. 2610 */ 2611 int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) 2612 { 2613 u8 rate = dp_lttpr_common_cap(caps, DP_MAX_LINK_RATE_PHY_REPEATER); 2614 2615 return drm_dp_bw_code_to_link_rate(rate); 2616 } 2617 EXPORT_SYMBOL(drm_dp_lttpr_max_link_rate); 2618 2619 /** 2620 * drm_dp_lttpr_max_lane_count - get the maximum lane count supported by all LTTPRs 2621 * @caps: LTTPR common capabilities 2622 * 2623 * Returns the maximum lane count supported by all detected LTTPRs. 2624 */ 2625 int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) 2626 { 2627 u8 max_lanes = dp_lttpr_common_cap(caps, DP_MAX_LANE_COUNT_PHY_REPEATER); 2628 2629 return max_lanes & DP_MAX_LANE_COUNT_MASK; 2630 } 2631 EXPORT_SYMBOL(drm_dp_lttpr_max_lane_count); 2632 2633 /** 2634 * drm_dp_lttpr_voltage_swing_level_3_supported - check for LTTPR vswing3 support 2635 * @caps: LTTPR PHY capabilities 2636 * 2637 * Returns true if the @caps for an LTTPR TX PHY indicate support for 2638 * voltage swing level 3. 2639 */ 2640 bool 2641 drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]) 2642 { 2643 u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1); 2644 2645 return txcap & DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED; 2646 } 2647 EXPORT_SYMBOL(drm_dp_lttpr_voltage_swing_level_3_supported); 2648 2649 /** 2650 * drm_dp_lttpr_pre_emphasis_level_3_supported - check for LTTPR preemph3 support 2651 * @caps: LTTPR PHY capabilities 2652 * 2653 * Returns true if the @caps for an LTTPR TX PHY indicate support for 2654 * pre-emphasis level 3. 2655 */ 2656 bool 2657 drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]) 2658 { 2659 u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1); 2660 2661 return txcap & DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED; 2662 } 2663 EXPORT_SYMBOL(drm_dp_lttpr_pre_emphasis_level_3_supported); 2664 2665 /** 2666 * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink. 2667 * @aux: DisplayPort AUX channel 2668 * @data: DP phy compliance test parameters. 2669 * 2670 * Returns 0 on success or a negative error code on failure. 2671 */ 2672 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, 2673 struct drm_dp_phy_test_params *data) 2674 { 2675 int err; 2676 u8 rate, lanes; 2677 2678 err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate); 2679 if (err < 0) 2680 return err; 2681 data->link_rate = drm_dp_bw_code_to_link_rate(rate); 2682 2683 err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes); 2684 if (err < 0) 2685 return err; 2686 data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK; 2687 2688 if (lanes & DP_ENHANCED_FRAME_CAP) 2689 data->enhanced_frame_cap = true; 2690 2691 err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern); 2692 if (err < 0) 2693 return err; 2694 2695 switch (data->phy_pattern) { 2696 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: 2697 err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0, 2698 &data->custom80, sizeof(data->custom80)); 2699 if (err < 0) 2700 return err; 2701 2702 break; 2703 case DP_PHY_TEST_PATTERN_CP2520: 2704 err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET, 2705 &data->hbr2_reset, 2706 sizeof(data->hbr2_reset)); 2707 if (err < 0) 2708 return err; 2709 } 2710 2711 return 0; 2712 } 2713 EXPORT_SYMBOL(drm_dp_get_phy_test_pattern); 2714 2715 /** 2716 * drm_dp_set_phy_test_pattern() - set the pattern to the sink. 2717 * @aux: DisplayPort AUX channel 2718 * @data: DP phy compliance test parameters. 2719 * @dp_rev: DP revision to use for compliance testing 2720 * 2721 * Returns 0 on success or a negative error code on failure. 2722 */ 2723 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux, 2724 struct drm_dp_phy_test_params *data, u8 dp_rev) 2725 { 2726 int err, i; 2727 u8 test_pattern; 2728 2729 test_pattern = data->phy_pattern; 2730 if (dp_rev < 0x12) { 2731 test_pattern = (test_pattern << 2) & 2732 DP_LINK_QUAL_PATTERN_11_MASK; 2733 err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, 2734 test_pattern); 2735 if (err < 0) 2736 return err; 2737 } else { 2738 for (i = 0; i < data->num_lanes; i++) { 2739 err = drm_dp_dpcd_writeb(aux, 2740 DP_LINK_QUAL_LANE0_SET + i, 2741 test_pattern); 2742 if (err < 0) 2743 return err; 2744 } 2745 } 2746 2747 return 0; 2748 } 2749 EXPORT_SYMBOL(drm_dp_set_phy_test_pattern); 2750 2751 static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat) 2752 { 2753 if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED) 2754 return "Invalid"; 2755 2756 switch (pixelformat) { 2757 case DP_PIXELFORMAT_RGB: 2758 return "RGB"; 2759 case DP_PIXELFORMAT_YUV444: 2760 return "YUV444"; 2761 case DP_PIXELFORMAT_YUV422: 2762 return "YUV422"; 2763 case DP_PIXELFORMAT_YUV420: 2764 return "YUV420"; 2765 case DP_PIXELFORMAT_Y_ONLY: 2766 return "Y_ONLY"; 2767 case DP_PIXELFORMAT_RAW: 2768 return "RAW"; 2769 default: 2770 return "Reserved"; 2771 } 2772 } 2773 2774 static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat, 2775 enum dp_colorimetry colorimetry) 2776 { 2777 if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED) 2778 return "Invalid"; 2779 2780 switch (colorimetry) { 2781 case DP_COLORIMETRY_DEFAULT: 2782 switch (pixelformat) { 2783 case DP_PIXELFORMAT_RGB: 2784 return "sRGB"; 2785 case DP_PIXELFORMAT_YUV444: 2786 case DP_PIXELFORMAT_YUV422: 2787 case DP_PIXELFORMAT_YUV420: 2788 return "BT.601"; 2789 case DP_PIXELFORMAT_Y_ONLY: 2790 return "DICOM PS3.14"; 2791 case DP_PIXELFORMAT_RAW: 2792 return "Custom Color Profile"; 2793 default: 2794 return "Reserved"; 2795 } 2796 case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */ 2797 switch (pixelformat) { 2798 case DP_PIXELFORMAT_RGB: 2799 return "Wide Fixed"; 2800 case DP_PIXELFORMAT_YUV444: 2801 case DP_PIXELFORMAT_YUV422: 2802 case DP_PIXELFORMAT_YUV420: 2803 return "BT.709"; 2804 default: 2805 return "Reserved"; 2806 } 2807 case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */ 2808 switch (pixelformat) { 2809 case DP_PIXELFORMAT_RGB: 2810 return "Wide Float"; 2811 case DP_PIXELFORMAT_YUV444: 2812 case DP_PIXELFORMAT_YUV422: 2813 case DP_PIXELFORMAT_YUV420: 2814 return "xvYCC 601"; 2815 default: 2816 return "Reserved"; 2817 } 2818 case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */ 2819 switch (pixelformat) { 2820 case DP_PIXELFORMAT_RGB: 2821 return "OpRGB"; 2822 case DP_PIXELFORMAT_YUV444: 2823 case DP_PIXELFORMAT_YUV422: 2824 case DP_PIXELFORMAT_YUV420: 2825 return "xvYCC 709"; 2826 default: 2827 return "Reserved"; 2828 } 2829 case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */ 2830 switch (pixelformat) { 2831 case DP_PIXELFORMAT_RGB: 2832 return "DCI-P3"; 2833 case DP_PIXELFORMAT_YUV444: 2834 case DP_PIXELFORMAT_YUV422: 2835 case DP_PIXELFORMAT_YUV420: 2836 return "sYCC 601"; 2837 default: 2838 return "Reserved"; 2839 } 2840 case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */ 2841 switch (pixelformat) { 2842 case DP_PIXELFORMAT_RGB: 2843 return "Custom Profile"; 2844 case DP_PIXELFORMAT_YUV444: 2845 case DP_PIXELFORMAT_YUV422: 2846 case DP_PIXELFORMAT_YUV420: 2847 return "OpYCC 601"; 2848 default: 2849 return "Reserved"; 2850 } 2851 case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */ 2852 switch (pixelformat) { 2853 case DP_PIXELFORMAT_RGB: 2854 return "BT.2020 RGB"; 2855 case DP_PIXELFORMAT_YUV444: 2856 case DP_PIXELFORMAT_YUV422: 2857 case DP_PIXELFORMAT_YUV420: 2858 return "BT.2020 CYCC"; 2859 default: 2860 return "Reserved"; 2861 } 2862 case DP_COLORIMETRY_BT2020_YCC: 2863 switch (pixelformat) { 2864 case DP_PIXELFORMAT_YUV444: 2865 case DP_PIXELFORMAT_YUV422: 2866 case DP_PIXELFORMAT_YUV420: 2867 return "BT.2020 YCC"; 2868 default: 2869 return "Reserved"; 2870 } 2871 default: 2872 return "Invalid"; 2873 } 2874 } 2875 2876 static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range) 2877 { 2878 switch (dynamic_range) { 2879 case DP_DYNAMIC_RANGE_VESA: 2880 return "VESA range"; 2881 case DP_DYNAMIC_RANGE_CTA: 2882 return "CTA range"; 2883 default: 2884 return "Invalid"; 2885 } 2886 } 2887 2888 static const char *dp_content_type_get_name(enum dp_content_type content_type) 2889 { 2890 switch (content_type) { 2891 case DP_CONTENT_TYPE_NOT_DEFINED: 2892 return "Not defined"; 2893 case DP_CONTENT_TYPE_GRAPHICS: 2894 return "Graphics"; 2895 case DP_CONTENT_TYPE_PHOTO: 2896 return "Photo"; 2897 case DP_CONTENT_TYPE_VIDEO: 2898 return "Video"; 2899 case DP_CONTENT_TYPE_GAME: 2900 return "Game"; 2901 default: 2902 return "Reserved"; 2903 } 2904 } 2905 2906 void drm_dp_vsc_sdp_log(const char *level, struct device *dev, 2907 const struct drm_dp_vsc_sdp *vsc) 2908 { 2909 #define DP_SDP_LOG(fmt, ...) dev_printk(level, dev, fmt, ##__VA_ARGS__) 2910 DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC", 2911 vsc->revision, vsc->length); 2912 DP_SDP_LOG(" pixelformat: %s\n", 2913 dp_pixelformat_get_name(vsc->pixelformat)); 2914 DP_SDP_LOG(" colorimetry: %s\n", 2915 dp_colorimetry_get_name(vsc->pixelformat, vsc->colorimetry)); 2916 DP_SDP_LOG(" bpc: %u\n", vsc->bpc); 2917 DP_SDP_LOG(" dynamic range: %s\n", 2918 dp_dynamic_range_get_name(vsc->dynamic_range)); 2919 DP_SDP_LOG(" content type: %s\n", 2920 dp_content_type_get_name(vsc->content_type)); 2921 #undef DP_SDP_LOG 2922 } 2923 EXPORT_SYMBOL(drm_dp_vsc_sdp_log); 2924 2925 /** 2926 * drm_dp_get_pcon_max_frl_bw() - maximum frl supported by PCON 2927 * @dpcd: DisplayPort configuration data 2928 * @port_cap: port capabilities 2929 * 2930 * Returns maximum frl bandwidth supported by PCON in GBPS, 2931 * returns 0 if not supported. 2932 */ 2933 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 2934 const u8 port_cap[4]) 2935 { 2936 int bw; 2937 u8 buf; 2938 2939 buf = port_cap[2]; 2940 bw = buf & DP_PCON_MAX_FRL_BW; 2941 2942 switch (bw) { 2943 case DP_PCON_MAX_9GBPS: 2944 return 9; 2945 case DP_PCON_MAX_18GBPS: 2946 return 18; 2947 case DP_PCON_MAX_24GBPS: 2948 return 24; 2949 case DP_PCON_MAX_32GBPS: 2950 return 32; 2951 case DP_PCON_MAX_40GBPS: 2952 return 40; 2953 case DP_PCON_MAX_48GBPS: 2954 return 48; 2955 case DP_PCON_MAX_0GBPS: 2956 default: 2957 return 0; 2958 } 2959 2960 return 0; 2961 } 2962 EXPORT_SYMBOL(drm_dp_get_pcon_max_frl_bw); 2963 2964 /** 2965 * drm_dp_pcon_frl_prepare() - Prepare PCON for FRL. 2966 * @aux: DisplayPort AUX channel 2967 * @enable_frl_ready_hpd: Configure DP_PCON_ENABLE_HPD_READY. 2968 * 2969 * Returns 0 if success, else returns negative error code. 2970 */ 2971 int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd) 2972 { 2973 int ret; 2974 u8 buf = DP_PCON_ENABLE_SOURCE_CTL_MODE | 2975 DP_PCON_ENABLE_LINK_FRL_MODE; 2976 2977 if (enable_frl_ready_hpd) 2978 buf |= DP_PCON_ENABLE_HPD_READY; 2979 2980 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 2981 2982 return ret; 2983 } 2984 EXPORT_SYMBOL(drm_dp_pcon_frl_prepare); 2985 2986 /** 2987 * drm_dp_pcon_is_frl_ready() - Is PCON ready for FRL 2988 * @aux: DisplayPort AUX channel 2989 * 2990 * Returns true if success, else returns false. 2991 */ 2992 bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux) 2993 { 2994 int ret; 2995 u8 buf; 2996 2997 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf); 2998 if (ret < 0) 2999 return false; 3000 3001 if (buf & DP_PCON_FRL_READY) 3002 return true; 3003 3004 return false; 3005 } 3006 EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready); 3007 3008 /** 3009 * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1 3010 * @aux: DisplayPort AUX channel 3011 * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink 3012 * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential. 3013 * In Concurrent Mode, the FRL link bring up can be done along with 3014 * DP Link training. In Sequential mode, the FRL link bring up is done prior to 3015 * the DP Link training. 3016 * 3017 * Returns 0 if success, else returns negative error code. 3018 */ 3019 3020 int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, 3021 u8 frl_mode) 3022 { 3023 int ret; 3024 u8 buf; 3025 3026 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf); 3027 if (ret < 0) 3028 return ret; 3029 3030 if (frl_mode == DP_PCON_ENABLE_CONCURRENT_LINK) 3031 buf |= DP_PCON_ENABLE_CONCURRENT_LINK; 3032 else 3033 buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK; 3034 3035 switch (max_frl_gbps) { 3036 case 9: 3037 buf |= DP_PCON_ENABLE_MAX_BW_9GBPS; 3038 break; 3039 case 18: 3040 buf |= DP_PCON_ENABLE_MAX_BW_18GBPS; 3041 break; 3042 case 24: 3043 buf |= DP_PCON_ENABLE_MAX_BW_24GBPS; 3044 break; 3045 case 32: 3046 buf |= DP_PCON_ENABLE_MAX_BW_32GBPS; 3047 break; 3048 case 40: 3049 buf |= DP_PCON_ENABLE_MAX_BW_40GBPS; 3050 break; 3051 case 48: 3052 buf |= DP_PCON_ENABLE_MAX_BW_48GBPS; 3053 break; 3054 case 0: 3055 buf |= DP_PCON_ENABLE_MAX_BW_0GBPS; 3056 break; 3057 default: 3058 return -EINVAL; 3059 } 3060 3061 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 3062 if (ret < 0) 3063 return ret; 3064 3065 return 0; 3066 } 3067 EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1); 3068 3069 /** 3070 * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2 3071 * @aux: DisplayPort AUX channel 3072 * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink 3073 * @frl_type : FRL training type, can be Extended, or Normal. 3074 * In Normal FRL training, the PCON tries each frl bw from the max_frl_mask 3075 * starting from min, and stops when link training is successful. In Extended 3076 * FRL training, all frl bw selected in the mask are trained by the PCON. 3077 * 3078 * Returns 0 if success, else returns negative error code. 3079 */ 3080 int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, 3081 u8 frl_type) 3082 { 3083 int ret; 3084 u8 buf = max_frl_mask; 3085 3086 if (frl_type == DP_PCON_FRL_LINK_TRAIN_EXTENDED) 3087 buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED; 3088 else 3089 buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED; 3090 3091 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf); 3092 if (ret < 0) 3093 return ret; 3094 3095 return 0; 3096 } 3097 EXPORT_SYMBOL(drm_dp_pcon_frl_configure_2); 3098 3099 /** 3100 * drm_dp_pcon_reset_frl_config() - Re-Set HDMI Link configuration. 3101 * @aux: DisplayPort AUX channel 3102 * 3103 * Returns 0 if success, else returns negative error code. 3104 */ 3105 int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux) 3106 { 3107 int ret; 3108 3109 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, 0x0); 3110 if (ret < 0) 3111 return ret; 3112 3113 return 0; 3114 } 3115 EXPORT_SYMBOL(drm_dp_pcon_reset_frl_config); 3116 3117 /** 3118 * drm_dp_pcon_frl_enable() - Enable HDMI link through FRL 3119 * @aux: DisplayPort AUX channel 3120 * 3121 * Returns 0 if success, else returns negative error code. 3122 */ 3123 int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux) 3124 { 3125 int ret; 3126 u8 buf = 0; 3127 3128 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf); 3129 if (ret < 0) 3130 return ret; 3131 if (!(buf & DP_PCON_ENABLE_SOURCE_CTL_MODE)) { 3132 drm_dbg_kms(aux->drm_dev, "%s: PCON in Autonomous mode, can't enable FRL\n", 3133 aux->name); 3134 return -EINVAL; 3135 } 3136 buf |= DP_PCON_ENABLE_HDMI_LINK; 3137 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 3138 if (ret < 0) 3139 return ret; 3140 3141 return 0; 3142 } 3143 EXPORT_SYMBOL(drm_dp_pcon_frl_enable); 3144 3145 /** 3146 * drm_dp_pcon_hdmi_link_active() - check if the PCON HDMI LINK status is active. 3147 * @aux: DisplayPort AUX channel 3148 * 3149 * Returns true if link is active else returns false. 3150 */ 3151 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux) 3152 { 3153 u8 buf; 3154 int ret; 3155 3156 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf); 3157 if (ret < 0) 3158 return false; 3159 3160 return buf & DP_PCON_HDMI_TX_LINK_ACTIVE; 3161 } 3162 EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_active); 3163 3164 /** 3165 * drm_dp_pcon_hdmi_link_mode() - get the PCON HDMI LINK MODE 3166 * @aux: DisplayPort AUX channel 3167 * @frl_trained_mask: pointer to store bitmask of the trained bw configuration. 3168 * Valid only if the MODE returned is FRL. For Normal Link training mode 3169 * only 1 of the bits will be set, but in case of Extended mode, more than 3170 * one bits can be set. 3171 * 3172 * Returns the link mode : TMDS or FRL on success, else returns negative error 3173 * code. 3174 */ 3175 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask) 3176 { 3177 u8 buf; 3178 int mode; 3179 int ret; 3180 3181 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_POST_FRL_STATUS, &buf); 3182 if (ret < 0) 3183 return ret; 3184 3185 mode = buf & DP_PCON_HDMI_LINK_MODE; 3186 3187 if (frl_trained_mask && DP_PCON_HDMI_MODE_FRL == mode) 3188 *frl_trained_mask = (buf & DP_PCON_HDMI_FRL_TRAINED_BW) >> 1; 3189 3190 return mode; 3191 } 3192 EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_mode); 3193 3194 /** 3195 * drm_dp_pcon_hdmi_frl_link_error_count() - print the error count per lane 3196 * during link failure between PCON and HDMI sink 3197 * @aux: DisplayPort AUX channel 3198 * @connector: DRM connector 3199 * code. 3200 **/ 3201 3202 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux, 3203 struct drm_connector *connector) 3204 { 3205 u8 buf, error_count; 3206 int i, num_error; 3207 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3208 3209 for (i = 0; i < hdmi->max_lanes; i++) { 3210 if (drm_dp_dpcd_readb(aux, DP_PCON_HDMI_ERROR_STATUS_LN0 + i, &buf) < 0) 3211 return; 3212 3213 error_count = buf & DP_PCON_HDMI_ERROR_COUNT_MASK; 3214 switch (error_count) { 3215 case DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS: 3216 num_error = 100; 3217 break; 3218 case DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS: 3219 num_error = 10; 3220 break; 3221 case DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS: 3222 num_error = 3; 3223 break; 3224 default: 3225 num_error = 0; 3226 } 3227 3228 drm_err(aux->drm_dev, "%s: More than %d errors since the last read for lane %d", 3229 aux->name, num_error, i); 3230 } 3231 } 3232 EXPORT_SYMBOL(drm_dp_pcon_hdmi_frl_link_error_count); 3233 3234 /* 3235 * drm_dp_pcon_enc_is_dsc_1_2 - Does PCON Encoder supports DSC 1.2 3236 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder 3237 * 3238 * Returns true is PCON encoder is DSC 1.2 else returns false. 3239 */ 3240 bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]) 3241 { 3242 u8 buf; 3243 u8 major_v, minor_v; 3244 3245 buf = pcon_dsc_dpcd[DP_PCON_DSC_VERSION - DP_PCON_DSC_ENCODER]; 3246 major_v = (buf & DP_PCON_DSC_MAJOR_MASK) >> DP_PCON_DSC_MAJOR_SHIFT; 3247 minor_v = (buf & DP_PCON_DSC_MINOR_MASK) >> DP_PCON_DSC_MINOR_SHIFT; 3248 3249 if (major_v == 1 && minor_v == 2) 3250 return true; 3251 3252 return false; 3253 } 3254 EXPORT_SYMBOL(drm_dp_pcon_enc_is_dsc_1_2); 3255 3256 /* 3257 * drm_dp_pcon_dsc_max_slices - Get max slices supported by PCON DSC Encoder 3258 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder 3259 * 3260 * Returns maximum no. of slices supported by the PCON DSC Encoder. 3261 */ 3262 int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]) 3263 { 3264 u8 slice_cap1, slice_cap2; 3265 3266 slice_cap1 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_1 - DP_PCON_DSC_ENCODER]; 3267 slice_cap2 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_2 - DP_PCON_DSC_ENCODER]; 3268 3269 if (slice_cap2 & DP_PCON_DSC_24_PER_DSC_ENC) 3270 return 24; 3271 if (slice_cap2 & DP_PCON_DSC_20_PER_DSC_ENC) 3272 return 20; 3273 if (slice_cap2 & DP_PCON_DSC_16_PER_DSC_ENC) 3274 return 16; 3275 if (slice_cap1 & DP_PCON_DSC_12_PER_DSC_ENC) 3276 return 12; 3277 if (slice_cap1 & DP_PCON_DSC_10_PER_DSC_ENC) 3278 return 10; 3279 if (slice_cap1 & DP_PCON_DSC_8_PER_DSC_ENC) 3280 return 8; 3281 if (slice_cap1 & DP_PCON_DSC_6_PER_DSC_ENC) 3282 return 6; 3283 if (slice_cap1 & DP_PCON_DSC_4_PER_DSC_ENC) 3284 return 4; 3285 if (slice_cap1 & DP_PCON_DSC_2_PER_DSC_ENC) 3286 return 2; 3287 if (slice_cap1 & DP_PCON_DSC_1_PER_DSC_ENC) 3288 return 1; 3289 3290 return 0; 3291 } 3292 EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slices); 3293 3294 /* 3295 * drm_dp_pcon_dsc_max_slice_width() - Get max slice width for Pcon DSC encoder 3296 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder 3297 * 3298 * Returns maximum width of the slices in pixel width i.e. no. of pixels x 320. 3299 */ 3300 int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]) 3301 { 3302 u8 buf; 3303 3304 buf = pcon_dsc_dpcd[DP_PCON_DSC_MAX_SLICE_WIDTH - DP_PCON_DSC_ENCODER]; 3305 3306 return buf * DP_DSC_SLICE_WIDTH_MULTIPLIER; 3307 } 3308 EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slice_width); 3309 3310 /* 3311 * drm_dp_pcon_dsc_bpp_incr() - Get bits per pixel increment for PCON DSC encoder 3312 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder 3313 * 3314 * Returns the bpp precision supported by the PCON encoder. 3315 */ 3316 int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]) 3317 { 3318 u8 buf; 3319 3320 buf = pcon_dsc_dpcd[DP_PCON_DSC_BPP_INCR - DP_PCON_DSC_ENCODER]; 3321 3322 switch (buf & DP_PCON_DSC_BPP_INCR_MASK) { 3323 case DP_PCON_DSC_ONE_16TH_BPP: 3324 return 16; 3325 case DP_PCON_DSC_ONE_8TH_BPP: 3326 return 8; 3327 case DP_PCON_DSC_ONE_4TH_BPP: 3328 return 4; 3329 case DP_PCON_DSC_ONE_HALF_BPP: 3330 return 2; 3331 case DP_PCON_DSC_ONE_BPP: 3332 return 1; 3333 } 3334 3335 return 0; 3336 } 3337 EXPORT_SYMBOL(drm_dp_pcon_dsc_bpp_incr); 3338 3339 static 3340 int drm_dp_pcon_configure_dsc_enc(struct drm_dp_aux *aux, u8 pps_buf_config) 3341 { 3342 u8 buf; 3343 int ret; 3344 3345 ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf); 3346 if (ret < 0) 3347 return ret; 3348 3349 buf |= DP_PCON_ENABLE_DSC_ENCODER; 3350 3351 if (pps_buf_config <= DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER) { 3352 buf &= ~DP_PCON_ENCODER_PPS_OVERRIDE_MASK; 3353 buf |= pps_buf_config << 2; 3354 } 3355 3356 ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf); 3357 if (ret < 0) 3358 return ret; 3359 3360 return 0; 3361 } 3362 3363 /** 3364 * drm_dp_pcon_pps_default() - Let PCON fill the default pps parameters 3365 * for DSC1.2 between PCON & HDMI2.1 sink 3366 * @aux: DisplayPort AUX channel 3367 * 3368 * Returns 0 on success, else returns negative error code. 3369 */ 3370 int drm_dp_pcon_pps_default(struct drm_dp_aux *aux) 3371 { 3372 int ret; 3373 3374 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_DISABLED); 3375 if (ret < 0) 3376 return ret; 3377 3378 return 0; 3379 } 3380 EXPORT_SYMBOL(drm_dp_pcon_pps_default); 3381 3382 /** 3383 * drm_dp_pcon_pps_override_buf() - Configure PPS encoder override buffer for 3384 * HDMI sink 3385 * @aux: DisplayPort AUX channel 3386 * @pps_buf: 128 bytes to be written into PPS buffer for HDMI sink by PCON. 3387 * 3388 * Returns 0 on success, else returns negative error code. 3389 */ 3390 int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]) 3391 { 3392 int ret; 3393 3394 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVERRIDE_BASE, &pps_buf, 128); 3395 if (ret < 0) 3396 return ret; 3397 3398 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER); 3399 if (ret < 0) 3400 return ret; 3401 3402 return 0; 3403 } 3404 EXPORT_SYMBOL(drm_dp_pcon_pps_override_buf); 3405 3406 /* 3407 * drm_dp_pcon_pps_override_param() - Write PPS parameters to DSC encoder 3408 * override registers 3409 * @aux: DisplayPort AUX channel 3410 * @pps_param: 3 Parameters (2 Bytes each) : Slice Width, Slice Height, 3411 * bits_per_pixel. 3412 * 3413 * Returns 0 on success, else returns negative error code. 3414 */ 3415 int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]) 3416 { 3417 int ret; 3418 3419 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT, &pps_param[0], 2); 3420 if (ret < 0) 3421 return ret; 3422 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH, &pps_param[2], 2); 3423 if (ret < 0) 3424 return ret; 3425 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_BPP, &pps_param[4], 2); 3426 if (ret < 0) 3427 return ret; 3428 3429 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER); 3430 if (ret < 0) 3431 return ret; 3432 3433 return 0; 3434 } 3435 EXPORT_SYMBOL(drm_dp_pcon_pps_override_param); 3436 3437 /* 3438 * drm_dp_pcon_convert_rgb_to_ycbcr() - Configure the PCon to convert RGB to Ycbcr 3439 * @aux: displayPort AUX channel 3440 * @color_spc: Color-space/s for which conversion is to be enabled, 0 for disable. 3441 * 3442 * Returns 0 on success, else returns negative error code. 3443 */ 3444 int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc) 3445 { 3446 int ret; 3447 u8 buf; 3448 3449 ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf); 3450 if (ret < 0) 3451 return ret; 3452 3453 if (color_spc & DP_CONVERSION_RGB_YCBCR_MASK) 3454 buf |= (color_spc & DP_CONVERSION_RGB_YCBCR_MASK); 3455 else 3456 buf &= ~DP_CONVERSION_RGB_YCBCR_MASK; 3457 3458 ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf); 3459 if (ret < 0) 3460 return ret; 3461 3462 return 0; 3463 } 3464 EXPORT_SYMBOL(drm_dp_pcon_convert_rgb_to_ycbcr); 3465 3466 /** 3467 * drm_edp_backlight_set_level() - Set the backlight level of an eDP panel via AUX 3468 * @aux: The DP AUX channel to use 3469 * @bl: Backlight capability info from drm_edp_backlight_init() 3470 * @level: The brightness level to set 3471 * 3472 * Sets the brightness level of an eDP panel's backlight. Note that the panel's backlight must 3473 * already have been enabled by the driver by calling drm_edp_backlight_enable(). 3474 * 3475 * Returns: %0 on success, negative error code on failure 3476 */ 3477 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 3478 u16 level) 3479 { 3480 int ret; 3481 u8 buf[2] = { 0 }; 3482 3483 /* The panel uses the PWM for controlling brightness levels */ 3484 if (!bl->aux_set) 3485 return 0; 3486 3487 if (bl->lsb_reg_used) { 3488 buf[0] = (level & 0xff00) >> 8; 3489 buf[1] = (level & 0x00ff); 3490 } else { 3491 buf[0] = level; 3492 } 3493 3494 ret = drm_dp_dpcd_write(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, sizeof(buf)); 3495 if (ret != sizeof(buf)) { 3496 drm_err(aux->drm_dev, 3497 "%s: Failed to write aux backlight level: %d\n", 3498 aux->name, ret); 3499 return ret < 0 ? ret : -EIO; 3500 } 3501 3502 return 0; 3503 } 3504 EXPORT_SYMBOL(drm_edp_backlight_set_level); 3505 3506 static int 3507 drm_edp_backlight_set_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 3508 bool enable) 3509 { 3510 int ret; 3511 u8 buf; 3512 3513 /* This panel uses the EDP_BL_PWR GPIO for enablement */ 3514 if (!bl->aux_enable) 3515 return 0; 3516 3517 ret = drm_dp_dpcd_readb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, &buf); 3518 if (ret != 1) { 3519 drm_err(aux->drm_dev, "%s: Failed to read eDP display control register: %d\n", 3520 aux->name, ret); 3521 return ret < 0 ? ret : -EIO; 3522 } 3523 if (enable) 3524 buf |= DP_EDP_BACKLIGHT_ENABLE; 3525 else 3526 buf &= ~DP_EDP_BACKLIGHT_ENABLE; 3527 3528 ret = drm_dp_dpcd_writeb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, buf); 3529 if (ret != 1) { 3530 drm_err(aux->drm_dev, "%s: Failed to write eDP display control register: %d\n", 3531 aux->name, ret); 3532 return ret < 0 ? ret : -EIO; 3533 } 3534 3535 return 0; 3536 } 3537 3538 /** 3539 * drm_edp_backlight_enable() - Enable an eDP panel's backlight using DPCD 3540 * @aux: The DP AUX channel to use 3541 * @bl: Backlight capability info from drm_edp_backlight_init() 3542 * @level: The initial backlight level to set via AUX, if there is one 3543 * 3544 * This function handles enabling DPCD backlight controls on a panel over DPCD, while additionally 3545 * restoring any important backlight state such as the given backlight level, the brightness byte 3546 * count, backlight frequency, etc. 3547 * 3548 * Note that certain panels do not support being enabled or disabled via DPCD, but instead require 3549 * that the driver handle enabling/disabling the panel through implementation-specific means using 3550 * the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false, 3551 * this function becomes a no-op, and the driver is expected to handle powering the panel on using 3552 * the EDP_BL_PWR GPIO. 3553 * 3554 * Returns: %0 on success, negative error code on failure. 3555 */ 3556 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 3557 const u16 level) 3558 { 3559 int ret; 3560 u8 dpcd_buf; 3561 3562 if (bl->aux_set) 3563 dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD; 3564 else 3565 dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_PWM; 3566 3567 if (bl->pwmgen_bit_count) { 3568 ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, bl->pwmgen_bit_count); 3569 if (ret != 1) 3570 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n", 3571 aux->name, ret); 3572 } 3573 3574 if (bl->pwm_freq_pre_divider) { 3575 ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_FREQ_SET, bl->pwm_freq_pre_divider); 3576 if (ret != 1) 3577 drm_dbg_kms(aux->drm_dev, 3578 "%s: Failed to write aux backlight frequency: %d\n", 3579 aux->name, ret); 3580 else 3581 dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE; 3582 } 3583 3584 ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, dpcd_buf); 3585 if (ret != 1) { 3586 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux backlight mode: %d\n", 3587 aux->name, ret); 3588 return ret < 0 ? ret : -EIO; 3589 } 3590 3591 ret = drm_edp_backlight_set_level(aux, bl, level); 3592 if (ret < 0) 3593 return ret; 3594 ret = drm_edp_backlight_set_enable(aux, bl, true); 3595 if (ret < 0) 3596 return ret; 3597 3598 return 0; 3599 } 3600 EXPORT_SYMBOL(drm_edp_backlight_enable); 3601 3602 /** 3603 * drm_edp_backlight_disable() - Disable an eDP backlight using DPCD, if supported 3604 * @aux: The DP AUX channel to use 3605 * @bl: Backlight capability info from drm_edp_backlight_init() 3606 * 3607 * This function handles disabling DPCD backlight controls on a panel over AUX. 3608 * 3609 * Note that certain panels do not support being enabled or disabled via DPCD, but instead require 3610 * that the driver handle enabling/disabling the panel through implementation-specific means using 3611 * the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false, 3612 * this function becomes a no-op, and the driver is expected to handle powering the panel off using 3613 * the EDP_BL_PWR GPIO. 3614 * 3615 * Returns: %0 on success or no-op, negative error code on failure. 3616 */ 3617 int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl) 3618 { 3619 int ret; 3620 3621 ret = drm_edp_backlight_set_enable(aux, bl, false); 3622 if (ret < 0) 3623 return ret; 3624 3625 return 0; 3626 } 3627 EXPORT_SYMBOL(drm_edp_backlight_disable); 3628 3629 static inline int 3630 drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, 3631 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]) 3632 { 3633 int fxp, fxp_min, fxp_max, fxp_actual, f = 1; 3634 int ret; 3635 u8 pn, pn_min, pn_max; 3636 3637 if (!bl->aux_set) 3638 return 0; 3639 3640 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT, &pn); 3641 if (ret != 1) { 3642 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap: %d\n", 3643 aux->name, ret); 3644 return -ENODEV; 3645 } 3646 3647 pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK; 3648 bl->max = (1 << pn) - 1; 3649 if (!driver_pwm_freq_hz) 3650 return 0; 3651 3652 /* 3653 * Set PWM Frequency divider to match desired frequency provided by the driver. 3654 * The PWM Frequency is calculated as 27Mhz / (F x P). 3655 * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the 3656 * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h) 3657 * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the 3658 * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h) 3659 */ 3660 3661 /* Find desired value of (F x P) 3662 * Note that, if F x P is out of supported range, the maximum value or minimum value will 3663 * applied automatically. So no need to check that. 3664 */ 3665 fxp = DIV_ROUND_CLOSEST(1000 * DP_EDP_BACKLIGHT_FREQ_BASE_KHZ, driver_pwm_freq_hz); 3666 3667 /* Use highest possible value of Pn for more granularity of brightness adjustment while 3668 * satisfying the conditions below. 3669 * - Pn is in the range of Pn_min and Pn_max 3670 * - F is in the range of 1 and 255 3671 * - FxP is within 25% of desired value. 3672 * Note: 25% is arbitrary value and may need some tweak. 3673 */ 3674 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min); 3675 if (ret != 1) { 3676 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n", 3677 aux->name, ret); 3678 return 0; 3679 } 3680 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max); 3681 if (ret != 1) { 3682 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n", 3683 aux->name, ret); 3684 return 0; 3685 } 3686 pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK; 3687 pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK; 3688 3689 /* Ensure frequency is within 25% of desired value */ 3690 fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4); 3691 fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4); 3692 if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) { 3693 drm_dbg_kms(aux->drm_dev, 3694 "%s: Driver defined backlight frequency (%d) out of range\n", 3695 aux->name, driver_pwm_freq_hz); 3696 return 0; 3697 } 3698 3699 for (pn = pn_max; pn >= pn_min; pn--) { 3700 f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255); 3701 fxp_actual = f << pn; 3702 if (fxp_min <= fxp_actual && fxp_actual <= fxp_max) 3703 break; 3704 } 3705 3706 ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, pn); 3707 if (ret != 1) { 3708 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n", 3709 aux->name, ret); 3710 return 0; 3711 } 3712 bl->pwmgen_bit_count = pn; 3713 bl->max = (1 << pn) - 1; 3714 3715 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP) { 3716 bl->pwm_freq_pre_divider = f; 3717 drm_dbg_kms(aux->drm_dev, "%s: Using backlight frequency from driver (%dHz)\n", 3718 aux->name, driver_pwm_freq_hz); 3719 } 3720 3721 return 0; 3722 } 3723 3724 static inline int 3725 drm_edp_backlight_probe_state(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, 3726 u8 *current_mode) 3727 { 3728 int ret; 3729 u8 buf[2]; 3730 u8 mode_reg; 3731 3732 ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg); 3733 if (ret != 1) { 3734 drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight mode: %d\n", 3735 aux->name, ret); 3736 return ret < 0 ? ret : -EIO; 3737 } 3738 3739 *current_mode = (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK); 3740 if (!bl->aux_set) 3741 return 0; 3742 3743 if (*current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) { 3744 int size = 1 + bl->lsb_reg_used; 3745 3746 ret = drm_dp_dpcd_read(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, size); 3747 if (ret != size) { 3748 drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight level: %d\n", 3749 aux->name, ret); 3750 return ret < 0 ? ret : -EIO; 3751 } 3752 3753 if (bl->lsb_reg_used) 3754 return (buf[0] << 8) | buf[1]; 3755 else 3756 return buf[0]; 3757 } 3758 3759 /* 3760 * If we're not in DPCD control mode yet, the programmed brightness value is meaningless and 3761 * the driver should assume max brightness 3762 */ 3763 return bl->max; 3764 } 3765 3766 /** 3767 * drm_edp_backlight_init() - Probe a display panel's TCON using the standard VESA eDP backlight 3768 * interface. 3769 * @aux: The DP aux device to use for probing 3770 * @bl: The &drm_edp_backlight_info struct to fill out with information on the backlight 3771 * @driver_pwm_freq_hz: Optional PWM frequency from the driver in hz 3772 * @edp_dpcd: A cached copy of the eDP DPCD 3773 * @current_level: Where to store the probed brightness level, if any 3774 * @current_mode: Where to store the currently set backlight control mode 3775 * 3776 * Initializes a &drm_edp_backlight_info struct by probing @aux for it's backlight capabilities, 3777 * along with also probing the current and maximum supported brightness levels. 3778 * 3779 * If @driver_pwm_freq_hz is non-zero, this will be used as the backlight frequency. Otherwise, the 3780 * default frequency from the panel is used. 3781 * 3782 * Returns: %0 on success, negative error code on failure. 3783 */ 3784 int 3785 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, 3786 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE], 3787 u16 *current_level, u8 *current_mode) 3788 { 3789 int ret; 3790 3791 if (edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) 3792 bl->aux_enable = true; 3793 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP) 3794 bl->aux_set = true; 3795 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) 3796 bl->lsb_reg_used = true; 3797 3798 /* Sanity check caps */ 3799 if (!bl->aux_set && !(edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) { 3800 drm_dbg_kms(aux->drm_dev, 3801 "%s: Panel supports neither AUX or PWM brightness control? Aborting\n", 3802 aux->name); 3803 return -EINVAL; 3804 } 3805 3806 ret = drm_edp_backlight_probe_max(aux, bl, driver_pwm_freq_hz, edp_dpcd); 3807 if (ret < 0) 3808 return ret; 3809 3810 ret = drm_edp_backlight_probe_state(aux, bl, current_mode); 3811 if (ret < 0) 3812 return ret; 3813 *current_level = ret; 3814 3815 drm_dbg_kms(aux->drm_dev, 3816 "%s: Found backlight: aux_set=%d aux_enable=%d mode=%d\n", 3817 aux->name, bl->aux_set, bl->aux_enable, *current_mode); 3818 if (bl->aux_set) { 3819 drm_dbg_kms(aux->drm_dev, 3820 "%s: Backlight caps: level=%d/%d pwm_freq_pre_divider=%d lsb_reg_used=%d\n", 3821 aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider, 3822 bl->lsb_reg_used); 3823 } 3824 3825 return 0; 3826 } 3827 EXPORT_SYMBOL(drm_edp_backlight_init); 3828 3829 #if IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \ 3830 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE)) 3831 3832 static int dp_aux_backlight_update_status(struct backlight_device *bd) 3833 { 3834 STUB(); 3835 return -ENOSYS; 3836 #ifdef notyet 3837 struct dp_aux_backlight *bl = bl_get_data(bd); 3838 u16 brightness = backlight_get_brightness(bd); 3839 int ret = 0; 3840 3841 if (!backlight_is_blank(bd)) { 3842 if (!bl->enabled) { 3843 drm_edp_backlight_enable(bl->aux, &bl->info, brightness); 3844 bl->enabled = true; 3845 return 0; 3846 } 3847 ret = drm_edp_backlight_set_level(bl->aux, &bl->info, brightness); 3848 } else { 3849 if (bl->enabled) { 3850 drm_edp_backlight_disable(bl->aux, &bl->info); 3851 bl->enabled = false; 3852 } 3853 } 3854 3855 return ret; 3856 #endif 3857 } 3858 3859 static const struct backlight_ops dp_aux_bl_ops = { 3860 .update_status = dp_aux_backlight_update_status, 3861 }; 3862 3863 /** 3864 * drm_panel_dp_aux_backlight - create and use DP AUX backlight 3865 * @panel: DRM panel 3866 * @aux: The DP AUX channel to use 3867 * 3868 * Use this function to create and handle backlight if your panel 3869 * supports backlight control over DP AUX channel using DPCD 3870 * registers as per VESA's standard backlight control interface. 3871 * 3872 * When the panel is enabled backlight will be enabled after a 3873 * successful call to &drm_panel_funcs.enable() 3874 * 3875 * When the panel is disabled backlight will be disabled before the 3876 * call to &drm_panel_funcs.disable(). 3877 * 3878 * A typical implementation for a panel driver supporting backlight 3879 * control over DP AUX will call this function at probe time. 3880 * Backlight will then be handled transparently without requiring 3881 * any intervention from the driver. 3882 * 3883 * drm_panel_dp_aux_backlight() must be called after the call to drm_panel_init(). 3884 * 3885 * Return: 0 on success or a negative error code on failure. 3886 */ 3887 int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux) 3888 { 3889 struct dp_aux_backlight *bl; 3890 struct backlight_properties props = { 0 }; 3891 u16 current_level; 3892 u8 current_mode; 3893 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; 3894 int ret; 3895 3896 if (!panel || !panel->dev || !aux) 3897 return -EINVAL; 3898 3899 ret = drm_dp_dpcd_read(aux, DP_EDP_DPCD_REV, edp_dpcd, 3900 EDP_DISPLAY_CTL_CAP_SIZE); 3901 if (ret < 0) 3902 return ret; 3903 3904 if (!drm_edp_backlight_supported(edp_dpcd)) { 3905 DRM_DEV_INFO(panel->dev, "DP AUX backlight is not supported\n"); 3906 return 0; 3907 } 3908 3909 bl = devm_kzalloc(panel->dev, sizeof(*bl), GFP_KERNEL); 3910 if (!bl) 3911 return -ENOMEM; 3912 3913 bl->aux = aux; 3914 3915 ret = drm_edp_backlight_init(aux, &bl->info, 0, edp_dpcd, 3916 ¤t_level, ¤t_mode); 3917 if (ret < 0) 3918 return ret; 3919 3920 props.type = BACKLIGHT_RAW; 3921 props.brightness = current_level; 3922 props.max_brightness = bl->info.max; 3923 3924 bl->base = devm_backlight_device_register(panel->dev, "dp_aux_backlight", 3925 panel->dev, bl, 3926 &dp_aux_bl_ops, &props); 3927 if (IS_ERR(bl->base)) 3928 return PTR_ERR(bl->base); 3929 3930 backlight_disable(bl->base); 3931 3932 panel->backlight = bl->base; 3933 3934 return 0; 3935 } 3936 EXPORT_SYMBOL(drm_panel_dp_aux_backlight); 3937 3938 #endif 3939