1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "vangogh_ppt.h" 37 #include "aldebaran_ppt.h" 38 #include "yellow_carp_ppt.h" 39 #include "cyan_skillfish_ppt.h" 40 #include "smu_v13_0_0_ppt.h" 41 #include "smu_v13_0_4_ppt.h" 42 #include "smu_v13_0_5_ppt.h" 43 #include "smu_v13_0_7_ppt.h" 44 #include "amd_pcie.h" 45 46 /* 47 * DO NOT use these for err/warn/info/debug messages. 48 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 49 * They are more MGPU friendly. 50 */ 51 #undef pr_err 52 #undef pr_warn 53 #undef pr_info 54 #undef pr_debug 55 56 static const struct amd_pm_funcs swsmu_pm_funcs; 57 static int smu_force_smuclk_levels(struct smu_context *smu, 58 enum smu_clk_type clk_type, 59 uint32_t mask); 60 static int smu_handle_task(struct smu_context *smu, 61 enum amd_dpm_forced_level level, 62 enum amd_pp_task task_id); 63 static int smu_reset(struct smu_context *smu); 64 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 65 static int smu_set_fan_control_mode(void *handle, u32 value); 66 static int smu_set_power_limit(void *handle, uint32_t limit); 67 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 68 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 69 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 70 71 static int smu_sys_get_pp_feature_mask(void *handle, 72 char *buf) 73 { 74 struct smu_context *smu = handle; 75 76 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 77 return -EOPNOTSUPP; 78 79 return smu_get_pp_feature_mask(smu, buf); 80 } 81 82 static int smu_sys_set_pp_feature_mask(void *handle, 83 uint64_t new_mask) 84 { 85 struct smu_context *smu = handle; 86 87 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 88 return -EOPNOTSUPP; 89 90 return smu_set_pp_feature_mask(smu, new_mask); 91 } 92 93 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 94 { 95 if (!smu->ppt_funcs->set_gfx_off_residency) 96 return -EINVAL; 97 98 return smu_set_gfx_off_residency(smu, value); 99 } 100 101 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 102 { 103 if (!smu->ppt_funcs->get_gfx_off_residency) 104 return -EINVAL; 105 106 return smu_get_gfx_off_residency(smu, value); 107 } 108 109 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 110 { 111 if (!smu->ppt_funcs->get_gfx_off_entrycount) 112 return -EINVAL; 113 114 return smu_get_gfx_off_entrycount(smu, value); 115 } 116 117 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 118 { 119 if (!smu->ppt_funcs->get_gfx_off_status) 120 return -EINVAL; 121 122 *value = smu_get_gfx_off_status(smu); 123 124 return 0; 125 } 126 127 int smu_set_soft_freq_range(struct smu_context *smu, 128 enum smu_clk_type clk_type, 129 uint32_t min, 130 uint32_t max) 131 { 132 int ret = 0; 133 134 if (smu->ppt_funcs->set_soft_freq_limited_range) 135 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 136 clk_type, 137 min, 138 max); 139 140 return ret; 141 } 142 143 int smu_get_dpm_freq_range(struct smu_context *smu, 144 enum smu_clk_type clk_type, 145 uint32_t *min, 146 uint32_t *max) 147 { 148 int ret = -ENOTSUPP; 149 150 if (!min && !max) 151 return -EINVAL; 152 153 if (smu->ppt_funcs->get_dpm_ultimate_freq) 154 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 155 clk_type, 156 min, 157 max); 158 159 return ret; 160 } 161 162 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 163 { 164 int ret = 0; 165 struct amdgpu_device *adev = smu->adev; 166 167 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 168 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 169 if (ret) 170 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 171 } 172 return ret; 173 } 174 175 static u32 smu_get_mclk(void *handle, bool low) 176 { 177 struct smu_context *smu = handle; 178 uint32_t clk_freq; 179 int ret = 0; 180 181 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 182 low ? &clk_freq : NULL, 183 !low ? &clk_freq : NULL); 184 if (ret) 185 return 0; 186 return clk_freq * 100; 187 } 188 189 static u32 smu_get_sclk(void *handle, bool low) 190 { 191 struct smu_context *smu = handle; 192 uint32_t clk_freq; 193 int ret = 0; 194 195 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 196 low ? &clk_freq : NULL, 197 !low ? &clk_freq : NULL); 198 if (ret) 199 return 0; 200 return clk_freq * 100; 201 } 202 203 static int smu_set_gfx_imu_enable(struct smu_context *smu) 204 { 205 struct amdgpu_device *adev = smu->adev; 206 207 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 208 return 0; 209 210 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 211 return 0; 212 213 return smu_set_gfx_power_up_by_imu(smu); 214 } 215 216 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 217 bool enable) 218 { 219 struct smu_power_context *smu_power = &smu->smu_power; 220 struct smu_power_gate *power_gate = &smu_power->power_gate; 221 int ret = 0; 222 223 if (!smu->ppt_funcs->dpm_set_vcn_enable) 224 return 0; 225 226 if (atomic_read(&power_gate->vcn_gated) ^ enable) 227 return 0; 228 229 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 230 if (!ret) 231 atomic_set(&power_gate->vcn_gated, !enable); 232 233 return ret; 234 } 235 236 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 237 bool enable) 238 { 239 struct smu_power_context *smu_power = &smu->smu_power; 240 struct smu_power_gate *power_gate = &smu_power->power_gate; 241 int ret = 0; 242 243 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 244 return 0; 245 246 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 247 return 0; 248 249 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 250 if (!ret) 251 atomic_set(&power_gate->jpeg_gated, !enable); 252 253 return ret; 254 } 255 256 /** 257 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 258 * 259 * @handle: smu_context pointer 260 * @block_type: the IP block to power gate/ungate 261 * @gate: to power gate if true, ungate otherwise 262 * 263 * This API uses no smu->mutex lock protection due to: 264 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 265 * This is guarded to be race condition free by the caller. 266 * 2. Or get called on user setting request of power_dpm_force_performance_level. 267 * Under this case, the smu->mutex lock protection is already enforced on 268 * the parent API smu_force_performance_level of the call path. 269 */ 270 static int smu_dpm_set_power_gate(void *handle, 271 uint32_t block_type, 272 bool gate) 273 { 274 struct smu_context *smu = handle; 275 int ret = 0; 276 277 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 278 dev_WARN(smu->adev->dev, 279 "SMU uninitialized but power %s requested for %u!\n", 280 gate ? "gate" : "ungate", block_type); 281 return -EOPNOTSUPP; 282 } 283 284 switch (block_type) { 285 /* 286 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 287 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 288 */ 289 case AMD_IP_BLOCK_TYPE_UVD: 290 case AMD_IP_BLOCK_TYPE_VCN: 291 ret = smu_dpm_set_vcn_enable(smu, !gate); 292 if (ret) 293 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 294 gate ? "gate" : "ungate"); 295 break; 296 case AMD_IP_BLOCK_TYPE_GFX: 297 ret = smu_gfx_off_control(smu, gate); 298 if (ret) 299 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 300 gate ? "enable" : "disable"); 301 break; 302 case AMD_IP_BLOCK_TYPE_SDMA: 303 ret = smu_powergate_sdma(smu, gate); 304 if (ret) 305 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 306 gate ? "gate" : "ungate"); 307 break; 308 case AMD_IP_BLOCK_TYPE_JPEG: 309 ret = smu_dpm_set_jpeg_enable(smu, !gate); 310 if (ret) 311 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 312 gate ? "gate" : "ungate"); 313 break; 314 default: 315 dev_err(smu->adev->dev, "Unsupported block type!\n"); 316 return -EINVAL; 317 } 318 319 return ret; 320 } 321 322 /** 323 * smu_set_user_clk_dependencies - set user profile clock dependencies 324 * 325 * @smu: smu_context pointer 326 * @clk: enum smu_clk_type type 327 * 328 * Enable/Disable the clock dependency for the @clk type. 329 */ 330 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 331 { 332 if (smu->adev->in_suspend) 333 return; 334 335 if (clk == SMU_MCLK) { 336 smu->user_dpm_profile.clk_dependency = 0; 337 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 338 } else if (clk == SMU_FCLK) { 339 /* MCLK takes precedence over FCLK */ 340 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 341 return; 342 343 smu->user_dpm_profile.clk_dependency = 0; 344 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 345 } else if (clk == SMU_SOCCLK) { 346 /* MCLK takes precedence over SOCCLK */ 347 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 348 return; 349 350 smu->user_dpm_profile.clk_dependency = 0; 351 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 352 } else 353 /* Add clk dependencies here, if any */ 354 return; 355 } 356 357 /** 358 * smu_restore_dpm_user_profile - reinstate user dpm profile 359 * 360 * @smu: smu_context pointer 361 * 362 * Restore the saved user power configurations include power limit, 363 * clock frequencies, fan control mode and fan speed. 364 */ 365 static void smu_restore_dpm_user_profile(struct smu_context *smu) 366 { 367 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 368 int ret = 0; 369 370 if (!smu->adev->in_suspend) 371 return; 372 373 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 374 return; 375 376 /* Enable restore flag */ 377 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 378 379 /* set the user dpm power limit */ 380 if (smu->user_dpm_profile.power_limit) { 381 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 382 if (ret) 383 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 384 } 385 386 /* set the user dpm clock configurations */ 387 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 388 enum smu_clk_type clk_type; 389 390 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 391 /* 392 * Iterate over smu clk type and force the saved user clk 393 * configs, skip if clock dependency is enabled 394 */ 395 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 396 smu->user_dpm_profile.clk_mask[clk_type]) { 397 ret = smu_force_smuclk_levels(smu, clk_type, 398 smu->user_dpm_profile.clk_mask[clk_type]); 399 if (ret) 400 dev_err(smu->adev->dev, 401 "Failed to set clock type = %d\n", clk_type); 402 } 403 } 404 } 405 406 /* set the user dpm fan configurations */ 407 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 408 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 409 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 410 if (ret != -EOPNOTSUPP) { 411 smu->user_dpm_profile.fan_speed_pwm = 0; 412 smu->user_dpm_profile.fan_speed_rpm = 0; 413 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 414 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 415 } 416 417 if (smu->user_dpm_profile.fan_speed_pwm) { 418 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 419 if (ret != -EOPNOTSUPP) 420 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 421 } 422 423 if (smu->user_dpm_profile.fan_speed_rpm) { 424 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 425 if (ret != -EOPNOTSUPP) 426 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 427 } 428 } 429 430 /* Restore user customized OD settings */ 431 if (smu->user_dpm_profile.user_od) { 432 if (smu->ppt_funcs->restore_user_od_settings) { 433 ret = smu->ppt_funcs->restore_user_od_settings(smu); 434 if (ret) 435 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 436 } 437 } 438 439 /* Disable restore flag */ 440 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 441 } 442 443 static int smu_get_power_num_states(void *handle, 444 struct pp_states_info *state_info) 445 { 446 if (!state_info) 447 return -EINVAL; 448 449 /* not support power state */ 450 memset(state_info, 0, sizeof(struct pp_states_info)); 451 state_info->nums = 1; 452 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 453 454 return 0; 455 } 456 457 bool is_support_sw_smu(struct amdgpu_device *adev) 458 { 459 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 460 if (adev->asic_type == CHIP_VEGA20) 461 return false; 462 463 if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0)) 464 return true; 465 466 return false; 467 } 468 469 bool is_support_cclk_dpm(struct amdgpu_device *adev) 470 { 471 struct smu_context *smu = adev->powerplay.pp_handle; 472 473 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 474 return false; 475 476 return true; 477 } 478 479 480 static int smu_sys_get_pp_table(void *handle, 481 char **table) 482 { 483 struct smu_context *smu = handle; 484 struct smu_table_context *smu_table = &smu->smu_table; 485 486 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 487 return -EOPNOTSUPP; 488 489 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 490 return -EINVAL; 491 492 if (smu_table->hardcode_pptable) 493 *table = smu_table->hardcode_pptable; 494 else 495 *table = smu_table->power_play_table; 496 497 return smu_table->power_play_table_size; 498 } 499 500 static int smu_sys_set_pp_table(void *handle, 501 const char *buf, 502 size_t size) 503 { 504 struct smu_context *smu = handle; 505 struct smu_table_context *smu_table = &smu->smu_table; 506 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 507 int ret = 0; 508 509 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 510 return -EOPNOTSUPP; 511 512 if (header->usStructureSize != size) { 513 dev_err(smu->adev->dev, "pp table size not matched !\n"); 514 return -EIO; 515 } 516 517 if (!smu_table->hardcode_pptable) { 518 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 519 if (!smu_table->hardcode_pptable) 520 return -ENOMEM; 521 } 522 523 memcpy(smu_table->hardcode_pptable, buf, size); 524 smu_table->power_play_table = smu_table->hardcode_pptable; 525 smu_table->power_play_table_size = size; 526 527 /* 528 * Special hw_fini action(for Navi1x, the DPMs disablement will be 529 * skipped) may be needed for custom pptable uploading. 530 */ 531 smu->uploading_custom_pp_table = true; 532 533 ret = smu_reset(smu); 534 if (ret) 535 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 536 537 smu->uploading_custom_pp_table = false; 538 539 return ret; 540 } 541 542 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 543 { 544 struct smu_feature *feature = &smu->smu_feature; 545 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 546 int ret = 0; 547 548 /* 549 * With SCPM enabled, the allowed featuremasks setting(via 550 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 551 * That means there is no way to let PMFW knows the settings below. 552 * Thus, we just assume all the features are allowed under 553 * such scenario. 554 */ 555 if (smu->adev->scpm_enabled) { 556 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 557 return 0; 558 } 559 560 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 561 562 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 563 SMU_FEATURE_MAX/32); 564 if (ret) 565 return ret; 566 567 bitmap_or(feature->allowed, feature->allowed, 568 (unsigned long *)allowed_feature_mask, 569 feature->feature_num); 570 571 return ret; 572 } 573 574 static int smu_set_funcs(struct amdgpu_device *adev) 575 { 576 struct smu_context *smu = adev->powerplay.pp_handle; 577 578 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 579 smu->od_enabled = true; 580 581 switch (adev->ip_versions[MP1_HWIP][0]) { 582 case IP_VERSION(11, 0, 0): 583 case IP_VERSION(11, 0, 5): 584 case IP_VERSION(11, 0, 9): 585 navi10_set_ppt_funcs(smu); 586 break; 587 case IP_VERSION(11, 0, 7): 588 case IP_VERSION(11, 0, 11): 589 case IP_VERSION(11, 0, 12): 590 case IP_VERSION(11, 0, 13): 591 sienna_cichlid_set_ppt_funcs(smu); 592 break; 593 case IP_VERSION(12, 0, 0): 594 case IP_VERSION(12, 0, 1): 595 renoir_set_ppt_funcs(smu); 596 break; 597 case IP_VERSION(11, 5, 0): 598 vangogh_set_ppt_funcs(smu); 599 break; 600 case IP_VERSION(13, 0, 1): 601 case IP_VERSION(13, 0, 3): 602 case IP_VERSION(13, 0, 8): 603 yellow_carp_set_ppt_funcs(smu); 604 break; 605 case IP_VERSION(13, 0, 4): 606 case IP_VERSION(13, 0, 11): 607 smu_v13_0_4_set_ppt_funcs(smu); 608 break; 609 case IP_VERSION(13, 0, 5): 610 smu_v13_0_5_set_ppt_funcs(smu); 611 break; 612 case IP_VERSION(11, 0, 8): 613 cyan_skillfish_set_ppt_funcs(smu); 614 break; 615 case IP_VERSION(11, 0, 2): 616 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 617 arcturus_set_ppt_funcs(smu); 618 /* OD is not supported on Arcturus */ 619 smu->od_enabled =false; 620 break; 621 case IP_VERSION(13, 0, 2): 622 aldebaran_set_ppt_funcs(smu); 623 /* Enable pp_od_clk_voltage node */ 624 smu->od_enabled = true; 625 break; 626 case IP_VERSION(13, 0, 0): 627 case IP_VERSION(13, 0, 10): 628 smu_v13_0_0_set_ppt_funcs(smu); 629 break; 630 case IP_VERSION(13, 0, 7): 631 smu_v13_0_7_set_ppt_funcs(smu); 632 break; 633 default: 634 return -EINVAL; 635 } 636 637 return 0; 638 } 639 640 static int smu_early_init(void *handle) 641 { 642 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 643 struct smu_context *smu; 644 645 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 646 if (!smu) 647 return -ENOMEM; 648 649 smu->adev = adev; 650 smu->pm_enabled = !!amdgpu_dpm; 651 smu->is_apu = false; 652 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 653 smu->smu_baco.platform_support = false; 654 smu->user_dpm_profile.fan_mode = -1; 655 656 rw_init(&smu->message_lock, "smuml"); 657 658 adev->powerplay.pp_handle = smu; 659 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 660 661 return smu_set_funcs(adev); 662 } 663 664 static int smu_set_default_dpm_table(struct smu_context *smu) 665 { 666 struct smu_power_context *smu_power = &smu->smu_power; 667 struct smu_power_gate *power_gate = &smu_power->power_gate; 668 int vcn_gate, jpeg_gate; 669 int ret = 0; 670 671 if (!smu->ppt_funcs->set_default_dpm_table) 672 return 0; 673 674 vcn_gate = atomic_read(&power_gate->vcn_gated); 675 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 676 677 ret = smu_dpm_set_vcn_enable(smu, true); 678 if (ret) 679 return ret; 680 681 ret = smu_dpm_set_jpeg_enable(smu, true); 682 if (ret) 683 goto err_out; 684 685 ret = smu->ppt_funcs->set_default_dpm_table(smu); 686 if (ret) 687 dev_err(smu->adev->dev, 688 "Failed to setup default dpm clock tables!\n"); 689 690 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 691 err_out: 692 smu_dpm_set_vcn_enable(smu, !vcn_gate); 693 return ret; 694 } 695 696 static int smu_apply_default_config_table_settings(struct smu_context *smu) 697 { 698 struct amdgpu_device *adev = smu->adev; 699 int ret = 0; 700 701 ret = smu_get_default_config_table_settings(smu, 702 &adev->pm.config_table); 703 if (ret) 704 return ret; 705 706 return smu_set_config_table(smu, &adev->pm.config_table); 707 } 708 709 static int smu_late_init(void *handle) 710 { 711 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 712 struct smu_context *smu = adev->powerplay.pp_handle; 713 int ret = 0; 714 715 smu_set_fine_grain_gfx_freq_parameters(smu); 716 717 if (!smu->pm_enabled) 718 return 0; 719 720 ret = smu_post_init(smu); 721 if (ret) { 722 dev_err(adev->dev, "Failed to post smu init!\n"); 723 return ret; 724 } 725 726 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) || 727 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3))) 728 return 0; 729 730 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 731 ret = smu_set_default_od_settings(smu); 732 if (ret) { 733 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 734 return ret; 735 } 736 } 737 738 ret = smu_populate_umd_state_clk(smu); 739 if (ret) { 740 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 741 return ret; 742 } 743 744 ret = smu_get_asic_power_limits(smu, 745 &smu->current_power_limit, 746 &smu->default_power_limit, 747 &smu->max_power_limit); 748 if (ret) { 749 dev_err(adev->dev, "Failed to get asic power limits!\n"); 750 return ret; 751 } 752 753 if (!amdgpu_sriov_vf(adev)) 754 smu_get_unique_id(smu); 755 756 smu_get_fan_parameters(smu); 757 758 smu_handle_task(smu, 759 smu->smu_dpm.dpm_level, 760 AMD_PP_TASK_COMPLETE_INIT); 761 762 ret = smu_apply_default_config_table_settings(smu); 763 if (ret && (ret != -EOPNOTSUPP)) { 764 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 765 return ret; 766 } 767 768 smu_restore_dpm_user_profile(smu); 769 770 return 0; 771 } 772 773 static int smu_init_fb_allocations(struct smu_context *smu) 774 { 775 struct amdgpu_device *adev = smu->adev; 776 struct smu_table_context *smu_table = &smu->smu_table; 777 struct smu_table *tables = smu_table->tables; 778 struct smu_table *driver_table = &(smu_table->driver_table); 779 uint32_t max_table_size = 0; 780 int ret, i; 781 782 /* VRAM allocation for tool table */ 783 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 784 ret = amdgpu_bo_create_kernel(adev, 785 tables[SMU_TABLE_PMSTATUSLOG].size, 786 tables[SMU_TABLE_PMSTATUSLOG].align, 787 tables[SMU_TABLE_PMSTATUSLOG].domain, 788 &tables[SMU_TABLE_PMSTATUSLOG].bo, 789 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 790 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 791 if (ret) { 792 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 793 return ret; 794 } 795 } 796 797 /* VRAM allocation for driver table */ 798 for (i = 0; i < SMU_TABLE_COUNT; i++) { 799 if (tables[i].size == 0) 800 continue; 801 802 if (i == SMU_TABLE_PMSTATUSLOG) 803 continue; 804 805 if (max_table_size < tables[i].size) 806 max_table_size = tables[i].size; 807 } 808 809 driver_table->size = max_table_size; 810 driver_table->align = PAGE_SIZE; 811 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 812 813 ret = amdgpu_bo_create_kernel(adev, 814 driver_table->size, 815 driver_table->align, 816 driver_table->domain, 817 &driver_table->bo, 818 &driver_table->mc_address, 819 &driver_table->cpu_addr); 820 if (ret) { 821 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 822 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 823 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 824 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 825 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 826 } 827 828 return ret; 829 } 830 831 static int smu_fini_fb_allocations(struct smu_context *smu) 832 { 833 struct smu_table_context *smu_table = &smu->smu_table; 834 struct smu_table *tables = smu_table->tables; 835 struct smu_table *driver_table = &(smu_table->driver_table); 836 837 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 838 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 839 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 840 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 841 842 amdgpu_bo_free_kernel(&driver_table->bo, 843 &driver_table->mc_address, 844 &driver_table->cpu_addr); 845 846 return 0; 847 } 848 849 /** 850 * smu_alloc_memory_pool - allocate memory pool in the system memory 851 * 852 * @smu: amdgpu_device pointer 853 * 854 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 855 * and DramLogSetDramAddr can notify it changed. 856 * 857 * Returns 0 on success, error on failure. 858 */ 859 static int smu_alloc_memory_pool(struct smu_context *smu) 860 { 861 struct amdgpu_device *adev = smu->adev; 862 struct smu_table_context *smu_table = &smu->smu_table; 863 struct smu_table *memory_pool = &smu_table->memory_pool; 864 uint64_t pool_size = smu->pool_size; 865 int ret = 0; 866 867 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 868 return ret; 869 870 memory_pool->size = pool_size; 871 memory_pool->align = PAGE_SIZE; 872 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 873 874 switch (pool_size) { 875 case SMU_MEMORY_POOL_SIZE_256_MB: 876 case SMU_MEMORY_POOL_SIZE_512_MB: 877 case SMU_MEMORY_POOL_SIZE_1_GB: 878 case SMU_MEMORY_POOL_SIZE_2_GB: 879 ret = amdgpu_bo_create_kernel(adev, 880 memory_pool->size, 881 memory_pool->align, 882 memory_pool->domain, 883 &memory_pool->bo, 884 &memory_pool->mc_address, 885 &memory_pool->cpu_addr); 886 if (ret) 887 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 888 break; 889 default: 890 break; 891 } 892 893 return ret; 894 } 895 896 static int smu_free_memory_pool(struct smu_context *smu) 897 { 898 struct smu_table_context *smu_table = &smu->smu_table; 899 struct smu_table *memory_pool = &smu_table->memory_pool; 900 901 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 902 return 0; 903 904 amdgpu_bo_free_kernel(&memory_pool->bo, 905 &memory_pool->mc_address, 906 &memory_pool->cpu_addr); 907 908 memset(memory_pool, 0, sizeof(struct smu_table)); 909 910 return 0; 911 } 912 913 static int smu_alloc_dummy_read_table(struct smu_context *smu) 914 { 915 struct smu_table_context *smu_table = &smu->smu_table; 916 struct smu_table *dummy_read_1_table = 917 &smu_table->dummy_read_1_table; 918 struct amdgpu_device *adev = smu->adev; 919 int ret = 0; 920 921 dummy_read_1_table->size = 0x40000; 922 dummy_read_1_table->align = PAGE_SIZE; 923 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 924 925 ret = amdgpu_bo_create_kernel(adev, 926 dummy_read_1_table->size, 927 dummy_read_1_table->align, 928 dummy_read_1_table->domain, 929 &dummy_read_1_table->bo, 930 &dummy_read_1_table->mc_address, 931 &dummy_read_1_table->cpu_addr); 932 if (ret) 933 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 934 935 return ret; 936 } 937 938 static void smu_free_dummy_read_table(struct smu_context *smu) 939 { 940 struct smu_table_context *smu_table = &smu->smu_table; 941 struct smu_table *dummy_read_1_table = 942 &smu_table->dummy_read_1_table; 943 944 945 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 946 &dummy_read_1_table->mc_address, 947 &dummy_read_1_table->cpu_addr); 948 949 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 950 } 951 952 static int smu_smc_table_sw_init(struct smu_context *smu) 953 { 954 int ret; 955 956 /** 957 * Create smu_table structure, and init smc tables such as 958 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 959 */ 960 ret = smu_init_smc_tables(smu); 961 if (ret) { 962 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 963 return ret; 964 } 965 966 /** 967 * Create smu_power_context structure, and allocate smu_dpm_context and 968 * context size to fill the smu_power_context data. 969 */ 970 ret = smu_init_power(smu); 971 if (ret) { 972 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 973 return ret; 974 } 975 976 /* 977 * allocate vram bos to store smc table contents. 978 */ 979 ret = smu_init_fb_allocations(smu); 980 if (ret) 981 return ret; 982 983 ret = smu_alloc_memory_pool(smu); 984 if (ret) 985 return ret; 986 987 ret = smu_alloc_dummy_read_table(smu); 988 if (ret) 989 return ret; 990 991 ret = smu_i2c_init(smu); 992 if (ret) 993 return ret; 994 995 return 0; 996 } 997 998 static int smu_smc_table_sw_fini(struct smu_context *smu) 999 { 1000 int ret; 1001 1002 smu_i2c_fini(smu); 1003 1004 smu_free_dummy_read_table(smu); 1005 1006 ret = smu_free_memory_pool(smu); 1007 if (ret) 1008 return ret; 1009 1010 ret = smu_fini_fb_allocations(smu); 1011 if (ret) 1012 return ret; 1013 1014 ret = smu_fini_power(smu); 1015 if (ret) { 1016 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1017 return ret; 1018 } 1019 1020 ret = smu_fini_smc_tables(smu); 1021 if (ret) { 1022 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1023 return ret; 1024 } 1025 1026 return 0; 1027 } 1028 1029 static void smu_throttling_logging_work_fn(struct work_struct *work) 1030 { 1031 struct smu_context *smu = container_of(work, struct smu_context, 1032 throttling_logging_work); 1033 1034 smu_log_thermal_throttling(smu); 1035 } 1036 1037 static void smu_interrupt_work_fn(struct work_struct *work) 1038 { 1039 struct smu_context *smu = container_of(work, struct smu_context, 1040 interrupt_work); 1041 1042 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1043 smu->ppt_funcs->interrupt_work(smu); 1044 } 1045 1046 static int smu_sw_init(void *handle) 1047 { 1048 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1049 struct smu_context *smu = adev->powerplay.pp_handle; 1050 int ret; 1051 1052 smu->pool_size = adev->pm.smu_prv_buffer_size; 1053 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1054 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1055 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1056 1057 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1058 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1059 atomic64_set(&smu->throttle_int_counter, 0); 1060 smu->watermarks_bitmap = 0; 1061 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1062 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1063 1064 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1065 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1066 1067 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1068 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1069 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1070 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1071 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1072 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1073 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1074 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1075 1076 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1077 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1078 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1079 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1080 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1081 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1082 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1083 smu->display_config = &adev->pm.pm_display_cfg; 1084 1085 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1086 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1087 1088 ret = smu_init_microcode(smu); 1089 if (ret) { 1090 dev_err(adev->dev, "Failed to load smu firmware!\n"); 1091 return ret; 1092 } 1093 1094 ret = smu_smc_table_sw_init(smu); 1095 if (ret) { 1096 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1097 return ret; 1098 } 1099 1100 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1101 ret = smu_get_vbios_bootup_values(smu); 1102 if (ret) { 1103 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1104 return ret; 1105 } 1106 1107 ret = smu_init_pptable_microcode(smu); 1108 if (ret) { 1109 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1110 return ret; 1111 } 1112 1113 ret = smu_register_irq_handler(smu); 1114 if (ret) { 1115 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1116 return ret; 1117 } 1118 1119 /* If there is no way to query fan control mode, fan control is not supported */ 1120 if (!smu->ppt_funcs->get_fan_control_mode) 1121 smu->adev->pm.no_fan = true; 1122 1123 return 0; 1124 } 1125 1126 static int smu_sw_fini(void *handle) 1127 { 1128 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1129 struct smu_context *smu = adev->powerplay.pp_handle; 1130 int ret; 1131 1132 ret = smu_smc_table_sw_fini(smu); 1133 if (ret) { 1134 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1135 return ret; 1136 } 1137 1138 smu_fini_microcode(smu); 1139 1140 return 0; 1141 } 1142 1143 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1144 { 1145 struct amdgpu_device *adev = smu->adev; 1146 struct smu_temperature_range *range = 1147 &smu->thermal_range; 1148 int ret = 0; 1149 1150 if (!smu->ppt_funcs->get_thermal_temperature_range) 1151 return 0; 1152 1153 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1154 if (ret) 1155 return ret; 1156 1157 adev->pm.dpm.thermal.min_temp = range->min; 1158 adev->pm.dpm.thermal.max_temp = range->max; 1159 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1160 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1161 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1162 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1163 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1164 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1165 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1166 1167 return ret; 1168 } 1169 1170 static int smu_smc_hw_setup(struct smu_context *smu) 1171 { 1172 struct smu_feature *feature = &smu->smu_feature; 1173 struct amdgpu_device *adev = smu->adev; 1174 uint32_t pcie_gen = 0, pcie_width = 0; 1175 uint64_t features_supported; 1176 int ret = 0; 1177 1178 switch (adev->ip_versions[MP1_HWIP][0]) { 1179 case IP_VERSION(11, 0, 7): 1180 case IP_VERSION(11, 0, 11): 1181 case IP_VERSION(11, 5, 0): 1182 case IP_VERSION(11, 0, 12): 1183 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1184 dev_info(adev->dev, "dpm has been enabled\n"); 1185 ret = smu_system_features_control(smu, true); 1186 if (ret) 1187 dev_err(adev->dev, "Failed system features control!\n"); 1188 return ret; 1189 } 1190 break; 1191 default: 1192 break; 1193 } 1194 1195 ret = smu_init_display_count(smu, 0); 1196 if (ret) { 1197 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1198 return ret; 1199 } 1200 1201 ret = smu_set_driver_table_location(smu); 1202 if (ret) { 1203 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1204 return ret; 1205 } 1206 1207 /* 1208 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1209 */ 1210 ret = smu_set_tool_table_location(smu); 1211 if (ret) { 1212 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1213 return ret; 1214 } 1215 1216 /* 1217 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1218 * pool location. 1219 */ 1220 ret = smu_notify_memory_pool_location(smu); 1221 if (ret) { 1222 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1223 return ret; 1224 } 1225 1226 ret = smu_setup_pptable(smu); 1227 if (ret) { 1228 dev_err(adev->dev, "Failed to setup pptable!\n"); 1229 return ret; 1230 } 1231 1232 /* smu_dump_pptable(smu); */ 1233 1234 /* 1235 * With SCPM enabled, PSP is responsible for the PPTable transferring 1236 * (to SMU). Driver involvement is not needed and permitted. 1237 */ 1238 if (!adev->scpm_enabled) { 1239 /* 1240 * Copy pptable bo in the vram to smc with SMU MSGs such as 1241 * SetDriverDramAddr and TransferTableDram2Smu. 1242 */ 1243 ret = smu_write_pptable(smu); 1244 if (ret) { 1245 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1246 return ret; 1247 } 1248 } 1249 1250 /* issue Run*Btc msg */ 1251 ret = smu_run_btc(smu); 1252 if (ret) 1253 return ret; 1254 1255 /* 1256 * With SCPM enabled, these actions(and relevant messages) are 1257 * not needed and permitted. 1258 */ 1259 if (!adev->scpm_enabled) { 1260 ret = smu_feature_set_allowed_mask(smu); 1261 if (ret) { 1262 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1263 return ret; 1264 } 1265 } 1266 1267 ret = smu_system_features_control(smu, true); 1268 if (ret) { 1269 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1270 return ret; 1271 } 1272 1273 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1274 if (ret) { 1275 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1276 return ret; 1277 } 1278 bitmap_copy(feature->supported, 1279 (unsigned long *)&features_supported, 1280 feature->feature_num); 1281 1282 if (!smu_is_dpm_running(smu)) 1283 dev_info(adev->dev, "dpm has been disabled\n"); 1284 1285 /* 1286 * Set initialized values (get from vbios) to dpm tables context such as 1287 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1288 * type of clks. 1289 */ 1290 ret = smu_set_default_dpm_table(smu); 1291 if (ret) { 1292 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1293 return ret; 1294 } 1295 1296 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1297 pcie_gen = 3; 1298 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1299 pcie_gen = 2; 1300 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1301 pcie_gen = 1; 1302 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1303 pcie_gen = 0; 1304 1305 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1306 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1307 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1308 */ 1309 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1310 pcie_width = 6; 1311 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1312 pcie_width = 5; 1313 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1314 pcie_width = 4; 1315 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1316 pcie_width = 3; 1317 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1318 pcie_width = 2; 1319 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1320 pcie_width = 1; 1321 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1322 if (ret) { 1323 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1324 return ret; 1325 } 1326 1327 ret = smu_get_thermal_temperature_range(smu); 1328 if (ret) { 1329 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1330 return ret; 1331 } 1332 1333 ret = smu_enable_thermal_alert(smu); 1334 if (ret) { 1335 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1336 return ret; 1337 } 1338 1339 ret = smu_notify_display_change(smu); 1340 if (ret) { 1341 dev_err(adev->dev, "Failed to notify display change!\n"); 1342 return ret; 1343 } 1344 1345 /* 1346 * Set min deep sleep dce fclk with bootup value from vbios via 1347 * SetMinDeepSleepDcefclk MSG. 1348 */ 1349 ret = smu_set_min_dcef_deep_sleep(smu, 1350 smu->smu_table.boot_values.dcefclk / 100); 1351 1352 return ret; 1353 } 1354 1355 static int smu_start_smc_engine(struct smu_context *smu) 1356 { 1357 struct amdgpu_device *adev = smu->adev; 1358 int ret = 0; 1359 1360 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1361 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) { 1362 if (smu->ppt_funcs->load_microcode) { 1363 ret = smu->ppt_funcs->load_microcode(smu); 1364 if (ret) 1365 return ret; 1366 } 1367 } 1368 } 1369 1370 if (smu->ppt_funcs->check_fw_status) { 1371 ret = smu->ppt_funcs->check_fw_status(smu); 1372 if (ret) { 1373 dev_err(adev->dev, "SMC is not ready\n"); 1374 return ret; 1375 } 1376 } 1377 1378 /* 1379 * Send msg GetDriverIfVersion to check if the return value is equal 1380 * with DRIVER_IF_VERSION of smc header. 1381 */ 1382 ret = smu_check_fw_version(smu); 1383 if (ret) 1384 return ret; 1385 1386 return ret; 1387 } 1388 1389 static int smu_hw_init(void *handle) 1390 { 1391 int ret; 1392 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1393 struct smu_context *smu = adev->powerplay.pp_handle; 1394 1395 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1396 smu->pm_enabled = false; 1397 return 0; 1398 } 1399 1400 ret = smu_start_smc_engine(smu); 1401 if (ret) { 1402 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1403 return ret; 1404 } 1405 1406 if (smu->is_apu) { 1407 ret = smu_set_gfx_imu_enable(smu); 1408 if (ret) 1409 return ret; 1410 smu_dpm_set_vcn_enable(smu, true); 1411 smu_dpm_set_jpeg_enable(smu, true); 1412 smu_set_gfx_cgpg(smu, true); 1413 } 1414 1415 if (!smu->pm_enabled) 1416 return 0; 1417 1418 ret = smu_get_driver_allowed_feature_mask(smu); 1419 if (ret) 1420 return ret; 1421 1422 ret = smu_smc_hw_setup(smu); 1423 if (ret) { 1424 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1425 return ret; 1426 } 1427 1428 /* 1429 * Move maximum sustainable clock retrieving here considering 1430 * 1. It is not needed on resume(from S3). 1431 * 2. DAL settings come between .hw_init and .late_init of SMU. 1432 * And DAL needs to know the maximum sustainable clocks. Thus 1433 * it cannot be put in .late_init(). 1434 */ 1435 ret = smu_init_max_sustainable_clocks(smu); 1436 if (ret) { 1437 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1438 return ret; 1439 } 1440 1441 adev->pm.dpm_enabled = true; 1442 1443 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1444 1445 return 0; 1446 } 1447 1448 static int smu_disable_dpms(struct smu_context *smu) 1449 { 1450 struct amdgpu_device *adev = smu->adev; 1451 int ret = 0; 1452 bool use_baco = !smu->is_apu && 1453 ((amdgpu_in_reset(adev) && 1454 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1455 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1456 1457 /* 1458 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1459 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1460 */ 1461 switch (adev->ip_versions[MP1_HWIP][0]) { 1462 case IP_VERSION(13, 0, 0): 1463 case IP_VERSION(13, 0, 7): 1464 return 0; 1465 default: 1466 break; 1467 } 1468 1469 /* 1470 * For custom pptable uploading, skip the DPM features 1471 * disable process on Navi1x ASICs. 1472 * - As the gfx related features are under control of 1473 * RLC on those ASICs. RLC reinitialization will be 1474 * needed to reenable them. That will cost much more 1475 * efforts. 1476 * 1477 * - SMU firmware can handle the DPM reenablement 1478 * properly. 1479 */ 1480 if (smu->uploading_custom_pp_table) { 1481 switch (adev->ip_versions[MP1_HWIP][0]) { 1482 case IP_VERSION(11, 0, 0): 1483 case IP_VERSION(11, 0, 5): 1484 case IP_VERSION(11, 0, 9): 1485 case IP_VERSION(11, 0, 7): 1486 case IP_VERSION(11, 0, 11): 1487 case IP_VERSION(11, 5, 0): 1488 case IP_VERSION(11, 0, 12): 1489 case IP_VERSION(11, 0, 13): 1490 return 0; 1491 default: 1492 break; 1493 } 1494 } 1495 1496 /* 1497 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1498 * on BACO in. Driver involvement is unnecessary. 1499 */ 1500 if (use_baco) { 1501 switch (adev->ip_versions[MP1_HWIP][0]) { 1502 case IP_VERSION(11, 0, 7): 1503 case IP_VERSION(11, 0, 0): 1504 case IP_VERSION(11, 0, 5): 1505 case IP_VERSION(11, 0, 9): 1506 case IP_VERSION(13, 0, 7): 1507 return 0; 1508 default: 1509 break; 1510 } 1511 } 1512 1513 /* 1514 * For SMU 13.0.4/11, PMFW will handle the features disablement properly 1515 * for gpu reset case. Driver involvement is unnecessary. 1516 */ 1517 if (amdgpu_in_reset(adev)) { 1518 switch (adev->ip_versions[MP1_HWIP][0]) { 1519 case IP_VERSION(13, 0, 4): 1520 case IP_VERSION(13, 0, 11): 1521 return 0; 1522 default: 1523 break; 1524 } 1525 } 1526 1527 /* 1528 * For gpu reset, runpm and hibernation through BACO, 1529 * BACO feature has to be kept enabled. 1530 */ 1531 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1532 ret = smu_disable_all_features_with_exception(smu, 1533 SMU_FEATURE_BACO_BIT); 1534 if (ret) 1535 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1536 } else { 1537 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1538 if (!adev->scpm_enabled) { 1539 ret = smu_system_features_control(smu, false); 1540 if (ret) 1541 dev_err(adev->dev, "Failed to disable smu features.\n"); 1542 } 1543 } 1544 1545 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) && 1546 adev->gfx.rlc.funcs->stop) 1547 adev->gfx.rlc.funcs->stop(adev); 1548 1549 return ret; 1550 } 1551 1552 static int smu_smc_hw_cleanup(struct smu_context *smu) 1553 { 1554 struct amdgpu_device *adev = smu->adev; 1555 int ret = 0; 1556 1557 cancel_work_sync(&smu->throttling_logging_work); 1558 cancel_work_sync(&smu->interrupt_work); 1559 1560 ret = smu_disable_thermal_alert(smu); 1561 if (ret) { 1562 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1563 return ret; 1564 } 1565 1566 ret = smu_disable_dpms(smu); 1567 if (ret) { 1568 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1569 return ret; 1570 } 1571 1572 return 0; 1573 } 1574 1575 static int smu_hw_fini(void *handle) 1576 { 1577 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1578 struct smu_context *smu = adev->powerplay.pp_handle; 1579 1580 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1581 return 0; 1582 1583 smu_dpm_set_vcn_enable(smu, false); 1584 smu_dpm_set_jpeg_enable(smu, false); 1585 1586 adev->vcn.cur_state = AMD_PG_STATE_GATE; 1587 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 1588 1589 if (!smu->pm_enabled) 1590 return 0; 1591 1592 adev->pm.dpm_enabled = false; 1593 1594 return smu_smc_hw_cleanup(smu); 1595 } 1596 1597 static void smu_late_fini(void *handle) 1598 { 1599 struct amdgpu_device *adev = handle; 1600 struct smu_context *smu = adev->powerplay.pp_handle; 1601 1602 kfree(smu); 1603 } 1604 1605 static int smu_reset(struct smu_context *smu) 1606 { 1607 struct amdgpu_device *adev = smu->adev; 1608 int ret; 1609 1610 ret = smu_hw_fini(adev); 1611 if (ret) 1612 return ret; 1613 1614 ret = smu_hw_init(adev); 1615 if (ret) 1616 return ret; 1617 1618 ret = smu_late_init(adev); 1619 if (ret) 1620 return ret; 1621 1622 return 0; 1623 } 1624 1625 static int smu_suspend(void *handle) 1626 { 1627 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1628 struct smu_context *smu = adev->powerplay.pp_handle; 1629 int ret; 1630 uint64_t count; 1631 1632 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1633 return 0; 1634 1635 if (!smu->pm_enabled) 1636 return 0; 1637 1638 adev->pm.dpm_enabled = false; 1639 1640 ret = smu_smc_hw_cleanup(smu); 1641 if (ret) 1642 return ret; 1643 1644 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1645 1646 smu_set_gfx_cgpg(smu, false); 1647 1648 /* 1649 * pwfw resets entrycount when device is suspended, so we save the 1650 * last value to be used when we resume to keep it consistent 1651 */ 1652 ret = smu_get_entrycount_gfxoff(smu, &count); 1653 if (!ret) 1654 adev->gfx.gfx_off_entrycount = count; 1655 1656 return 0; 1657 } 1658 1659 static int smu_resume(void *handle) 1660 { 1661 int ret; 1662 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1663 struct smu_context *smu = adev->powerplay.pp_handle; 1664 1665 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1666 return 0; 1667 1668 if (!smu->pm_enabled) 1669 return 0; 1670 1671 dev_info(adev->dev, "SMU is resuming...\n"); 1672 1673 ret = smu_start_smc_engine(smu); 1674 if (ret) { 1675 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1676 return ret; 1677 } 1678 1679 ret = smu_smc_hw_setup(smu); 1680 if (ret) { 1681 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1682 return ret; 1683 } 1684 1685 ret = smu_set_gfx_imu_enable(smu); 1686 if (ret) 1687 return ret; 1688 1689 smu_set_gfx_cgpg(smu, true); 1690 1691 smu->disable_uclk_switch = 0; 1692 1693 adev->pm.dpm_enabled = true; 1694 1695 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1696 1697 return 0; 1698 } 1699 1700 static int smu_display_configuration_change(void *handle, 1701 const struct amd_pp_display_configuration *display_config) 1702 { 1703 struct smu_context *smu = handle; 1704 int index = 0; 1705 int num_of_active_display = 0; 1706 1707 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1708 return -EOPNOTSUPP; 1709 1710 if (!display_config) 1711 return -EINVAL; 1712 1713 smu_set_min_dcef_deep_sleep(smu, 1714 display_config->min_dcef_deep_sleep_set_clk / 100); 1715 1716 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1717 if (display_config->displays[index].controller_id != 0) 1718 num_of_active_display++; 1719 } 1720 1721 return 0; 1722 } 1723 1724 static int smu_set_clockgating_state(void *handle, 1725 enum amd_clockgating_state state) 1726 { 1727 return 0; 1728 } 1729 1730 static int smu_set_powergating_state(void *handle, 1731 enum amd_powergating_state state) 1732 { 1733 return 0; 1734 } 1735 1736 static int smu_enable_umd_pstate(void *handle, 1737 enum amd_dpm_forced_level *level) 1738 { 1739 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1740 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1741 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1742 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1743 1744 struct smu_context *smu = (struct smu_context*)(handle); 1745 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1746 1747 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1748 return -EINVAL; 1749 1750 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1751 /* enter umd pstate, save current level, disable gfx cg*/ 1752 if (*level & profile_mode_mask) { 1753 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1754 smu_gpo_control(smu, false); 1755 smu_gfx_ulv_control(smu, false); 1756 smu_deep_sleep_control(smu, false); 1757 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1758 } 1759 } else { 1760 /* exit umd pstate, restore level, enable gfx cg*/ 1761 if (!(*level & profile_mode_mask)) { 1762 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1763 *level = smu_dpm_ctx->saved_dpm_level; 1764 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1765 smu_deep_sleep_control(smu, true); 1766 smu_gfx_ulv_control(smu, true); 1767 smu_gpo_control(smu, true); 1768 } 1769 } 1770 1771 return 0; 1772 } 1773 1774 static int smu_bump_power_profile_mode(struct smu_context *smu, 1775 long *param, 1776 uint32_t param_size) 1777 { 1778 int ret = 0; 1779 1780 if (smu->ppt_funcs->set_power_profile_mode) 1781 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 1782 1783 return ret; 1784 } 1785 1786 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1787 enum amd_dpm_forced_level level, 1788 bool skip_display_settings) 1789 { 1790 int ret = 0; 1791 int index = 0; 1792 long workload; 1793 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1794 1795 if (!skip_display_settings) { 1796 ret = smu_display_config_changed(smu); 1797 if (ret) { 1798 dev_err(smu->adev->dev, "Failed to change display config!"); 1799 return ret; 1800 } 1801 } 1802 1803 ret = smu_apply_clocks_adjust_rules(smu); 1804 if (ret) { 1805 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1806 return ret; 1807 } 1808 1809 if (!skip_display_settings) { 1810 ret = smu_notify_smc_display_config(smu); 1811 if (ret) { 1812 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1813 return ret; 1814 } 1815 } 1816 1817 if (smu_dpm_ctx->dpm_level != level) { 1818 ret = smu_asic_set_performance_level(smu, level); 1819 if (ret) { 1820 dev_err(smu->adev->dev, "Failed to set performance level!"); 1821 return ret; 1822 } 1823 1824 /* update the saved copy */ 1825 smu_dpm_ctx->dpm_level = level; 1826 } 1827 1828 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1829 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1830 index = fls(smu->workload_mask); 1831 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1832 workload = smu->workload_setting[index]; 1833 1834 if (smu->power_profile_mode != workload) 1835 smu_bump_power_profile_mode(smu, &workload, 0); 1836 } 1837 1838 return ret; 1839 } 1840 1841 static int smu_handle_task(struct smu_context *smu, 1842 enum amd_dpm_forced_level level, 1843 enum amd_pp_task task_id) 1844 { 1845 int ret = 0; 1846 1847 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1848 return -EOPNOTSUPP; 1849 1850 switch (task_id) { 1851 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1852 ret = smu_pre_display_config_changed(smu); 1853 if (ret) 1854 return ret; 1855 ret = smu_adjust_power_state_dynamic(smu, level, false); 1856 break; 1857 case AMD_PP_TASK_COMPLETE_INIT: 1858 case AMD_PP_TASK_READJUST_POWER_STATE: 1859 ret = smu_adjust_power_state_dynamic(smu, level, true); 1860 break; 1861 default: 1862 break; 1863 } 1864 1865 return ret; 1866 } 1867 1868 static int smu_handle_dpm_task(void *handle, 1869 enum amd_pp_task task_id, 1870 enum amd_pm_state_type *user_state) 1871 { 1872 struct smu_context *smu = handle; 1873 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1874 1875 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 1876 1877 } 1878 1879 static int smu_switch_power_profile(void *handle, 1880 enum PP_SMC_POWER_PROFILE type, 1881 bool en) 1882 { 1883 struct smu_context *smu = handle; 1884 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1885 long workload; 1886 uint32_t index; 1887 1888 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1889 return -EOPNOTSUPP; 1890 1891 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1892 return -EINVAL; 1893 1894 if (!en) { 1895 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1896 index = fls(smu->workload_mask); 1897 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1898 workload = smu->workload_setting[index]; 1899 } else { 1900 smu->workload_mask |= (1 << smu->workload_prority[type]); 1901 index = fls(smu->workload_mask); 1902 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1903 workload = smu->workload_setting[index]; 1904 } 1905 1906 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1907 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 1908 smu_bump_power_profile_mode(smu, &workload, 0); 1909 1910 return 0; 1911 } 1912 1913 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 1914 { 1915 struct smu_context *smu = handle; 1916 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1917 1918 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1919 return -EOPNOTSUPP; 1920 1921 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1922 return -EINVAL; 1923 1924 return smu_dpm_ctx->dpm_level; 1925 } 1926 1927 static int smu_force_performance_level(void *handle, 1928 enum amd_dpm_forced_level level) 1929 { 1930 struct smu_context *smu = handle; 1931 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1932 int ret = 0; 1933 1934 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1935 return -EOPNOTSUPP; 1936 1937 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1938 return -EINVAL; 1939 1940 ret = smu_enable_umd_pstate(smu, &level); 1941 if (ret) 1942 return ret; 1943 1944 ret = smu_handle_task(smu, level, 1945 AMD_PP_TASK_READJUST_POWER_STATE); 1946 1947 /* reset user dpm clock state */ 1948 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1949 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 1950 smu->user_dpm_profile.clk_dependency = 0; 1951 } 1952 1953 return ret; 1954 } 1955 1956 static int smu_set_display_count(void *handle, uint32_t count) 1957 { 1958 struct smu_context *smu = handle; 1959 1960 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1961 return -EOPNOTSUPP; 1962 1963 return smu_init_display_count(smu, count); 1964 } 1965 1966 static int smu_force_smuclk_levels(struct smu_context *smu, 1967 enum smu_clk_type clk_type, 1968 uint32_t mask) 1969 { 1970 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1971 int ret = 0; 1972 1973 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1974 return -EOPNOTSUPP; 1975 1976 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1977 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1978 return -EINVAL; 1979 } 1980 1981 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 1982 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1983 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 1984 smu->user_dpm_profile.clk_mask[clk_type] = mask; 1985 smu_set_user_clk_dependencies(smu, clk_type); 1986 } 1987 } 1988 1989 return ret; 1990 } 1991 1992 static int smu_force_ppclk_levels(void *handle, 1993 enum pp_clock_type type, 1994 uint32_t mask) 1995 { 1996 struct smu_context *smu = handle; 1997 enum smu_clk_type clk_type; 1998 1999 switch (type) { 2000 case PP_SCLK: 2001 clk_type = SMU_SCLK; break; 2002 case PP_MCLK: 2003 clk_type = SMU_MCLK; break; 2004 case PP_PCIE: 2005 clk_type = SMU_PCIE; break; 2006 case PP_SOCCLK: 2007 clk_type = SMU_SOCCLK; break; 2008 case PP_FCLK: 2009 clk_type = SMU_FCLK; break; 2010 case PP_DCEFCLK: 2011 clk_type = SMU_DCEFCLK; break; 2012 case PP_VCLK: 2013 clk_type = SMU_VCLK; break; 2014 case PP_DCLK: 2015 clk_type = SMU_DCLK; break; 2016 case OD_SCLK: 2017 clk_type = SMU_OD_SCLK; break; 2018 case OD_MCLK: 2019 clk_type = SMU_OD_MCLK; break; 2020 case OD_VDDC_CURVE: 2021 clk_type = SMU_OD_VDDC_CURVE; break; 2022 case OD_RANGE: 2023 clk_type = SMU_OD_RANGE; break; 2024 default: 2025 return -EINVAL; 2026 } 2027 2028 return smu_force_smuclk_levels(smu, clk_type, mask); 2029 } 2030 2031 /* 2032 * On system suspending or resetting, the dpm_enabled 2033 * flag will be cleared. So that those SMU services which 2034 * are not supported will be gated. 2035 * However, the mp1 state setting should still be granted 2036 * even if the dpm_enabled cleared. 2037 */ 2038 static int smu_set_mp1_state(void *handle, 2039 enum pp_mp1_state mp1_state) 2040 { 2041 struct smu_context *smu = handle; 2042 int ret = 0; 2043 2044 if (!smu->pm_enabled) 2045 return -EOPNOTSUPP; 2046 2047 if (smu->ppt_funcs && 2048 smu->ppt_funcs->set_mp1_state) 2049 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2050 2051 return ret; 2052 } 2053 2054 static int smu_set_df_cstate(void *handle, 2055 enum pp_df_cstate state) 2056 { 2057 struct smu_context *smu = handle; 2058 int ret = 0; 2059 2060 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2061 return -EOPNOTSUPP; 2062 2063 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2064 return 0; 2065 2066 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2067 if (ret) 2068 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2069 2070 return ret; 2071 } 2072 2073 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 2074 { 2075 int ret = 0; 2076 2077 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2078 return -EOPNOTSUPP; 2079 2080 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 2081 return 0; 2082 2083 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 2084 if (ret) 2085 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 2086 2087 return ret; 2088 } 2089 2090 int smu_write_watermarks_table(struct smu_context *smu) 2091 { 2092 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2093 return -EOPNOTSUPP; 2094 2095 return smu_set_watermarks_table(smu, NULL); 2096 } 2097 2098 static int smu_set_watermarks_for_clock_ranges(void *handle, 2099 struct pp_smu_wm_range_sets *clock_ranges) 2100 { 2101 struct smu_context *smu = handle; 2102 2103 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2104 return -EOPNOTSUPP; 2105 2106 if (smu->disable_watermark) 2107 return 0; 2108 2109 return smu_set_watermarks_table(smu, clock_ranges); 2110 } 2111 2112 int smu_set_ac_dc(struct smu_context *smu) 2113 { 2114 int ret = 0; 2115 2116 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2117 return -EOPNOTSUPP; 2118 2119 /* controlled by firmware */ 2120 if (smu->dc_controlled_by_gpio) 2121 return 0; 2122 2123 ret = smu_set_power_source(smu, 2124 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2125 SMU_POWER_SOURCE_DC); 2126 if (ret) 2127 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2128 smu->adev->pm.ac_power ? "AC" : "DC"); 2129 2130 return ret; 2131 } 2132 2133 const struct amd_ip_funcs smu_ip_funcs = { 2134 .name = "smu", 2135 .early_init = smu_early_init, 2136 .late_init = smu_late_init, 2137 .sw_init = smu_sw_init, 2138 .sw_fini = smu_sw_fini, 2139 .hw_init = smu_hw_init, 2140 .hw_fini = smu_hw_fini, 2141 .late_fini = smu_late_fini, 2142 .suspend = smu_suspend, 2143 .resume = smu_resume, 2144 .is_idle = NULL, 2145 .check_soft_reset = NULL, 2146 .wait_for_idle = NULL, 2147 .soft_reset = NULL, 2148 .set_clockgating_state = smu_set_clockgating_state, 2149 .set_powergating_state = smu_set_powergating_state, 2150 }; 2151 2152 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 2153 { 2154 .type = AMD_IP_BLOCK_TYPE_SMC, 2155 .major = 11, 2156 .minor = 0, 2157 .rev = 0, 2158 .funcs = &smu_ip_funcs, 2159 }; 2160 2161 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 2162 { 2163 .type = AMD_IP_BLOCK_TYPE_SMC, 2164 .major = 12, 2165 .minor = 0, 2166 .rev = 0, 2167 .funcs = &smu_ip_funcs, 2168 }; 2169 2170 const struct amdgpu_ip_block_version smu_v13_0_ip_block = 2171 { 2172 .type = AMD_IP_BLOCK_TYPE_SMC, 2173 .major = 13, 2174 .minor = 0, 2175 .rev = 0, 2176 .funcs = &smu_ip_funcs, 2177 }; 2178 2179 static int smu_load_microcode(void *handle) 2180 { 2181 struct smu_context *smu = handle; 2182 struct amdgpu_device *adev = smu->adev; 2183 int ret = 0; 2184 2185 if (!smu->pm_enabled) 2186 return -EOPNOTSUPP; 2187 2188 /* This should be used for non PSP loading */ 2189 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2190 return 0; 2191 2192 if (smu->ppt_funcs->load_microcode) { 2193 ret = smu->ppt_funcs->load_microcode(smu); 2194 if (ret) { 2195 dev_err(adev->dev, "Load microcode failed\n"); 2196 return ret; 2197 } 2198 } 2199 2200 if (smu->ppt_funcs->check_fw_status) { 2201 ret = smu->ppt_funcs->check_fw_status(smu); 2202 if (ret) { 2203 dev_err(adev->dev, "SMC is not ready\n"); 2204 return ret; 2205 } 2206 } 2207 2208 return ret; 2209 } 2210 2211 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2212 { 2213 int ret = 0; 2214 2215 if (smu->ppt_funcs->set_gfx_cgpg) 2216 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2217 2218 return ret; 2219 } 2220 2221 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2222 { 2223 struct smu_context *smu = handle; 2224 int ret = 0; 2225 2226 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2227 return -EOPNOTSUPP; 2228 2229 if (!smu->ppt_funcs->set_fan_speed_rpm) 2230 return -EOPNOTSUPP; 2231 2232 if (speed == U32_MAX) 2233 return -EINVAL; 2234 2235 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2236 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2237 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2238 smu->user_dpm_profile.fan_speed_rpm = speed; 2239 2240 /* Override custom PWM setting as they cannot co-exist */ 2241 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2242 smu->user_dpm_profile.fan_speed_pwm = 0; 2243 } 2244 2245 return ret; 2246 } 2247 2248 /** 2249 * smu_get_power_limit - Request one of the SMU Power Limits 2250 * 2251 * @handle: pointer to smu context 2252 * @limit: requested limit is written back to this variable 2253 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2254 * @pp_power_type: &pp_power_type type of power 2255 * Return: 0 on success, <0 on error 2256 * 2257 */ 2258 int smu_get_power_limit(void *handle, 2259 uint32_t *limit, 2260 enum pp_power_limit_level pp_limit_level, 2261 enum pp_power_type pp_power_type) 2262 { 2263 struct smu_context *smu = handle; 2264 struct amdgpu_device *adev = smu->adev; 2265 enum smu_ppt_limit_level limit_level; 2266 uint32_t limit_type; 2267 int ret = 0; 2268 2269 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2270 return -EOPNOTSUPP; 2271 2272 switch(pp_power_type) { 2273 case PP_PWR_TYPE_SUSTAINED: 2274 limit_type = SMU_DEFAULT_PPT_LIMIT; 2275 break; 2276 case PP_PWR_TYPE_FAST: 2277 limit_type = SMU_FAST_PPT_LIMIT; 2278 break; 2279 default: 2280 return -EOPNOTSUPP; 2281 break; 2282 } 2283 2284 switch(pp_limit_level){ 2285 case PP_PWR_LIMIT_CURRENT: 2286 limit_level = SMU_PPT_LIMIT_CURRENT; 2287 break; 2288 case PP_PWR_LIMIT_DEFAULT: 2289 limit_level = SMU_PPT_LIMIT_DEFAULT; 2290 break; 2291 case PP_PWR_LIMIT_MAX: 2292 limit_level = SMU_PPT_LIMIT_MAX; 2293 break; 2294 case PP_PWR_LIMIT_MIN: 2295 default: 2296 return -EOPNOTSUPP; 2297 break; 2298 } 2299 2300 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2301 if (smu->ppt_funcs->get_ppt_limit) 2302 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2303 } else { 2304 switch (limit_level) { 2305 case SMU_PPT_LIMIT_CURRENT: 2306 switch (adev->ip_versions[MP1_HWIP][0]) { 2307 case IP_VERSION(13, 0, 2): 2308 case IP_VERSION(11, 0, 7): 2309 case IP_VERSION(11, 0, 11): 2310 case IP_VERSION(11, 0, 12): 2311 case IP_VERSION(11, 0, 13): 2312 ret = smu_get_asic_power_limits(smu, 2313 &smu->current_power_limit, 2314 NULL, 2315 NULL); 2316 break; 2317 default: 2318 break; 2319 } 2320 *limit = smu->current_power_limit; 2321 break; 2322 case SMU_PPT_LIMIT_DEFAULT: 2323 *limit = smu->default_power_limit; 2324 break; 2325 case SMU_PPT_LIMIT_MAX: 2326 *limit = smu->max_power_limit; 2327 break; 2328 default: 2329 break; 2330 } 2331 } 2332 2333 return ret; 2334 } 2335 2336 static int smu_set_power_limit(void *handle, uint32_t limit) 2337 { 2338 struct smu_context *smu = handle; 2339 uint32_t limit_type = limit >> 24; 2340 int ret = 0; 2341 2342 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2343 return -EOPNOTSUPP; 2344 2345 limit &= (1<<24)-1; 2346 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2347 if (smu->ppt_funcs->set_power_limit) 2348 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2349 2350 if (limit > smu->max_power_limit) { 2351 dev_err(smu->adev->dev, 2352 "New power limit (%d) is over the max allowed %d\n", 2353 limit, smu->max_power_limit); 2354 return -EINVAL; 2355 } 2356 2357 if (!limit) 2358 limit = smu->current_power_limit; 2359 2360 if (smu->ppt_funcs->set_power_limit) { 2361 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2362 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2363 smu->user_dpm_profile.power_limit = limit; 2364 } 2365 2366 return ret; 2367 } 2368 2369 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2370 { 2371 int ret = 0; 2372 2373 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2374 return -EOPNOTSUPP; 2375 2376 if (smu->ppt_funcs->print_clk_levels) 2377 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2378 2379 return ret; 2380 } 2381 2382 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2383 { 2384 enum smu_clk_type clk_type; 2385 2386 switch (type) { 2387 case PP_SCLK: 2388 clk_type = SMU_SCLK; break; 2389 case PP_MCLK: 2390 clk_type = SMU_MCLK; break; 2391 case PP_PCIE: 2392 clk_type = SMU_PCIE; break; 2393 case PP_SOCCLK: 2394 clk_type = SMU_SOCCLK; break; 2395 case PP_FCLK: 2396 clk_type = SMU_FCLK; break; 2397 case PP_DCEFCLK: 2398 clk_type = SMU_DCEFCLK; break; 2399 case PP_VCLK: 2400 clk_type = SMU_VCLK; break; 2401 case PP_DCLK: 2402 clk_type = SMU_DCLK; break; 2403 case OD_SCLK: 2404 clk_type = SMU_OD_SCLK; break; 2405 case OD_MCLK: 2406 clk_type = SMU_OD_MCLK; break; 2407 case OD_VDDC_CURVE: 2408 clk_type = SMU_OD_VDDC_CURVE; break; 2409 case OD_RANGE: 2410 clk_type = SMU_OD_RANGE; break; 2411 case OD_VDDGFX_OFFSET: 2412 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2413 case OD_CCLK: 2414 clk_type = SMU_OD_CCLK; break; 2415 default: 2416 clk_type = SMU_CLK_COUNT; break; 2417 } 2418 2419 return clk_type; 2420 } 2421 2422 static int smu_print_ppclk_levels(void *handle, 2423 enum pp_clock_type type, 2424 char *buf) 2425 { 2426 struct smu_context *smu = handle; 2427 enum smu_clk_type clk_type; 2428 2429 clk_type = smu_convert_to_smuclk(type); 2430 if (clk_type == SMU_CLK_COUNT) 2431 return -EINVAL; 2432 2433 return smu_print_smuclk_levels(smu, clk_type, buf); 2434 } 2435 2436 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2437 { 2438 struct smu_context *smu = handle; 2439 enum smu_clk_type clk_type; 2440 2441 clk_type = smu_convert_to_smuclk(type); 2442 if (clk_type == SMU_CLK_COUNT) 2443 return -EINVAL; 2444 2445 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2446 return -EOPNOTSUPP; 2447 2448 if (!smu->ppt_funcs->emit_clk_levels) 2449 return -ENOENT; 2450 2451 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2452 2453 } 2454 2455 static int smu_od_edit_dpm_table(void *handle, 2456 enum PP_OD_DPM_TABLE_COMMAND type, 2457 long *input, uint32_t size) 2458 { 2459 struct smu_context *smu = handle; 2460 int ret = 0; 2461 2462 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2463 return -EOPNOTSUPP; 2464 2465 if (smu->ppt_funcs->od_edit_dpm_table) { 2466 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2467 } 2468 2469 return ret; 2470 } 2471 2472 static int smu_read_sensor(void *handle, 2473 int sensor, 2474 void *data, 2475 int *size_arg) 2476 { 2477 struct smu_context *smu = handle; 2478 struct smu_umd_pstate_table *pstate_table = 2479 &smu->pstate_table; 2480 int ret = 0; 2481 uint32_t *size, size_val; 2482 2483 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2484 return -EOPNOTSUPP; 2485 2486 if (!data || !size_arg) 2487 return -EINVAL; 2488 2489 size_val = *size_arg; 2490 size = &size_val; 2491 2492 if (smu->ppt_funcs->read_sensor) 2493 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2494 goto unlock; 2495 2496 switch (sensor) { 2497 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2498 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2499 *size = 4; 2500 break; 2501 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2502 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2503 *size = 4; 2504 break; 2505 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2506 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 2507 *size = 8; 2508 break; 2509 case AMDGPU_PP_SENSOR_UVD_POWER: 2510 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2511 *size = 4; 2512 break; 2513 case AMDGPU_PP_SENSOR_VCE_POWER: 2514 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2515 *size = 4; 2516 break; 2517 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2518 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2519 *size = 4; 2520 break; 2521 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2522 *(uint32_t *)data = 0; 2523 *size = 4; 2524 break; 2525 default: 2526 *size = 0; 2527 ret = -EOPNOTSUPP; 2528 break; 2529 } 2530 2531 unlock: 2532 // assign uint32_t to int 2533 *size_arg = size_val; 2534 2535 return ret; 2536 } 2537 2538 static int smu_get_power_profile_mode(void *handle, char *buf) 2539 { 2540 struct smu_context *smu = handle; 2541 2542 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2543 !smu->ppt_funcs->get_power_profile_mode) 2544 return -EOPNOTSUPP; 2545 if (!buf) 2546 return -EINVAL; 2547 2548 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 2549 } 2550 2551 static int smu_set_power_profile_mode(void *handle, 2552 long *param, 2553 uint32_t param_size) 2554 { 2555 struct smu_context *smu = handle; 2556 2557 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2558 !smu->ppt_funcs->set_power_profile_mode) 2559 return -EOPNOTSUPP; 2560 2561 return smu_bump_power_profile_mode(smu, param, param_size); 2562 } 2563 2564 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 2565 { 2566 struct smu_context *smu = handle; 2567 2568 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2569 return -EOPNOTSUPP; 2570 2571 if (!smu->ppt_funcs->get_fan_control_mode) 2572 return -EOPNOTSUPP; 2573 2574 if (!fan_mode) 2575 return -EINVAL; 2576 2577 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 2578 2579 return 0; 2580 } 2581 2582 static int smu_set_fan_control_mode(void *handle, u32 value) 2583 { 2584 struct smu_context *smu = handle; 2585 int ret = 0; 2586 2587 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2588 return -EOPNOTSUPP; 2589 2590 if (!smu->ppt_funcs->set_fan_control_mode) 2591 return -EOPNOTSUPP; 2592 2593 if (value == U32_MAX) 2594 return -EINVAL; 2595 2596 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2597 if (ret) 2598 goto out; 2599 2600 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2601 smu->user_dpm_profile.fan_mode = value; 2602 2603 /* reset user dpm fan speed */ 2604 if (value != AMD_FAN_CTRL_MANUAL) { 2605 smu->user_dpm_profile.fan_speed_pwm = 0; 2606 smu->user_dpm_profile.fan_speed_rpm = 0; 2607 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 2608 } 2609 } 2610 2611 out: 2612 return ret; 2613 } 2614 2615 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 2616 { 2617 struct smu_context *smu = handle; 2618 int ret = 0; 2619 2620 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2621 return -EOPNOTSUPP; 2622 2623 if (!smu->ppt_funcs->get_fan_speed_pwm) 2624 return -EOPNOTSUPP; 2625 2626 if (!speed) 2627 return -EINVAL; 2628 2629 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 2630 2631 return ret; 2632 } 2633 2634 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 2635 { 2636 struct smu_context *smu = handle; 2637 int ret = 0; 2638 2639 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2640 return -EOPNOTSUPP; 2641 2642 if (!smu->ppt_funcs->set_fan_speed_pwm) 2643 return -EOPNOTSUPP; 2644 2645 if (speed == U32_MAX) 2646 return -EINVAL; 2647 2648 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 2649 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2650 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 2651 smu->user_dpm_profile.fan_speed_pwm = speed; 2652 2653 /* Override custom RPM setting as they cannot co-exist */ 2654 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 2655 smu->user_dpm_profile.fan_speed_rpm = 0; 2656 } 2657 2658 return ret; 2659 } 2660 2661 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 2662 { 2663 struct smu_context *smu = handle; 2664 int ret = 0; 2665 2666 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2667 return -EOPNOTSUPP; 2668 2669 if (!smu->ppt_funcs->get_fan_speed_rpm) 2670 return -EOPNOTSUPP; 2671 2672 if (!speed) 2673 return -EINVAL; 2674 2675 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 2676 2677 return ret; 2678 } 2679 2680 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 2681 { 2682 struct smu_context *smu = handle; 2683 2684 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2685 return -EOPNOTSUPP; 2686 2687 return smu_set_min_dcef_deep_sleep(smu, clk); 2688 } 2689 2690 static int smu_get_clock_by_type_with_latency(void *handle, 2691 enum amd_pp_clock_type type, 2692 struct pp_clock_levels_with_latency *clocks) 2693 { 2694 struct smu_context *smu = handle; 2695 enum smu_clk_type clk_type; 2696 int ret = 0; 2697 2698 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2699 return -EOPNOTSUPP; 2700 2701 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 2702 switch (type) { 2703 case amd_pp_sys_clock: 2704 clk_type = SMU_GFXCLK; 2705 break; 2706 case amd_pp_mem_clock: 2707 clk_type = SMU_MCLK; 2708 break; 2709 case amd_pp_dcef_clock: 2710 clk_type = SMU_DCEFCLK; 2711 break; 2712 case amd_pp_disp_clock: 2713 clk_type = SMU_DISPCLK; 2714 break; 2715 default: 2716 dev_err(smu->adev->dev, "Invalid clock type!\n"); 2717 return -EINVAL; 2718 } 2719 2720 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2721 } 2722 2723 return ret; 2724 } 2725 2726 static int smu_display_clock_voltage_request(void *handle, 2727 struct pp_display_clock_request *clock_req) 2728 { 2729 struct smu_context *smu = handle; 2730 int ret = 0; 2731 2732 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2733 return -EOPNOTSUPP; 2734 2735 if (smu->ppt_funcs->display_clock_voltage_request) 2736 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2737 2738 return ret; 2739 } 2740 2741 2742 static int smu_display_disable_memory_clock_switch(void *handle, 2743 bool disable_memory_clock_switch) 2744 { 2745 struct smu_context *smu = handle; 2746 int ret = -EINVAL; 2747 2748 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2749 return -EOPNOTSUPP; 2750 2751 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2752 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2753 2754 return ret; 2755 } 2756 2757 static int smu_set_xgmi_pstate(void *handle, 2758 uint32_t pstate) 2759 { 2760 struct smu_context *smu = handle; 2761 int ret = 0; 2762 2763 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2764 return -EOPNOTSUPP; 2765 2766 if (smu->ppt_funcs->set_xgmi_pstate) 2767 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2768 2769 if(ret) 2770 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2771 2772 return ret; 2773 } 2774 2775 static int smu_get_baco_capability(void *handle, bool *cap) 2776 { 2777 struct smu_context *smu = handle; 2778 2779 *cap = false; 2780 2781 if (!smu->pm_enabled) 2782 return 0; 2783 2784 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2785 *cap = smu->ppt_funcs->baco_is_support(smu); 2786 2787 return 0; 2788 } 2789 2790 static int smu_baco_set_state(void *handle, int state) 2791 { 2792 struct smu_context *smu = handle; 2793 int ret = 0; 2794 2795 if (!smu->pm_enabled) 2796 return -EOPNOTSUPP; 2797 2798 if (state == 0) { 2799 if (smu->ppt_funcs->baco_exit) 2800 ret = smu->ppt_funcs->baco_exit(smu); 2801 } else if (state == 1) { 2802 if (smu->ppt_funcs->baco_enter) 2803 ret = smu->ppt_funcs->baco_enter(smu); 2804 } else { 2805 return -EINVAL; 2806 } 2807 2808 if (ret) 2809 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 2810 (state)?"enter":"exit"); 2811 2812 return ret; 2813 } 2814 2815 bool smu_mode1_reset_is_support(struct smu_context *smu) 2816 { 2817 bool ret = false; 2818 2819 if (!smu->pm_enabled) 2820 return false; 2821 2822 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2823 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2824 2825 return ret; 2826 } 2827 2828 bool smu_mode2_reset_is_support(struct smu_context *smu) 2829 { 2830 bool ret = false; 2831 2832 if (!smu->pm_enabled) 2833 return false; 2834 2835 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 2836 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 2837 2838 return ret; 2839 } 2840 2841 int smu_mode1_reset(struct smu_context *smu) 2842 { 2843 int ret = 0; 2844 2845 if (!smu->pm_enabled) 2846 return -EOPNOTSUPP; 2847 2848 if (smu->ppt_funcs->mode1_reset) 2849 ret = smu->ppt_funcs->mode1_reset(smu); 2850 2851 return ret; 2852 } 2853 2854 static int smu_mode2_reset(void *handle) 2855 { 2856 struct smu_context *smu = handle; 2857 int ret = 0; 2858 2859 if (!smu->pm_enabled) 2860 return -EOPNOTSUPP; 2861 2862 if (smu->ppt_funcs->mode2_reset) 2863 ret = smu->ppt_funcs->mode2_reset(smu); 2864 2865 if (ret) 2866 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2867 2868 return ret; 2869 } 2870 2871 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 2872 struct pp_smu_nv_clock_table *max_clocks) 2873 { 2874 struct smu_context *smu = handle; 2875 int ret = 0; 2876 2877 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2878 return -EOPNOTSUPP; 2879 2880 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2881 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2882 2883 return ret; 2884 } 2885 2886 static int smu_get_uclk_dpm_states(void *handle, 2887 unsigned int *clock_values_in_khz, 2888 unsigned int *num_states) 2889 { 2890 struct smu_context *smu = handle; 2891 int ret = 0; 2892 2893 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2894 return -EOPNOTSUPP; 2895 2896 if (smu->ppt_funcs->get_uclk_dpm_states) 2897 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2898 2899 return ret; 2900 } 2901 2902 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 2903 { 2904 struct smu_context *smu = handle; 2905 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2906 2907 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2908 return -EOPNOTSUPP; 2909 2910 if (smu->ppt_funcs->get_current_power_state) 2911 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2912 2913 return pm_state; 2914 } 2915 2916 static int smu_get_dpm_clock_table(void *handle, 2917 struct dpm_clocks *clock_table) 2918 { 2919 struct smu_context *smu = handle; 2920 int ret = 0; 2921 2922 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2923 return -EOPNOTSUPP; 2924 2925 if (smu->ppt_funcs->get_dpm_clock_table) 2926 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 2927 2928 return ret; 2929 } 2930 2931 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 2932 { 2933 struct smu_context *smu = handle; 2934 2935 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2936 return -EOPNOTSUPP; 2937 2938 if (!smu->ppt_funcs->get_gpu_metrics) 2939 return -EOPNOTSUPP; 2940 2941 return smu->ppt_funcs->get_gpu_metrics(smu, table); 2942 } 2943 2944 static int smu_enable_mgpu_fan_boost(void *handle) 2945 { 2946 struct smu_context *smu = handle; 2947 int ret = 0; 2948 2949 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2950 return -EOPNOTSUPP; 2951 2952 if (smu->ppt_funcs->enable_mgpu_fan_boost) 2953 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 2954 2955 return ret; 2956 } 2957 2958 static int smu_gfx_state_change_set(void *handle, 2959 uint32_t state) 2960 { 2961 struct smu_context *smu = handle; 2962 int ret = 0; 2963 2964 if (smu->ppt_funcs->gfx_state_change_set) 2965 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 2966 2967 return ret; 2968 } 2969 2970 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 2971 { 2972 int ret = 0; 2973 2974 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 2975 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 2976 2977 return ret; 2978 } 2979 2980 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 2981 { 2982 int ret = -EOPNOTSUPP; 2983 2984 if (smu->ppt_funcs && 2985 smu->ppt_funcs->get_ecc_info) 2986 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 2987 2988 return ret; 2989 2990 } 2991 2992 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 2993 { 2994 struct smu_context *smu = handle; 2995 struct smu_table_context *smu_table = &smu->smu_table; 2996 struct smu_table *memory_pool = &smu_table->memory_pool; 2997 2998 if (!addr || !size) 2999 return -EINVAL; 3000 3001 *addr = NULL; 3002 *size = 0; 3003 if (memory_pool->bo) { 3004 *addr = memory_pool->cpu_addr; 3005 *size = memory_pool->size; 3006 } 3007 3008 return 0; 3009 } 3010 3011 static const struct amd_pm_funcs swsmu_pm_funcs = { 3012 /* export for sysfs */ 3013 .set_fan_control_mode = smu_set_fan_control_mode, 3014 .get_fan_control_mode = smu_get_fan_control_mode, 3015 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3016 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3017 .force_clock_level = smu_force_ppclk_levels, 3018 .print_clock_levels = smu_print_ppclk_levels, 3019 .emit_clock_levels = smu_emit_ppclk_levels, 3020 .force_performance_level = smu_force_performance_level, 3021 .read_sensor = smu_read_sensor, 3022 .get_performance_level = smu_get_performance_level, 3023 .get_current_power_state = smu_get_current_power_state, 3024 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3025 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3026 .get_pp_num_states = smu_get_power_num_states, 3027 .get_pp_table = smu_sys_get_pp_table, 3028 .set_pp_table = smu_sys_set_pp_table, 3029 .switch_power_profile = smu_switch_power_profile, 3030 /* export to amdgpu */ 3031 .dispatch_tasks = smu_handle_dpm_task, 3032 .load_firmware = smu_load_microcode, 3033 .set_powergating_by_smu = smu_dpm_set_power_gate, 3034 .set_power_limit = smu_set_power_limit, 3035 .get_power_limit = smu_get_power_limit, 3036 .get_power_profile_mode = smu_get_power_profile_mode, 3037 .set_power_profile_mode = smu_set_power_profile_mode, 3038 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3039 .set_mp1_state = smu_set_mp1_state, 3040 .gfx_state_change_set = smu_gfx_state_change_set, 3041 /* export to DC */ 3042 .get_sclk = smu_get_sclk, 3043 .get_mclk = smu_get_mclk, 3044 .display_configuration_change = smu_display_configuration_change, 3045 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3046 .display_clock_voltage_request = smu_display_clock_voltage_request, 3047 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3048 .set_active_display_count = smu_set_display_count, 3049 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3050 .get_asic_baco_capability = smu_get_baco_capability, 3051 .set_asic_baco_state = smu_baco_set_state, 3052 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3053 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3054 .asic_reset_mode_2 = smu_mode2_reset, 3055 .set_df_cstate = smu_set_df_cstate, 3056 .set_xgmi_pstate = smu_set_xgmi_pstate, 3057 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3058 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3059 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3060 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3061 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3062 .get_dpm_clock_table = smu_get_dpm_clock_table, 3063 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3064 }; 3065 3066 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3067 uint64_t event_arg) 3068 { 3069 int ret = -EINVAL; 3070 3071 if (smu->ppt_funcs->wait_for_event) 3072 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3073 3074 return ret; 3075 } 3076 3077 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3078 { 3079 3080 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3081 return -EOPNOTSUPP; 3082 3083 /* Confirm the buffer allocated is of correct size */ 3084 if (size != smu->stb_context.stb_buf_size) 3085 return -EINVAL; 3086 3087 /* 3088 * No need to lock smu mutex as we access STB directly through MMIO 3089 * and not going through SMU messaging route (for now at least). 3090 * For registers access rely on implementation internal locking. 3091 */ 3092 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3093 } 3094 3095 #if defined(CONFIG_DEBUG_FS) 3096 3097 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3098 { 3099 struct amdgpu_device *adev = filp->f_inode->i_private; 3100 struct smu_context *smu = adev->powerplay.pp_handle; 3101 unsigned char *buf; 3102 int r; 3103 3104 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3105 if (!buf) 3106 return -ENOMEM; 3107 3108 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3109 if (r) 3110 goto out; 3111 3112 filp->private_data = buf; 3113 3114 return 0; 3115 3116 out: 3117 kvfree(buf); 3118 return r; 3119 } 3120 3121 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3122 loff_t *pos) 3123 { 3124 struct amdgpu_device *adev = filp->f_inode->i_private; 3125 struct smu_context *smu = adev->powerplay.pp_handle; 3126 3127 3128 if (!filp->private_data) 3129 return -EINVAL; 3130 3131 return simple_read_from_buffer(buf, 3132 size, 3133 pos, filp->private_data, 3134 smu->stb_context.stb_buf_size); 3135 } 3136 3137 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3138 { 3139 kvfree(filp->private_data); 3140 filp->private_data = NULL; 3141 3142 return 0; 3143 } 3144 3145 /* 3146 * We have to define not only read method but also 3147 * open and release because .read takes up to PAGE_SIZE 3148 * data each time so and so is invoked multiple times. 3149 * We allocate the STB buffer in .open and release it 3150 * in .release 3151 */ 3152 static const struct file_operations smu_stb_debugfs_fops = { 3153 .owner = THIS_MODULE, 3154 .open = smu_stb_debugfs_open, 3155 .read = smu_stb_debugfs_read, 3156 .release = smu_stb_debugfs_release, 3157 .llseek = default_llseek, 3158 }; 3159 3160 #endif 3161 3162 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3163 { 3164 #if defined(CONFIG_DEBUG_FS) 3165 3166 struct smu_context *smu = adev->powerplay.pp_handle; 3167 3168 if (!smu || (!smu->stb_context.stb_buf_size)) 3169 return; 3170 3171 debugfs_create_file_size("amdgpu_smu_stb_dump", 3172 S_IRUSR, 3173 adev_to_drm(adev)->primary->debugfs_root, 3174 adev, 3175 &smu_stb_debugfs_fops, 3176 smu->stb_context.stb_buf_size); 3177 #endif 3178 } 3179 3180 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3181 { 3182 int ret = 0; 3183 3184 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3185 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3186 3187 return ret; 3188 } 3189 3190 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3191 { 3192 int ret = 0; 3193 3194 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3195 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3196 3197 return ret; 3198 } 3199