1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "vangogh_ppt.h" 37 #include "aldebaran_ppt.h" 38 #include "yellow_carp_ppt.h" 39 #include "cyan_skillfish_ppt.h" 40 #include "amd_pcie.h" 41 42 /* 43 * DO NOT use these for err/warn/info/debug messages. 44 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 45 * They are more MGPU friendly. 46 */ 47 #undef pr_err 48 #undef pr_warn 49 #undef pr_info 50 #undef pr_debug 51 52 static const struct amd_pm_funcs swsmu_pm_funcs; 53 static int smu_force_smuclk_levels(struct smu_context *smu, 54 enum smu_clk_type clk_type, 55 uint32_t mask); 56 static int smu_handle_task(struct smu_context *smu, 57 enum amd_dpm_forced_level level, 58 enum amd_pp_task task_id, 59 bool lock_needed); 60 static int smu_reset(struct smu_context *smu); 61 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 62 static int smu_set_fan_control_mode(struct smu_context *smu, int value); 63 static int smu_set_power_limit(void *handle, uint32_t limit); 64 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 65 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 66 67 static int smu_sys_get_pp_feature_mask(void *handle, 68 char *buf) 69 { 70 struct smu_context *smu = handle; 71 int size = 0; 72 73 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 74 return -EOPNOTSUPP; 75 76 mutex_lock(&smu->mutex); 77 78 size = smu_get_pp_feature_mask(smu, buf); 79 80 mutex_unlock(&smu->mutex); 81 82 return size; 83 } 84 85 static int smu_sys_set_pp_feature_mask(void *handle, 86 uint64_t new_mask) 87 { 88 struct smu_context *smu = handle; 89 int ret = 0; 90 91 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 92 return -EOPNOTSUPP; 93 94 mutex_lock(&smu->mutex); 95 96 ret = smu_set_pp_feature_mask(smu, new_mask); 97 98 mutex_unlock(&smu->mutex); 99 100 return ret; 101 } 102 103 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) 104 { 105 int ret = 0; 106 struct smu_context *smu = &adev->smu; 107 108 if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status) 109 *value = smu_get_gfx_off_status(smu); 110 else 111 ret = -EINVAL; 112 113 return ret; 114 } 115 116 int smu_set_soft_freq_range(struct smu_context *smu, 117 enum smu_clk_type clk_type, 118 uint32_t min, 119 uint32_t max) 120 { 121 int ret = 0; 122 123 mutex_lock(&smu->mutex); 124 125 if (smu->ppt_funcs->set_soft_freq_limited_range) 126 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 127 clk_type, 128 min, 129 max); 130 131 mutex_unlock(&smu->mutex); 132 133 return ret; 134 } 135 136 int smu_get_dpm_freq_range(struct smu_context *smu, 137 enum smu_clk_type clk_type, 138 uint32_t *min, 139 uint32_t *max) 140 { 141 int ret = -ENOTSUPP; 142 143 if (!min && !max) 144 return -EINVAL; 145 146 mutex_lock(&smu->mutex); 147 148 if (smu->ppt_funcs->get_dpm_ultimate_freq) 149 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 150 clk_type, 151 min, 152 max); 153 154 mutex_unlock(&smu->mutex); 155 156 return ret; 157 } 158 159 static u32 smu_get_mclk(void *handle, bool low) 160 { 161 struct smu_context *smu = handle; 162 uint32_t clk_freq; 163 int ret = 0; 164 165 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 166 low ? &clk_freq : NULL, 167 !low ? &clk_freq : NULL); 168 if (ret) 169 return 0; 170 return clk_freq * 100; 171 } 172 173 static u32 smu_get_sclk(void *handle, bool low) 174 { 175 struct smu_context *smu = handle; 176 uint32_t clk_freq; 177 int ret = 0; 178 179 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 180 low ? &clk_freq : NULL, 181 !low ? &clk_freq : NULL); 182 if (ret) 183 return 0; 184 return clk_freq * 100; 185 } 186 187 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu, 188 bool enable) 189 { 190 struct smu_power_context *smu_power = &smu->smu_power; 191 struct smu_power_gate *power_gate = &smu_power->power_gate; 192 int ret = 0; 193 194 if (!smu->ppt_funcs->dpm_set_vcn_enable) 195 return 0; 196 197 if (atomic_read(&power_gate->vcn_gated) ^ enable) 198 return 0; 199 200 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 201 if (!ret) 202 atomic_set(&power_gate->vcn_gated, !enable); 203 204 return ret; 205 } 206 207 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 208 bool enable) 209 { 210 struct smu_power_context *smu_power = &smu->smu_power; 211 struct smu_power_gate *power_gate = &smu_power->power_gate; 212 int ret = 0; 213 214 mutex_lock(&power_gate->vcn_gate_lock); 215 216 ret = smu_dpm_set_vcn_enable_locked(smu, enable); 217 218 mutex_unlock(&power_gate->vcn_gate_lock); 219 220 return ret; 221 } 222 223 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu, 224 bool enable) 225 { 226 struct smu_power_context *smu_power = &smu->smu_power; 227 struct smu_power_gate *power_gate = &smu_power->power_gate; 228 int ret = 0; 229 230 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 231 return 0; 232 233 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 234 return 0; 235 236 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 237 if (!ret) 238 atomic_set(&power_gate->jpeg_gated, !enable); 239 240 return ret; 241 } 242 243 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 244 bool enable) 245 { 246 struct smu_power_context *smu_power = &smu->smu_power; 247 struct smu_power_gate *power_gate = &smu_power->power_gate; 248 int ret = 0; 249 250 mutex_lock(&power_gate->jpeg_gate_lock); 251 252 ret = smu_dpm_set_jpeg_enable_locked(smu, enable); 253 254 mutex_unlock(&power_gate->jpeg_gate_lock); 255 256 return ret; 257 } 258 259 /** 260 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 261 * 262 * @handle: smu_context pointer 263 * @block_type: the IP block to power gate/ungate 264 * @gate: to power gate if true, ungate otherwise 265 * 266 * This API uses no smu->mutex lock protection due to: 267 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 268 * This is guarded to be race condition free by the caller. 269 * 2. Or get called on user setting request of power_dpm_force_performance_level. 270 * Under this case, the smu->mutex lock protection is already enforced on 271 * the parent API smu_force_performance_level of the call path. 272 */ 273 static int smu_dpm_set_power_gate(void *handle, 274 uint32_t block_type, 275 bool gate) 276 { 277 struct smu_context *smu = handle; 278 int ret = 0; 279 280 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 281 return -EOPNOTSUPP; 282 283 switch (block_type) { 284 /* 285 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 286 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 287 */ 288 case AMD_IP_BLOCK_TYPE_UVD: 289 case AMD_IP_BLOCK_TYPE_VCN: 290 ret = smu_dpm_set_vcn_enable(smu, !gate); 291 if (ret) 292 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 293 gate ? "gate" : "ungate"); 294 break; 295 case AMD_IP_BLOCK_TYPE_GFX: 296 ret = smu_gfx_off_control(smu, gate); 297 if (ret) 298 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 299 gate ? "enable" : "disable"); 300 break; 301 case AMD_IP_BLOCK_TYPE_SDMA: 302 ret = smu_powergate_sdma(smu, gate); 303 if (ret) 304 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 305 gate ? "gate" : "ungate"); 306 break; 307 case AMD_IP_BLOCK_TYPE_JPEG: 308 ret = smu_dpm_set_jpeg_enable(smu, !gate); 309 if (ret) 310 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 311 gate ? "gate" : "ungate"); 312 break; 313 default: 314 dev_err(smu->adev->dev, "Unsupported block type!\n"); 315 return -EINVAL; 316 } 317 318 return ret; 319 } 320 321 /** 322 * smu_set_user_clk_dependencies - set user profile clock dependencies 323 * 324 * @smu: smu_context pointer 325 * @clk: enum smu_clk_type type 326 * 327 * Enable/Disable the clock dependency for the @clk type. 328 */ 329 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 330 { 331 if (smu->adev->in_suspend) 332 return; 333 334 if (clk == SMU_MCLK) { 335 smu->user_dpm_profile.clk_dependency = 0; 336 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 337 } else if (clk == SMU_FCLK) { 338 /* MCLK takes precedence over FCLK */ 339 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 340 return; 341 342 smu->user_dpm_profile.clk_dependency = 0; 343 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 344 } else if (clk == SMU_SOCCLK) { 345 /* MCLK takes precedence over SOCCLK */ 346 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 347 return; 348 349 smu->user_dpm_profile.clk_dependency = 0; 350 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 351 } else 352 /* Add clk dependencies here, if any */ 353 return; 354 } 355 356 /** 357 * smu_restore_dpm_user_profile - reinstate user dpm profile 358 * 359 * @smu: smu_context pointer 360 * 361 * Restore the saved user power configurations include power limit, 362 * clock frequencies, fan control mode and fan speed. 363 */ 364 static void smu_restore_dpm_user_profile(struct smu_context *smu) 365 { 366 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 367 int ret = 0; 368 369 if (!smu->adev->in_suspend) 370 return; 371 372 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 373 return; 374 375 /* Enable restore flag */ 376 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 377 378 /* set the user dpm power limit */ 379 if (smu->user_dpm_profile.power_limit) { 380 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 381 if (ret) 382 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 383 } 384 385 /* set the user dpm clock configurations */ 386 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 387 enum smu_clk_type clk_type; 388 389 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 390 /* 391 * Iterate over smu clk type and force the saved user clk 392 * configs, skip if clock dependency is enabled 393 */ 394 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 395 smu->user_dpm_profile.clk_mask[clk_type]) { 396 ret = smu_force_smuclk_levels(smu, clk_type, 397 smu->user_dpm_profile.clk_mask[clk_type]); 398 if (ret) 399 dev_err(smu->adev->dev, 400 "Failed to set clock type = %d\n", clk_type); 401 } 402 } 403 } 404 405 /* set the user dpm fan configurations */ 406 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 407 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 408 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 409 if (ret) { 410 smu->user_dpm_profile.fan_speed_pwm = 0; 411 smu->user_dpm_profile.fan_speed_rpm = 0; 412 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 413 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 414 } 415 416 if (smu->user_dpm_profile.fan_speed_pwm) { 417 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 418 if (ret) 419 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 420 } 421 422 if (smu->user_dpm_profile.fan_speed_rpm) { 423 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 424 if (ret) 425 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 426 } 427 } 428 429 /* Restore user customized OD settings */ 430 if (smu->user_dpm_profile.user_od) { 431 if (smu->ppt_funcs->restore_user_od_settings) { 432 ret = smu->ppt_funcs->restore_user_od_settings(smu); 433 if (ret) 434 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 435 } 436 } 437 438 /* Disable restore flag */ 439 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 440 } 441 442 static int smu_get_power_num_states(void *handle, 443 struct pp_states_info *state_info) 444 { 445 if (!state_info) 446 return -EINVAL; 447 448 /* not support power state */ 449 memset(state_info, 0, sizeof(struct pp_states_info)); 450 state_info->nums = 1; 451 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 452 453 return 0; 454 } 455 456 bool is_support_sw_smu(struct amdgpu_device *adev) 457 { 458 if (adev->asic_type >= CHIP_ARCTURUS) 459 return true; 460 461 return false; 462 } 463 464 bool is_support_cclk_dpm(struct amdgpu_device *adev) 465 { 466 struct smu_context *smu = &adev->smu; 467 468 if (!is_support_sw_smu(adev)) 469 return false; 470 471 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 472 return false; 473 474 return true; 475 } 476 477 478 static int smu_sys_get_pp_table(void *handle, 479 char **table) 480 { 481 struct smu_context *smu = handle; 482 struct smu_table_context *smu_table = &smu->smu_table; 483 uint32_t powerplay_table_size; 484 485 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 486 return -EOPNOTSUPP; 487 488 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 489 return -EINVAL; 490 491 mutex_lock(&smu->mutex); 492 493 if (smu_table->hardcode_pptable) 494 *table = smu_table->hardcode_pptable; 495 else 496 *table = smu_table->power_play_table; 497 498 powerplay_table_size = smu_table->power_play_table_size; 499 500 mutex_unlock(&smu->mutex); 501 502 return powerplay_table_size; 503 } 504 505 static int smu_sys_set_pp_table(void *handle, 506 const char *buf, 507 size_t size) 508 { 509 struct smu_context *smu = handle; 510 struct smu_table_context *smu_table = &smu->smu_table; 511 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 512 int ret = 0; 513 514 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 515 return -EOPNOTSUPP; 516 517 if (header->usStructureSize != size) { 518 dev_err(smu->adev->dev, "pp table size not matched !\n"); 519 return -EIO; 520 } 521 522 mutex_lock(&smu->mutex); 523 if (!smu_table->hardcode_pptable) 524 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 525 if (!smu_table->hardcode_pptable) { 526 ret = -ENOMEM; 527 goto failed; 528 } 529 530 memcpy(smu_table->hardcode_pptable, buf, size); 531 smu_table->power_play_table = smu_table->hardcode_pptable; 532 smu_table->power_play_table_size = size; 533 534 /* 535 * Special hw_fini action(for Navi1x, the DPMs disablement will be 536 * skipped) may be needed for custom pptable uploading. 537 */ 538 smu->uploading_custom_pp_table = true; 539 540 ret = smu_reset(smu); 541 if (ret) 542 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 543 544 smu->uploading_custom_pp_table = false; 545 546 failed: 547 mutex_unlock(&smu->mutex); 548 return ret; 549 } 550 551 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 552 { 553 struct smu_feature *feature = &smu->smu_feature; 554 int ret = 0; 555 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 556 557 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 558 559 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 560 SMU_FEATURE_MAX/32); 561 if (ret) 562 return ret; 563 564 bitmap_or(feature->allowed, feature->allowed, 565 (unsigned long *)allowed_feature_mask, 566 feature->feature_num); 567 568 return ret; 569 } 570 571 static int smu_set_funcs(struct amdgpu_device *adev) 572 { 573 struct smu_context *smu = &adev->smu; 574 575 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 576 smu->od_enabled = true; 577 578 switch (adev->asic_type) { 579 case CHIP_NAVI10: 580 case CHIP_NAVI14: 581 case CHIP_NAVI12: 582 navi10_set_ppt_funcs(smu); 583 break; 584 case CHIP_ARCTURUS: 585 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 586 arcturus_set_ppt_funcs(smu); 587 /* OD is not supported on Arcturus */ 588 smu->od_enabled =false; 589 break; 590 case CHIP_SIENNA_CICHLID: 591 case CHIP_NAVY_FLOUNDER: 592 case CHIP_DIMGREY_CAVEFISH: 593 case CHIP_BEIGE_GOBY: 594 sienna_cichlid_set_ppt_funcs(smu); 595 break; 596 case CHIP_ALDEBARAN: 597 aldebaran_set_ppt_funcs(smu); 598 /* Enable pp_od_clk_voltage node */ 599 smu->od_enabled = true; 600 break; 601 case CHIP_RENOIR: 602 renoir_set_ppt_funcs(smu); 603 break; 604 case CHIP_VANGOGH: 605 vangogh_set_ppt_funcs(smu); 606 break; 607 case CHIP_YELLOW_CARP: 608 yellow_carp_set_ppt_funcs(smu); 609 break; 610 case CHIP_CYAN_SKILLFISH: 611 cyan_skillfish_set_ppt_funcs(smu); 612 break; 613 default: 614 return -EINVAL; 615 } 616 617 return 0; 618 } 619 620 static int smu_early_init(void *handle) 621 { 622 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 623 struct smu_context *smu = &adev->smu; 624 625 smu->adev = adev; 626 smu->pm_enabled = !!amdgpu_dpm; 627 smu->is_apu = false; 628 rw_init(&smu->mutex, "smurw"); 629 rw_init(&smu->smu_baco.mutex, "smubc"); 630 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 631 smu->smu_baco.platform_support = false; 632 smu->user_dpm_profile.fan_mode = -1; 633 634 adev->powerplay.pp_handle = smu; 635 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 636 637 return smu_set_funcs(adev); 638 } 639 640 static int smu_set_default_dpm_table(struct smu_context *smu) 641 { 642 struct smu_power_context *smu_power = &smu->smu_power; 643 struct smu_power_gate *power_gate = &smu_power->power_gate; 644 int vcn_gate, jpeg_gate; 645 int ret = 0; 646 647 if (!smu->ppt_funcs->set_default_dpm_table) 648 return 0; 649 650 mutex_lock(&power_gate->vcn_gate_lock); 651 mutex_lock(&power_gate->jpeg_gate_lock); 652 653 vcn_gate = atomic_read(&power_gate->vcn_gated); 654 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 655 656 ret = smu_dpm_set_vcn_enable_locked(smu, true); 657 if (ret) 658 goto err0_out; 659 660 ret = smu_dpm_set_jpeg_enable_locked(smu, true); 661 if (ret) 662 goto err1_out; 663 664 ret = smu->ppt_funcs->set_default_dpm_table(smu); 665 if (ret) 666 dev_err(smu->adev->dev, 667 "Failed to setup default dpm clock tables!\n"); 668 669 smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate); 670 err1_out: 671 smu_dpm_set_vcn_enable_locked(smu, !vcn_gate); 672 err0_out: 673 mutex_unlock(&power_gate->jpeg_gate_lock); 674 mutex_unlock(&power_gate->vcn_gate_lock); 675 676 return ret; 677 } 678 679 680 static int smu_late_init(void *handle) 681 { 682 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 683 struct smu_context *smu = &adev->smu; 684 int ret = 0; 685 686 smu_set_fine_grain_gfx_freq_parameters(smu); 687 688 if (!smu->pm_enabled) 689 return 0; 690 691 ret = smu_post_init(smu); 692 if (ret) { 693 dev_err(adev->dev, "Failed to post smu init!\n"); 694 return ret; 695 } 696 697 if (adev->asic_type == CHIP_YELLOW_CARP) 698 return 0; 699 700 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 701 ret = smu_set_default_od_settings(smu); 702 if (ret) { 703 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 704 return ret; 705 } 706 } 707 708 ret = smu_populate_umd_state_clk(smu); 709 if (ret) { 710 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 711 return ret; 712 } 713 714 ret = smu_get_asic_power_limits(smu, 715 &smu->current_power_limit, 716 &smu->default_power_limit, 717 &smu->max_power_limit); 718 if (ret) { 719 dev_err(adev->dev, "Failed to get asic power limits!\n"); 720 return ret; 721 } 722 723 if (!amdgpu_sriov_vf(adev)) 724 smu_get_unique_id(smu); 725 726 smu_get_fan_parameters(smu); 727 728 smu_handle_task(&adev->smu, 729 smu->smu_dpm.dpm_level, 730 AMD_PP_TASK_COMPLETE_INIT, 731 false); 732 733 smu_restore_dpm_user_profile(smu); 734 735 return 0; 736 } 737 738 static int smu_init_fb_allocations(struct smu_context *smu) 739 { 740 struct amdgpu_device *adev = smu->adev; 741 struct smu_table_context *smu_table = &smu->smu_table; 742 struct smu_table *tables = smu_table->tables; 743 struct smu_table *driver_table = &(smu_table->driver_table); 744 uint32_t max_table_size = 0; 745 int ret, i; 746 747 /* VRAM allocation for tool table */ 748 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 749 ret = amdgpu_bo_create_kernel(adev, 750 tables[SMU_TABLE_PMSTATUSLOG].size, 751 tables[SMU_TABLE_PMSTATUSLOG].align, 752 tables[SMU_TABLE_PMSTATUSLOG].domain, 753 &tables[SMU_TABLE_PMSTATUSLOG].bo, 754 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 755 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 756 if (ret) { 757 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 758 return ret; 759 } 760 } 761 762 /* VRAM allocation for driver table */ 763 for (i = 0; i < SMU_TABLE_COUNT; i++) { 764 if (tables[i].size == 0) 765 continue; 766 767 if (i == SMU_TABLE_PMSTATUSLOG) 768 continue; 769 770 if (max_table_size < tables[i].size) 771 max_table_size = tables[i].size; 772 } 773 774 driver_table->size = max_table_size; 775 driver_table->align = PAGE_SIZE; 776 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 777 778 ret = amdgpu_bo_create_kernel(adev, 779 driver_table->size, 780 driver_table->align, 781 driver_table->domain, 782 &driver_table->bo, 783 &driver_table->mc_address, 784 &driver_table->cpu_addr); 785 if (ret) { 786 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 787 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 788 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 789 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 790 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 791 } 792 793 return ret; 794 } 795 796 static int smu_fini_fb_allocations(struct smu_context *smu) 797 { 798 struct smu_table_context *smu_table = &smu->smu_table; 799 struct smu_table *tables = smu_table->tables; 800 struct smu_table *driver_table = &(smu_table->driver_table); 801 802 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 803 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 804 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 805 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 806 807 amdgpu_bo_free_kernel(&driver_table->bo, 808 &driver_table->mc_address, 809 &driver_table->cpu_addr); 810 811 return 0; 812 } 813 814 /** 815 * smu_alloc_memory_pool - allocate memory pool in the system memory 816 * 817 * @smu: amdgpu_device pointer 818 * 819 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 820 * and DramLogSetDramAddr can notify it changed. 821 * 822 * Returns 0 on success, error on failure. 823 */ 824 static int smu_alloc_memory_pool(struct smu_context *smu) 825 { 826 struct amdgpu_device *adev = smu->adev; 827 struct smu_table_context *smu_table = &smu->smu_table; 828 struct smu_table *memory_pool = &smu_table->memory_pool; 829 uint64_t pool_size = smu->pool_size; 830 int ret = 0; 831 832 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 833 return ret; 834 835 memory_pool->size = pool_size; 836 memory_pool->align = PAGE_SIZE; 837 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 838 839 switch (pool_size) { 840 case SMU_MEMORY_POOL_SIZE_256_MB: 841 case SMU_MEMORY_POOL_SIZE_512_MB: 842 case SMU_MEMORY_POOL_SIZE_1_GB: 843 case SMU_MEMORY_POOL_SIZE_2_GB: 844 ret = amdgpu_bo_create_kernel(adev, 845 memory_pool->size, 846 memory_pool->align, 847 memory_pool->domain, 848 &memory_pool->bo, 849 &memory_pool->mc_address, 850 &memory_pool->cpu_addr); 851 if (ret) 852 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 853 break; 854 default: 855 break; 856 } 857 858 return ret; 859 } 860 861 static int smu_free_memory_pool(struct smu_context *smu) 862 { 863 struct smu_table_context *smu_table = &smu->smu_table; 864 struct smu_table *memory_pool = &smu_table->memory_pool; 865 866 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 867 return 0; 868 869 amdgpu_bo_free_kernel(&memory_pool->bo, 870 &memory_pool->mc_address, 871 &memory_pool->cpu_addr); 872 873 memset(memory_pool, 0, sizeof(struct smu_table)); 874 875 return 0; 876 } 877 878 static int smu_alloc_dummy_read_table(struct smu_context *smu) 879 { 880 struct smu_table_context *smu_table = &smu->smu_table; 881 struct smu_table *dummy_read_1_table = 882 &smu_table->dummy_read_1_table; 883 struct amdgpu_device *adev = smu->adev; 884 int ret = 0; 885 886 dummy_read_1_table->size = 0x40000; 887 dummy_read_1_table->align = PAGE_SIZE; 888 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 889 890 ret = amdgpu_bo_create_kernel(adev, 891 dummy_read_1_table->size, 892 dummy_read_1_table->align, 893 dummy_read_1_table->domain, 894 &dummy_read_1_table->bo, 895 &dummy_read_1_table->mc_address, 896 &dummy_read_1_table->cpu_addr); 897 if (ret) 898 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 899 900 return ret; 901 } 902 903 static void smu_free_dummy_read_table(struct smu_context *smu) 904 { 905 struct smu_table_context *smu_table = &smu->smu_table; 906 struct smu_table *dummy_read_1_table = 907 &smu_table->dummy_read_1_table; 908 909 910 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 911 &dummy_read_1_table->mc_address, 912 &dummy_read_1_table->cpu_addr); 913 914 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 915 } 916 917 static int smu_smc_table_sw_init(struct smu_context *smu) 918 { 919 int ret; 920 921 /** 922 * Create smu_table structure, and init smc tables such as 923 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 924 */ 925 ret = smu_init_smc_tables(smu); 926 if (ret) { 927 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 928 return ret; 929 } 930 931 /** 932 * Create smu_power_context structure, and allocate smu_dpm_context and 933 * context size to fill the smu_power_context data. 934 */ 935 ret = smu_init_power(smu); 936 if (ret) { 937 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 938 return ret; 939 } 940 941 /* 942 * allocate vram bos to store smc table contents. 943 */ 944 ret = smu_init_fb_allocations(smu); 945 if (ret) 946 return ret; 947 948 ret = smu_alloc_memory_pool(smu); 949 if (ret) 950 return ret; 951 952 ret = smu_alloc_dummy_read_table(smu); 953 if (ret) 954 return ret; 955 956 ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c); 957 if (ret) 958 return ret; 959 960 return 0; 961 } 962 963 static int smu_smc_table_sw_fini(struct smu_context *smu) 964 { 965 int ret; 966 967 smu_i2c_fini(smu, &smu->adev->pm.smu_i2c); 968 969 smu_free_dummy_read_table(smu); 970 971 ret = smu_free_memory_pool(smu); 972 if (ret) 973 return ret; 974 975 ret = smu_fini_fb_allocations(smu); 976 if (ret) 977 return ret; 978 979 ret = smu_fini_power(smu); 980 if (ret) { 981 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 982 return ret; 983 } 984 985 ret = smu_fini_smc_tables(smu); 986 if (ret) { 987 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 988 return ret; 989 } 990 991 return 0; 992 } 993 994 static void smu_throttling_logging_work_fn(struct work_struct *work) 995 { 996 struct smu_context *smu = container_of(work, struct smu_context, 997 throttling_logging_work); 998 999 smu_log_thermal_throttling(smu); 1000 } 1001 1002 static void smu_interrupt_work_fn(struct work_struct *work) 1003 { 1004 struct smu_context *smu = container_of(work, struct smu_context, 1005 interrupt_work); 1006 1007 mutex_lock(&smu->mutex); 1008 1009 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1010 smu->ppt_funcs->interrupt_work(smu); 1011 1012 mutex_unlock(&smu->mutex); 1013 } 1014 1015 static int smu_sw_init(void *handle) 1016 { 1017 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1018 struct smu_context *smu = &adev->smu; 1019 int ret; 1020 1021 smu->pool_size = adev->pm.smu_prv_buffer_size; 1022 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1023 rw_init(&smu->smu_feature.mutex, "smuft"); 1024 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1025 bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX); 1026 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1027 1028 rw_init(&smu->sensor_lock, "smusen"); 1029 rw_init(&smu->metrics_lock, "smumt"); 1030 rw_init(&smu->message_lock, "smuml"); 1031 1032 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1033 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1034 atomic64_set(&smu->throttle_int_counter, 0); 1035 smu->watermarks_bitmap = 0; 1036 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1037 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1038 1039 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1040 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1041 rw_init(&smu->smu_power.power_gate.vcn_gate_lock, "vcngl"); 1042 rw_init(&smu->smu_power.power_gate.jpeg_gate_lock, "jpgglk"); 1043 1044 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1045 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1046 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1047 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1048 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1049 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1050 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1051 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1052 1053 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1054 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1055 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1056 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1057 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1058 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1059 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1060 smu->display_config = &adev->pm.pm_display_cfg; 1061 1062 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1063 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1064 1065 ret = smu_init_microcode(smu); 1066 if (ret) { 1067 dev_err(adev->dev, "Failed to load smu firmware!\n"); 1068 return ret; 1069 } 1070 1071 ret = smu_smc_table_sw_init(smu); 1072 if (ret) { 1073 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1074 return ret; 1075 } 1076 1077 ret = smu_register_irq_handler(smu); 1078 if (ret) { 1079 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1080 return ret; 1081 } 1082 1083 /* If there is no way to query fan control mode, fan control is not supported */ 1084 if (!smu->ppt_funcs->get_fan_control_mode) 1085 smu->adev->pm.no_fan = true; 1086 1087 return 0; 1088 } 1089 1090 static int smu_sw_fini(void *handle) 1091 { 1092 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1093 struct smu_context *smu = &adev->smu; 1094 int ret; 1095 1096 ret = smu_smc_table_sw_fini(smu); 1097 if (ret) { 1098 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1099 return ret; 1100 } 1101 1102 smu_fini_microcode(smu); 1103 1104 return 0; 1105 } 1106 1107 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1108 { 1109 struct amdgpu_device *adev = smu->adev; 1110 struct smu_temperature_range *range = 1111 &smu->thermal_range; 1112 int ret = 0; 1113 1114 if (!smu->ppt_funcs->get_thermal_temperature_range) 1115 return 0; 1116 1117 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1118 if (ret) 1119 return ret; 1120 1121 adev->pm.dpm.thermal.min_temp = range->min; 1122 adev->pm.dpm.thermal.max_temp = range->max; 1123 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1124 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1125 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1126 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1127 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1128 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1129 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1130 1131 return ret; 1132 } 1133 1134 static int smu_smc_hw_setup(struct smu_context *smu) 1135 { 1136 struct amdgpu_device *adev = smu->adev; 1137 uint32_t pcie_gen = 0, pcie_width = 0; 1138 int ret = 0; 1139 1140 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1141 dev_info(adev->dev, "dpm has been enabled\n"); 1142 /* this is needed specifically */ 1143 if ((adev->asic_type >= CHIP_SIENNA_CICHLID) && 1144 (adev->asic_type <= CHIP_DIMGREY_CAVEFISH)) 1145 ret = smu_system_features_control(smu, true); 1146 return ret; 1147 } 1148 1149 ret = smu_init_display_count(smu, 0); 1150 if (ret) { 1151 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1152 return ret; 1153 } 1154 1155 ret = smu_set_driver_table_location(smu); 1156 if (ret) { 1157 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1158 return ret; 1159 } 1160 1161 /* 1162 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1163 */ 1164 ret = smu_set_tool_table_location(smu); 1165 if (ret) { 1166 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1167 return ret; 1168 } 1169 1170 /* 1171 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1172 * pool location. 1173 */ 1174 ret = smu_notify_memory_pool_location(smu); 1175 if (ret) { 1176 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1177 return ret; 1178 } 1179 1180 /* smu_dump_pptable(smu); */ 1181 /* 1182 * Copy pptable bo in the vram to smc with SMU MSGs such as 1183 * SetDriverDramAddr and TransferTableDram2Smu. 1184 */ 1185 ret = smu_write_pptable(smu); 1186 if (ret) { 1187 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1188 return ret; 1189 } 1190 1191 /* issue Run*Btc msg */ 1192 ret = smu_run_btc(smu); 1193 if (ret) 1194 return ret; 1195 1196 ret = smu_feature_set_allowed_mask(smu); 1197 if (ret) { 1198 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1199 return ret; 1200 } 1201 1202 ret = smu_system_features_control(smu, true); 1203 if (ret) { 1204 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1205 return ret; 1206 } 1207 1208 if (!smu_is_dpm_running(smu)) 1209 dev_info(adev->dev, "dpm has been disabled\n"); 1210 1211 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1212 pcie_gen = 3; 1213 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1214 pcie_gen = 2; 1215 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1216 pcie_gen = 1; 1217 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1218 pcie_gen = 0; 1219 1220 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1221 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1222 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1223 */ 1224 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1225 pcie_width = 6; 1226 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1227 pcie_width = 5; 1228 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1229 pcie_width = 4; 1230 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1231 pcie_width = 3; 1232 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1233 pcie_width = 2; 1234 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1235 pcie_width = 1; 1236 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1237 if (ret) { 1238 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1239 return ret; 1240 } 1241 1242 ret = smu_get_thermal_temperature_range(smu); 1243 if (ret) { 1244 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1245 return ret; 1246 } 1247 1248 ret = smu_enable_thermal_alert(smu); 1249 if (ret) { 1250 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1251 return ret; 1252 } 1253 1254 /* 1255 * Set initialized values (get from vbios) to dpm tables context such as 1256 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1257 * type of clks. 1258 */ 1259 ret = smu_set_default_dpm_table(smu); 1260 if (ret) { 1261 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1262 return ret; 1263 } 1264 1265 ret = smu_notify_display_change(smu); 1266 if (ret) 1267 return ret; 1268 1269 /* 1270 * Set min deep sleep dce fclk with bootup value from vbios via 1271 * SetMinDeepSleepDcefclk MSG. 1272 */ 1273 ret = smu_set_min_dcef_deep_sleep(smu, 1274 smu->smu_table.boot_values.dcefclk / 100); 1275 if (ret) 1276 return ret; 1277 1278 return ret; 1279 } 1280 1281 static int smu_start_smc_engine(struct smu_context *smu) 1282 { 1283 struct amdgpu_device *adev = smu->adev; 1284 int ret = 0; 1285 1286 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1287 if (adev->asic_type < CHIP_NAVI10) { 1288 if (smu->ppt_funcs->load_microcode) { 1289 ret = smu->ppt_funcs->load_microcode(smu); 1290 if (ret) 1291 return ret; 1292 } 1293 } 1294 } 1295 1296 if (smu->ppt_funcs->check_fw_status) { 1297 ret = smu->ppt_funcs->check_fw_status(smu); 1298 if (ret) { 1299 dev_err(adev->dev, "SMC is not ready\n"); 1300 return ret; 1301 } 1302 } 1303 1304 /* 1305 * Send msg GetDriverIfVersion to check if the return value is equal 1306 * with DRIVER_IF_VERSION of smc header. 1307 */ 1308 ret = smu_check_fw_version(smu); 1309 if (ret) 1310 return ret; 1311 1312 return ret; 1313 } 1314 1315 static int smu_hw_init(void *handle) 1316 { 1317 int ret; 1318 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1319 struct smu_context *smu = &adev->smu; 1320 1321 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1322 smu->pm_enabled = false; 1323 return 0; 1324 } 1325 1326 ret = smu_start_smc_engine(smu); 1327 if (ret) { 1328 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1329 return ret; 1330 } 1331 1332 if (smu->is_apu) { 1333 smu_powergate_sdma(&adev->smu, false); 1334 smu_dpm_set_vcn_enable(smu, true); 1335 smu_dpm_set_jpeg_enable(smu, true); 1336 smu_set_gfx_cgpg(&adev->smu, true); 1337 } 1338 1339 if (!smu->pm_enabled) 1340 return 0; 1341 1342 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1343 ret = smu_get_vbios_bootup_values(smu); 1344 if (ret) { 1345 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1346 return ret; 1347 } 1348 1349 ret = smu_setup_pptable(smu); 1350 if (ret) { 1351 dev_err(adev->dev, "Failed to setup pptable!\n"); 1352 return ret; 1353 } 1354 1355 ret = smu_get_driver_allowed_feature_mask(smu); 1356 if (ret) 1357 return ret; 1358 1359 ret = smu_smc_hw_setup(smu); 1360 if (ret) { 1361 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1362 return ret; 1363 } 1364 1365 /* 1366 * Move maximum sustainable clock retrieving here considering 1367 * 1. It is not needed on resume(from S3). 1368 * 2. DAL settings come between .hw_init and .late_init of SMU. 1369 * And DAL needs to know the maximum sustainable clocks. Thus 1370 * it cannot be put in .late_init(). 1371 */ 1372 ret = smu_init_max_sustainable_clocks(smu); 1373 if (ret) { 1374 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1375 return ret; 1376 } 1377 1378 adev->pm.dpm_enabled = true; 1379 1380 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1381 1382 return 0; 1383 } 1384 1385 static int smu_disable_dpms(struct smu_context *smu) 1386 { 1387 struct amdgpu_device *adev = smu->adev; 1388 int ret = 0; 1389 /* 1390 * TODO: (adev->in_suspend && !adev->in_s0ix) is added to pair 1391 * the workaround which always reset the asic in suspend. 1392 * It's likely that workaround will be dropped in the future. 1393 * Then the change here should be dropped together. 1394 */ 1395 bool use_baco = !smu->is_apu && 1396 (((amdgpu_in_reset(adev) || (adev->in_suspend && !adev->in_s0ix)) && 1397 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1398 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1399 1400 /* 1401 * For custom pptable uploading, skip the DPM features 1402 * disable process on Navi1x ASICs. 1403 * - As the gfx related features are under control of 1404 * RLC on those ASICs. RLC reinitialization will be 1405 * needed to reenable them. That will cost much more 1406 * efforts. 1407 * 1408 * - SMU firmware can handle the DPM reenablement 1409 * properly. 1410 */ 1411 if (smu->uploading_custom_pp_table && 1412 (adev->asic_type >= CHIP_NAVI10) && 1413 (adev->asic_type <= CHIP_BEIGE_GOBY)) 1414 return smu_disable_all_features_with_exception(smu, 1415 true, 1416 SMU_FEATURE_COUNT); 1417 1418 /* 1419 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1420 * on BACO in. Driver involvement is unnecessary. 1421 */ 1422 if (((adev->asic_type == CHIP_SIENNA_CICHLID) || 1423 ((adev->asic_type >= CHIP_NAVI10) && (adev->asic_type <= CHIP_NAVI12))) && 1424 use_baco) 1425 return smu_disable_all_features_with_exception(smu, 1426 true, 1427 SMU_FEATURE_BACO_BIT); 1428 1429 /* 1430 * For gpu reset, runpm and hibernation through BACO, 1431 * BACO feature has to be kept enabled. 1432 */ 1433 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1434 ret = smu_disable_all_features_with_exception(smu, 1435 false, 1436 SMU_FEATURE_BACO_BIT); 1437 if (ret) 1438 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1439 } else { 1440 ret = smu_system_features_control(smu, false); 1441 if (ret) 1442 dev_err(adev->dev, "Failed to disable smu features.\n"); 1443 } 1444 1445 if (adev->asic_type >= CHIP_NAVI10 && 1446 adev->gfx.rlc.funcs->stop) 1447 adev->gfx.rlc.funcs->stop(adev); 1448 1449 return ret; 1450 } 1451 1452 static int smu_smc_hw_cleanup(struct smu_context *smu) 1453 { 1454 struct amdgpu_device *adev = smu->adev; 1455 int ret = 0; 1456 1457 cancel_work_sync(&smu->throttling_logging_work); 1458 cancel_work_sync(&smu->interrupt_work); 1459 1460 ret = smu_disable_thermal_alert(smu); 1461 if (ret) { 1462 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1463 return ret; 1464 } 1465 1466 ret = smu_disable_dpms(smu); 1467 if (ret) { 1468 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1469 return ret; 1470 } 1471 1472 return 0; 1473 } 1474 1475 static int smu_hw_fini(void *handle) 1476 { 1477 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1478 struct smu_context *smu = &adev->smu; 1479 1480 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1481 return 0; 1482 1483 if (smu->is_apu) { 1484 smu_powergate_sdma(&adev->smu, true); 1485 } 1486 1487 smu_dpm_set_vcn_enable(smu, false); 1488 smu_dpm_set_jpeg_enable(smu, false); 1489 1490 adev->vcn.cur_state = AMD_PG_STATE_GATE; 1491 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 1492 1493 if (!smu->pm_enabled) 1494 return 0; 1495 1496 adev->pm.dpm_enabled = false; 1497 1498 return smu_smc_hw_cleanup(smu); 1499 } 1500 1501 static int smu_reset(struct smu_context *smu) 1502 { 1503 struct amdgpu_device *adev = smu->adev; 1504 int ret; 1505 1506 amdgpu_gfx_off_ctrl(smu->adev, false); 1507 1508 ret = smu_hw_fini(adev); 1509 if (ret) 1510 return ret; 1511 1512 ret = smu_hw_init(adev); 1513 if (ret) 1514 return ret; 1515 1516 ret = smu_late_init(adev); 1517 if (ret) 1518 return ret; 1519 1520 amdgpu_gfx_off_ctrl(smu->adev, true); 1521 1522 return 0; 1523 } 1524 1525 static int smu_suspend(void *handle) 1526 { 1527 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1528 struct smu_context *smu = &adev->smu; 1529 int ret; 1530 1531 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1532 return 0; 1533 1534 if (!smu->pm_enabled) 1535 return 0; 1536 1537 adev->pm.dpm_enabled = false; 1538 1539 ret = smu_smc_hw_cleanup(smu); 1540 if (ret) 1541 return ret; 1542 1543 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1544 1545 smu_set_gfx_cgpg(&adev->smu, false); 1546 1547 return 0; 1548 } 1549 1550 static int smu_resume(void *handle) 1551 { 1552 int ret; 1553 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1554 struct smu_context *smu = &adev->smu; 1555 1556 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1557 return 0; 1558 1559 if (!smu->pm_enabled) 1560 return 0; 1561 1562 dev_info(adev->dev, "SMU is resuming...\n"); 1563 1564 ret = smu_start_smc_engine(smu); 1565 if (ret) { 1566 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1567 return ret; 1568 } 1569 1570 ret = smu_smc_hw_setup(smu); 1571 if (ret) { 1572 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1573 return ret; 1574 } 1575 1576 smu_set_gfx_cgpg(&adev->smu, true); 1577 1578 smu->disable_uclk_switch = 0; 1579 1580 adev->pm.dpm_enabled = true; 1581 1582 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1583 1584 return 0; 1585 } 1586 1587 static int smu_display_configuration_change(void *handle, 1588 const struct amd_pp_display_configuration *display_config) 1589 { 1590 struct smu_context *smu = handle; 1591 int index = 0; 1592 int num_of_active_display = 0; 1593 1594 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1595 return -EOPNOTSUPP; 1596 1597 if (!display_config) 1598 return -EINVAL; 1599 1600 mutex_lock(&smu->mutex); 1601 1602 smu_set_min_dcef_deep_sleep(smu, 1603 display_config->min_dcef_deep_sleep_set_clk / 100); 1604 1605 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1606 if (display_config->displays[index].controller_id != 0) 1607 num_of_active_display++; 1608 } 1609 1610 mutex_unlock(&smu->mutex); 1611 1612 return 0; 1613 } 1614 1615 static int smu_set_clockgating_state(void *handle, 1616 enum amd_clockgating_state state) 1617 { 1618 return 0; 1619 } 1620 1621 static int smu_set_powergating_state(void *handle, 1622 enum amd_powergating_state state) 1623 { 1624 return 0; 1625 } 1626 1627 static int smu_enable_umd_pstate(void *handle, 1628 enum amd_dpm_forced_level *level) 1629 { 1630 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1631 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1632 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1633 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1634 1635 struct smu_context *smu = (struct smu_context*)(handle); 1636 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1637 1638 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1639 return -EINVAL; 1640 1641 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1642 /* enter umd pstate, save current level, disable gfx cg*/ 1643 if (*level & profile_mode_mask) { 1644 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1645 smu_dpm_ctx->enable_umd_pstate = true; 1646 smu_gpo_control(smu, false); 1647 amdgpu_device_ip_set_powergating_state(smu->adev, 1648 AMD_IP_BLOCK_TYPE_GFX, 1649 AMD_PG_STATE_UNGATE); 1650 amdgpu_device_ip_set_clockgating_state(smu->adev, 1651 AMD_IP_BLOCK_TYPE_GFX, 1652 AMD_CG_STATE_UNGATE); 1653 smu_gfx_ulv_control(smu, false); 1654 smu_deep_sleep_control(smu, false); 1655 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1656 } 1657 } else { 1658 /* exit umd pstate, restore level, enable gfx cg*/ 1659 if (!(*level & profile_mode_mask)) { 1660 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1661 *level = smu_dpm_ctx->saved_dpm_level; 1662 smu_dpm_ctx->enable_umd_pstate = false; 1663 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1664 smu_deep_sleep_control(smu, true); 1665 smu_gfx_ulv_control(smu, true); 1666 amdgpu_device_ip_set_clockgating_state(smu->adev, 1667 AMD_IP_BLOCK_TYPE_GFX, 1668 AMD_CG_STATE_GATE); 1669 amdgpu_device_ip_set_powergating_state(smu->adev, 1670 AMD_IP_BLOCK_TYPE_GFX, 1671 AMD_PG_STATE_GATE); 1672 smu_gpo_control(smu, true); 1673 } 1674 } 1675 1676 return 0; 1677 } 1678 1679 static int smu_bump_power_profile_mode(struct smu_context *smu, 1680 long *param, 1681 uint32_t param_size) 1682 { 1683 int ret = 0; 1684 1685 if (smu->ppt_funcs->set_power_profile_mode) 1686 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 1687 1688 return ret; 1689 } 1690 1691 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1692 enum amd_dpm_forced_level level, 1693 bool skip_display_settings) 1694 { 1695 int ret = 0; 1696 int index = 0; 1697 long workload; 1698 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1699 1700 if (!skip_display_settings) { 1701 ret = smu_display_config_changed(smu); 1702 if (ret) { 1703 dev_err(smu->adev->dev, "Failed to change display config!"); 1704 return ret; 1705 } 1706 } 1707 1708 ret = smu_apply_clocks_adjust_rules(smu); 1709 if (ret) { 1710 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1711 return ret; 1712 } 1713 1714 if (!skip_display_settings) { 1715 ret = smu_notify_smc_display_config(smu); 1716 if (ret) { 1717 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1718 return ret; 1719 } 1720 } 1721 1722 if (smu_dpm_ctx->dpm_level != level) { 1723 ret = smu_asic_set_performance_level(smu, level); 1724 if (ret) { 1725 dev_err(smu->adev->dev, "Failed to set performance level!"); 1726 return ret; 1727 } 1728 1729 /* update the saved copy */ 1730 smu_dpm_ctx->dpm_level = level; 1731 } 1732 1733 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1734 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1735 index = fls(smu->workload_mask); 1736 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1737 workload = smu->workload_setting[index]; 1738 1739 if (smu->power_profile_mode != workload) 1740 smu_bump_power_profile_mode(smu, &workload, 0); 1741 } 1742 1743 return ret; 1744 } 1745 1746 static int smu_handle_task(struct smu_context *smu, 1747 enum amd_dpm_forced_level level, 1748 enum amd_pp_task task_id, 1749 bool lock_needed) 1750 { 1751 int ret = 0; 1752 1753 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1754 return -EOPNOTSUPP; 1755 1756 if (lock_needed) 1757 mutex_lock(&smu->mutex); 1758 1759 switch (task_id) { 1760 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1761 ret = smu_pre_display_config_changed(smu); 1762 if (ret) 1763 goto out; 1764 ret = smu_adjust_power_state_dynamic(smu, level, false); 1765 break; 1766 case AMD_PP_TASK_COMPLETE_INIT: 1767 case AMD_PP_TASK_READJUST_POWER_STATE: 1768 ret = smu_adjust_power_state_dynamic(smu, level, true); 1769 break; 1770 default: 1771 break; 1772 } 1773 1774 out: 1775 if (lock_needed) 1776 mutex_unlock(&smu->mutex); 1777 1778 return ret; 1779 } 1780 1781 static int smu_handle_dpm_task(void *handle, 1782 enum amd_pp_task task_id, 1783 enum amd_pm_state_type *user_state) 1784 { 1785 struct smu_context *smu = handle; 1786 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1787 1788 return smu_handle_task(smu, smu_dpm->dpm_level, task_id, true); 1789 1790 } 1791 1792 static int smu_switch_power_profile(void *handle, 1793 enum PP_SMC_POWER_PROFILE type, 1794 bool en) 1795 { 1796 struct smu_context *smu = handle; 1797 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1798 long workload; 1799 uint32_t index; 1800 1801 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1802 return -EOPNOTSUPP; 1803 1804 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1805 return -EINVAL; 1806 1807 mutex_lock(&smu->mutex); 1808 1809 if (!en) { 1810 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1811 index = fls(smu->workload_mask); 1812 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1813 workload = smu->workload_setting[index]; 1814 } else { 1815 smu->workload_mask |= (1 << smu->workload_prority[type]); 1816 index = fls(smu->workload_mask); 1817 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1818 workload = smu->workload_setting[index]; 1819 } 1820 1821 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1822 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 1823 smu_bump_power_profile_mode(smu, &workload, 0); 1824 1825 mutex_unlock(&smu->mutex); 1826 1827 return 0; 1828 } 1829 1830 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 1831 { 1832 struct smu_context *smu = handle; 1833 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1834 enum amd_dpm_forced_level level; 1835 1836 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1837 return -EOPNOTSUPP; 1838 1839 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1840 return -EINVAL; 1841 1842 mutex_lock(&(smu->mutex)); 1843 level = smu_dpm_ctx->dpm_level; 1844 mutex_unlock(&(smu->mutex)); 1845 1846 return level; 1847 } 1848 1849 static int smu_force_performance_level(void *handle, 1850 enum amd_dpm_forced_level level) 1851 { 1852 struct smu_context *smu = handle; 1853 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1854 int ret = 0; 1855 1856 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1857 return -EOPNOTSUPP; 1858 1859 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1860 return -EINVAL; 1861 1862 mutex_lock(&smu->mutex); 1863 1864 ret = smu_enable_umd_pstate(smu, &level); 1865 if (ret) { 1866 mutex_unlock(&smu->mutex); 1867 return ret; 1868 } 1869 1870 ret = smu_handle_task(smu, level, 1871 AMD_PP_TASK_READJUST_POWER_STATE, 1872 false); 1873 1874 mutex_unlock(&smu->mutex); 1875 1876 /* reset user dpm clock state */ 1877 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1878 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 1879 smu->user_dpm_profile.clk_dependency = 0; 1880 } 1881 1882 return ret; 1883 } 1884 1885 static int smu_set_display_count(void *handle, uint32_t count) 1886 { 1887 struct smu_context *smu = handle; 1888 int ret = 0; 1889 1890 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1891 return -EOPNOTSUPP; 1892 1893 mutex_lock(&smu->mutex); 1894 ret = smu_init_display_count(smu, count); 1895 mutex_unlock(&smu->mutex); 1896 1897 return ret; 1898 } 1899 1900 static int smu_force_smuclk_levels(struct smu_context *smu, 1901 enum smu_clk_type clk_type, 1902 uint32_t mask) 1903 { 1904 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1905 int ret = 0; 1906 1907 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1908 return -EOPNOTSUPP; 1909 1910 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1911 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1912 return -EINVAL; 1913 } 1914 1915 mutex_lock(&smu->mutex); 1916 1917 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 1918 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1919 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 1920 smu->user_dpm_profile.clk_mask[clk_type] = mask; 1921 smu_set_user_clk_dependencies(smu, clk_type); 1922 } 1923 } 1924 1925 mutex_unlock(&smu->mutex); 1926 1927 return ret; 1928 } 1929 1930 static int smu_force_ppclk_levels(void *handle, 1931 enum pp_clock_type type, 1932 uint32_t mask) 1933 { 1934 struct smu_context *smu = handle; 1935 enum smu_clk_type clk_type; 1936 1937 switch (type) { 1938 case PP_SCLK: 1939 clk_type = SMU_SCLK; break; 1940 case PP_MCLK: 1941 clk_type = SMU_MCLK; break; 1942 case PP_PCIE: 1943 clk_type = SMU_PCIE; break; 1944 case PP_SOCCLK: 1945 clk_type = SMU_SOCCLK; break; 1946 case PP_FCLK: 1947 clk_type = SMU_FCLK; break; 1948 case PP_DCEFCLK: 1949 clk_type = SMU_DCEFCLK; break; 1950 case PP_VCLK: 1951 clk_type = SMU_VCLK; break; 1952 case PP_DCLK: 1953 clk_type = SMU_DCLK; break; 1954 case OD_SCLK: 1955 clk_type = SMU_OD_SCLK; break; 1956 case OD_MCLK: 1957 clk_type = SMU_OD_MCLK; break; 1958 case OD_VDDC_CURVE: 1959 clk_type = SMU_OD_VDDC_CURVE; break; 1960 case OD_RANGE: 1961 clk_type = SMU_OD_RANGE; break; 1962 default: 1963 return -EINVAL; 1964 } 1965 1966 return smu_force_smuclk_levels(smu, clk_type, mask); 1967 } 1968 1969 /* 1970 * On system suspending or resetting, the dpm_enabled 1971 * flag will be cleared. So that those SMU services which 1972 * are not supported will be gated. 1973 * However, the mp1 state setting should still be granted 1974 * even if the dpm_enabled cleared. 1975 */ 1976 static int smu_set_mp1_state(void *handle, 1977 enum pp_mp1_state mp1_state) 1978 { 1979 struct smu_context *smu = handle; 1980 int ret = 0; 1981 1982 if (!smu->pm_enabled) 1983 return -EOPNOTSUPP; 1984 1985 mutex_lock(&smu->mutex); 1986 1987 if (smu->ppt_funcs && 1988 smu->ppt_funcs->set_mp1_state) 1989 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 1990 1991 mutex_unlock(&smu->mutex); 1992 1993 return ret; 1994 } 1995 1996 static int smu_set_df_cstate(void *handle, 1997 enum pp_df_cstate state) 1998 { 1999 struct smu_context *smu = handle; 2000 int ret = 0; 2001 2002 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2003 return -EOPNOTSUPP; 2004 2005 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2006 return 0; 2007 2008 mutex_lock(&smu->mutex); 2009 2010 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2011 if (ret) 2012 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2013 2014 mutex_unlock(&smu->mutex); 2015 2016 return ret; 2017 } 2018 2019 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 2020 { 2021 int ret = 0; 2022 2023 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2024 return -EOPNOTSUPP; 2025 2026 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 2027 return 0; 2028 2029 mutex_lock(&smu->mutex); 2030 2031 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 2032 if (ret) 2033 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 2034 2035 mutex_unlock(&smu->mutex); 2036 2037 return ret; 2038 } 2039 2040 int smu_write_watermarks_table(struct smu_context *smu) 2041 { 2042 int ret = 0; 2043 2044 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2045 return -EOPNOTSUPP; 2046 2047 mutex_lock(&smu->mutex); 2048 2049 ret = smu_set_watermarks_table(smu, NULL); 2050 2051 mutex_unlock(&smu->mutex); 2052 2053 return ret; 2054 } 2055 2056 static int smu_set_watermarks_for_clock_ranges(void *handle, 2057 struct pp_smu_wm_range_sets *clock_ranges) 2058 { 2059 struct smu_context *smu = handle; 2060 int ret = 0; 2061 2062 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2063 return -EOPNOTSUPP; 2064 2065 if (smu->disable_watermark) 2066 return 0; 2067 2068 mutex_lock(&smu->mutex); 2069 2070 ret = smu_set_watermarks_table(smu, clock_ranges); 2071 2072 mutex_unlock(&smu->mutex); 2073 2074 return ret; 2075 } 2076 2077 int smu_set_ac_dc(struct smu_context *smu) 2078 { 2079 int ret = 0; 2080 2081 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2082 return -EOPNOTSUPP; 2083 2084 /* controlled by firmware */ 2085 if (smu->dc_controlled_by_gpio) 2086 return 0; 2087 2088 mutex_lock(&smu->mutex); 2089 ret = smu_set_power_source(smu, 2090 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2091 SMU_POWER_SOURCE_DC); 2092 if (ret) 2093 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2094 smu->adev->pm.ac_power ? "AC" : "DC"); 2095 mutex_unlock(&smu->mutex); 2096 2097 return ret; 2098 } 2099 2100 const struct amd_ip_funcs smu_ip_funcs = { 2101 .name = "smu", 2102 .early_init = smu_early_init, 2103 .late_init = smu_late_init, 2104 .sw_init = smu_sw_init, 2105 .sw_fini = smu_sw_fini, 2106 .hw_init = smu_hw_init, 2107 .hw_fini = smu_hw_fini, 2108 .suspend = smu_suspend, 2109 .resume = smu_resume, 2110 .is_idle = NULL, 2111 .check_soft_reset = NULL, 2112 .wait_for_idle = NULL, 2113 .soft_reset = NULL, 2114 .set_clockgating_state = smu_set_clockgating_state, 2115 .set_powergating_state = smu_set_powergating_state, 2116 .enable_umd_pstate = smu_enable_umd_pstate, 2117 }; 2118 2119 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 2120 { 2121 .type = AMD_IP_BLOCK_TYPE_SMC, 2122 .major = 11, 2123 .minor = 0, 2124 .rev = 0, 2125 .funcs = &smu_ip_funcs, 2126 }; 2127 2128 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 2129 { 2130 .type = AMD_IP_BLOCK_TYPE_SMC, 2131 .major = 12, 2132 .minor = 0, 2133 .rev = 0, 2134 .funcs = &smu_ip_funcs, 2135 }; 2136 2137 const struct amdgpu_ip_block_version smu_v13_0_ip_block = 2138 { 2139 .type = AMD_IP_BLOCK_TYPE_SMC, 2140 .major = 13, 2141 .minor = 0, 2142 .rev = 0, 2143 .funcs = &smu_ip_funcs, 2144 }; 2145 2146 static int smu_load_microcode(void *handle) 2147 { 2148 struct smu_context *smu = handle; 2149 struct amdgpu_device *adev = smu->adev; 2150 int ret = 0; 2151 2152 if (!smu->pm_enabled) 2153 return -EOPNOTSUPP; 2154 2155 /* This should be used for non PSP loading */ 2156 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2157 return 0; 2158 2159 if (smu->ppt_funcs->load_microcode) { 2160 ret = smu->ppt_funcs->load_microcode(smu); 2161 if (ret) { 2162 dev_err(adev->dev, "Load microcode failed\n"); 2163 return ret; 2164 } 2165 } 2166 2167 if (smu->ppt_funcs->check_fw_status) { 2168 ret = smu->ppt_funcs->check_fw_status(smu); 2169 if (ret) { 2170 dev_err(adev->dev, "SMC is not ready\n"); 2171 return ret; 2172 } 2173 } 2174 2175 return ret; 2176 } 2177 2178 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2179 { 2180 int ret = 0; 2181 2182 mutex_lock(&smu->mutex); 2183 2184 if (smu->ppt_funcs->set_gfx_cgpg) 2185 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2186 2187 mutex_unlock(&smu->mutex); 2188 2189 return ret; 2190 } 2191 2192 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2193 { 2194 struct smu_context *smu = handle; 2195 int ret = 0; 2196 2197 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2198 return -EOPNOTSUPP; 2199 2200 mutex_lock(&smu->mutex); 2201 2202 if (smu->ppt_funcs->set_fan_speed_rpm) { 2203 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2204 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2205 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2206 smu->user_dpm_profile.fan_speed_rpm = speed; 2207 2208 /* Override custom PWM setting as they cannot co-exist */ 2209 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2210 smu->user_dpm_profile.fan_speed_pwm = 0; 2211 } 2212 } 2213 2214 mutex_unlock(&smu->mutex); 2215 2216 return ret; 2217 } 2218 2219 /** 2220 * smu_get_power_limit - Request one of the SMU Power Limits 2221 * 2222 * @handle: pointer to smu context 2223 * @limit: requested limit is written back to this variable 2224 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2225 * @pp_power_type: &pp_power_type type of power 2226 * Return: 0 on success, <0 on error 2227 * 2228 */ 2229 int smu_get_power_limit(void *handle, 2230 uint32_t *limit, 2231 enum pp_power_limit_level pp_limit_level, 2232 enum pp_power_type pp_power_type) 2233 { 2234 struct smu_context *smu = handle; 2235 enum smu_ppt_limit_level limit_level; 2236 uint32_t limit_type; 2237 int ret = 0; 2238 2239 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2240 return -EOPNOTSUPP; 2241 2242 switch(pp_power_type) { 2243 case PP_PWR_TYPE_SUSTAINED: 2244 limit_type = SMU_DEFAULT_PPT_LIMIT; 2245 break; 2246 case PP_PWR_TYPE_FAST: 2247 limit_type = SMU_FAST_PPT_LIMIT; 2248 break; 2249 default: 2250 return -EOPNOTSUPP; 2251 break; 2252 } 2253 2254 switch(pp_limit_level){ 2255 case PP_PWR_LIMIT_CURRENT: 2256 limit_level = SMU_PPT_LIMIT_CURRENT; 2257 break; 2258 case PP_PWR_LIMIT_DEFAULT: 2259 limit_level = SMU_PPT_LIMIT_DEFAULT; 2260 break; 2261 case PP_PWR_LIMIT_MAX: 2262 limit_level = SMU_PPT_LIMIT_MAX; 2263 break; 2264 case PP_PWR_LIMIT_MIN: 2265 default: 2266 return -EOPNOTSUPP; 2267 break; 2268 } 2269 2270 mutex_lock(&smu->mutex); 2271 2272 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2273 if (smu->ppt_funcs->get_ppt_limit) 2274 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2275 } else { 2276 switch (limit_level) { 2277 case SMU_PPT_LIMIT_CURRENT: 2278 if ((smu->adev->asic_type == CHIP_ALDEBARAN) || 2279 (smu->adev->asic_type == CHIP_SIENNA_CICHLID) || 2280 (smu->adev->asic_type == CHIP_NAVY_FLOUNDER) || 2281 (smu->adev->asic_type == CHIP_DIMGREY_CAVEFISH) || 2282 (smu->adev->asic_type == CHIP_BEIGE_GOBY)) 2283 ret = smu_get_asic_power_limits(smu, 2284 &smu->current_power_limit, 2285 NULL, 2286 NULL); 2287 *limit = smu->current_power_limit; 2288 break; 2289 case SMU_PPT_LIMIT_DEFAULT: 2290 *limit = smu->default_power_limit; 2291 break; 2292 case SMU_PPT_LIMIT_MAX: 2293 *limit = smu->max_power_limit; 2294 break; 2295 default: 2296 break; 2297 } 2298 } 2299 2300 mutex_unlock(&smu->mutex); 2301 2302 return ret; 2303 } 2304 2305 static int smu_set_power_limit(void *handle, uint32_t limit) 2306 { 2307 struct smu_context *smu = handle; 2308 uint32_t limit_type = limit >> 24; 2309 int ret = 0; 2310 2311 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2312 return -EOPNOTSUPP; 2313 2314 mutex_lock(&smu->mutex); 2315 2316 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2317 if (smu->ppt_funcs->set_power_limit) { 2318 ret = smu->ppt_funcs->set_power_limit(smu, limit); 2319 goto out; 2320 } 2321 2322 if (limit > smu->max_power_limit) { 2323 dev_err(smu->adev->dev, 2324 "New power limit (%d) is over the max allowed %d\n", 2325 limit, smu->max_power_limit); 2326 ret = -EINVAL; 2327 goto out; 2328 } 2329 2330 if (!limit) 2331 limit = smu->current_power_limit; 2332 2333 if (smu->ppt_funcs->set_power_limit) { 2334 ret = smu->ppt_funcs->set_power_limit(smu, limit); 2335 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2336 smu->user_dpm_profile.power_limit = limit; 2337 } 2338 2339 out: 2340 mutex_unlock(&smu->mutex); 2341 2342 return ret; 2343 } 2344 2345 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2346 { 2347 int ret = 0; 2348 2349 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2350 return -EOPNOTSUPP; 2351 2352 mutex_lock(&smu->mutex); 2353 2354 if (smu->ppt_funcs->print_clk_levels) 2355 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2356 2357 mutex_unlock(&smu->mutex); 2358 2359 return ret; 2360 } 2361 2362 static int smu_print_ppclk_levels(void *handle, 2363 enum pp_clock_type type, 2364 char *buf) 2365 { 2366 struct smu_context *smu = handle; 2367 enum smu_clk_type clk_type; 2368 2369 switch (type) { 2370 case PP_SCLK: 2371 clk_type = SMU_SCLK; break; 2372 case PP_MCLK: 2373 clk_type = SMU_MCLK; break; 2374 case PP_PCIE: 2375 clk_type = SMU_PCIE; break; 2376 case PP_SOCCLK: 2377 clk_type = SMU_SOCCLK; break; 2378 case PP_FCLK: 2379 clk_type = SMU_FCLK; break; 2380 case PP_DCEFCLK: 2381 clk_type = SMU_DCEFCLK; break; 2382 case PP_VCLK: 2383 clk_type = SMU_VCLK; break; 2384 case PP_DCLK: 2385 clk_type = SMU_DCLK; break; 2386 case OD_SCLK: 2387 clk_type = SMU_OD_SCLK; break; 2388 case OD_MCLK: 2389 clk_type = SMU_OD_MCLK; break; 2390 case OD_VDDC_CURVE: 2391 clk_type = SMU_OD_VDDC_CURVE; break; 2392 case OD_RANGE: 2393 clk_type = SMU_OD_RANGE; break; 2394 case OD_VDDGFX_OFFSET: 2395 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2396 case OD_CCLK: 2397 clk_type = SMU_OD_CCLK; break; 2398 default: 2399 return -EINVAL; 2400 } 2401 2402 return smu_print_smuclk_levels(smu, clk_type, buf); 2403 } 2404 2405 static int smu_od_edit_dpm_table(void *handle, 2406 enum PP_OD_DPM_TABLE_COMMAND type, 2407 long *input, uint32_t size) 2408 { 2409 struct smu_context *smu = handle; 2410 int ret = 0; 2411 2412 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2413 return -EOPNOTSUPP; 2414 2415 mutex_lock(&smu->mutex); 2416 2417 if (smu->ppt_funcs->od_edit_dpm_table) { 2418 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2419 } 2420 2421 mutex_unlock(&smu->mutex); 2422 2423 return ret; 2424 } 2425 2426 static int smu_read_sensor(void *handle, 2427 int sensor, 2428 void *data, 2429 int *size_arg) 2430 { 2431 struct smu_context *smu = handle; 2432 struct smu_umd_pstate_table *pstate_table = 2433 &smu->pstate_table; 2434 int ret = 0; 2435 uint32_t *size, size_val; 2436 2437 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2438 return -EOPNOTSUPP; 2439 2440 if (!data || !size_arg) 2441 return -EINVAL; 2442 2443 size_val = *size_arg; 2444 size = &size_val; 2445 2446 mutex_lock(&smu->mutex); 2447 2448 if (smu->ppt_funcs->read_sensor) 2449 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2450 goto unlock; 2451 2452 switch (sensor) { 2453 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2454 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2455 *size = 4; 2456 break; 2457 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2458 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2459 *size = 4; 2460 break; 2461 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2462 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2); 2463 *size = 8; 2464 break; 2465 case AMDGPU_PP_SENSOR_UVD_POWER: 2466 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2467 *size = 4; 2468 break; 2469 case AMDGPU_PP_SENSOR_VCE_POWER: 2470 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2471 *size = 4; 2472 break; 2473 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2474 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2475 *size = 4; 2476 break; 2477 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2478 *(uint32_t *)data = 0; 2479 *size = 4; 2480 break; 2481 default: 2482 *size = 0; 2483 ret = -EOPNOTSUPP; 2484 break; 2485 } 2486 2487 unlock: 2488 mutex_unlock(&smu->mutex); 2489 2490 // assign uint32_t to int 2491 *size_arg = size_val; 2492 2493 return ret; 2494 } 2495 2496 static int smu_get_power_profile_mode(void *handle, char *buf) 2497 { 2498 struct smu_context *smu = handle; 2499 int ret = 0; 2500 2501 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2502 return -EOPNOTSUPP; 2503 2504 mutex_lock(&smu->mutex); 2505 2506 if (smu->ppt_funcs->get_power_profile_mode) 2507 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf); 2508 2509 mutex_unlock(&smu->mutex); 2510 2511 return ret; 2512 } 2513 2514 static int smu_set_power_profile_mode(void *handle, 2515 long *param, 2516 uint32_t param_size) 2517 { 2518 struct smu_context *smu = handle; 2519 int ret = 0; 2520 2521 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2522 return -EOPNOTSUPP; 2523 2524 mutex_lock(&smu->mutex); 2525 2526 smu_bump_power_profile_mode(smu, param, param_size); 2527 2528 mutex_unlock(&smu->mutex); 2529 2530 return ret; 2531 } 2532 2533 2534 static u32 smu_get_fan_control_mode(void *handle) 2535 { 2536 struct smu_context *smu = handle; 2537 u32 ret = 0; 2538 2539 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2540 return AMD_FAN_CTRL_NONE; 2541 2542 mutex_lock(&smu->mutex); 2543 2544 if (smu->ppt_funcs->get_fan_control_mode) 2545 ret = smu->ppt_funcs->get_fan_control_mode(smu); 2546 2547 mutex_unlock(&smu->mutex); 2548 2549 return ret; 2550 } 2551 2552 static int smu_set_fan_control_mode(struct smu_context *smu, int value) 2553 { 2554 int ret = 0; 2555 2556 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2557 return -EOPNOTSUPP; 2558 2559 mutex_lock(&smu->mutex); 2560 2561 if (smu->ppt_funcs->set_fan_control_mode) { 2562 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2563 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2564 smu->user_dpm_profile.fan_mode = value; 2565 } 2566 2567 mutex_unlock(&smu->mutex); 2568 2569 /* reset user dpm fan speed */ 2570 if (!ret && value != AMD_FAN_CTRL_MANUAL && 2571 !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2572 smu->user_dpm_profile.fan_speed_pwm = 0; 2573 smu->user_dpm_profile.fan_speed_rpm = 0; 2574 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 2575 } 2576 2577 return ret; 2578 } 2579 2580 static void smu_pp_set_fan_control_mode(void *handle, u32 value) 2581 { 2582 struct smu_context *smu = handle; 2583 2584 smu_set_fan_control_mode(smu, value); 2585 } 2586 2587 2588 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 2589 { 2590 struct smu_context *smu = handle; 2591 int ret = 0; 2592 2593 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2594 return -EOPNOTSUPP; 2595 2596 mutex_lock(&smu->mutex); 2597 2598 if (smu->ppt_funcs->get_fan_speed_pwm) 2599 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 2600 2601 mutex_unlock(&smu->mutex); 2602 2603 return ret; 2604 } 2605 2606 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 2607 { 2608 struct smu_context *smu = handle; 2609 int ret = 0; 2610 2611 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2612 return -EOPNOTSUPP; 2613 2614 mutex_lock(&smu->mutex); 2615 2616 if (smu->ppt_funcs->set_fan_speed_pwm) { 2617 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 2618 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2619 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 2620 smu->user_dpm_profile.fan_speed_pwm = speed; 2621 2622 /* Override custom RPM setting as they cannot co-exist */ 2623 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 2624 smu->user_dpm_profile.fan_speed_rpm = 0; 2625 } 2626 } 2627 2628 mutex_unlock(&smu->mutex); 2629 2630 return ret; 2631 } 2632 2633 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 2634 { 2635 struct smu_context *smu = handle; 2636 int ret = 0; 2637 2638 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2639 return -EOPNOTSUPP; 2640 2641 mutex_lock(&smu->mutex); 2642 2643 if (smu->ppt_funcs->get_fan_speed_rpm) 2644 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 2645 2646 mutex_unlock(&smu->mutex); 2647 2648 return ret; 2649 } 2650 2651 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 2652 { 2653 struct smu_context *smu = handle; 2654 int ret = 0; 2655 2656 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2657 return -EOPNOTSUPP; 2658 2659 mutex_lock(&smu->mutex); 2660 2661 ret = smu_set_min_dcef_deep_sleep(smu, clk); 2662 2663 mutex_unlock(&smu->mutex); 2664 2665 return ret; 2666 } 2667 2668 static int smu_get_clock_by_type_with_latency(void *handle, 2669 enum amd_pp_clock_type type, 2670 struct pp_clock_levels_with_latency *clocks) 2671 { 2672 struct smu_context *smu = handle; 2673 enum smu_clk_type clk_type; 2674 int ret = 0; 2675 2676 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2677 return -EOPNOTSUPP; 2678 2679 mutex_lock(&smu->mutex); 2680 2681 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 2682 switch (type) { 2683 case amd_pp_sys_clock: 2684 clk_type = SMU_GFXCLK; 2685 break; 2686 case amd_pp_mem_clock: 2687 clk_type = SMU_MCLK; 2688 break; 2689 case amd_pp_dcef_clock: 2690 clk_type = SMU_DCEFCLK; 2691 break; 2692 case amd_pp_disp_clock: 2693 clk_type = SMU_DISPCLK; 2694 break; 2695 default: 2696 dev_err(smu->adev->dev, "Invalid clock type!\n"); 2697 mutex_unlock(&smu->mutex); 2698 return -EINVAL; 2699 } 2700 2701 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2702 } 2703 2704 mutex_unlock(&smu->mutex); 2705 2706 return ret; 2707 } 2708 2709 static int smu_display_clock_voltage_request(void *handle, 2710 struct pp_display_clock_request *clock_req) 2711 { 2712 struct smu_context *smu = handle; 2713 int ret = 0; 2714 2715 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2716 return -EOPNOTSUPP; 2717 2718 mutex_lock(&smu->mutex); 2719 2720 if (smu->ppt_funcs->display_clock_voltage_request) 2721 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2722 2723 mutex_unlock(&smu->mutex); 2724 2725 return ret; 2726 } 2727 2728 2729 static int smu_display_disable_memory_clock_switch(void *handle, 2730 bool disable_memory_clock_switch) 2731 { 2732 struct smu_context *smu = handle; 2733 int ret = -EINVAL; 2734 2735 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2736 return -EOPNOTSUPP; 2737 2738 mutex_lock(&smu->mutex); 2739 2740 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2741 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2742 2743 mutex_unlock(&smu->mutex); 2744 2745 return ret; 2746 } 2747 2748 static int smu_set_xgmi_pstate(void *handle, 2749 uint32_t pstate) 2750 { 2751 struct smu_context *smu = handle; 2752 int ret = 0; 2753 2754 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2755 return -EOPNOTSUPP; 2756 2757 mutex_lock(&smu->mutex); 2758 2759 if (smu->ppt_funcs->set_xgmi_pstate) 2760 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2761 2762 mutex_unlock(&smu->mutex); 2763 2764 if(ret) 2765 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2766 2767 return ret; 2768 } 2769 2770 static int smu_get_baco_capability(void *handle, bool *cap) 2771 { 2772 struct smu_context *smu = handle; 2773 int ret = 0; 2774 2775 *cap = false; 2776 2777 if (!smu->pm_enabled) 2778 return 0; 2779 2780 mutex_lock(&smu->mutex); 2781 2782 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2783 *cap = smu->ppt_funcs->baco_is_support(smu); 2784 2785 mutex_unlock(&smu->mutex); 2786 2787 return ret; 2788 } 2789 2790 static int smu_baco_set_state(void *handle, int state) 2791 { 2792 struct smu_context *smu = handle; 2793 int ret = 0; 2794 2795 if (!smu->pm_enabled) 2796 return -EOPNOTSUPP; 2797 2798 if (state == 0) { 2799 mutex_lock(&smu->mutex); 2800 2801 if (smu->ppt_funcs->baco_exit) 2802 ret = smu->ppt_funcs->baco_exit(smu); 2803 2804 mutex_unlock(&smu->mutex); 2805 } else if (state == 1) { 2806 mutex_lock(&smu->mutex); 2807 2808 if (smu->ppt_funcs->baco_enter) 2809 ret = smu->ppt_funcs->baco_enter(smu); 2810 2811 mutex_unlock(&smu->mutex); 2812 2813 } else { 2814 return -EINVAL; 2815 } 2816 2817 if (ret) 2818 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 2819 (state)?"enter":"exit"); 2820 2821 return ret; 2822 } 2823 2824 bool smu_mode1_reset_is_support(struct smu_context *smu) 2825 { 2826 bool ret = false; 2827 2828 if (!smu->pm_enabled) 2829 return false; 2830 2831 mutex_lock(&smu->mutex); 2832 2833 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2834 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2835 2836 mutex_unlock(&smu->mutex); 2837 2838 return ret; 2839 } 2840 2841 bool smu_mode2_reset_is_support(struct smu_context *smu) 2842 { 2843 bool ret = false; 2844 2845 if (!smu->pm_enabled) 2846 return false; 2847 2848 mutex_lock(&smu->mutex); 2849 2850 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 2851 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 2852 2853 mutex_unlock(&smu->mutex); 2854 2855 return ret; 2856 } 2857 2858 int smu_mode1_reset(struct smu_context *smu) 2859 { 2860 int ret = 0; 2861 2862 if (!smu->pm_enabled) 2863 return -EOPNOTSUPP; 2864 2865 mutex_lock(&smu->mutex); 2866 2867 if (smu->ppt_funcs->mode1_reset) 2868 ret = smu->ppt_funcs->mode1_reset(smu); 2869 2870 mutex_unlock(&smu->mutex); 2871 2872 return ret; 2873 } 2874 2875 static int smu_mode2_reset(void *handle) 2876 { 2877 struct smu_context *smu = handle; 2878 int ret = 0; 2879 2880 if (!smu->pm_enabled) 2881 return -EOPNOTSUPP; 2882 2883 mutex_lock(&smu->mutex); 2884 2885 if (smu->ppt_funcs->mode2_reset) 2886 ret = smu->ppt_funcs->mode2_reset(smu); 2887 2888 mutex_unlock(&smu->mutex); 2889 2890 if (ret) 2891 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2892 2893 return ret; 2894 } 2895 2896 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 2897 struct pp_smu_nv_clock_table *max_clocks) 2898 { 2899 struct smu_context *smu = handle; 2900 int ret = 0; 2901 2902 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2903 return -EOPNOTSUPP; 2904 2905 mutex_lock(&smu->mutex); 2906 2907 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2908 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2909 2910 mutex_unlock(&smu->mutex); 2911 2912 return ret; 2913 } 2914 2915 static int smu_get_uclk_dpm_states(void *handle, 2916 unsigned int *clock_values_in_khz, 2917 unsigned int *num_states) 2918 { 2919 struct smu_context *smu = handle; 2920 int ret = 0; 2921 2922 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2923 return -EOPNOTSUPP; 2924 2925 mutex_lock(&smu->mutex); 2926 2927 if (smu->ppt_funcs->get_uclk_dpm_states) 2928 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2929 2930 mutex_unlock(&smu->mutex); 2931 2932 return ret; 2933 } 2934 2935 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 2936 { 2937 struct smu_context *smu = handle; 2938 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2939 2940 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2941 return -EOPNOTSUPP; 2942 2943 mutex_lock(&smu->mutex); 2944 2945 if (smu->ppt_funcs->get_current_power_state) 2946 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2947 2948 mutex_unlock(&smu->mutex); 2949 2950 return pm_state; 2951 } 2952 2953 static int smu_get_dpm_clock_table(void *handle, 2954 struct dpm_clocks *clock_table) 2955 { 2956 struct smu_context *smu = handle; 2957 int ret = 0; 2958 2959 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2960 return -EOPNOTSUPP; 2961 2962 mutex_lock(&smu->mutex); 2963 2964 if (smu->ppt_funcs->get_dpm_clock_table) 2965 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 2966 2967 mutex_unlock(&smu->mutex); 2968 2969 return ret; 2970 } 2971 2972 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 2973 { 2974 struct smu_context *smu = handle; 2975 ssize_t size; 2976 2977 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2978 return -EOPNOTSUPP; 2979 2980 if (!smu->ppt_funcs->get_gpu_metrics) 2981 return -EOPNOTSUPP; 2982 2983 mutex_lock(&smu->mutex); 2984 2985 size = smu->ppt_funcs->get_gpu_metrics(smu, table); 2986 2987 mutex_unlock(&smu->mutex); 2988 2989 return size; 2990 } 2991 2992 static int smu_enable_mgpu_fan_boost(void *handle) 2993 { 2994 struct smu_context *smu = handle; 2995 int ret = 0; 2996 2997 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2998 return -EOPNOTSUPP; 2999 3000 mutex_lock(&smu->mutex); 3001 3002 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3003 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3004 3005 mutex_unlock(&smu->mutex); 3006 3007 return ret; 3008 } 3009 3010 static int smu_gfx_state_change_set(void *handle, 3011 uint32_t state) 3012 { 3013 struct smu_context *smu = handle; 3014 int ret = 0; 3015 3016 mutex_lock(&smu->mutex); 3017 if (smu->ppt_funcs->gfx_state_change_set) 3018 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3019 mutex_unlock(&smu->mutex); 3020 3021 return ret; 3022 } 3023 3024 int smu_set_light_sbr(struct smu_context *smu, bool enable) 3025 { 3026 int ret = 0; 3027 3028 mutex_lock(&smu->mutex); 3029 if (smu->ppt_funcs->set_light_sbr) 3030 ret = smu->ppt_funcs->set_light_sbr(smu, enable); 3031 mutex_unlock(&smu->mutex); 3032 3033 return ret; 3034 } 3035 3036 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3037 { 3038 struct smu_context *smu = handle; 3039 struct smu_table_context *smu_table = &smu->smu_table; 3040 struct smu_table *memory_pool = &smu_table->memory_pool; 3041 3042 if (!addr || !size) 3043 return -EINVAL; 3044 3045 *addr = NULL; 3046 *size = 0; 3047 mutex_lock(&smu->mutex); 3048 if (memory_pool->bo) { 3049 *addr = memory_pool->cpu_addr; 3050 *size = memory_pool->size; 3051 } 3052 mutex_unlock(&smu->mutex); 3053 3054 return 0; 3055 } 3056 3057 static const struct amd_pm_funcs swsmu_pm_funcs = { 3058 /* export for sysfs */ 3059 .set_fan_control_mode = smu_pp_set_fan_control_mode, 3060 .get_fan_control_mode = smu_get_fan_control_mode, 3061 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3062 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3063 .force_clock_level = smu_force_ppclk_levels, 3064 .print_clock_levels = smu_print_ppclk_levels, 3065 .force_performance_level = smu_force_performance_level, 3066 .read_sensor = smu_read_sensor, 3067 .get_performance_level = smu_get_performance_level, 3068 .get_current_power_state = smu_get_current_power_state, 3069 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3070 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3071 .get_pp_num_states = smu_get_power_num_states, 3072 .get_pp_table = smu_sys_get_pp_table, 3073 .set_pp_table = smu_sys_set_pp_table, 3074 .switch_power_profile = smu_switch_power_profile, 3075 /* export to amdgpu */ 3076 .dispatch_tasks = smu_handle_dpm_task, 3077 .load_firmware = smu_load_microcode, 3078 .set_powergating_by_smu = smu_dpm_set_power_gate, 3079 .set_power_limit = smu_set_power_limit, 3080 .get_power_limit = smu_get_power_limit, 3081 .get_power_profile_mode = smu_get_power_profile_mode, 3082 .set_power_profile_mode = smu_set_power_profile_mode, 3083 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3084 .set_mp1_state = smu_set_mp1_state, 3085 .gfx_state_change_set = smu_gfx_state_change_set, 3086 /* export to DC */ 3087 .get_sclk = smu_get_sclk, 3088 .get_mclk = smu_get_mclk, 3089 .display_configuration_change = smu_display_configuration_change, 3090 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3091 .display_clock_voltage_request = smu_display_clock_voltage_request, 3092 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3093 .set_active_display_count = smu_set_display_count, 3094 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3095 .get_asic_baco_capability = smu_get_baco_capability, 3096 .set_asic_baco_state = smu_baco_set_state, 3097 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3098 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3099 .asic_reset_mode_2 = smu_mode2_reset, 3100 .set_df_cstate = smu_set_df_cstate, 3101 .set_xgmi_pstate = smu_set_xgmi_pstate, 3102 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3103 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3104 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3105 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3106 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3107 .get_dpm_clock_table = smu_get_dpm_clock_table, 3108 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3109 }; 3110 3111 int smu_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event, 3112 uint64_t event_arg) 3113 { 3114 int ret = -EINVAL; 3115 struct smu_context *smu = &adev->smu; 3116 3117 if (smu->ppt_funcs->wait_for_event) { 3118 mutex_lock(&smu->mutex); 3119 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3120 mutex_unlock(&smu->mutex); 3121 } 3122 3123 return ret; 3124 } 3125