1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "vangogh_ppt.h" 37 #include "aldebaran_ppt.h" 38 #include "yellow_carp_ppt.h" 39 #include "cyan_skillfish_ppt.h" 40 #include "amd_pcie.h" 41 42 /* 43 * DO NOT use these for err/warn/info/debug messages. 44 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 45 * They are more MGPU friendly. 46 */ 47 #undef pr_err 48 #undef pr_warn 49 #undef pr_info 50 #undef pr_debug 51 52 static const struct amd_pm_funcs swsmu_pm_funcs; 53 static int smu_force_smuclk_levels(struct smu_context *smu, 54 enum smu_clk_type clk_type, 55 uint32_t mask); 56 static int smu_handle_task(struct smu_context *smu, 57 enum amd_dpm_forced_level level, 58 enum amd_pp_task task_id, 59 bool lock_needed); 60 static int smu_reset(struct smu_context *smu); 61 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 62 static int smu_set_fan_control_mode(struct smu_context *smu, int value); 63 static int smu_set_power_limit(void *handle, uint32_t limit); 64 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 65 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 66 67 static int smu_sys_get_pp_feature_mask(void *handle, 68 char *buf) 69 { 70 struct smu_context *smu = handle; 71 int size = 0; 72 73 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 74 return -EOPNOTSUPP; 75 76 mutex_lock(&smu->mutex); 77 78 size = smu_get_pp_feature_mask(smu, buf); 79 80 mutex_unlock(&smu->mutex); 81 82 return size; 83 } 84 85 static int smu_sys_set_pp_feature_mask(void *handle, 86 uint64_t new_mask) 87 { 88 struct smu_context *smu = handle; 89 int ret = 0; 90 91 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 92 return -EOPNOTSUPP; 93 94 mutex_lock(&smu->mutex); 95 96 ret = smu_set_pp_feature_mask(smu, new_mask); 97 98 mutex_unlock(&smu->mutex); 99 100 return ret; 101 } 102 103 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) 104 { 105 int ret = 0; 106 struct smu_context *smu = &adev->smu; 107 108 if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status) 109 *value = smu_get_gfx_off_status(smu); 110 else 111 ret = -EINVAL; 112 113 return ret; 114 } 115 116 int smu_set_soft_freq_range(struct smu_context *smu, 117 enum smu_clk_type clk_type, 118 uint32_t min, 119 uint32_t max) 120 { 121 int ret = 0; 122 123 mutex_lock(&smu->mutex); 124 125 if (smu->ppt_funcs->set_soft_freq_limited_range) 126 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 127 clk_type, 128 min, 129 max); 130 131 mutex_unlock(&smu->mutex); 132 133 return ret; 134 } 135 136 int smu_get_dpm_freq_range(struct smu_context *smu, 137 enum smu_clk_type clk_type, 138 uint32_t *min, 139 uint32_t *max) 140 { 141 int ret = -ENOTSUPP; 142 143 if (!min && !max) 144 return -EINVAL; 145 146 mutex_lock(&smu->mutex); 147 148 if (smu->ppt_funcs->get_dpm_ultimate_freq) 149 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 150 clk_type, 151 min, 152 max); 153 154 mutex_unlock(&smu->mutex); 155 156 return ret; 157 } 158 159 static u32 smu_get_mclk(void *handle, bool low) 160 { 161 struct smu_context *smu = handle; 162 uint32_t clk_freq; 163 int ret = 0; 164 165 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 166 low ? &clk_freq : NULL, 167 !low ? &clk_freq : NULL); 168 if (ret) 169 return 0; 170 return clk_freq * 100; 171 } 172 173 static u32 smu_get_sclk(void *handle, bool low) 174 { 175 struct smu_context *smu = handle; 176 uint32_t clk_freq; 177 int ret = 0; 178 179 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 180 low ? &clk_freq : NULL, 181 !low ? &clk_freq : NULL); 182 if (ret) 183 return 0; 184 return clk_freq * 100; 185 } 186 187 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu, 188 bool enable) 189 { 190 struct smu_power_context *smu_power = &smu->smu_power; 191 struct smu_power_gate *power_gate = &smu_power->power_gate; 192 int ret = 0; 193 194 if (!smu->ppt_funcs->dpm_set_vcn_enable) 195 return 0; 196 197 if (atomic_read(&power_gate->vcn_gated) ^ enable) 198 return 0; 199 200 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 201 if (!ret) 202 atomic_set(&power_gate->vcn_gated, !enable); 203 204 return ret; 205 } 206 207 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 208 bool enable) 209 { 210 struct smu_power_context *smu_power = &smu->smu_power; 211 struct smu_power_gate *power_gate = &smu_power->power_gate; 212 int ret = 0; 213 214 mutex_lock(&power_gate->vcn_gate_lock); 215 216 ret = smu_dpm_set_vcn_enable_locked(smu, enable); 217 218 mutex_unlock(&power_gate->vcn_gate_lock); 219 220 return ret; 221 } 222 223 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu, 224 bool enable) 225 { 226 struct smu_power_context *smu_power = &smu->smu_power; 227 struct smu_power_gate *power_gate = &smu_power->power_gate; 228 int ret = 0; 229 230 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 231 return 0; 232 233 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 234 return 0; 235 236 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 237 if (!ret) 238 atomic_set(&power_gate->jpeg_gated, !enable); 239 240 return ret; 241 } 242 243 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 244 bool enable) 245 { 246 struct smu_power_context *smu_power = &smu->smu_power; 247 struct smu_power_gate *power_gate = &smu_power->power_gate; 248 int ret = 0; 249 250 mutex_lock(&power_gate->jpeg_gate_lock); 251 252 ret = smu_dpm_set_jpeg_enable_locked(smu, enable); 253 254 mutex_unlock(&power_gate->jpeg_gate_lock); 255 256 return ret; 257 } 258 259 /** 260 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 261 * 262 * @handle: smu_context pointer 263 * @block_type: the IP block to power gate/ungate 264 * @gate: to power gate if true, ungate otherwise 265 * 266 * This API uses no smu->mutex lock protection due to: 267 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 268 * This is guarded to be race condition free by the caller. 269 * 2. Or get called on user setting request of power_dpm_force_performance_level. 270 * Under this case, the smu->mutex lock protection is already enforced on 271 * the parent API smu_force_performance_level of the call path. 272 */ 273 static int smu_dpm_set_power_gate(void *handle, 274 uint32_t block_type, 275 bool gate) 276 { 277 struct smu_context *smu = handle; 278 int ret = 0; 279 280 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 281 return -EOPNOTSUPP; 282 283 switch (block_type) { 284 /* 285 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 286 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 287 */ 288 case AMD_IP_BLOCK_TYPE_UVD: 289 case AMD_IP_BLOCK_TYPE_VCN: 290 ret = smu_dpm_set_vcn_enable(smu, !gate); 291 if (ret) 292 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 293 gate ? "gate" : "ungate"); 294 break; 295 case AMD_IP_BLOCK_TYPE_GFX: 296 ret = smu_gfx_off_control(smu, gate); 297 if (ret) 298 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 299 gate ? "enable" : "disable"); 300 break; 301 case AMD_IP_BLOCK_TYPE_SDMA: 302 ret = smu_powergate_sdma(smu, gate); 303 if (ret) 304 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 305 gate ? "gate" : "ungate"); 306 break; 307 case AMD_IP_BLOCK_TYPE_JPEG: 308 ret = smu_dpm_set_jpeg_enable(smu, !gate); 309 if (ret) 310 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 311 gate ? "gate" : "ungate"); 312 break; 313 default: 314 dev_err(smu->adev->dev, "Unsupported block type!\n"); 315 return -EINVAL; 316 } 317 318 return ret; 319 } 320 321 /** 322 * smu_set_user_clk_dependencies - set user profile clock dependencies 323 * 324 * @smu: smu_context pointer 325 * @clk: enum smu_clk_type type 326 * 327 * Enable/Disable the clock dependency for the @clk type. 328 */ 329 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 330 { 331 if (smu->adev->in_suspend) 332 return; 333 334 if (clk == SMU_MCLK) { 335 smu->user_dpm_profile.clk_dependency = 0; 336 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 337 } else if (clk == SMU_FCLK) { 338 /* MCLK takes precedence over FCLK */ 339 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 340 return; 341 342 smu->user_dpm_profile.clk_dependency = 0; 343 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 344 } else if (clk == SMU_SOCCLK) { 345 /* MCLK takes precedence over SOCCLK */ 346 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 347 return; 348 349 smu->user_dpm_profile.clk_dependency = 0; 350 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 351 } else 352 /* Add clk dependencies here, if any */ 353 return; 354 } 355 356 /** 357 * smu_restore_dpm_user_profile - reinstate user dpm profile 358 * 359 * @smu: smu_context pointer 360 * 361 * Restore the saved user power configurations include power limit, 362 * clock frequencies, fan control mode and fan speed. 363 */ 364 static void smu_restore_dpm_user_profile(struct smu_context *smu) 365 { 366 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 367 int ret = 0; 368 369 if (!smu->adev->in_suspend) 370 return; 371 372 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 373 return; 374 375 /* Enable restore flag */ 376 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 377 378 /* set the user dpm power limit */ 379 if (smu->user_dpm_profile.power_limit) { 380 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 381 if (ret) 382 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 383 } 384 385 /* set the user dpm clock configurations */ 386 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 387 enum smu_clk_type clk_type; 388 389 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 390 /* 391 * Iterate over smu clk type and force the saved user clk 392 * configs, skip if clock dependency is enabled 393 */ 394 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 395 smu->user_dpm_profile.clk_mask[clk_type]) { 396 ret = smu_force_smuclk_levels(smu, clk_type, 397 smu->user_dpm_profile.clk_mask[clk_type]); 398 if (ret) 399 dev_err(smu->adev->dev, 400 "Failed to set clock type = %d\n", clk_type); 401 } 402 } 403 } 404 405 /* set the user dpm fan configurations */ 406 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 407 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 408 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 409 if (ret) { 410 smu->user_dpm_profile.fan_speed_pwm = 0; 411 smu->user_dpm_profile.fan_speed_rpm = 0; 412 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 413 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 414 } 415 416 if (smu->user_dpm_profile.fan_speed_pwm) { 417 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 418 if (ret) 419 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 420 } 421 422 if (smu->user_dpm_profile.fan_speed_rpm) { 423 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 424 if (ret) 425 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 426 } 427 } 428 429 /* Restore user customized OD settings */ 430 if (smu->user_dpm_profile.user_od) { 431 if (smu->ppt_funcs->restore_user_od_settings) { 432 ret = smu->ppt_funcs->restore_user_od_settings(smu); 433 if (ret) 434 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 435 } 436 } 437 438 /* Disable restore flag */ 439 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 440 } 441 442 static int smu_get_power_num_states(void *handle, 443 struct pp_states_info *state_info) 444 { 445 if (!state_info) 446 return -EINVAL; 447 448 /* not support power state */ 449 memset(state_info, 0, sizeof(struct pp_states_info)); 450 state_info->nums = 1; 451 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 452 453 return 0; 454 } 455 456 bool is_support_sw_smu(struct amdgpu_device *adev) 457 { 458 if (adev->asic_type >= CHIP_ARCTURUS) 459 return true; 460 461 return false; 462 } 463 464 bool is_support_cclk_dpm(struct amdgpu_device *adev) 465 { 466 struct smu_context *smu = &adev->smu; 467 468 if (!is_support_sw_smu(adev)) 469 return false; 470 471 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 472 return false; 473 474 return true; 475 } 476 477 478 static int smu_sys_get_pp_table(void *handle, 479 char **table) 480 { 481 struct smu_context *smu = handle; 482 struct smu_table_context *smu_table = &smu->smu_table; 483 uint32_t powerplay_table_size; 484 485 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 486 return -EOPNOTSUPP; 487 488 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 489 return -EINVAL; 490 491 mutex_lock(&smu->mutex); 492 493 if (smu_table->hardcode_pptable) 494 *table = smu_table->hardcode_pptable; 495 else 496 *table = smu_table->power_play_table; 497 498 powerplay_table_size = smu_table->power_play_table_size; 499 500 mutex_unlock(&smu->mutex); 501 502 return powerplay_table_size; 503 } 504 505 static int smu_sys_set_pp_table(void *handle, 506 const char *buf, 507 size_t size) 508 { 509 struct smu_context *smu = handle; 510 struct smu_table_context *smu_table = &smu->smu_table; 511 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 512 int ret = 0; 513 514 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 515 return -EOPNOTSUPP; 516 517 if (header->usStructureSize != size) { 518 dev_err(smu->adev->dev, "pp table size not matched !\n"); 519 return -EIO; 520 } 521 522 mutex_lock(&smu->mutex); 523 if (!smu_table->hardcode_pptable) 524 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 525 if (!smu_table->hardcode_pptable) { 526 ret = -ENOMEM; 527 goto failed; 528 } 529 530 memcpy(smu_table->hardcode_pptable, buf, size); 531 smu_table->power_play_table = smu_table->hardcode_pptable; 532 smu_table->power_play_table_size = size; 533 534 /* 535 * Special hw_fini action(for Navi1x, the DPMs disablement will be 536 * skipped) may be needed for custom pptable uploading. 537 */ 538 smu->uploading_custom_pp_table = true; 539 540 ret = smu_reset(smu); 541 if (ret) 542 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 543 544 smu->uploading_custom_pp_table = false; 545 546 failed: 547 mutex_unlock(&smu->mutex); 548 return ret; 549 } 550 551 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 552 { 553 struct smu_feature *feature = &smu->smu_feature; 554 int ret = 0; 555 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 556 557 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 558 559 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 560 SMU_FEATURE_MAX/32); 561 if (ret) 562 return ret; 563 564 bitmap_or(feature->allowed, feature->allowed, 565 (unsigned long *)allowed_feature_mask, 566 feature->feature_num); 567 568 return ret; 569 } 570 571 static int smu_set_funcs(struct amdgpu_device *adev) 572 { 573 struct smu_context *smu = &adev->smu; 574 575 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 576 smu->od_enabled = true; 577 578 switch (adev->asic_type) { 579 case CHIP_NAVI10: 580 case CHIP_NAVI14: 581 case CHIP_NAVI12: 582 navi10_set_ppt_funcs(smu); 583 break; 584 case CHIP_ARCTURUS: 585 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 586 arcturus_set_ppt_funcs(smu); 587 /* OD is not supported on Arcturus */ 588 smu->od_enabled =false; 589 break; 590 case CHIP_SIENNA_CICHLID: 591 case CHIP_NAVY_FLOUNDER: 592 case CHIP_DIMGREY_CAVEFISH: 593 case CHIP_BEIGE_GOBY: 594 sienna_cichlid_set_ppt_funcs(smu); 595 break; 596 case CHIP_ALDEBARAN: 597 aldebaran_set_ppt_funcs(smu); 598 /* Enable pp_od_clk_voltage node */ 599 smu->od_enabled = true; 600 break; 601 case CHIP_RENOIR: 602 renoir_set_ppt_funcs(smu); 603 break; 604 case CHIP_VANGOGH: 605 vangogh_set_ppt_funcs(smu); 606 break; 607 case CHIP_YELLOW_CARP: 608 yellow_carp_set_ppt_funcs(smu); 609 break; 610 case CHIP_CYAN_SKILLFISH: 611 cyan_skillfish_set_ppt_funcs(smu); 612 break; 613 default: 614 return -EINVAL; 615 } 616 617 return 0; 618 } 619 620 static int smu_early_init(void *handle) 621 { 622 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 623 struct smu_context *smu = &adev->smu; 624 625 smu->adev = adev; 626 smu->pm_enabled = !!amdgpu_dpm; 627 smu->is_apu = false; 628 rw_init(&smu->mutex, "smurw"); 629 rw_init(&smu->smu_baco.mutex, "smubc"); 630 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 631 smu->smu_baco.platform_support = false; 632 smu->user_dpm_profile.fan_mode = -1; 633 634 adev->powerplay.pp_handle = smu; 635 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 636 637 return smu_set_funcs(adev); 638 } 639 640 static int smu_set_default_dpm_table(struct smu_context *smu) 641 { 642 struct smu_power_context *smu_power = &smu->smu_power; 643 struct smu_power_gate *power_gate = &smu_power->power_gate; 644 int vcn_gate, jpeg_gate; 645 int ret = 0; 646 647 if (!smu->ppt_funcs->set_default_dpm_table) 648 return 0; 649 650 mutex_lock(&power_gate->vcn_gate_lock); 651 mutex_lock(&power_gate->jpeg_gate_lock); 652 653 vcn_gate = atomic_read(&power_gate->vcn_gated); 654 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 655 656 ret = smu_dpm_set_vcn_enable_locked(smu, true); 657 if (ret) 658 goto err0_out; 659 660 ret = smu_dpm_set_jpeg_enable_locked(smu, true); 661 if (ret) 662 goto err1_out; 663 664 ret = smu->ppt_funcs->set_default_dpm_table(smu); 665 if (ret) 666 dev_err(smu->adev->dev, 667 "Failed to setup default dpm clock tables!\n"); 668 669 smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate); 670 err1_out: 671 smu_dpm_set_vcn_enable_locked(smu, !vcn_gate); 672 err0_out: 673 mutex_unlock(&power_gate->jpeg_gate_lock); 674 mutex_unlock(&power_gate->vcn_gate_lock); 675 676 return ret; 677 } 678 679 680 static int smu_late_init(void *handle) 681 { 682 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 683 struct smu_context *smu = &adev->smu; 684 int ret = 0; 685 686 smu_set_fine_grain_gfx_freq_parameters(smu); 687 688 if (!smu->pm_enabled) 689 return 0; 690 691 ret = smu_post_init(smu); 692 if (ret) { 693 dev_err(adev->dev, "Failed to post smu init!\n"); 694 return ret; 695 } 696 697 if (adev->asic_type == CHIP_YELLOW_CARP) 698 return 0; 699 700 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 701 ret = smu_set_default_od_settings(smu); 702 if (ret) { 703 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 704 return ret; 705 } 706 } 707 708 ret = smu_populate_umd_state_clk(smu); 709 if (ret) { 710 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 711 return ret; 712 } 713 714 ret = smu_get_asic_power_limits(smu, 715 &smu->current_power_limit, 716 &smu->default_power_limit, 717 &smu->max_power_limit); 718 if (ret) { 719 dev_err(adev->dev, "Failed to get asic power limits!\n"); 720 return ret; 721 } 722 723 if (!amdgpu_sriov_vf(adev)) 724 smu_get_unique_id(smu); 725 726 smu_get_fan_parameters(smu); 727 728 smu_handle_task(&adev->smu, 729 smu->smu_dpm.dpm_level, 730 AMD_PP_TASK_COMPLETE_INIT, 731 false); 732 733 smu_restore_dpm_user_profile(smu); 734 735 return 0; 736 } 737 738 static int smu_init_fb_allocations(struct smu_context *smu) 739 { 740 struct amdgpu_device *adev = smu->adev; 741 struct smu_table_context *smu_table = &smu->smu_table; 742 struct smu_table *tables = smu_table->tables; 743 struct smu_table *driver_table = &(smu_table->driver_table); 744 uint32_t max_table_size = 0; 745 int ret, i; 746 747 /* VRAM allocation for tool table */ 748 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 749 ret = amdgpu_bo_create_kernel(adev, 750 tables[SMU_TABLE_PMSTATUSLOG].size, 751 tables[SMU_TABLE_PMSTATUSLOG].align, 752 tables[SMU_TABLE_PMSTATUSLOG].domain, 753 &tables[SMU_TABLE_PMSTATUSLOG].bo, 754 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 755 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 756 if (ret) { 757 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 758 return ret; 759 } 760 } 761 762 /* VRAM allocation for driver table */ 763 for (i = 0; i < SMU_TABLE_COUNT; i++) { 764 if (tables[i].size == 0) 765 continue; 766 767 if (i == SMU_TABLE_PMSTATUSLOG) 768 continue; 769 770 if (max_table_size < tables[i].size) 771 max_table_size = tables[i].size; 772 } 773 774 driver_table->size = max_table_size; 775 driver_table->align = PAGE_SIZE; 776 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 777 778 ret = amdgpu_bo_create_kernel(adev, 779 driver_table->size, 780 driver_table->align, 781 driver_table->domain, 782 &driver_table->bo, 783 &driver_table->mc_address, 784 &driver_table->cpu_addr); 785 if (ret) { 786 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 787 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 788 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 789 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 790 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 791 } 792 793 return ret; 794 } 795 796 static int smu_fini_fb_allocations(struct smu_context *smu) 797 { 798 struct smu_table_context *smu_table = &smu->smu_table; 799 struct smu_table *tables = smu_table->tables; 800 struct smu_table *driver_table = &(smu_table->driver_table); 801 802 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 803 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 804 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 805 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 806 807 amdgpu_bo_free_kernel(&driver_table->bo, 808 &driver_table->mc_address, 809 &driver_table->cpu_addr); 810 811 return 0; 812 } 813 814 /** 815 * smu_alloc_memory_pool - allocate memory pool in the system memory 816 * 817 * @smu: amdgpu_device pointer 818 * 819 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 820 * and DramLogSetDramAddr can notify it changed. 821 * 822 * Returns 0 on success, error on failure. 823 */ 824 static int smu_alloc_memory_pool(struct smu_context *smu) 825 { 826 struct amdgpu_device *adev = smu->adev; 827 struct smu_table_context *smu_table = &smu->smu_table; 828 struct smu_table *memory_pool = &smu_table->memory_pool; 829 uint64_t pool_size = smu->pool_size; 830 int ret = 0; 831 832 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 833 return ret; 834 835 memory_pool->size = pool_size; 836 memory_pool->align = PAGE_SIZE; 837 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 838 839 switch (pool_size) { 840 case SMU_MEMORY_POOL_SIZE_256_MB: 841 case SMU_MEMORY_POOL_SIZE_512_MB: 842 case SMU_MEMORY_POOL_SIZE_1_GB: 843 case SMU_MEMORY_POOL_SIZE_2_GB: 844 ret = amdgpu_bo_create_kernel(adev, 845 memory_pool->size, 846 memory_pool->align, 847 memory_pool->domain, 848 &memory_pool->bo, 849 &memory_pool->mc_address, 850 &memory_pool->cpu_addr); 851 if (ret) 852 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 853 break; 854 default: 855 break; 856 } 857 858 return ret; 859 } 860 861 static int smu_free_memory_pool(struct smu_context *smu) 862 { 863 struct smu_table_context *smu_table = &smu->smu_table; 864 struct smu_table *memory_pool = &smu_table->memory_pool; 865 866 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 867 return 0; 868 869 amdgpu_bo_free_kernel(&memory_pool->bo, 870 &memory_pool->mc_address, 871 &memory_pool->cpu_addr); 872 873 memset(memory_pool, 0, sizeof(struct smu_table)); 874 875 return 0; 876 } 877 878 static int smu_alloc_dummy_read_table(struct smu_context *smu) 879 { 880 struct smu_table_context *smu_table = &smu->smu_table; 881 struct smu_table *dummy_read_1_table = 882 &smu_table->dummy_read_1_table; 883 struct amdgpu_device *adev = smu->adev; 884 int ret = 0; 885 886 dummy_read_1_table->size = 0x40000; 887 dummy_read_1_table->align = PAGE_SIZE; 888 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 889 890 ret = amdgpu_bo_create_kernel(adev, 891 dummy_read_1_table->size, 892 dummy_read_1_table->align, 893 dummy_read_1_table->domain, 894 &dummy_read_1_table->bo, 895 &dummy_read_1_table->mc_address, 896 &dummy_read_1_table->cpu_addr); 897 if (ret) 898 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 899 900 return ret; 901 } 902 903 static void smu_free_dummy_read_table(struct smu_context *smu) 904 { 905 struct smu_table_context *smu_table = &smu->smu_table; 906 struct smu_table *dummy_read_1_table = 907 &smu_table->dummy_read_1_table; 908 909 910 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 911 &dummy_read_1_table->mc_address, 912 &dummy_read_1_table->cpu_addr); 913 914 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 915 } 916 917 static int smu_smc_table_sw_init(struct smu_context *smu) 918 { 919 int ret; 920 921 /** 922 * Create smu_table structure, and init smc tables such as 923 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 924 */ 925 ret = smu_init_smc_tables(smu); 926 if (ret) { 927 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 928 return ret; 929 } 930 931 /** 932 * Create smu_power_context structure, and allocate smu_dpm_context and 933 * context size to fill the smu_power_context data. 934 */ 935 ret = smu_init_power(smu); 936 if (ret) { 937 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 938 return ret; 939 } 940 941 /* 942 * allocate vram bos to store smc table contents. 943 */ 944 ret = smu_init_fb_allocations(smu); 945 if (ret) 946 return ret; 947 948 ret = smu_alloc_memory_pool(smu); 949 if (ret) 950 return ret; 951 952 ret = smu_alloc_dummy_read_table(smu); 953 if (ret) 954 return ret; 955 956 ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c); 957 if (ret) 958 return ret; 959 960 return 0; 961 } 962 963 static int smu_smc_table_sw_fini(struct smu_context *smu) 964 { 965 int ret; 966 967 smu_i2c_fini(smu, &smu->adev->pm.smu_i2c); 968 969 smu_free_dummy_read_table(smu); 970 971 ret = smu_free_memory_pool(smu); 972 if (ret) 973 return ret; 974 975 ret = smu_fini_fb_allocations(smu); 976 if (ret) 977 return ret; 978 979 ret = smu_fini_power(smu); 980 if (ret) { 981 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 982 return ret; 983 } 984 985 ret = smu_fini_smc_tables(smu); 986 if (ret) { 987 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 988 return ret; 989 } 990 991 return 0; 992 } 993 994 static void smu_throttling_logging_work_fn(struct work_struct *work) 995 { 996 struct smu_context *smu = container_of(work, struct smu_context, 997 throttling_logging_work); 998 999 smu_log_thermal_throttling(smu); 1000 } 1001 1002 static void smu_interrupt_work_fn(struct work_struct *work) 1003 { 1004 struct smu_context *smu = container_of(work, struct smu_context, 1005 interrupt_work); 1006 1007 mutex_lock(&smu->mutex); 1008 1009 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1010 smu->ppt_funcs->interrupt_work(smu); 1011 1012 mutex_unlock(&smu->mutex); 1013 } 1014 1015 static int smu_sw_init(void *handle) 1016 { 1017 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1018 struct smu_context *smu = &adev->smu; 1019 int ret; 1020 1021 smu->pool_size = adev->pm.smu_prv_buffer_size; 1022 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1023 rw_init(&smu->smu_feature.mutex, "smuft"); 1024 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1025 bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX); 1026 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1027 1028 rw_init(&smu->sensor_lock, "smusen"); 1029 rw_init(&smu->metrics_lock, "smumt"); 1030 rw_init(&smu->message_lock, "smuml"); 1031 1032 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1033 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1034 atomic64_set(&smu->throttle_int_counter, 0); 1035 smu->watermarks_bitmap = 0; 1036 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1037 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1038 1039 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1040 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1041 rw_init(&smu->smu_power.power_gate.vcn_gate_lock, "vcngl"); 1042 rw_init(&smu->smu_power.power_gate.jpeg_gate_lock, "jpgglk"); 1043 1044 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1045 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1046 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1047 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1048 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1049 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1050 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1051 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1052 1053 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1054 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1055 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1056 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1057 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1058 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1059 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1060 smu->display_config = &adev->pm.pm_display_cfg; 1061 1062 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1063 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1064 1065 ret = smu_init_microcode(smu); 1066 if (ret) { 1067 dev_err(adev->dev, "Failed to load smu firmware!\n"); 1068 return ret; 1069 } 1070 1071 ret = smu_smc_table_sw_init(smu); 1072 if (ret) { 1073 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1074 return ret; 1075 } 1076 1077 ret = smu_register_irq_handler(smu); 1078 if (ret) { 1079 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1080 return ret; 1081 } 1082 1083 /* If there is no way to query fan control mode, fan control is not supported */ 1084 if (!smu->ppt_funcs->get_fan_control_mode) 1085 smu->adev->pm.no_fan = true; 1086 1087 return 0; 1088 } 1089 1090 static int smu_sw_fini(void *handle) 1091 { 1092 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1093 struct smu_context *smu = &adev->smu; 1094 int ret; 1095 1096 ret = smu_smc_table_sw_fini(smu); 1097 if (ret) { 1098 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1099 return ret; 1100 } 1101 1102 smu_fini_microcode(smu); 1103 1104 return 0; 1105 } 1106 1107 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1108 { 1109 struct amdgpu_device *adev = smu->adev; 1110 struct smu_temperature_range *range = 1111 &smu->thermal_range; 1112 int ret = 0; 1113 1114 if (!smu->ppt_funcs->get_thermal_temperature_range) 1115 return 0; 1116 1117 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1118 if (ret) 1119 return ret; 1120 1121 adev->pm.dpm.thermal.min_temp = range->min; 1122 adev->pm.dpm.thermal.max_temp = range->max; 1123 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1124 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1125 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1126 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1127 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1128 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1129 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1130 1131 return ret; 1132 } 1133 1134 static int smu_smc_hw_setup(struct smu_context *smu) 1135 { 1136 struct amdgpu_device *adev = smu->adev; 1137 uint32_t pcie_gen = 0, pcie_width = 0; 1138 int ret = 0; 1139 1140 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1141 dev_info(adev->dev, "dpm has been enabled\n"); 1142 /* this is needed specifically */ 1143 if ((adev->asic_type >= CHIP_SIENNA_CICHLID) && 1144 (adev->asic_type <= CHIP_DIMGREY_CAVEFISH)) 1145 ret = smu_system_features_control(smu, true); 1146 return ret; 1147 } 1148 1149 ret = smu_init_display_count(smu, 0); 1150 if (ret) { 1151 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1152 return ret; 1153 } 1154 1155 ret = smu_set_driver_table_location(smu); 1156 if (ret) { 1157 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1158 return ret; 1159 } 1160 1161 /* 1162 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1163 */ 1164 ret = smu_set_tool_table_location(smu); 1165 if (ret) { 1166 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1167 return ret; 1168 } 1169 1170 /* 1171 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1172 * pool location. 1173 */ 1174 ret = smu_notify_memory_pool_location(smu); 1175 if (ret) { 1176 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1177 return ret; 1178 } 1179 1180 /* smu_dump_pptable(smu); */ 1181 /* 1182 * Copy pptable bo in the vram to smc with SMU MSGs such as 1183 * SetDriverDramAddr and TransferTableDram2Smu. 1184 */ 1185 ret = smu_write_pptable(smu); 1186 if (ret) { 1187 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1188 return ret; 1189 } 1190 1191 /* issue Run*Btc msg */ 1192 ret = smu_run_btc(smu); 1193 if (ret) 1194 return ret; 1195 1196 ret = smu_feature_set_allowed_mask(smu); 1197 if (ret) { 1198 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1199 return ret; 1200 } 1201 1202 ret = smu_system_features_control(smu, true); 1203 if (ret) { 1204 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1205 return ret; 1206 } 1207 1208 if (!smu_is_dpm_running(smu)) 1209 dev_info(adev->dev, "dpm has been disabled\n"); 1210 1211 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1212 pcie_gen = 3; 1213 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1214 pcie_gen = 2; 1215 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1216 pcie_gen = 1; 1217 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1218 pcie_gen = 0; 1219 1220 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1221 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1222 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1223 */ 1224 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1225 pcie_width = 6; 1226 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1227 pcie_width = 5; 1228 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1229 pcie_width = 4; 1230 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1231 pcie_width = 3; 1232 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1233 pcie_width = 2; 1234 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1235 pcie_width = 1; 1236 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1237 if (ret) { 1238 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1239 return ret; 1240 } 1241 1242 ret = smu_get_thermal_temperature_range(smu); 1243 if (ret) { 1244 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1245 return ret; 1246 } 1247 1248 ret = smu_enable_thermal_alert(smu); 1249 if (ret) { 1250 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1251 return ret; 1252 } 1253 1254 /* 1255 * Set initialized values (get from vbios) to dpm tables context such as 1256 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1257 * type of clks. 1258 */ 1259 ret = smu_set_default_dpm_table(smu); 1260 if (ret) { 1261 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1262 return ret; 1263 } 1264 1265 ret = smu_notify_display_change(smu); 1266 if (ret) 1267 return ret; 1268 1269 /* 1270 * Set min deep sleep dce fclk with bootup value from vbios via 1271 * SetMinDeepSleepDcefclk MSG. 1272 */ 1273 ret = smu_set_min_dcef_deep_sleep(smu, 1274 smu->smu_table.boot_values.dcefclk / 100); 1275 if (ret) 1276 return ret; 1277 1278 return ret; 1279 } 1280 1281 static int smu_start_smc_engine(struct smu_context *smu) 1282 { 1283 struct amdgpu_device *adev = smu->adev; 1284 int ret = 0; 1285 1286 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1287 if (adev->asic_type < CHIP_NAVI10) { 1288 if (smu->ppt_funcs->load_microcode) { 1289 ret = smu->ppt_funcs->load_microcode(smu); 1290 if (ret) 1291 return ret; 1292 } 1293 } 1294 } 1295 1296 if (smu->ppt_funcs->check_fw_status) { 1297 ret = smu->ppt_funcs->check_fw_status(smu); 1298 if (ret) { 1299 dev_err(adev->dev, "SMC is not ready\n"); 1300 return ret; 1301 } 1302 } 1303 1304 /* 1305 * Send msg GetDriverIfVersion to check if the return value is equal 1306 * with DRIVER_IF_VERSION of smc header. 1307 */ 1308 ret = smu_check_fw_version(smu); 1309 if (ret) 1310 return ret; 1311 1312 return ret; 1313 } 1314 1315 static int smu_hw_init(void *handle) 1316 { 1317 int ret; 1318 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1319 struct smu_context *smu = &adev->smu; 1320 1321 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1322 smu->pm_enabled = false; 1323 return 0; 1324 } 1325 1326 ret = smu_start_smc_engine(smu); 1327 if (ret) { 1328 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1329 return ret; 1330 } 1331 1332 if (smu->is_apu) { 1333 smu_powergate_sdma(&adev->smu, false); 1334 smu_dpm_set_vcn_enable(smu, true); 1335 smu_dpm_set_jpeg_enable(smu, true); 1336 smu_set_gfx_cgpg(&adev->smu, true); 1337 } 1338 1339 if (!smu->pm_enabled) 1340 return 0; 1341 1342 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1343 ret = smu_get_vbios_bootup_values(smu); 1344 if (ret) { 1345 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1346 return ret; 1347 } 1348 1349 ret = smu_setup_pptable(smu); 1350 if (ret) { 1351 dev_err(adev->dev, "Failed to setup pptable!\n"); 1352 return ret; 1353 } 1354 1355 ret = smu_get_driver_allowed_feature_mask(smu); 1356 if (ret) 1357 return ret; 1358 1359 ret = smu_smc_hw_setup(smu); 1360 if (ret) { 1361 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1362 return ret; 1363 } 1364 1365 /* 1366 * Move maximum sustainable clock retrieving here considering 1367 * 1. It is not needed on resume(from S3). 1368 * 2. DAL settings come between .hw_init and .late_init of SMU. 1369 * And DAL needs to know the maximum sustainable clocks. Thus 1370 * it cannot be put in .late_init(). 1371 */ 1372 ret = smu_init_max_sustainable_clocks(smu); 1373 if (ret) { 1374 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1375 return ret; 1376 } 1377 1378 adev->pm.dpm_enabled = true; 1379 1380 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1381 1382 return 0; 1383 } 1384 1385 static int smu_disable_dpms(struct smu_context *smu) 1386 { 1387 struct amdgpu_device *adev = smu->adev; 1388 int ret = 0; 1389 bool use_baco = !smu->is_apu && 1390 ((amdgpu_in_reset(adev) && 1391 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1392 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1393 1394 /* 1395 * For custom pptable uploading, skip the DPM features 1396 * disable process on Navi1x ASICs. 1397 * - As the gfx related features are under control of 1398 * RLC on those ASICs. RLC reinitialization will be 1399 * needed to reenable them. That will cost much more 1400 * efforts. 1401 * 1402 * - SMU firmware can handle the DPM reenablement 1403 * properly. 1404 */ 1405 if (smu->uploading_custom_pp_table && 1406 (adev->asic_type >= CHIP_NAVI10) && 1407 (adev->asic_type <= CHIP_BEIGE_GOBY)) 1408 return smu_disable_all_features_with_exception(smu, 1409 true, 1410 SMU_FEATURE_COUNT); 1411 1412 /* 1413 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1414 * on BACO in. Driver involvement is unnecessary. 1415 */ 1416 if (((adev->asic_type == CHIP_SIENNA_CICHLID) || 1417 ((adev->asic_type >= CHIP_NAVI10) && (adev->asic_type <= CHIP_NAVI12))) && 1418 use_baco) 1419 return smu_disable_all_features_with_exception(smu, 1420 true, 1421 SMU_FEATURE_BACO_BIT); 1422 1423 /* 1424 * For gpu reset, runpm and hibernation through BACO, 1425 * BACO feature has to be kept enabled. 1426 */ 1427 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1428 ret = smu_disable_all_features_with_exception(smu, 1429 false, 1430 SMU_FEATURE_BACO_BIT); 1431 if (ret) 1432 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1433 } else { 1434 ret = smu_system_features_control(smu, false); 1435 if (ret) 1436 dev_err(adev->dev, "Failed to disable smu features.\n"); 1437 } 1438 1439 if (adev->asic_type >= CHIP_NAVI10 && 1440 adev->gfx.rlc.funcs->stop) 1441 adev->gfx.rlc.funcs->stop(adev); 1442 1443 return ret; 1444 } 1445 1446 static int smu_smc_hw_cleanup(struct smu_context *smu) 1447 { 1448 struct amdgpu_device *adev = smu->adev; 1449 int ret = 0; 1450 1451 cancel_work_sync(&smu->throttling_logging_work); 1452 cancel_work_sync(&smu->interrupt_work); 1453 1454 ret = smu_disable_thermal_alert(smu); 1455 if (ret) { 1456 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1457 return ret; 1458 } 1459 1460 ret = smu_disable_dpms(smu); 1461 if (ret) { 1462 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1463 return ret; 1464 } 1465 1466 return 0; 1467 } 1468 1469 static int smu_hw_fini(void *handle) 1470 { 1471 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1472 struct smu_context *smu = &adev->smu; 1473 1474 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1475 return 0; 1476 1477 if (smu->is_apu) { 1478 smu_powergate_sdma(&adev->smu, true); 1479 } 1480 1481 smu_dpm_set_vcn_enable(smu, false); 1482 smu_dpm_set_jpeg_enable(smu, false); 1483 1484 adev->vcn.cur_state = AMD_PG_STATE_GATE; 1485 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 1486 1487 if (!smu->pm_enabled) 1488 return 0; 1489 1490 adev->pm.dpm_enabled = false; 1491 1492 return smu_smc_hw_cleanup(smu); 1493 } 1494 1495 static int smu_reset(struct smu_context *smu) 1496 { 1497 struct amdgpu_device *adev = smu->adev; 1498 int ret; 1499 1500 amdgpu_gfx_off_ctrl(smu->adev, false); 1501 1502 ret = smu_hw_fini(adev); 1503 if (ret) 1504 return ret; 1505 1506 ret = smu_hw_init(adev); 1507 if (ret) 1508 return ret; 1509 1510 ret = smu_late_init(adev); 1511 if (ret) 1512 return ret; 1513 1514 amdgpu_gfx_off_ctrl(smu->adev, true); 1515 1516 return 0; 1517 } 1518 1519 static int smu_suspend(void *handle) 1520 { 1521 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1522 struct smu_context *smu = &adev->smu; 1523 int ret; 1524 1525 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1526 return 0; 1527 1528 if (!smu->pm_enabled) 1529 return 0; 1530 1531 adev->pm.dpm_enabled = false; 1532 1533 ret = smu_smc_hw_cleanup(smu); 1534 if (ret) 1535 return ret; 1536 1537 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1538 1539 smu_set_gfx_cgpg(&adev->smu, false); 1540 1541 return 0; 1542 } 1543 1544 static int smu_resume(void *handle) 1545 { 1546 int ret; 1547 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1548 struct smu_context *smu = &adev->smu; 1549 1550 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1551 return 0; 1552 1553 if (!smu->pm_enabled) 1554 return 0; 1555 1556 dev_info(adev->dev, "SMU is resuming...\n"); 1557 1558 ret = smu_start_smc_engine(smu); 1559 if (ret) { 1560 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1561 return ret; 1562 } 1563 1564 ret = smu_smc_hw_setup(smu); 1565 if (ret) { 1566 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1567 return ret; 1568 } 1569 1570 smu_set_gfx_cgpg(&adev->smu, true); 1571 1572 smu->disable_uclk_switch = 0; 1573 1574 adev->pm.dpm_enabled = true; 1575 1576 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1577 1578 return 0; 1579 } 1580 1581 static int smu_display_configuration_change(void *handle, 1582 const struct amd_pp_display_configuration *display_config) 1583 { 1584 struct smu_context *smu = handle; 1585 int index = 0; 1586 int num_of_active_display = 0; 1587 1588 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1589 return -EOPNOTSUPP; 1590 1591 if (!display_config) 1592 return -EINVAL; 1593 1594 mutex_lock(&smu->mutex); 1595 1596 smu_set_min_dcef_deep_sleep(smu, 1597 display_config->min_dcef_deep_sleep_set_clk / 100); 1598 1599 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1600 if (display_config->displays[index].controller_id != 0) 1601 num_of_active_display++; 1602 } 1603 1604 mutex_unlock(&smu->mutex); 1605 1606 return 0; 1607 } 1608 1609 static int smu_set_clockgating_state(void *handle, 1610 enum amd_clockgating_state state) 1611 { 1612 return 0; 1613 } 1614 1615 static int smu_set_powergating_state(void *handle, 1616 enum amd_powergating_state state) 1617 { 1618 return 0; 1619 } 1620 1621 static int smu_enable_umd_pstate(void *handle, 1622 enum amd_dpm_forced_level *level) 1623 { 1624 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1625 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1626 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1627 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1628 1629 struct smu_context *smu = (struct smu_context*)(handle); 1630 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1631 1632 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1633 return -EINVAL; 1634 1635 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1636 /* enter umd pstate, save current level, disable gfx cg*/ 1637 if (*level & profile_mode_mask) { 1638 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1639 smu_dpm_ctx->enable_umd_pstate = true; 1640 smu_gpo_control(smu, false); 1641 amdgpu_device_ip_set_powergating_state(smu->adev, 1642 AMD_IP_BLOCK_TYPE_GFX, 1643 AMD_PG_STATE_UNGATE); 1644 amdgpu_device_ip_set_clockgating_state(smu->adev, 1645 AMD_IP_BLOCK_TYPE_GFX, 1646 AMD_CG_STATE_UNGATE); 1647 smu_gfx_ulv_control(smu, false); 1648 smu_deep_sleep_control(smu, false); 1649 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1650 } 1651 } else { 1652 /* exit umd pstate, restore level, enable gfx cg*/ 1653 if (!(*level & profile_mode_mask)) { 1654 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1655 *level = smu_dpm_ctx->saved_dpm_level; 1656 smu_dpm_ctx->enable_umd_pstate = false; 1657 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1658 smu_deep_sleep_control(smu, true); 1659 smu_gfx_ulv_control(smu, true); 1660 amdgpu_device_ip_set_clockgating_state(smu->adev, 1661 AMD_IP_BLOCK_TYPE_GFX, 1662 AMD_CG_STATE_GATE); 1663 amdgpu_device_ip_set_powergating_state(smu->adev, 1664 AMD_IP_BLOCK_TYPE_GFX, 1665 AMD_PG_STATE_GATE); 1666 smu_gpo_control(smu, true); 1667 } 1668 } 1669 1670 return 0; 1671 } 1672 1673 static int smu_bump_power_profile_mode(struct smu_context *smu, 1674 long *param, 1675 uint32_t param_size) 1676 { 1677 int ret = 0; 1678 1679 if (smu->ppt_funcs->set_power_profile_mode) 1680 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 1681 1682 return ret; 1683 } 1684 1685 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1686 enum amd_dpm_forced_level level, 1687 bool skip_display_settings) 1688 { 1689 int ret = 0; 1690 int index = 0; 1691 long workload; 1692 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1693 1694 if (!skip_display_settings) { 1695 ret = smu_display_config_changed(smu); 1696 if (ret) { 1697 dev_err(smu->adev->dev, "Failed to change display config!"); 1698 return ret; 1699 } 1700 } 1701 1702 ret = smu_apply_clocks_adjust_rules(smu); 1703 if (ret) { 1704 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1705 return ret; 1706 } 1707 1708 if (!skip_display_settings) { 1709 ret = smu_notify_smc_display_config(smu); 1710 if (ret) { 1711 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1712 return ret; 1713 } 1714 } 1715 1716 if (smu_dpm_ctx->dpm_level != level) { 1717 ret = smu_asic_set_performance_level(smu, level); 1718 if (ret) { 1719 dev_err(smu->adev->dev, "Failed to set performance level!"); 1720 return ret; 1721 } 1722 1723 /* update the saved copy */ 1724 smu_dpm_ctx->dpm_level = level; 1725 } 1726 1727 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1728 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1729 index = fls(smu->workload_mask); 1730 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1731 workload = smu->workload_setting[index]; 1732 1733 if (smu->power_profile_mode != workload) 1734 smu_bump_power_profile_mode(smu, &workload, 0); 1735 } 1736 1737 return ret; 1738 } 1739 1740 static int smu_handle_task(struct smu_context *smu, 1741 enum amd_dpm_forced_level level, 1742 enum amd_pp_task task_id, 1743 bool lock_needed) 1744 { 1745 int ret = 0; 1746 1747 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1748 return -EOPNOTSUPP; 1749 1750 if (lock_needed) 1751 mutex_lock(&smu->mutex); 1752 1753 switch (task_id) { 1754 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1755 ret = smu_pre_display_config_changed(smu); 1756 if (ret) 1757 goto out; 1758 ret = smu_adjust_power_state_dynamic(smu, level, false); 1759 break; 1760 case AMD_PP_TASK_COMPLETE_INIT: 1761 case AMD_PP_TASK_READJUST_POWER_STATE: 1762 ret = smu_adjust_power_state_dynamic(smu, level, true); 1763 break; 1764 default: 1765 break; 1766 } 1767 1768 out: 1769 if (lock_needed) 1770 mutex_unlock(&smu->mutex); 1771 1772 return ret; 1773 } 1774 1775 static int smu_handle_dpm_task(void *handle, 1776 enum amd_pp_task task_id, 1777 enum amd_pm_state_type *user_state) 1778 { 1779 struct smu_context *smu = handle; 1780 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1781 1782 return smu_handle_task(smu, smu_dpm->dpm_level, task_id, true); 1783 1784 } 1785 1786 static int smu_switch_power_profile(void *handle, 1787 enum PP_SMC_POWER_PROFILE type, 1788 bool en) 1789 { 1790 struct smu_context *smu = handle; 1791 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1792 long workload; 1793 uint32_t index; 1794 1795 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1796 return -EOPNOTSUPP; 1797 1798 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1799 return -EINVAL; 1800 1801 mutex_lock(&smu->mutex); 1802 1803 if (!en) { 1804 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1805 index = fls(smu->workload_mask); 1806 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1807 workload = smu->workload_setting[index]; 1808 } else { 1809 smu->workload_mask |= (1 << smu->workload_prority[type]); 1810 index = fls(smu->workload_mask); 1811 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1812 workload = smu->workload_setting[index]; 1813 } 1814 1815 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1816 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 1817 smu_bump_power_profile_mode(smu, &workload, 0); 1818 1819 mutex_unlock(&smu->mutex); 1820 1821 return 0; 1822 } 1823 1824 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 1825 { 1826 struct smu_context *smu = handle; 1827 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1828 enum amd_dpm_forced_level level; 1829 1830 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1831 return -EOPNOTSUPP; 1832 1833 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1834 return -EINVAL; 1835 1836 mutex_lock(&(smu->mutex)); 1837 level = smu_dpm_ctx->dpm_level; 1838 mutex_unlock(&(smu->mutex)); 1839 1840 return level; 1841 } 1842 1843 static int smu_force_performance_level(void *handle, 1844 enum amd_dpm_forced_level level) 1845 { 1846 struct smu_context *smu = handle; 1847 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1848 int ret = 0; 1849 1850 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1851 return -EOPNOTSUPP; 1852 1853 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1854 return -EINVAL; 1855 1856 mutex_lock(&smu->mutex); 1857 1858 ret = smu_enable_umd_pstate(smu, &level); 1859 if (ret) { 1860 mutex_unlock(&smu->mutex); 1861 return ret; 1862 } 1863 1864 ret = smu_handle_task(smu, level, 1865 AMD_PP_TASK_READJUST_POWER_STATE, 1866 false); 1867 1868 mutex_unlock(&smu->mutex); 1869 1870 /* reset user dpm clock state */ 1871 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1872 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 1873 smu->user_dpm_profile.clk_dependency = 0; 1874 } 1875 1876 return ret; 1877 } 1878 1879 static int smu_set_display_count(void *handle, uint32_t count) 1880 { 1881 struct smu_context *smu = handle; 1882 int ret = 0; 1883 1884 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1885 return -EOPNOTSUPP; 1886 1887 mutex_lock(&smu->mutex); 1888 ret = smu_init_display_count(smu, count); 1889 mutex_unlock(&smu->mutex); 1890 1891 return ret; 1892 } 1893 1894 static int smu_force_smuclk_levels(struct smu_context *smu, 1895 enum smu_clk_type clk_type, 1896 uint32_t mask) 1897 { 1898 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1899 int ret = 0; 1900 1901 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1902 return -EOPNOTSUPP; 1903 1904 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1905 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1906 return -EINVAL; 1907 } 1908 1909 mutex_lock(&smu->mutex); 1910 1911 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 1912 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1913 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 1914 smu->user_dpm_profile.clk_mask[clk_type] = mask; 1915 smu_set_user_clk_dependencies(smu, clk_type); 1916 } 1917 } 1918 1919 mutex_unlock(&smu->mutex); 1920 1921 return ret; 1922 } 1923 1924 static int smu_force_ppclk_levels(void *handle, 1925 enum pp_clock_type type, 1926 uint32_t mask) 1927 { 1928 struct smu_context *smu = handle; 1929 enum smu_clk_type clk_type; 1930 1931 switch (type) { 1932 case PP_SCLK: 1933 clk_type = SMU_SCLK; break; 1934 case PP_MCLK: 1935 clk_type = SMU_MCLK; break; 1936 case PP_PCIE: 1937 clk_type = SMU_PCIE; break; 1938 case PP_SOCCLK: 1939 clk_type = SMU_SOCCLK; break; 1940 case PP_FCLK: 1941 clk_type = SMU_FCLK; break; 1942 case PP_DCEFCLK: 1943 clk_type = SMU_DCEFCLK; break; 1944 case PP_VCLK: 1945 clk_type = SMU_VCLK; break; 1946 case PP_DCLK: 1947 clk_type = SMU_DCLK; break; 1948 case OD_SCLK: 1949 clk_type = SMU_OD_SCLK; break; 1950 case OD_MCLK: 1951 clk_type = SMU_OD_MCLK; break; 1952 case OD_VDDC_CURVE: 1953 clk_type = SMU_OD_VDDC_CURVE; break; 1954 case OD_RANGE: 1955 clk_type = SMU_OD_RANGE; break; 1956 default: 1957 return -EINVAL; 1958 } 1959 1960 return smu_force_smuclk_levels(smu, clk_type, mask); 1961 } 1962 1963 /* 1964 * On system suspending or resetting, the dpm_enabled 1965 * flag will be cleared. So that those SMU services which 1966 * are not supported will be gated. 1967 * However, the mp1 state setting should still be granted 1968 * even if the dpm_enabled cleared. 1969 */ 1970 static int smu_set_mp1_state(void *handle, 1971 enum pp_mp1_state mp1_state) 1972 { 1973 struct smu_context *smu = handle; 1974 int ret = 0; 1975 1976 if (!smu->pm_enabled) 1977 return -EOPNOTSUPP; 1978 1979 mutex_lock(&smu->mutex); 1980 1981 if (smu->ppt_funcs && 1982 smu->ppt_funcs->set_mp1_state) 1983 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 1984 1985 mutex_unlock(&smu->mutex); 1986 1987 return ret; 1988 } 1989 1990 static int smu_set_df_cstate(void *handle, 1991 enum pp_df_cstate state) 1992 { 1993 struct smu_context *smu = handle; 1994 int ret = 0; 1995 1996 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1997 return -EOPNOTSUPP; 1998 1999 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2000 return 0; 2001 2002 mutex_lock(&smu->mutex); 2003 2004 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2005 if (ret) 2006 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2007 2008 mutex_unlock(&smu->mutex); 2009 2010 return ret; 2011 } 2012 2013 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 2014 { 2015 int ret = 0; 2016 2017 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2018 return -EOPNOTSUPP; 2019 2020 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 2021 return 0; 2022 2023 mutex_lock(&smu->mutex); 2024 2025 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 2026 if (ret) 2027 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 2028 2029 mutex_unlock(&smu->mutex); 2030 2031 return ret; 2032 } 2033 2034 int smu_write_watermarks_table(struct smu_context *smu) 2035 { 2036 int ret = 0; 2037 2038 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2039 return -EOPNOTSUPP; 2040 2041 mutex_lock(&smu->mutex); 2042 2043 ret = smu_set_watermarks_table(smu, NULL); 2044 2045 mutex_unlock(&smu->mutex); 2046 2047 return ret; 2048 } 2049 2050 static int smu_set_watermarks_for_clock_ranges(void *handle, 2051 struct pp_smu_wm_range_sets *clock_ranges) 2052 { 2053 struct smu_context *smu = handle; 2054 int ret = 0; 2055 2056 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2057 return -EOPNOTSUPP; 2058 2059 if (smu->disable_watermark) 2060 return 0; 2061 2062 mutex_lock(&smu->mutex); 2063 2064 ret = smu_set_watermarks_table(smu, clock_ranges); 2065 2066 mutex_unlock(&smu->mutex); 2067 2068 return ret; 2069 } 2070 2071 int smu_set_ac_dc(struct smu_context *smu) 2072 { 2073 int ret = 0; 2074 2075 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2076 return -EOPNOTSUPP; 2077 2078 /* controlled by firmware */ 2079 if (smu->dc_controlled_by_gpio) 2080 return 0; 2081 2082 mutex_lock(&smu->mutex); 2083 ret = smu_set_power_source(smu, 2084 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2085 SMU_POWER_SOURCE_DC); 2086 if (ret) 2087 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2088 smu->adev->pm.ac_power ? "AC" : "DC"); 2089 mutex_unlock(&smu->mutex); 2090 2091 return ret; 2092 } 2093 2094 const struct amd_ip_funcs smu_ip_funcs = { 2095 .name = "smu", 2096 .early_init = smu_early_init, 2097 .late_init = smu_late_init, 2098 .sw_init = smu_sw_init, 2099 .sw_fini = smu_sw_fini, 2100 .hw_init = smu_hw_init, 2101 .hw_fini = smu_hw_fini, 2102 .suspend = smu_suspend, 2103 .resume = smu_resume, 2104 .is_idle = NULL, 2105 .check_soft_reset = NULL, 2106 .wait_for_idle = NULL, 2107 .soft_reset = NULL, 2108 .set_clockgating_state = smu_set_clockgating_state, 2109 .set_powergating_state = smu_set_powergating_state, 2110 .enable_umd_pstate = smu_enable_umd_pstate, 2111 }; 2112 2113 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 2114 { 2115 .type = AMD_IP_BLOCK_TYPE_SMC, 2116 .major = 11, 2117 .minor = 0, 2118 .rev = 0, 2119 .funcs = &smu_ip_funcs, 2120 }; 2121 2122 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 2123 { 2124 .type = AMD_IP_BLOCK_TYPE_SMC, 2125 .major = 12, 2126 .minor = 0, 2127 .rev = 0, 2128 .funcs = &smu_ip_funcs, 2129 }; 2130 2131 const struct amdgpu_ip_block_version smu_v13_0_ip_block = 2132 { 2133 .type = AMD_IP_BLOCK_TYPE_SMC, 2134 .major = 13, 2135 .minor = 0, 2136 .rev = 0, 2137 .funcs = &smu_ip_funcs, 2138 }; 2139 2140 static int smu_load_microcode(void *handle) 2141 { 2142 struct smu_context *smu = handle; 2143 struct amdgpu_device *adev = smu->adev; 2144 int ret = 0; 2145 2146 if (!smu->pm_enabled) 2147 return -EOPNOTSUPP; 2148 2149 /* This should be used for non PSP loading */ 2150 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2151 return 0; 2152 2153 if (smu->ppt_funcs->load_microcode) { 2154 ret = smu->ppt_funcs->load_microcode(smu); 2155 if (ret) { 2156 dev_err(adev->dev, "Load microcode failed\n"); 2157 return ret; 2158 } 2159 } 2160 2161 if (smu->ppt_funcs->check_fw_status) { 2162 ret = smu->ppt_funcs->check_fw_status(smu); 2163 if (ret) { 2164 dev_err(adev->dev, "SMC is not ready\n"); 2165 return ret; 2166 } 2167 } 2168 2169 return ret; 2170 } 2171 2172 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2173 { 2174 int ret = 0; 2175 2176 mutex_lock(&smu->mutex); 2177 2178 if (smu->ppt_funcs->set_gfx_cgpg) 2179 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2180 2181 mutex_unlock(&smu->mutex); 2182 2183 return ret; 2184 } 2185 2186 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2187 { 2188 struct smu_context *smu = handle; 2189 int ret = 0; 2190 2191 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2192 return -EOPNOTSUPP; 2193 2194 mutex_lock(&smu->mutex); 2195 2196 if (smu->ppt_funcs->set_fan_speed_rpm) { 2197 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2198 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2199 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2200 smu->user_dpm_profile.fan_speed_rpm = speed; 2201 2202 /* Override custom PWM setting as they cannot co-exist */ 2203 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2204 smu->user_dpm_profile.fan_speed_pwm = 0; 2205 } 2206 } 2207 2208 mutex_unlock(&smu->mutex); 2209 2210 return ret; 2211 } 2212 2213 /** 2214 * smu_get_power_limit - Request one of the SMU Power Limits 2215 * 2216 * @handle: pointer to smu context 2217 * @limit: requested limit is written back to this variable 2218 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2219 * @pp_power_type: &pp_power_type type of power 2220 * Return: 0 on success, <0 on error 2221 * 2222 */ 2223 int smu_get_power_limit(void *handle, 2224 uint32_t *limit, 2225 enum pp_power_limit_level pp_limit_level, 2226 enum pp_power_type pp_power_type) 2227 { 2228 struct smu_context *smu = handle; 2229 enum smu_ppt_limit_level limit_level; 2230 uint32_t limit_type; 2231 int ret = 0; 2232 2233 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2234 return -EOPNOTSUPP; 2235 2236 switch(pp_power_type) { 2237 case PP_PWR_TYPE_SUSTAINED: 2238 limit_type = SMU_DEFAULT_PPT_LIMIT; 2239 break; 2240 case PP_PWR_TYPE_FAST: 2241 limit_type = SMU_FAST_PPT_LIMIT; 2242 break; 2243 default: 2244 return -EOPNOTSUPP; 2245 break; 2246 } 2247 2248 switch(pp_limit_level){ 2249 case PP_PWR_LIMIT_CURRENT: 2250 limit_level = SMU_PPT_LIMIT_CURRENT; 2251 break; 2252 case PP_PWR_LIMIT_DEFAULT: 2253 limit_level = SMU_PPT_LIMIT_DEFAULT; 2254 break; 2255 case PP_PWR_LIMIT_MAX: 2256 limit_level = SMU_PPT_LIMIT_MAX; 2257 break; 2258 case PP_PWR_LIMIT_MIN: 2259 default: 2260 return -EOPNOTSUPP; 2261 break; 2262 } 2263 2264 mutex_lock(&smu->mutex); 2265 2266 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2267 if (smu->ppt_funcs->get_ppt_limit) 2268 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2269 } else { 2270 switch (limit_level) { 2271 case SMU_PPT_LIMIT_CURRENT: 2272 if ((smu->adev->asic_type == CHIP_ALDEBARAN) || 2273 (smu->adev->asic_type == CHIP_SIENNA_CICHLID) || 2274 (smu->adev->asic_type == CHIP_NAVY_FLOUNDER) || 2275 (smu->adev->asic_type == CHIP_DIMGREY_CAVEFISH) || 2276 (smu->adev->asic_type == CHIP_BEIGE_GOBY)) 2277 ret = smu_get_asic_power_limits(smu, 2278 &smu->current_power_limit, 2279 NULL, 2280 NULL); 2281 *limit = smu->current_power_limit; 2282 break; 2283 case SMU_PPT_LIMIT_DEFAULT: 2284 *limit = smu->default_power_limit; 2285 break; 2286 case SMU_PPT_LIMIT_MAX: 2287 *limit = smu->max_power_limit; 2288 break; 2289 default: 2290 break; 2291 } 2292 } 2293 2294 mutex_unlock(&smu->mutex); 2295 2296 return ret; 2297 } 2298 2299 static int smu_set_power_limit(void *handle, uint32_t limit) 2300 { 2301 struct smu_context *smu = handle; 2302 uint32_t limit_type = limit >> 24; 2303 int ret = 0; 2304 2305 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2306 return -EOPNOTSUPP; 2307 2308 mutex_lock(&smu->mutex); 2309 2310 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2311 if (smu->ppt_funcs->set_power_limit) { 2312 ret = smu->ppt_funcs->set_power_limit(smu, limit); 2313 goto out; 2314 } 2315 2316 if (limit > smu->max_power_limit) { 2317 dev_err(smu->adev->dev, 2318 "New power limit (%d) is over the max allowed %d\n", 2319 limit, smu->max_power_limit); 2320 ret = -EINVAL; 2321 goto out; 2322 } 2323 2324 if (!limit) 2325 limit = smu->current_power_limit; 2326 2327 if (smu->ppt_funcs->set_power_limit) { 2328 ret = smu->ppt_funcs->set_power_limit(smu, limit); 2329 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2330 smu->user_dpm_profile.power_limit = limit; 2331 } 2332 2333 out: 2334 mutex_unlock(&smu->mutex); 2335 2336 return ret; 2337 } 2338 2339 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2340 { 2341 int ret = 0; 2342 2343 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2344 return -EOPNOTSUPP; 2345 2346 mutex_lock(&smu->mutex); 2347 2348 if (smu->ppt_funcs->print_clk_levels) 2349 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2350 2351 mutex_unlock(&smu->mutex); 2352 2353 return ret; 2354 } 2355 2356 static int smu_print_ppclk_levels(void *handle, 2357 enum pp_clock_type type, 2358 char *buf) 2359 { 2360 struct smu_context *smu = handle; 2361 enum smu_clk_type clk_type; 2362 2363 switch (type) { 2364 case PP_SCLK: 2365 clk_type = SMU_SCLK; break; 2366 case PP_MCLK: 2367 clk_type = SMU_MCLK; break; 2368 case PP_PCIE: 2369 clk_type = SMU_PCIE; break; 2370 case PP_SOCCLK: 2371 clk_type = SMU_SOCCLK; break; 2372 case PP_FCLK: 2373 clk_type = SMU_FCLK; break; 2374 case PP_DCEFCLK: 2375 clk_type = SMU_DCEFCLK; break; 2376 case PP_VCLK: 2377 clk_type = SMU_VCLK; break; 2378 case PP_DCLK: 2379 clk_type = SMU_DCLK; break; 2380 case OD_SCLK: 2381 clk_type = SMU_OD_SCLK; break; 2382 case OD_MCLK: 2383 clk_type = SMU_OD_MCLK; break; 2384 case OD_VDDC_CURVE: 2385 clk_type = SMU_OD_VDDC_CURVE; break; 2386 case OD_RANGE: 2387 clk_type = SMU_OD_RANGE; break; 2388 case OD_VDDGFX_OFFSET: 2389 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2390 case OD_CCLK: 2391 clk_type = SMU_OD_CCLK; break; 2392 default: 2393 return -EINVAL; 2394 } 2395 2396 return smu_print_smuclk_levels(smu, clk_type, buf); 2397 } 2398 2399 static int smu_od_edit_dpm_table(void *handle, 2400 enum PP_OD_DPM_TABLE_COMMAND type, 2401 long *input, uint32_t size) 2402 { 2403 struct smu_context *smu = handle; 2404 int ret = 0; 2405 2406 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2407 return -EOPNOTSUPP; 2408 2409 mutex_lock(&smu->mutex); 2410 2411 if (smu->ppt_funcs->od_edit_dpm_table) { 2412 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2413 } 2414 2415 mutex_unlock(&smu->mutex); 2416 2417 return ret; 2418 } 2419 2420 static int smu_read_sensor(void *handle, 2421 int sensor, 2422 void *data, 2423 int *size_arg) 2424 { 2425 struct smu_context *smu = handle; 2426 struct smu_umd_pstate_table *pstate_table = 2427 &smu->pstate_table; 2428 int ret = 0; 2429 uint32_t *size, size_val; 2430 2431 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2432 return -EOPNOTSUPP; 2433 2434 if (!data || !size_arg) 2435 return -EINVAL; 2436 2437 size_val = *size_arg; 2438 size = &size_val; 2439 2440 mutex_lock(&smu->mutex); 2441 2442 if (smu->ppt_funcs->read_sensor) 2443 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2444 goto unlock; 2445 2446 switch (sensor) { 2447 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2448 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2449 *size = 4; 2450 break; 2451 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2452 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2453 *size = 4; 2454 break; 2455 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2456 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2); 2457 *size = 8; 2458 break; 2459 case AMDGPU_PP_SENSOR_UVD_POWER: 2460 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2461 *size = 4; 2462 break; 2463 case AMDGPU_PP_SENSOR_VCE_POWER: 2464 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2465 *size = 4; 2466 break; 2467 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2468 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2469 *size = 4; 2470 break; 2471 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2472 *(uint32_t *)data = 0; 2473 *size = 4; 2474 break; 2475 default: 2476 *size = 0; 2477 ret = -EOPNOTSUPP; 2478 break; 2479 } 2480 2481 unlock: 2482 mutex_unlock(&smu->mutex); 2483 2484 // assign uint32_t to int 2485 *size_arg = size_val; 2486 2487 return ret; 2488 } 2489 2490 static int smu_get_power_profile_mode(void *handle, char *buf) 2491 { 2492 struct smu_context *smu = handle; 2493 int ret = 0; 2494 2495 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2496 return -EOPNOTSUPP; 2497 2498 mutex_lock(&smu->mutex); 2499 2500 if (smu->ppt_funcs->get_power_profile_mode) 2501 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf); 2502 2503 mutex_unlock(&smu->mutex); 2504 2505 return ret; 2506 } 2507 2508 static int smu_set_power_profile_mode(void *handle, 2509 long *param, 2510 uint32_t param_size) 2511 { 2512 struct smu_context *smu = handle; 2513 int ret = 0; 2514 2515 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2516 return -EOPNOTSUPP; 2517 2518 mutex_lock(&smu->mutex); 2519 2520 smu_bump_power_profile_mode(smu, param, param_size); 2521 2522 mutex_unlock(&smu->mutex); 2523 2524 return ret; 2525 } 2526 2527 2528 static u32 smu_get_fan_control_mode(void *handle) 2529 { 2530 struct smu_context *smu = handle; 2531 u32 ret = 0; 2532 2533 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2534 return AMD_FAN_CTRL_NONE; 2535 2536 mutex_lock(&smu->mutex); 2537 2538 if (smu->ppt_funcs->get_fan_control_mode) 2539 ret = smu->ppt_funcs->get_fan_control_mode(smu); 2540 2541 mutex_unlock(&smu->mutex); 2542 2543 return ret; 2544 } 2545 2546 static int smu_set_fan_control_mode(struct smu_context *smu, int value) 2547 { 2548 int ret = 0; 2549 2550 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2551 return -EOPNOTSUPP; 2552 2553 mutex_lock(&smu->mutex); 2554 2555 if (smu->ppt_funcs->set_fan_control_mode) { 2556 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2557 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2558 smu->user_dpm_profile.fan_mode = value; 2559 } 2560 2561 mutex_unlock(&smu->mutex); 2562 2563 /* reset user dpm fan speed */ 2564 if (!ret && value != AMD_FAN_CTRL_MANUAL && 2565 !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2566 smu->user_dpm_profile.fan_speed_pwm = 0; 2567 smu->user_dpm_profile.fan_speed_rpm = 0; 2568 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 2569 } 2570 2571 return ret; 2572 } 2573 2574 static void smu_pp_set_fan_control_mode(void *handle, u32 value) 2575 { 2576 struct smu_context *smu = handle; 2577 2578 smu_set_fan_control_mode(smu, value); 2579 } 2580 2581 2582 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 2583 { 2584 struct smu_context *smu = handle; 2585 int ret = 0; 2586 2587 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2588 return -EOPNOTSUPP; 2589 2590 mutex_lock(&smu->mutex); 2591 2592 if (smu->ppt_funcs->get_fan_speed_pwm) 2593 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 2594 2595 mutex_unlock(&smu->mutex); 2596 2597 return ret; 2598 } 2599 2600 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 2601 { 2602 struct smu_context *smu = handle; 2603 int ret = 0; 2604 2605 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2606 return -EOPNOTSUPP; 2607 2608 mutex_lock(&smu->mutex); 2609 2610 if (smu->ppt_funcs->set_fan_speed_pwm) { 2611 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 2612 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2613 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 2614 smu->user_dpm_profile.fan_speed_pwm = speed; 2615 2616 /* Override custom RPM setting as they cannot co-exist */ 2617 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 2618 smu->user_dpm_profile.fan_speed_rpm = 0; 2619 } 2620 } 2621 2622 mutex_unlock(&smu->mutex); 2623 2624 return ret; 2625 } 2626 2627 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 2628 { 2629 struct smu_context *smu = handle; 2630 int ret = 0; 2631 2632 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2633 return -EOPNOTSUPP; 2634 2635 mutex_lock(&smu->mutex); 2636 2637 if (smu->ppt_funcs->get_fan_speed_rpm) 2638 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 2639 2640 mutex_unlock(&smu->mutex); 2641 2642 return ret; 2643 } 2644 2645 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 2646 { 2647 struct smu_context *smu = handle; 2648 int ret = 0; 2649 2650 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2651 return -EOPNOTSUPP; 2652 2653 mutex_lock(&smu->mutex); 2654 2655 ret = smu_set_min_dcef_deep_sleep(smu, clk); 2656 2657 mutex_unlock(&smu->mutex); 2658 2659 return ret; 2660 } 2661 2662 static int smu_get_clock_by_type_with_latency(void *handle, 2663 enum amd_pp_clock_type type, 2664 struct pp_clock_levels_with_latency *clocks) 2665 { 2666 struct smu_context *smu = handle; 2667 enum smu_clk_type clk_type; 2668 int ret = 0; 2669 2670 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2671 return -EOPNOTSUPP; 2672 2673 mutex_lock(&smu->mutex); 2674 2675 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 2676 switch (type) { 2677 case amd_pp_sys_clock: 2678 clk_type = SMU_GFXCLK; 2679 break; 2680 case amd_pp_mem_clock: 2681 clk_type = SMU_MCLK; 2682 break; 2683 case amd_pp_dcef_clock: 2684 clk_type = SMU_DCEFCLK; 2685 break; 2686 case amd_pp_disp_clock: 2687 clk_type = SMU_DISPCLK; 2688 break; 2689 default: 2690 dev_err(smu->adev->dev, "Invalid clock type!\n"); 2691 mutex_unlock(&smu->mutex); 2692 return -EINVAL; 2693 } 2694 2695 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2696 } 2697 2698 mutex_unlock(&smu->mutex); 2699 2700 return ret; 2701 } 2702 2703 static int smu_display_clock_voltage_request(void *handle, 2704 struct pp_display_clock_request *clock_req) 2705 { 2706 struct smu_context *smu = handle; 2707 int ret = 0; 2708 2709 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2710 return -EOPNOTSUPP; 2711 2712 mutex_lock(&smu->mutex); 2713 2714 if (smu->ppt_funcs->display_clock_voltage_request) 2715 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2716 2717 mutex_unlock(&smu->mutex); 2718 2719 return ret; 2720 } 2721 2722 2723 static int smu_display_disable_memory_clock_switch(void *handle, 2724 bool disable_memory_clock_switch) 2725 { 2726 struct smu_context *smu = handle; 2727 int ret = -EINVAL; 2728 2729 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2730 return -EOPNOTSUPP; 2731 2732 mutex_lock(&smu->mutex); 2733 2734 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2735 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2736 2737 mutex_unlock(&smu->mutex); 2738 2739 return ret; 2740 } 2741 2742 static int smu_set_xgmi_pstate(void *handle, 2743 uint32_t pstate) 2744 { 2745 struct smu_context *smu = handle; 2746 int ret = 0; 2747 2748 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2749 return -EOPNOTSUPP; 2750 2751 mutex_lock(&smu->mutex); 2752 2753 if (smu->ppt_funcs->set_xgmi_pstate) 2754 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2755 2756 mutex_unlock(&smu->mutex); 2757 2758 if(ret) 2759 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2760 2761 return ret; 2762 } 2763 2764 static int smu_get_baco_capability(void *handle, bool *cap) 2765 { 2766 struct smu_context *smu = handle; 2767 int ret = 0; 2768 2769 *cap = false; 2770 2771 if (!smu->pm_enabled) 2772 return 0; 2773 2774 mutex_lock(&smu->mutex); 2775 2776 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2777 *cap = smu->ppt_funcs->baco_is_support(smu); 2778 2779 mutex_unlock(&smu->mutex); 2780 2781 return ret; 2782 } 2783 2784 static int smu_baco_set_state(void *handle, int state) 2785 { 2786 struct smu_context *smu = handle; 2787 int ret = 0; 2788 2789 if (!smu->pm_enabled) 2790 return -EOPNOTSUPP; 2791 2792 if (state == 0) { 2793 mutex_lock(&smu->mutex); 2794 2795 if (smu->ppt_funcs->baco_exit) 2796 ret = smu->ppt_funcs->baco_exit(smu); 2797 2798 mutex_unlock(&smu->mutex); 2799 } else if (state == 1) { 2800 mutex_lock(&smu->mutex); 2801 2802 if (smu->ppt_funcs->baco_enter) 2803 ret = smu->ppt_funcs->baco_enter(smu); 2804 2805 mutex_unlock(&smu->mutex); 2806 2807 } else { 2808 return -EINVAL; 2809 } 2810 2811 if (ret) 2812 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 2813 (state)?"enter":"exit"); 2814 2815 return ret; 2816 } 2817 2818 bool smu_mode1_reset_is_support(struct smu_context *smu) 2819 { 2820 bool ret = false; 2821 2822 if (!smu->pm_enabled) 2823 return false; 2824 2825 mutex_lock(&smu->mutex); 2826 2827 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2828 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2829 2830 mutex_unlock(&smu->mutex); 2831 2832 return ret; 2833 } 2834 2835 bool smu_mode2_reset_is_support(struct smu_context *smu) 2836 { 2837 bool ret = false; 2838 2839 if (!smu->pm_enabled) 2840 return false; 2841 2842 mutex_lock(&smu->mutex); 2843 2844 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 2845 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 2846 2847 mutex_unlock(&smu->mutex); 2848 2849 return ret; 2850 } 2851 2852 int smu_mode1_reset(struct smu_context *smu) 2853 { 2854 int ret = 0; 2855 2856 if (!smu->pm_enabled) 2857 return -EOPNOTSUPP; 2858 2859 mutex_lock(&smu->mutex); 2860 2861 if (smu->ppt_funcs->mode1_reset) 2862 ret = smu->ppt_funcs->mode1_reset(smu); 2863 2864 mutex_unlock(&smu->mutex); 2865 2866 return ret; 2867 } 2868 2869 static int smu_mode2_reset(void *handle) 2870 { 2871 struct smu_context *smu = handle; 2872 int ret = 0; 2873 2874 if (!smu->pm_enabled) 2875 return -EOPNOTSUPP; 2876 2877 mutex_lock(&smu->mutex); 2878 2879 if (smu->ppt_funcs->mode2_reset) 2880 ret = smu->ppt_funcs->mode2_reset(smu); 2881 2882 mutex_unlock(&smu->mutex); 2883 2884 if (ret) 2885 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2886 2887 return ret; 2888 } 2889 2890 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 2891 struct pp_smu_nv_clock_table *max_clocks) 2892 { 2893 struct smu_context *smu = handle; 2894 int ret = 0; 2895 2896 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2897 return -EOPNOTSUPP; 2898 2899 mutex_lock(&smu->mutex); 2900 2901 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2902 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2903 2904 mutex_unlock(&smu->mutex); 2905 2906 return ret; 2907 } 2908 2909 static int smu_get_uclk_dpm_states(void *handle, 2910 unsigned int *clock_values_in_khz, 2911 unsigned int *num_states) 2912 { 2913 struct smu_context *smu = handle; 2914 int ret = 0; 2915 2916 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2917 return -EOPNOTSUPP; 2918 2919 mutex_lock(&smu->mutex); 2920 2921 if (smu->ppt_funcs->get_uclk_dpm_states) 2922 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2923 2924 mutex_unlock(&smu->mutex); 2925 2926 return ret; 2927 } 2928 2929 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 2930 { 2931 struct smu_context *smu = handle; 2932 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2933 2934 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2935 return -EOPNOTSUPP; 2936 2937 mutex_lock(&smu->mutex); 2938 2939 if (smu->ppt_funcs->get_current_power_state) 2940 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2941 2942 mutex_unlock(&smu->mutex); 2943 2944 return pm_state; 2945 } 2946 2947 static int smu_get_dpm_clock_table(void *handle, 2948 struct dpm_clocks *clock_table) 2949 { 2950 struct smu_context *smu = handle; 2951 int ret = 0; 2952 2953 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2954 return -EOPNOTSUPP; 2955 2956 mutex_lock(&smu->mutex); 2957 2958 if (smu->ppt_funcs->get_dpm_clock_table) 2959 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 2960 2961 mutex_unlock(&smu->mutex); 2962 2963 return ret; 2964 } 2965 2966 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 2967 { 2968 struct smu_context *smu = handle; 2969 ssize_t size; 2970 2971 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2972 return -EOPNOTSUPP; 2973 2974 if (!smu->ppt_funcs->get_gpu_metrics) 2975 return -EOPNOTSUPP; 2976 2977 mutex_lock(&smu->mutex); 2978 2979 size = smu->ppt_funcs->get_gpu_metrics(smu, table); 2980 2981 mutex_unlock(&smu->mutex); 2982 2983 return size; 2984 } 2985 2986 static int smu_enable_mgpu_fan_boost(void *handle) 2987 { 2988 struct smu_context *smu = handle; 2989 int ret = 0; 2990 2991 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2992 return -EOPNOTSUPP; 2993 2994 mutex_lock(&smu->mutex); 2995 2996 if (smu->ppt_funcs->enable_mgpu_fan_boost) 2997 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 2998 2999 mutex_unlock(&smu->mutex); 3000 3001 return ret; 3002 } 3003 3004 static int smu_gfx_state_change_set(void *handle, 3005 uint32_t state) 3006 { 3007 struct smu_context *smu = handle; 3008 int ret = 0; 3009 3010 mutex_lock(&smu->mutex); 3011 if (smu->ppt_funcs->gfx_state_change_set) 3012 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3013 mutex_unlock(&smu->mutex); 3014 3015 return ret; 3016 } 3017 3018 int smu_set_light_sbr(struct smu_context *smu, bool enable) 3019 { 3020 int ret = 0; 3021 3022 mutex_lock(&smu->mutex); 3023 if (smu->ppt_funcs->set_light_sbr) 3024 ret = smu->ppt_funcs->set_light_sbr(smu, enable); 3025 mutex_unlock(&smu->mutex); 3026 3027 return ret; 3028 } 3029 3030 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3031 { 3032 struct smu_context *smu = handle; 3033 struct smu_table_context *smu_table = &smu->smu_table; 3034 struct smu_table *memory_pool = &smu_table->memory_pool; 3035 3036 if (!addr || !size) 3037 return -EINVAL; 3038 3039 *addr = NULL; 3040 *size = 0; 3041 mutex_lock(&smu->mutex); 3042 if (memory_pool->bo) { 3043 *addr = memory_pool->cpu_addr; 3044 *size = memory_pool->size; 3045 } 3046 mutex_unlock(&smu->mutex); 3047 3048 return 0; 3049 } 3050 3051 static const struct amd_pm_funcs swsmu_pm_funcs = { 3052 /* export for sysfs */ 3053 .set_fan_control_mode = smu_pp_set_fan_control_mode, 3054 .get_fan_control_mode = smu_get_fan_control_mode, 3055 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3056 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3057 .force_clock_level = smu_force_ppclk_levels, 3058 .print_clock_levels = smu_print_ppclk_levels, 3059 .force_performance_level = smu_force_performance_level, 3060 .read_sensor = smu_read_sensor, 3061 .get_performance_level = smu_get_performance_level, 3062 .get_current_power_state = smu_get_current_power_state, 3063 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3064 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3065 .get_pp_num_states = smu_get_power_num_states, 3066 .get_pp_table = smu_sys_get_pp_table, 3067 .set_pp_table = smu_sys_set_pp_table, 3068 .switch_power_profile = smu_switch_power_profile, 3069 /* export to amdgpu */ 3070 .dispatch_tasks = smu_handle_dpm_task, 3071 .load_firmware = smu_load_microcode, 3072 .set_powergating_by_smu = smu_dpm_set_power_gate, 3073 .set_power_limit = smu_set_power_limit, 3074 .get_power_limit = smu_get_power_limit, 3075 .get_power_profile_mode = smu_get_power_profile_mode, 3076 .set_power_profile_mode = smu_set_power_profile_mode, 3077 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3078 .set_mp1_state = smu_set_mp1_state, 3079 .gfx_state_change_set = smu_gfx_state_change_set, 3080 /* export to DC */ 3081 .get_sclk = smu_get_sclk, 3082 .get_mclk = smu_get_mclk, 3083 .display_configuration_change = smu_display_configuration_change, 3084 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3085 .display_clock_voltage_request = smu_display_clock_voltage_request, 3086 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3087 .set_active_display_count = smu_set_display_count, 3088 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3089 .get_asic_baco_capability = smu_get_baco_capability, 3090 .set_asic_baco_state = smu_baco_set_state, 3091 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3092 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3093 .asic_reset_mode_2 = smu_mode2_reset, 3094 .set_df_cstate = smu_set_df_cstate, 3095 .set_xgmi_pstate = smu_set_xgmi_pstate, 3096 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3097 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3098 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3099 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3100 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3101 .get_dpm_clock_table = smu_get_dpm_clock_table, 3102 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3103 }; 3104 3105 int smu_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event, 3106 uint64_t event_arg) 3107 { 3108 int ret = -EINVAL; 3109 struct smu_context *smu = &adev->smu; 3110 3111 if (smu->ppt_funcs->wait_for_event) { 3112 mutex_lock(&smu->mutex); 3113 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3114 mutex_unlock(&smu->mutex); 3115 } 3116 3117 return ret; 3118 } 3119