1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Rafał Miłecki <zajec5@gmail.com> 23 * Alex Deucher <alexdeucher@gmail.com> 24 */ 25 26 #include "amdgpu.h" 27 #include "amdgpu_drv.h" 28 #include "amdgpu_pm.h" 29 #include "amdgpu_dpm.h" 30 #include "atom.h" 31 #include <linux/pci.h> 32 #include <linux/hwmon.h> 33 #include <linux/hwmon-sysfs.h> 34 #include <linux/nospec.h> 35 #include <linux/pm_runtime.h> 36 #include <asm/processor.h> 37 38 static const struct hwmon_temp_label { 39 enum PP_HWMON_TEMP channel; 40 const char *label; 41 } temp_label[] = { 42 {PP_TEMP_EDGE, "edge"}, 43 {PP_TEMP_JUNCTION, "junction"}, 44 {PP_TEMP_MEM, "mem"}, 45 }; 46 47 const char * const amdgpu_pp_profile_name[] = { 48 "BOOTUP_DEFAULT", 49 "3D_FULL_SCREEN", 50 "POWER_SAVING", 51 "VIDEO", 52 "VR", 53 "COMPUTE", 54 "CUSTOM", 55 "WINDOW_3D", 56 "CAPPED", 57 "UNCAPPED", 58 }; 59 60 #ifdef __linux__ 61 62 /** 63 * DOC: power_dpm_state 64 * 65 * The power_dpm_state file is a legacy interface and is only provided for 66 * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting 67 * certain power related parameters. The file power_dpm_state is used for this. 68 * It accepts the following arguments: 69 * 70 * - battery 71 * 72 * - balanced 73 * 74 * - performance 75 * 76 * battery 77 * 78 * On older GPUs, the vbios provided a special power state for battery 79 * operation. Selecting battery switched to this state. This is no 80 * longer provided on newer GPUs so the option does nothing in that case. 81 * 82 * balanced 83 * 84 * On older GPUs, the vbios provided a special power state for balanced 85 * operation. Selecting balanced switched to this state. This is no 86 * longer provided on newer GPUs so the option does nothing in that case. 87 * 88 * performance 89 * 90 * On older GPUs, the vbios provided a special power state for performance 91 * operation. Selecting performance switched to this state. This is no 92 * longer provided on newer GPUs so the option does nothing in that case. 93 * 94 */ 95 96 static ssize_t amdgpu_get_power_dpm_state(struct device *dev, 97 struct device_attribute *attr, 98 char *buf) 99 { 100 struct drm_device *ddev = dev_get_drvdata(dev); 101 struct amdgpu_device *adev = drm_to_adev(ddev); 102 enum amd_pm_state_type pm; 103 int ret; 104 105 if (amdgpu_in_reset(adev)) 106 return -EPERM; 107 if (adev->in_suspend && !adev->in_runpm) 108 return -EPERM; 109 110 ret = pm_runtime_get_sync(ddev->dev); 111 if (ret < 0) { 112 pm_runtime_put_autosuspend(ddev->dev); 113 return ret; 114 } 115 116 amdgpu_dpm_get_current_power_state(adev, &pm); 117 118 pm_runtime_mark_last_busy(ddev->dev); 119 pm_runtime_put_autosuspend(ddev->dev); 120 121 return sysfs_emit(buf, "%s\n", 122 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : 123 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); 124 } 125 126 static ssize_t amdgpu_set_power_dpm_state(struct device *dev, 127 struct device_attribute *attr, 128 const char *buf, 129 size_t count) 130 { 131 struct drm_device *ddev = dev_get_drvdata(dev); 132 struct amdgpu_device *adev = drm_to_adev(ddev); 133 enum amd_pm_state_type state; 134 int ret; 135 136 if (amdgpu_in_reset(adev)) 137 return -EPERM; 138 if (adev->in_suspend && !adev->in_runpm) 139 return -EPERM; 140 141 if (strncmp("battery", buf, strlen("battery")) == 0) 142 state = POWER_STATE_TYPE_BATTERY; 143 else if (strncmp("balanced", buf, strlen("balanced")) == 0) 144 state = POWER_STATE_TYPE_BALANCED; 145 else if (strncmp("performance", buf, strlen("performance")) == 0) 146 state = POWER_STATE_TYPE_PERFORMANCE; 147 else 148 return -EINVAL; 149 150 ret = pm_runtime_get_sync(ddev->dev); 151 if (ret < 0) { 152 pm_runtime_put_autosuspend(ddev->dev); 153 return ret; 154 } 155 156 amdgpu_dpm_set_power_state(adev, state); 157 158 pm_runtime_mark_last_busy(ddev->dev); 159 pm_runtime_put_autosuspend(ddev->dev); 160 161 return count; 162 } 163 164 165 /** 166 * DOC: power_dpm_force_performance_level 167 * 168 * The amdgpu driver provides a sysfs API for adjusting certain power 169 * related parameters. The file power_dpm_force_performance_level is 170 * used for this. It accepts the following arguments: 171 * 172 * - auto 173 * 174 * - low 175 * 176 * - high 177 * 178 * - manual 179 * 180 * - profile_standard 181 * 182 * - profile_min_sclk 183 * 184 * - profile_min_mclk 185 * 186 * - profile_peak 187 * 188 * auto 189 * 190 * When auto is selected, the driver will attempt to dynamically select 191 * the optimal power profile for current conditions in the driver. 192 * 193 * low 194 * 195 * When low is selected, the clocks are forced to the lowest power state. 196 * 197 * high 198 * 199 * When high is selected, the clocks are forced to the highest power state. 200 * 201 * manual 202 * 203 * When manual is selected, the user can manually adjust which power states 204 * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk, 205 * and pp_dpm_pcie files and adjust the power state transition heuristics 206 * via the pp_power_profile_mode sysfs file. 207 * 208 * profile_standard 209 * profile_min_sclk 210 * profile_min_mclk 211 * profile_peak 212 * 213 * When the profiling modes are selected, clock and power gating are 214 * disabled and the clocks are set for different profiling cases. This 215 * mode is recommended for profiling specific work loads where you do 216 * not want clock or power gating for clock fluctuation to interfere 217 * with your results. profile_standard sets the clocks to a fixed clock 218 * level which varies from asic to asic. profile_min_sclk forces the sclk 219 * to the lowest level. profile_min_mclk forces the mclk to the lowest level. 220 * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels. 221 * 222 */ 223 224 static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev, 225 struct device_attribute *attr, 226 char *buf) 227 { 228 struct drm_device *ddev = dev_get_drvdata(dev); 229 struct amdgpu_device *adev = drm_to_adev(ddev); 230 enum amd_dpm_forced_level level = 0xff; 231 int ret; 232 233 if (amdgpu_in_reset(adev)) 234 return -EPERM; 235 if (adev->in_suspend && !adev->in_runpm) 236 return -EPERM; 237 238 ret = pm_runtime_get_sync(ddev->dev); 239 if (ret < 0) { 240 pm_runtime_put_autosuspend(ddev->dev); 241 return ret; 242 } 243 244 level = amdgpu_dpm_get_performance_level(adev); 245 246 pm_runtime_mark_last_busy(ddev->dev); 247 pm_runtime_put_autosuspend(ddev->dev); 248 249 return sysfs_emit(buf, "%s\n", 250 (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" : 251 (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" : 252 (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" : 253 (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" : 254 (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" : 255 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" : 256 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" : 257 (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" : 258 (level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" : 259 "unknown"); 260 } 261 262 static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev, 263 struct device_attribute *attr, 264 const char *buf, 265 size_t count) 266 { 267 struct drm_device *ddev = dev_get_drvdata(dev); 268 struct amdgpu_device *adev = drm_to_adev(ddev); 269 enum amd_dpm_forced_level level; 270 int ret = 0; 271 272 if (amdgpu_in_reset(adev)) 273 return -EPERM; 274 if (adev->in_suspend && !adev->in_runpm) 275 return -EPERM; 276 277 if (strncmp("low", buf, strlen("low")) == 0) { 278 level = AMD_DPM_FORCED_LEVEL_LOW; 279 } else if (strncmp("high", buf, strlen("high")) == 0) { 280 level = AMD_DPM_FORCED_LEVEL_HIGH; 281 } else if (strncmp("auto", buf, strlen("auto")) == 0) { 282 level = AMD_DPM_FORCED_LEVEL_AUTO; 283 } else if (strncmp("manual", buf, strlen("manual")) == 0) { 284 level = AMD_DPM_FORCED_LEVEL_MANUAL; 285 } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) { 286 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT; 287 } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) { 288 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD; 289 } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) { 290 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK; 291 } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) { 292 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK; 293 } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) { 294 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 295 } else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) { 296 level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM; 297 } else { 298 return -EINVAL; 299 } 300 301 ret = pm_runtime_get_sync(ddev->dev); 302 if (ret < 0) { 303 pm_runtime_put_autosuspend(ddev->dev); 304 return ret; 305 } 306 307 mutex_lock(&adev->pm.stable_pstate_ctx_lock); 308 if (amdgpu_dpm_force_performance_level(adev, level)) { 309 pm_runtime_mark_last_busy(ddev->dev); 310 pm_runtime_put_autosuspend(ddev->dev); 311 mutex_unlock(&adev->pm.stable_pstate_ctx_lock); 312 return -EINVAL; 313 } 314 /* override whatever a user ctx may have set */ 315 adev->pm.stable_pstate_ctx = NULL; 316 mutex_unlock(&adev->pm.stable_pstate_ctx_lock); 317 318 pm_runtime_mark_last_busy(ddev->dev); 319 pm_runtime_put_autosuspend(ddev->dev); 320 321 return count; 322 } 323 324 static ssize_t amdgpu_get_pp_num_states(struct device *dev, 325 struct device_attribute *attr, 326 char *buf) 327 { 328 struct drm_device *ddev = dev_get_drvdata(dev); 329 struct amdgpu_device *adev = drm_to_adev(ddev); 330 struct pp_states_info data; 331 uint32_t i; 332 int buf_len, ret; 333 334 if (amdgpu_in_reset(adev)) 335 return -EPERM; 336 if (adev->in_suspend && !adev->in_runpm) 337 return -EPERM; 338 339 ret = pm_runtime_get_sync(ddev->dev); 340 if (ret < 0) { 341 pm_runtime_put_autosuspend(ddev->dev); 342 return ret; 343 } 344 345 if (amdgpu_dpm_get_pp_num_states(adev, &data)) 346 memset(&data, 0, sizeof(data)); 347 348 pm_runtime_mark_last_busy(ddev->dev); 349 pm_runtime_put_autosuspend(ddev->dev); 350 351 buf_len = sysfs_emit(buf, "states: %d\n", data.nums); 352 for (i = 0; i < data.nums; i++) 353 buf_len += sysfs_emit_at(buf, buf_len, "%d %s\n", i, 354 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" : 355 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" : 356 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" : 357 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default"); 358 359 return buf_len; 360 } 361 362 static ssize_t amdgpu_get_pp_cur_state(struct device *dev, 363 struct device_attribute *attr, 364 char *buf) 365 { 366 struct drm_device *ddev = dev_get_drvdata(dev); 367 struct amdgpu_device *adev = drm_to_adev(ddev); 368 struct pp_states_info data = {0}; 369 enum amd_pm_state_type pm = 0; 370 int i = 0, ret = 0; 371 372 if (amdgpu_in_reset(adev)) 373 return -EPERM; 374 if (adev->in_suspend && !adev->in_runpm) 375 return -EPERM; 376 377 ret = pm_runtime_get_sync(ddev->dev); 378 if (ret < 0) { 379 pm_runtime_put_autosuspend(ddev->dev); 380 return ret; 381 } 382 383 amdgpu_dpm_get_current_power_state(adev, &pm); 384 385 ret = amdgpu_dpm_get_pp_num_states(adev, &data); 386 387 pm_runtime_mark_last_busy(ddev->dev); 388 pm_runtime_put_autosuspend(ddev->dev); 389 390 if (ret) 391 return ret; 392 393 for (i = 0; i < data.nums; i++) { 394 if (pm == data.states[i]) 395 break; 396 } 397 398 if (i == data.nums) 399 i = -EINVAL; 400 401 return sysfs_emit(buf, "%d\n", i); 402 } 403 404 static ssize_t amdgpu_get_pp_force_state(struct device *dev, 405 struct device_attribute *attr, 406 char *buf) 407 { 408 struct drm_device *ddev = dev_get_drvdata(dev); 409 struct amdgpu_device *adev = drm_to_adev(ddev); 410 411 if (amdgpu_in_reset(adev)) 412 return -EPERM; 413 if (adev->in_suspend && !adev->in_runpm) 414 return -EPERM; 415 416 if (adev->pm.pp_force_state_enabled) 417 return amdgpu_get_pp_cur_state(dev, attr, buf); 418 else 419 return sysfs_emit(buf, "\n"); 420 } 421 422 static ssize_t amdgpu_set_pp_force_state(struct device *dev, 423 struct device_attribute *attr, 424 const char *buf, 425 size_t count) 426 { 427 struct drm_device *ddev = dev_get_drvdata(dev); 428 struct amdgpu_device *adev = drm_to_adev(ddev); 429 enum amd_pm_state_type state = 0; 430 struct pp_states_info data; 431 unsigned long idx; 432 int ret; 433 434 if (amdgpu_in_reset(adev)) 435 return -EPERM; 436 if (adev->in_suspend && !adev->in_runpm) 437 return -EPERM; 438 439 adev->pm.pp_force_state_enabled = false; 440 441 if (strlen(buf) == 1) 442 return count; 443 444 ret = kstrtoul(buf, 0, &idx); 445 if (ret || idx >= ARRAY_SIZE(data.states)) 446 return -EINVAL; 447 448 idx = array_index_nospec(idx, ARRAY_SIZE(data.states)); 449 450 ret = pm_runtime_get_sync(ddev->dev); 451 if (ret < 0) { 452 pm_runtime_put_autosuspend(ddev->dev); 453 return ret; 454 } 455 456 ret = amdgpu_dpm_get_pp_num_states(adev, &data); 457 if (ret) 458 goto err_out; 459 460 state = data.states[idx]; 461 462 /* only set user selected power states */ 463 if (state != POWER_STATE_TYPE_INTERNAL_BOOT && 464 state != POWER_STATE_TYPE_DEFAULT) { 465 ret = amdgpu_dpm_dispatch_task(adev, 466 AMD_PP_TASK_ENABLE_USER_STATE, &state); 467 if (ret) 468 goto err_out; 469 470 adev->pm.pp_force_state_enabled = true; 471 } 472 473 pm_runtime_mark_last_busy(ddev->dev); 474 pm_runtime_put_autosuspend(ddev->dev); 475 476 return count; 477 478 err_out: 479 pm_runtime_mark_last_busy(ddev->dev); 480 pm_runtime_put_autosuspend(ddev->dev); 481 return ret; 482 } 483 484 /** 485 * DOC: pp_table 486 * 487 * The amdgpu driver provides a sysfs API for uploading new powerplay 488 * tables. The file pp_table is used for this. Reading the file 489 * will dump the current power play table. Writing to the file 490 * will attempt to upload a new powerplay table and re-initialize 491 * powerplay using that new table. 492 * 493 */ 494 495 static ssize_t amdgpu_get_pp_table(struct device *dev, 496 struct device_attribute *attr, 497 char *buf) 498 { 499 struct drm_device *ddev = dev_get_drvdata(dev); 500 struct amdgpu_device *adev = drm_to_adev(ddev); 501 char *table = NULL; 502 int size, ret; 503 504 if (amdgpu_in_reset(adev)) 505 return -EPERM; 506 if (adev->in_suspend && !adev->in_runpm) 507 return -EPERM; 508 509 ret = pm_runtime_get_sync(ddev->dev); 510 if (ret < 0) { 511 pm_runtime_put_autosuspend(ddev->dev); 512 return ret; 513 } 514 515 size = amdgpu_dpm_get_pp_table(adev, &table); 516 517 pm_runtime_mark_last_busy(ddev->dev); 518 pm_runtime_put_autosuspend(ddev->dev); 519 520 if (size <= 0) 521 return size; 522 523 if (size >= PAGE_SIZE) 524 size = PAGE_SIZE - 1; 525 526 memcpy(buf, table, size); 527 528 return size; 529 } 530 531 static ssize_t amdgpu_set_pp_table(struct device *dev, 532 struct device_attribute *attr, 533 const char *buf, 534 size_t count) 535 { 536 struct drm_device *ddev = dev_get_drvdata(dev); 537 struct amdgpu_device *adev = drm_to_adev(ddev); 538 int ret = 0; 539 540 if (amdgpu_in_reset(adev)) 541 return -EPERM; 542 if (adev->in_suspend && !adev->in_runpm) 543 return -EPERM; 544 545 ret = pm_runtime_get_sync(ddev->dev); 546 if (ret < 0) { 547 pm_runtime_put_autosuspend(ddev->dev); 548 return ret; 549 } 550 551 ret = amdgpu_dpm_set_pp_table(adev, buf, count); 552 553 pm_runtime_mark_last_busy(ddev->dev); 554 pm_runtime_put_autosuspend(ddev->dev); 555 556 if (ret) 557 return ret; 558 559 return count; 560 } 561 562 /** 563 * DOC: pp_od_clk_voltage 564 * 565 * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages 566 * in each power level within a power state. The pp_od_clk_voltage is used for 567 * this. 568 * 569 * Note that the actual memory controller clock rate are exposed, not 570 * the effective memory clock of the DRAMs. To translate it, use the 571 * following formula: 572 * 573 * Clock conversion (Mhz): 574 * 575 * HBM: effective_memory_clock = memory_controller_clock * 1 576 * 577 * G5: effective_memory_clock = memory_controller_clock * 1 578 * 579 * G6: effective_memory_clock = memory_controller_clock * 2 580 * 581 * DRAM data rate (MT/s): 582 * 583 * HBM: effective_memory_clock * 2 = data_rate 584 * 585 * G5: effective_memory_clock * 4 = data_rate 586 * 587 * G6: effective_memory_clock * 8 = data_rate 588 * 589 * Bandwidth (MB/s): 590 * 591 * data_rate * vram_bit_width / 8 = memory_bandwidth 592 * 593 * Some examples: 594 * 595 * G5 on RX460: 596 * 597 * memory_controller_clock = 1750 Mhz 598 * 599 * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz 600 * 601 * data rate = 1750 * 4 = 7000 MT/s 602 * 603 * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s 604 * 605 * G6 on RX5700: 606 * 607 * memory_controller_clock = 875 Mhz 608 * 609 * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz 610 * 611 * data rate = 1750 * 8 = 14000 MT/s 612 * 613 * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s 614 * 615 * < For Vega10 and previous ASICs > 616 * 617 * Reading the file will display: 618 * 619 * - a list of engine clock levels and voltages labeled OD_SCLK 620 * 621 * - a list of memory clock levels and voltages labeled OD_MCLK 622 * 623 * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE 624 * 625 * To manually adjust these settings, first select manual using 626 * power_dpm_force_performance_level. Enter a new value for each 627 * level by writing a string that contains "s/m level clock voltage" to 628 * the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz 629 * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at 630 * 810 mV. When you have edited all of the states as needed, write 631 * "c" (commit) to the file to commit your changes. If you want to reset to the 632 * default power levels, write "r" (reset) to the file to reset them. 633 * 634 * 635 * < For Vega20 and newer ASICs > 636 * 637 * Reading the file will display: 638 * 639 * - minimum and maximum engine clock labeled OD_SCLK 640 * 641 * - minimum(not available for Vega20 and Navi1x) and maximum memory 642 * clock labeled OD_MCLK 643 * 644 * - three <frequency, voltage> points labeled OD_VDDC_CURVE. 645 * They can be used to calibrate the sclk voltage curve. This is 646 * available for Vega20 and NV1X. 647 * 648 * - voltage offset for the six anchor points of the v/f curve labeled 649 * OD_VDDC_CURVE. They can be used to calibrate the v/f curve. This 650 * is only availabe for some SMU13 ASICs. 651 * 652 * - voltage offset(in mV) applied on target voltage calculation. 653 * This is available for Sienna Cichlid, Navy Flounder and Dimgrey 654 * Cavefish. For these ASICs, the target voltage calculation can be 655 * illustrated by "voltage = voltage calculated from v/f curve + 656 * overdrive vddgfx offset" 657 * 658 * - a list of valid ranges for sclk, mclk, and voltage curve points 659 * labeled OD_RANGE 660 * 661 * < For APUs > 662 * 663 * Reading the file will display: 664 * 665 * - minimum and maximum engine clock labeled OD_SCLK 666 * 667 * - a list of valid ranges for sclk labeled OD_RANGE 668 * 669 * < For VanGogh > 670 * 671 * Reading the file will display: 672 * 673 * - minimum and maximum engine clock labeled OD_SCLK 674 * - minimum and maximum core clocks labeled OD_CCLK 675 * 676 * - a list of valid ranges for sclk and cclk labeled OD_RANGE 677 * 678 * To manually adjust these settings: 679 * 680 * - First select manual using power_dpm_force_performance_level 681 * 682 * - For clock frequency setting, enter a new value by writing a 683 * string that contains "s/m index clock" to the file. The index 684 * should be 0 if to set minimum clock. And 1 if to set maximum 685 * clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz. 686 * "m 1 800" will update maximum mclk to be 800Mhz. For core 687 * clocks on VanGogh, the string contains "p core index clock". 688 * E.g., "p 2 0 800" would set the minimum core clock on core 689 * 2 to 800Mhz. 690 * 691 * For sclk voltage curve, 692 * - For NV1X, enter the new values by writing a string that 693 * contains "vc point clock voltage" to the file. The points 694 * are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will update 695 * point1 with clock set as 300Mhz and voltage as 600mV. "vc 2 696 * 1000 1000" will update point3 with clock set as 1000Mhz and 697 * voltage 1000mV. 698 * - For SMU13 ASICs, enter the new values by writing a string that 699 * contains "vc anchor_point_index voltage_offset" to the file. 700 * There are total six anchor points defined on the v/f curve with 701 * index as 0 - 5. 702 * - "vc 0 10" will update the voltage offset for point1 as 10mv. 703 * - "vc 5 -10" will update the voltage offset for point6 as -10mv. 704 * 705 * To update the voltage offset applied for gfxclk/voltage calculation, 706 * enter the new value by writing a string that contains "vo offset". 707 * This is supported by Sienna Cichlid, Navy Flounder and Dimgrey Cavefish. 708 * And the offset can be a positive or negative value. 709 * 710 * - When you have edited all of the states as needed, write "c" (commit) 711 * to the file to commit your changes 712 * 713 * - If you want to reset to the default power levels, write "r" (reset) 714 * to the file to reset them 715 * 716 */ 717 718 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev, 719 struct device_attribute *attr, 720 const char *buf, 721 size_t count) 722 { 723 struct drm_device *ddev = dev_get_drvdata(dev); 724 struct amdgpu_device *adev = drm_to_adev(ddev); 725 int ret; 726 uint32_t parameter_size = 0; 727 long parameter[64]; 728 char buf_cpy[128]; 729 char *tmp_str; 730 char *sub_str; 731 const char delimiter[3] = {' ', '\n', '\0'}; 732 uint32_t type; 733 734 if (amdgpu_in_reset(adev)) 735 return -EPERM; 736 if (adev->in_suspend && !adev->in_runpm) 737 return -EPERM; 738 739 if (count > 127 || count == 0) 740 return -EINVAL; 741 742 if (*buf == 's') 743 type = PP_OD_EDIT_SCLK_VDDC_TABLE; 744 else if (*buf == 'p') 745 type = PP_OD_EDIT_CCLK_VDDC_TABLE; 746 else if (*buf == 'm') 747 type = PP_OD_EDIT_MCLK_VDDC_TABLE; 748 else if (*buf == 'r') 749 type = PP_OD_RESTORE_DEFAULT_TABLE; 750 else if (*buf == 'c') 751 type = PP_OD_COMMIT_DPM_TABLE; 752 else if (!strncmp(buf, "vc", 2)) 753 type = PP_OD_EDIT_VDDC_CURVE; 754 else if (!strncmp(buf, "vo", 2)) 755 type = PP_OD_EDIT_VDDGFX_OFFSET; 756 else 757 return -EINVAL; 758 759 memcpy(buf_cpy, buf, count); 760 buf_cpy[count] = 0; 761 762 tmp_str = buf_cpy; 763 764 if ((type == PP_OD_EDIT_VDDC_CURVE) || 765 (type == PP_OD_EDIT_VDDGFX_OFFSET)) 766 tmp_str++; 767 while (isspace(*++tmp_str)); 768 769 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) { 770 if (strlen(sub_str) == 0) 771 continue; 772 ret = kstrtol(sub_str, 0, ¶meter[parameter_size]); 773 if (ret) 774 return -EINVAL; 775 parameter_size++; 776 777 if (!tmp_str) 778 break; 779 780 while (isspace(*tmp_str)) 781 tmp_str++; 782 } 783 784 ret = pm_runtime_get_sync(ddev->dev); 785 if (ret < 0) { 786 pm_runtime_put_autosuspend(ddev->dev); 787 return ret; 788 } 789 790 if (amdgpu_dpm_set_fine_grain_clk_vol(adev, 791 type, 792 parameter, 793 parameter_size)) 794 goto err_out; 795 796 if (amdgpu_dpm_odn_edit_dpm_table(adev, type, 797 parameter, parameter_size)) 798 goto err_out; 799 800 if (type == PP_OD_COMMIT_DPM_TABLE) { 801 if (amdgpu_dpm_dispatch_task(adev, 802 AMD_PP_TASK_READJUST_POWER_STATE, 803 NULL)) 804 goto err_out; 805 } 806 807 pm_runtime_mark_last_busy(ddev->dev); 808 pm_runtime_put_autosuspend(ddev->dev); 809 810 return count; 811 812 err_out: 813 pm_runtime_mark_last_busy(ddev->dev); 814 pm_runtime_put_autosuspend(ddev->dev); 815 return -EINVAL; 816 } 817 818 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev, 819 struct device_attribute *attr, 820 char *buf) 821 { 822 struct drm_device *ddev = dev_get_drvdata(dev); 823 struct amdgpu_device *adev = drm_to_adev(ddev); 824 int size = 0; 825 int ret; 826 enum pp_clock_type od_clocks[6] = { 827 OD_SCLK, 828 OD_MCLK, 829 OD_VDDC_CURVE, 830 OD_RANGE, 831 OD_VDDGFX_OFFSET, 832 OD_CCLK, 833 }; 834 uint clk_index; 835 836 if (amdgpu_in_reset(adev)) 837 return -EPERM; 838 if (adev->in_suspend && !adev->in_runpm) 839 return -EPERM; 840 841 ret = pm_runtime_get_sync(ddev->dev); 842 if (ret < 0) { 843 pm_runtime_put_autosuspend(ddev->dev); 844 return ret; 845 } 846 847 for (clk_index = 0 ; clk_index < 6 ; clk_index++) { 848 ret = amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size); 849 if (ret) 850 break; 851 } 852 if (ret == -ENOENT) { 853 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf); 854 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size); 855 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size); 856 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size); 857 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size); 858 size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size); 859 } 860 861 if (size == 0) 862 size = sysfs_emit(buf, "\n"); 863 864 pm_runtime_mark_last_busy(ddev->dev); 865 pm_runtime_put_autosuspend(ddev->dev); 866 867 return size; 868 } 869 870 /** 871 * DOC: pp_features 872 * 873 * The amdgpu driver provides a sysfs API for adjusting what powerplay 874 * features to be enabled. The file pp_features is used for this. And 875 * this is only available for Vega10 and later dGPUs. 876 * 877 * Reading back the file will show you the followings: 878 * - Current ppfeature masks 879 * - List of the all supported powerplay features with their naming, 880 * bitmasks and enablement status('Y'/'N' means "enabled"/"disabled"). 881 * 882 * To manually enable or disable a specific feature, just set or clear 883 * the corresponding bit from original ppfeature masks and input the 884 * new ppfeature masks. 885 */ 886 static ssize_t amdgpu_set_pp_features(struct device *dev, 887 struct device_attribute *attr, 888 const char *buf, 889 size_t count) 890 { 891 struct drm_device *ddev = dev_get_drvdata(dev); 892 struct amdgpu_device *adev = drm_to_adev(ddev); 893 uint64_t featuremask; 894 int ret; 895 896 if (amdgpu_in_reset(adev)) 897 return -EPERM; 898 if (adev->in_suspend && !adev->in_runpm) 899 return -EPERM; 900 901 ret = kstrtou64(buf, 0, &featuremask); 902 if (ret) 903 return -EINVAL; 904 905 ret = pm_runtime_get_sync(ddev->dev); 906 if (ret < 0) { 907 pm_runtime_put_autosuspend(ddev->dev); 908 return ret; 909 } 910 911 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask); 912 913 pm_runtime_mark_last_busy(ddev->dev); 914 pm_runtime_put_autosuspend(ddev->dev); 915 916 if (ret) 917 return -EINVAL; 918 919 return count; 920 } 921 922 static ssize_t amdgpu_get_pp_features(struct device *dev, 923 struct device_attribute *attr, 924 char *buf) 925 { 926 struct drm_device *ddev = dev_get_drvdata(dev); 927 struct amdgpu_device *adev = drm_to_adev(ddev); 928 ssize_t size; 929 int ret; 930 931 if (amdgpu_in_reset(adev)) 932 return -EPERM; 933 if (adev->in_suspend && !adev->in_runpm) 934 return -EPERM; 935 936 ret = pm_runtime_get_sync(ddev->dev); 937 if (ret < 0) { 938 pm_runtime_put_autosuspend(ddev->dev); 939 return ret; 940 } 941 942 size = amdgpu_dpm_get_ppfeature_status(adev, buf); 943 if (size <= 0) 944 size = sysfs_emit(buf, "\n"); 945 946 pm_runtime_mark_last_busy(ddev->dev); 947 pm_runtime_put_autosuspend(ddev->dev); 948 949 return size; 950 } 951 952 /** 953 * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie 954 * 955 * The amdgpu driver provides a sysfs API for adjusting what power levels 956 * are enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk, 957 * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for 958 * this. 959 * 960 * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for 961 * Vega10 and later ASICs. 962 * pp_dpm_fclk interface is only available for Vega20 and later ASICs. 963 * 964 * Reading back the files will show you the available power levels within 965 * the power state and the clock information for those levels. 966 * 967 * To manually adjust these states, first select manual using 968 * power_dpm_force_performance_level. 969 * Secondly, enter a new value for each level by inputing a string that 970 * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie" 971 * E.g., 972 * 973 * .. code-block:: bash 974 * 975 * echo "4 5 6" > pp_dpm_sclk 976 * 977 * will enable sclk levels 4, 5, and 6. 978 * 979 * NOTE: change to the dcefclk max dpm level is not supported now 980 */ 981 982 static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev, 983 enum pp_clock_type type, 984 char *buf) 985 { 986 struct drm_device *ddev = dev_get_drvdata(dev); 987 struct amdgpu_device *adev = drm_to_adev(ddev); 988 int size = 0; 989 int ret = 0; 990 991 if (amdgpu_in_reset(adev)) 992 return -EPERM; 993 if (adev->in_suspend && !adev->in_runpm) 994 return -EPERM; 995 996 ret = pm_runtime_get_sync(ddev->dev); 997 if (ret < 0) { 998 pm_runtime_put_autosuspend(ddev->dev); 999 return ret; 1000 } 1001 1002 ret = amdgpu_dpm_emit_clock_levels(adev, type, buf, &size); 1003 if (ret == -ENOENT) 1004 size = amdgpu_dpm_print_clock_levels(adev, type, buf); 1005 1006 if (size == 0) 1007 size = sysfs_emit(buf, "\n"); 1008 1009 pm_runtime_mark_last_busy(ddev->dev); 1010 pm_runtime_put_autosuspend(ddev->dev); 1011 1012 return size; 1013 } 1014 1015 /* 1016 * Worst case: 32 bits individually specified, in octal at 12 characters 1017 * per line (+1 for \n). 1018 */ 1019 #define AMDGPU_MASK_BUF_MAX (32 * 13) 1020 1021 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask) 1022 { 1023 int ret; 1024 unsigned long level; 1025 char *sub_str = NULL; 1026 char *tmp; 1027 char buf_cpy[AMDGPU_MASK_BUF_MAX + 1]; 1028 const char delimiter[3] = {' ', '\n', '\0'}; 1029 size_t bytes; 1030 1031 *mask = 0; 1032 1033 bytes = min(count, sizeof(buf_cpy) - 1); 1034 memcpy(buf_cpy, buf, bytes); 1035 buf_cpy[bytes] = '\0'; 1036 tmp = buf_cpy; 1037 while ((sub_str = strsep(&tmp, delimiter)) != NULL) { 1038 if (strlen(sub_str)) { 1039 ret = kstrtoul(sub_str, 0, &level); 1040 if (ret || level > 31) 1041 return -EINVAL; 1042 *mask |= 1 << level; 1043 } else 1044 break; 1045 } 1046 1047 return 0; 1048 } 1049 1050 static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev, 1051 enum pp_clock_type type, 1052 const char *buf, 1053 size_t count) 1054 { 1055 struct drm_device *ddev = dev_get_drvdata(dev); 1056 struct amdgpu_device *adev = drm_to_adev(ddev); 1057 int ret; 1058 uint32_t mask = 0; 1059 1060 if (amdgpu_in_reset(adev)) 1061 return -EPERM; 1062 if (adev->in_suspend && !adev->in_runpm) 1063 return -EPERM; 1064 1065 ret = amdgpu_read_mask(buf, count, &mask); 1066 if (ret) 1067 return ret; 1068 1069 ret = pm_runtime_get_sync(ddev->dev); 1070 if (ret < 0) { 1071 pm_runtime_put_autosuspend(ddev->dev); 1072 return ret; 1073 } 1074 1075 ret = amdgpu_dpm_force_clock_level(adev, type, mask); 1076 1077 pm_runtime_mark_last_busy(ddev->dev); 1078 pm_runtime_put_autosuspend(ddev->dev); 1079 1080 if (ret) 1081 return -EINVAL; 1082 1083 return count; 1084 } 1085 1086 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev, 1087 struct device_attribute *attr, 1088 char *buf) 1089 { 1090 return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf); 1091 } 1092 1093 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev, 1094 struct device_attribute *attr, 1095 const char *buf, 1096 size_t count) 1097 { 1098 return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count); 1099 } 1100 1101 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev, 1102 struct device_attribute *attr, 1103 char *buf) 1104 { 1105 return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf); 1106 } 1107 1108 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev, 1109 struct device_attribute *attr, 1110 const char *buf, 1111 size_t count) 1112 { 1113 return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count); 1114 } 1115 1116 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev, 1117 struct device_attribute *attr, 1118 char *buf) 1119 { 1120 return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf); 1121 } 1122 1123 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev, 1124 struct device_attribute *attr, 1125 const char *buf, 1126 size_t count) 1127 { 1128 return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count); 1129 } 1130 1131 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev, 1132 struct device_attribute *attr, 1133 char *buf) 1134 { 1135 return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf); 1136 } 1137 1138 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev, 1139 struct device_attribute *attr, 1140 const char *buf, 1141 size_t count) 1142 { 1143 return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count); 1144 } 1145 1146 static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev, 1147 struct device_attribute *attr, 1148 char *buf) 1149 { 1150 return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf); 1151 } 1152 1153 static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev, 1154 struct device_attribute *attr, 1155 const char *buf, 1156 size_t count) 1157 { 1158 return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count); 1159 } 1160 1161 static ssize_t amdgpu_get_pp_dpm_vclk1(struct device *dev, 1162 struct device_attribute *attr, 1163 char *buf) 1164 { 1165 return amdgpu_get_pp_dpm_clock(dev, PP_VCLK1, buf); 1166 } 1167 1168 static ssize_t amdgpu_set_pp_dpm_vclk1(struct device *dev, 1169 struct device_attribute *attr, 1170 const char *buf, 1171 size_t count) 1172 { 1173 return amdgpu_set_pp_dpm_clock(dev, PP_VCLK1, buf, count); 1174 } 1175 1176 static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev, 1177 struct device_attribute *attr, 1178 char *buf) 1179 { 1180 return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf); 1181 } 1182 1183 static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev, 1184 struct device_attribute *attr, 1185 const char *buf, 1186 size_t count) 1187 { 1188 return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count); 1189 } 1190 1191 static ssize_t amdgpu_get_pp_dpm_dclk1(struct device *dev, 1192 struct device_attribute *attr, 1193 char *buf) 1194 { 1195 return amdgpu_get_pp_dpm_clock(dev, PP_DCLK1, buf); 1196 } 1197 1198 static ssize_t amdgpu_set_pp_dpm_dclk1(struct device *dev, 1199 struct device_attribute *attr, 1200 const char *buf, 1201 size_t count) 1202 { 1203 return amdgpu_set_pp_dpm_clock(dev, PP_DCLK1, buf, count); 1204 } 1205 1206 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev, 1207 struct device_attribute *attr, 1208 char *buf) 1209 { 1210 return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf); 1211 } 1212 1213 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev, 1214 struct device_attribute *attr, 1215 const char *buf, 1216 size_t count) 1217 { 1218 return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count); 1219 } 1220 1221 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev, 1222 struct device_attribute *attr, 1223 char *buf) 1224 { 1225 return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf); 1226 } 1227 1228 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev, 1229 struct device_attribute *attr, 1230 const char *buf, 1231 size_t count) 1232 { 1233 return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count); 1234 } 1235 1236 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev, 1237 struct device_attribute *attr, 1238 char *buf) 1239 { 1240 struct drm_device *ddev = dev_get_drvdata(dev); 1241 struct amdgpu_device *adev = drm_to_adev(ddev); 1242 uint32_t value = 0; 1243 int ret; 1244 1245 if (amdgpu_in_reset(adev)) 1246 return -EPERM; 1247 if (adev->in_suspend && !adev->in_runpm) 1248 return -EPERM; 1249 1250 ret = pm_runtime_get_sync(ddev->dev); 1251 if (ret < 0) { 1252 pm_runtime_put_autosuspend(ddev->dev); 1253 return ret; 1254 } 1255 1256 value = amdgpu_dpm_get_sclk_od(adev); 1257 1258 pm_runtime_mark_last_busy(ddev->dev); 1259 pm_runtime_put_autosuspend(ddev->dev); 1260 1261 return sysfs_emit(buf, "%d\n", value); 1262 } 1263 1264 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev, 1265 struct device_attribute *attr, 1266 const char *buf, 1267 size_t count) 1268 { 1269 struct drm_device *ddev = dev_get_drvdata(dev); 1270 struct amdgpu_device *adev = drm_to_adev(ddev); 1271 int ret; 1272 long int value; 1273 1274 if (amdgpu_in_reset(adev)) 1275 return -EPERM; 1276 if (adev->in_suspend && !adev->in_runpm) 1277 return -EPERM; 1278 1279 ret = kstrtol(buf, 0, &value); 1280 1281 if (ret) 1282 return -EINVAL; 1283 1284 ret = pm_runtime_get_sync(ddev->dev); 1285 if (ret < 0) { 1286 pm_runtime_put_autosuspend(ddev->dev); 1287 return ret; 1288 } 1289 1290 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value); 1291 1292 pm_runtime_mark_last_busy(ddev->dev); 1293 pm_runtime_put_autosuspend(ddev->dev); 1294 1295 return count; 1296 } 1297 1298 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev, 1299 struct device_attribute *attr, 1300 char *buf) 1301 { 1302 struct drm_device *ddev = dev_get_drvdata(dev); 1303 struct amdgpu_device *adev = drm_to_adev(ddev); 1304 uint32_t value = 0; 1305 int ret; 1306 1307 if (amdgpu_in_reset(adev)) 1308 return -EPERM; 1309 if (adev->in_suspend && !adev->in_runpm) 1310 return -EPERM; 1311 1312 ret = pm_runtime_get_sync(ddev->dev); 1313 if (ret < 0) { 1314 pm_runtime_put_autosuspend(ddev->dev); 1315 return ret; 1316 } 1317 1318 value = amdgpu_dpm_get_mclk_od(adev); 1319 1320 pm_runtime_mark_last_busy(ddev->dev); 1321 pm_runtime_put_autosuspend(ddev->dev); 1322 1323 return sysfs_emit(buf, "%d\n", value); 1324 } 1325 1326 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev, 1327 struct device_attribute *attr, 1328 const char *buf, 1329 size_t count) 1330 { 1331 struct drm_device *ddev = dev_get_drvdata(dev); 1332 struct amdgpu_device *adev = drm_to_adev(ddev); 1333 int ret; 1334 long int value; 1335 1336 if (amdgpu_in_reset(adev)) 1337 return -EPERM; 1338 if (adev->in_suspend && !adev->in_runpm) 1339 return -EPERM; 1340 1341 ret = kstrtol(buf, 0, &value); 1342 1343 if (ret) 1344 return -EINVAL; 1345 1346 ret = pm_runtime_get_sync(ddev->dev); 1347 if (ret < 0) { 1348 pm_runtime_put_autosuspend(ddev->dev); 1349 return ret; 1350 } 1351 1352 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value); 1353 1354 pm_runtime_mark_last_busy(ddev->dev); 1355 pm_runtime_put_autosuspend(ddev->dev); 1356 1357 return count; 1358 } 1359 1360 /** 1361 * DOC: pp_power_profile_mode 1362 * 1363 * The amdgpu driver provides a sysfs API for adjusting the heuristics 1364 * related to switching between power levels in a power state. The file 1365 * pp_power_profile_mode is used for this. 1366 * 1367 * Reading this file outputs a list of all of the predefined power profiles 1368 * and the relevant heuristics settings for that profile. 1369 * 1370 * To select a profile or create a custom profile, first select manual using 1371 * power_dpm_force_performance_level. Writing the number of a predefined 1372 * profile to pp_power_profile_mode will enable those heuristics. To 1373 * create a custom set of heuristics, write a string of numbers to the file 1374 * starting with the number of the custom profile along with a setting 1375 * for each heuristic parameter. Due to differences across asic families 1376 * the heuristic parameters vary from family to family. 1377 * 1378 */ 1379 1380 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev, 1381 struct device_attribute *attr, 1382 char *buf) 1383 { 1384 struct drm_device *ddev = dev_get_drvdata(dev); 1385 struct amdgpu_device *adev = drm_to_adev(ddev); 1386 ssize_t size; 1387 int ret; 1388 1389 if (amdgpu_in_reset(adev)) 1390 return -EPERM; 1391 if (adev->in_suspend && !adev->in_runpm) 1392 return -EPERM; 1393 1394 ret = pm_runtime_get_sync(ddev->dev); 1395 if (ret < 0) { 1396 pm_runtime_put_autosuspend(ddev->dev); 1397 return ret; 1398 } 1399 1400 size = amdgpu_dpm_get_power_profile_mode(adev, buf); 1401 if (size <= 0) 1402 size = sysfs_emit(buf, "\n"); 1403 1404 pm_runtime_mark_last_busy(ddev->dev); 1405 pm_runtime_put_autosuspend(ddev->dev); 1406 1407 return size; 1408 } 1409 1410 1411 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev, 1412 struct device_attribute *attr, 1413 const char *buf, 1414 size_t count) 1415 { 1416 int ret; 1417 struct drm_device *ddev = dev_get_drvdata(dev); 1418 struct amdgpu_device *adev = drm_to_adev(ddev); 1419 uint32_t parameter_size = 0; 1420 long parameter[64]; 1421 char *sub_str, buf_cpy[128]; 1422 char *tmp_str; 1423 uint32_t i = 0; 1424 char tmp[2]; 1425 long int profile_mode = 0; 1426 const char delimiter[3] = {' ', '\n', '\0'}; 1427 1428 if (amdgpu_in_reset(adev)) 1429 return -EPERM; 1430 if (adev->in_suspend && !adev->in_runpm) 1431 return -EPERM; 1432 1433 tmp[0] = *(buf); 1434 tmp[1] = '\0'; 1435 ret = kstrtol(tmp, 0, &profile_mode); 1436 if (ret) 1437 return -EINVAL; 1438 1439 if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 1440 if (count < 2 || count > 127) 1441 return -EINVAL; 1442 while (isspace(*++buf)) 1443 i++; 1444 memcpy(buf_cpy, buf, count-i); 1445 tmp_str = buf_cpy; 1446 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) { 1447 if (strlen(sub_str) == 0) 1448 continue; 1449 ret = kstrtol(sub_str, 0, ¶meter[parameter_size]); 1450 if (ret) 1451 return -EINVAL; 1452 parameter_size++; 1453 while (isspace(*tmp_str)) 1454 tmp_str++; 1455 } 1456 } 1457 parameter[parameter_size] = profile_mode; 1458 1459 ret = pm_runtime_get_sync(ddev->dev); 1460 if (ret < 0) { 1461 pm_runtime_put_autosuspend(ddev->dev); 1462 return ret; 1463 } 1464 1465 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size); 1466 1467 pm_runtime_mark_last_busy(ddev->dev); 1468 pm_runtime_put_autosuspend(ddev->dev); 1469 1470 if (!ret) 1471 return count; 1472 1473 return -EINVAL; 1474 } 1475 1476 static unsigned int amdgpu_hwmon_get_sensor_generic(struct amdgpu_device *adev, 1477 enum amd_pp_sensors sensor, 1478 void *query) 1479 { 1480 int r, size = sizeof(uint32_t); 1481 1482 if (amdgpu_in_reset(adev)) 1483 return -EPERM; 1484 if (adev->in_suspend && !adev->in_runpm) 1485 return -EPERM; 1486 1487 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 1488 if (r < 0) { 1489 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1490 return r; 1491 } 1492 1493 /* get the sensor value */ 1494 r = amdgpu_dpm_read_sensor(adev, sensor, query, &size); 1495 1496 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 1497 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1498 1499 return r; 1500 } 1501 1502 /** 1503 * DOC: gpu_busy_percent 1504 * 1505 * The amdgpu driver provides a sysfs API for reading how busy the GPU 1506 * is as a percentage. The file gpu_busy_percent is used for this. 1507 * The SMU firmware computes a percentage of load based on the 1508 * aggregate activity level in the IP cores. 1509 */ 1510 static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev, 1511 struct device_attribute *attr, 1512 char *buf) 1513 { 1514 struct drm_device *ddev = dev_get_drvdata(dev); 1515 struct amdgpu_device *adev = drm_to_adev(ddev); 1516 unsigned int value; 1517 int r; 1518 1519 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_LOAD, &value); 1520 if (r) 1521 return r; 1522 1523 return sysfs_emit(buf, "%d\n", value); 1524 } 1525 1526 /** 1527 * DOC: mem_busy_percent 1528 * 1529 * The amdgpu driver provides a sysfs API for reading how busy the VRAM 1530 * is as a percentage. The file mem_busy_percent is used for this. 1531 * The SMU firmware computes a percentage of load based on the 1532 * aggregate activity level in the IP cores. 1533 */ 1534 static ssize_t amdgpu_get_mem_busy_percent(struct device *dev, 1535 struct device_attribute *attr, 1536 char *buf) 1537 { 1538 struct drm_device *ddev = dev_get_drvdata(dev); 1539 struct amdgpu_device *adev = drm_to_adev(ddev); 1540 unsigned int value; 1541 int r; 1542 1543 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_LOAD, &value); 1544 if (r) 1545 return r; 1546 1547 return sysfs_emit(buf, "%d\n", value); 1548 } 1549 1550 /** 1551 * DOC: pcie_bw 1552 * 1553 * The amdgpu driver provides a sysfs API for estimating how much data 1554 * has been received and sent by the GPU in the last second through PCIe. 1555 * The file pcie_bw is used for this. 1556 * The Perf counters count the number of received and sent messages and return 1557 * those values, as well as the maximum payload size of a PCIe packet (mps). 1558 * Note that it is not possible to easily and quickly obtain the size of each 1559 * packet transmitted, so we output the max payload size (mps) to allow for 1560 * quick estimation of the PCIe bandwidth usage 1561 */ 1562 static ssize_t amdgpu_get_pcie_bw(struct device *dev, 1563 struct device_attribute *attr, 1564 char *buf) 1565 { 1566 struct drm_device *ddev = dev_get_drvdata(dev); 1567 struct amdgpu_device *adev = drm_to_adev(ddev); 1568 uint64_t count0 = 0, count1 = 0; 1569 int ret; 1570 1571 if (amdgpu_in_reset(adev)) 1572 return -EPERM; 1573 if (adev->in_suspend && !adev->in_runpm) 1574 return -EPERM; 1575 1576 if (adev->flags & AMD_IS_APU) 1577 return -ENODATA; 1578 1579 if (!adev->asic_funcs->get_pcie_usage) 1580 return -ENODATA; 1581 1582 ret = pm_runtime_get_sync(ddev->dev); 1583 if (ret < 0) { 1584 pm_runtime_put_autosuspend(ddev->dev); 1585 return ret; 1586 } 1587 1588 amdgpu_asic_get_pcie_usage(adev, &count0, &count1); 1589 1590 pm_runtime_mark_last_busy(ddev->dev); 1591 pm_runtime_put_autosuspend(ddev->dev); 1592 1593 return sysfs_emit(buf, "%llu %llu %i\n", 1594 count0, count1, pcie_get_mps(adev->pdev)); 1595 } 1596 1597 /** 1598 * DOC: unique_id 1599 * 1600 * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU 1601 * The file unique_id is used for this. 1602 * This will provide a Unique ID that will persist from machine to machine 1603 * 1604 * NOTE: This will only work for GFX9 and newer. This file will be absent 1605 * on unsupported ASICs (GFX8 and older) 1606 */ 1607 static ssize_t amdgpu_get_unique_id(struct device *dev, 1608 struct device_attribute *attr, 1609 char *buf) 1610 { 1611 struct drm_device *ddev = dev_get_drvdata(dev); 1612 struct amdgpu_device *adev = drm_to_adev(ddev); 1613 1614 if (amdgpu_in_reset(adev)) 1615 return -EPERM; 1616 if (adev->in_suspend && !adev->in_runpm) 1617 return -EPERM; 1618 1619 if (adev->unique_id) 1620 return sysfs_emit(buf, "%016llx\n", adev->unique_id); 1621 1622 return 0; 1623 } 1624 1625 /** 1626 * DOC: thermal_throttling_logging 1627 * 1628 * Thermal throttling pulls down the clock frequency and thus the performance. 1629 * It's an useful mechanism to protect the chip from overheating. Since it 1630 * impacts performance, the user controls whether it is enabled and if so, 1631 * the log frequency. 1632 * 1633 * Reading back the file shows you the status(enabled or disabled) and 1634 * the interval(in seconds) between each thermal logging. 1635 * 1636 * Writing an integer to the file, sets a new logging interval, in seconds. 1637 * The value should be between 1 and 3600. If the value is less than 1, 1638 * thermal logging is disabled. Values greater than 3600 are ignored. 1639 */ 1640 static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev, 1641 struct device_attribute *attr, 1642 char *buf) 1643 { 1644 struct drm_device *ddev = dev_get_drvdata(dev); 1645 struct amdgpu_device *adev = drm_to_adev(ddev); 1646 1647 return sysfs_emit(buf, "%s: thermal throttling logging %s, with interval %d seconds\n", 1648 adev_to_drm(adev)->unique, 1649 atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled", 1650 adev->throttling_logging_rs.interval / HZ + 1); 1651 } 1652 1653 static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev, 1654 struct device_attribute *attr, 1655 const char *buf, 1656 size_t count) 1657 { 1658 struct drm_device *ddev = dev_get_drvdata(dev); 1659 struct amdgpu_device *adev = drm_to_adev(ddev); 1660 long throttling_logging_interval; 1661 unsigned long flags; 1662 int ret = 0; 1663 1664 ret = kstrtol(buf, 0, &throttling_logging_interval); 1665 if (ret) 1666 return ret; 1667 1668 if (throttling_logging_interval > 3600) 1669 return -EINVAL; 1670 1671 if (throttling_logging_interval > 0) { 1672 raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags); 1673 /* 1674 * Reset the ratelimit timer internals. 1675 * This can effectively restart the timer. 1676 */ 1677 adev->throttling_logging_rs.interval = 1678 (throttling_logging_interval - 1) * HZ; 1679 adev->throttling_logging_rs.begin = 0; 1680 adev->throttling_logging_rs.printed = 0; 1681 adev->throttling_logging_rs.missed = 0; 1682 raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags); 1683 1684 atomic_set(&adev->throttling_logging_enabled, 1); 1685 } else { 1686 atomic_set(&adev->throttling_logging_enabled, 0); 1687 } 1688 1689 return count; 1690 } 1691 1692 /** 1693 * DOC: apu_thermal_cap 1694 * 1695 * The amdgpu driver provides a sysfs API for retrieving/updating thermal 1696 * limit temperature in millidegrees Celsius 1697 * 1698 * Reading back the file shows you core limit value 1699 * 1700 * Writing an integer to the file, sets a new thermal limit. The value 1701 * should be between 0 and 100. If the value is less than 0 or greater 1702 * than 100, then the write request will be ignored. 1703 */ 1704 static ssize_t amdgpu_get_apu_thermal_cap(struct device *dev, 1705 struct device_attribute *attr, 1706 char *buf) 1707 { 1708 int ret, size; 1709 u32 limit; 1710 struct drm_device *ddev = dev_get_drvdata(dev); 1711 struct amdgpu_device *adev = drm_to_adev(ddev); 1712 1713 ret = pm_runtime_get_sync(ddev->dev); 1714 if (ret < 0) { 1715 pm_runtime_put_autosuspend(ddev->dev); 1716 return ret; 1717 } 1718 1719 ret = amdgpu_dpm_get_apu_thermal_limit(adev, &limit); 1720 if (!ret) 1721 size = sysfs_emit(buf, "%u\n", limit); 1722 else 1723 size = sysfs_emit(buf, "failed to get thermal limit\n"); 1724 1725 pm_runtime_mark_last_busy(ddev->dev); 1726 pm_runtime_put_autosuspend(ddev->dev); 1727 1728 return size; 1729 } 1730 1731 static ssize_t amdgpu_set_apu_thermal_cap(struct device *dev, 1732 struct device_attribute *attr, 1733 const char *buf, 1734 size_t count) 1735 { 1736 int ret; 1737 u32 value; 1738 struct drm_device *ddev = dev_get_drvdata(dev); 1739 struct amdgpu_device *adev = drm_to_adev(ddev); 1740 1741 ret = kstrtou32(buf, 10, &value); 1742 if (ret) 1743 return ret; 1744 1745 if (value > 100) { 1746 dev_err(dev, "Invalid argument !\n"); 1747 return -EINVAL; 1748 } 1749 1750 ret = pm_runtime_get_sync(ddev->dev); 1751 if (ret < 0) { 1752 pm_runtime_put_autosuspend(ddev->dev); 1753 return ret; 1754 } 1755 1756 ret = amdgpu_dpm_set_apu_thermal_limit(adev, value); 1757 if (ret) { 1758 dev_err(dev, "failed to update thermal limit\n"); 1759 return ret; 1760 } 1761 1762 pm_runtime_mark_last_busy(ddev->dev); 1763 pm_runtime_put_autosuspend(ddev->dev); 1764 1765 return count; 1766 } 1767 1768 /** 1769 * DOC: gpu_metrics 1770 * 1771 * The amdgpu driver provides a sysfs API for retrieving current gpu 1772 * metrics data. The file gpu_metrics is used for this. Reading the 1773 * file will dump all the current gpu metrics data. 1774 * 1775 * These data include temperature, frequency, engines utilization, 1776 * power consume, throttler status, fan speed and cpu core statistics( 1777 * available for APU only). That's it will give a snapshot of all sensors 1778 * at the same time. 1779 */ 1780 static ssize_t amdgpu_get_gpu_metrics(struct device *dev, 1781 struct device_attribute *attr, 1782 char *buf) 1783 { 1784 struct drm_device *ddev = dev_get_drvdata(dev); 1785 struct amdgpu_device *adev = drm_to_adev(ddev); 1786 void *gpu_metrics; 1787 ssize_t size = 0; 1788 int ret; 1789 1790 if (amdgpu_in_reset(adev)) 1791 return -EPERM; 1792 if (adev->in_suspend && !adev->in_runpm) 1793 return -EPERM; 1794 1795 ret = pm_runtime_get_sync(ddev->dev); 1796 if (ret < 0) { 1797 pm_runtime_put_autosuspend(ddev->dev); 1798 return ret; 1799 } 1800 1801 size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics); 1802 if (size <= 0) 1803 goto out; 1804 1805 if (size >= PAGE_SIZE) 1806 size = PAGE_SIZE - 1; 1807 1808 memcpy(buf, gpu_metrics, size); 1809 1810 out: 1811 pm_runtime_mark_last_busy(ddev->dev); 1812 pm_runtime_put_autosuspend(ddev->dev); 1813 1814 return size; 1815 } 1816 1817 static int amdgpu_show_powershift_percent(struct device *dev, 1818 char *buf, enum amd_pp_sensors sensor) 1819 { 1820 struct drm_device *ddev = dev_get_drvdata(dev); 1821 struct amdgpu_device *adev = drm_to_adev(ddev); 1822 uint32_t ss_power; 1823 int r = 0, i; 1824 1825 r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power); 1826 if (r == -EOPNOTSUPP) { 1827 /* sensor not available on dGPU, try to read from APU */ 1828 adev = NULL; 1829 mutex_lock(&mgpu_info.mutex); 1830 for (i = 0; i < mgpu_info.num_gpu; i++) { 1831 if (mgpu_info.gpu_ins[i].adev->flags & AMD_IS_APU) { 1832 adev = mgpu_info.gpu_ins[i].adev; 1833 break; 1834 } 1835 } 1836 mutex_unlock(&mgpu_info.mutex); 1837 if (adev) 1838 r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power); 1839 } 1840 1841 if (r) 1842 return r; 1843 1844 return sysfs_emit(buf, "%u%%\n", ss_power); 1845 } 1846 1847 /** 1848 * DOC: smartshift_apu_power 1849 * 1850 * The amdgpu driver provides a sysfs API for reporting APU power 1851 * shift in percentage if platform supports smartshift. Value 0 means that 1852 * there is no powershift and values between [1-100] means that the power 1853 * is shifted to APU, the percentage of boost is with respect to APU power 1854 * limit on the platform. 1855 */ 1856 1857 static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct device_attribute *attr, 1858 char *buf) 1859 { 1860 return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_APU_SHARE); 1861 } 1862 1863 /** 1864 * DOC: smartshift_dgpu_power 1865 * 1866 * The amdgpu driver provides a sysfs API for reporting dGPU power 1867 * shift in percentage if platform supports smartshift. Value 0 means that 1868 * there is no powershift and values between [1-100] means that the power is 1869 * shifted to dGPU, the percentage of boost is with respect to dGPU power 1870 * limit on the platform. 1871 */ 1872 1873 static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct device_attribute *attr, 1874 char *buf) 1875 { 1876 return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_DGPU_SHARE); 1877 } 1878 1879 /** 1880 * DOC: smartshift_bias 1881 * 1882 * The amdgpu driver provides a sysfs API for reporting the 1883 * smartshift(SS2.0) bias level. The value ranges from -100 to 100 1884 * and the default is 0. -100 sets maximum preference to APU 1885 * and 100 sets max perference to dGPU. 1886 */ 1887 1888 static ssize_t amdgpu_get_smartshift_bias(struct device *dev, 1889 struct device_attribute *attr, 1890 char *buf) 1891 { 1892 int r = 0; 1893 1894 r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias); 1895 1896 return r; 1897 } 1898 1899 static ssize_t amdgpu_set_smartshift_bias(struct device *dev, 1900 struct device_attribute *attr, 1901 const char *buf, size_t count) 1902 { 1903 struct drm_device *ddev = dev_get_drvdata(dev); 1904 struct amdgpu_device *adev = drm_to_adev(ddev); 1905 int r = 0; 1906 int bias = 0; 1907 1908 if (amdgpu_in_reset(adev)) 1909 return -EPERM; 1910 if (adev->in_suspend && !adev->in_runpm) 1911 return -EPERM; 1912 1913 r = pm_runtime_get_sync(ddev->dev); 1914 if (r < 0) { 1915 pm_runtime_put_autosuspend(ddev->dev); 1916 return r; 1917 } 1918 1919 r = kstrtoint(buf, 10, &bias); 1920 if (r) 1921 goto out; 1922 1923 if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS) 1924 bias = AMDGPU_SMARTSHIFT_MAX_BIAS; 1925 else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS) 1926 bias = AMDGPU_SMARTSHIFT_MIN_BIAS; 1927 1928 amdgpu_smartshift_bias = bias; 1929 r = count; 1930 1931 /* TODO: update bias level with SMU message */ 1932 1933 out: 1934 pm_runtime_mark_last_busy(ddev->dev); 1935 pm_runtime_put_autosuspend(ddev->dev); 1936 return r; 1937 } 1938 1939 static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 1940 uint32_t mask, enum amdgpu_device_attr_states *states) 1941 { 1942 if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev))) 1943 *states = ATTR_STATE_UNSUPPORTED; 1944 1945 return 0; 1946 } 1947 1948 static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 1949 uint32_t mask, enum amdgpu_device_attr_states *states) 1950 { 1951 uint32_t ss_power; 1952 1953 if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev))) 1954 *states = ATTR_STATE_UNSUPPORTED; 1955 else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE, 1956 (void *)&ss_power)) 1957 *states = ATTR_STATE_UNSUPPORTED; 1958 else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 1959 (void *)&ss_power)) 1960 *states = ATTR_STATE_UNSUPPORTED; 1961 1962 return 0; 1963 } 1964 1965 static struct amdgpu_device_attr amdgpu_device_attrs[] = { 1966 AMDGPU_DEVICE_ATTR_RW(power_dpm_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1967 AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1968 AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1969 AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1970 AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1971 AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1972 AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1973 AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1974 AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1975 AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1976 AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1977 AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk1, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1978 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1979 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk1, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1980 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1981 AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1982 AMDGPU_DEVICE_ATTR_RW(pp_sclk_od, ATTR_FLAG_BASIC), 1983 AMDGPU_DEVICE_ATTR_RW(pp_mclk_od, ATTR_FLAG_BASIC), 1984 AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1985 AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage, ATTR_FLAG_BASIC), 1986 AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1987 AMDGPU_DEVICE_ATTR_RO(mem_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1988 AMDGPU_DEVICE_ATTR_RO(pcie_bw, ATTR_FLAG_BASIC), 1989 AMDGPU_DEVICE_ATTR_RW(pp_features, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1990 AMDGPU_DEVICE_ATTR_RO(unique_id, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1991 AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1992 AMDGPU_DEVICE_ATTR_RW(apu_thermal_cap, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1993 AMDGPU_DEVICE_ATTR_RO(gpu_metrics, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1994 AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power, ATTR_FLAG_BASIC, 1995 .attr_update = ss_power_attr_update), 1996 AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power, ATTR_FLAG_BASIC, 1997 .attr_update = ss_power_attr_update), 1998 AMDGPU_DEVICE_ATTR_RW(smartshift_bias, ATTR_FLAG_BASIC, 1999 .attr_update = ss_bias_attr_update), 2000 }; 2001 2002 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2003 uint32_t mask, enum amdgpu_device_attr_states *states) 2004 { 2005 struct device_attribute *dev_attr = &attr->dev_attr; 2006 uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0]; 2007 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; 2008 const char *attr_name = dev_attr->attr.name; 2009 2010 if (!(attr->flags & mask)) { 2011 *states = ATTR_STATE_UNSUPPORTED; 2012 return 0; 2013 } 2014 2015 #define DEVICE_ATTR_IS(_name) (!strcmp(attr_name, #_name)) 2016 2017 if (DEVICE_ATTR_IS(pp_dpm_socclk)) { 2018 if (gc_ver < IP_VERSION(9, 0, 0)) 2019 *states = ATTR_STATE_UNSUPPORTED; 2020 } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) { 2021 if (gc_ver < IP_VERSION(9, 0, 0) || 2022 !amdgpu_device_has_display_hardware(adev)) 2023 *states = ATTR_STATE_UNSUPPORTED; 2024 } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) { 2025 if (mp1_ver < IP_VERSION(10, 0, 0)) 2026 *states = ATTR_STATE_UNSUPPORTED; 2027 } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) { 2028 *states = ATTR_STATE_UNSUPPORTED; 2029 if (amdgpu_dpm_is_overdrive_supported(adev)) 2030 *states = ATTR_STATE_SUPPORTED; 2031 } else if (DEVICE_ATTR_IS(mem_busy_percent)) { 2032 if (adev->flags & AMD_IS_APU || gc_ver == IP_VERSION(9, 0, 1)) 2033 *states = ATTR_STATE_UNSUPPORTED; 2034 } else if (DEVICE_ATTR_IS(pcie_bw)) { 2035 /* PCIe Perf counters won't work on APU nodes */ 2036 if (adev->flags & AMD_IS_APU) 2037 *states = ATTR_STATE_UNSUPPORTED; 2038 } else if (DEVICE_ATTR_IS(unique_id)) { 2039 switch (gc_ver) { 2040 case IP_VERSION(9, 0, 1): 2041 case IP_VERSION(9, 4, 0): 2042 case IP_VERSION(9, 4, 1): 2043 case IP_VERSION(9, 4, 2): 2044 case IP_VERSION(9, 4, 3): 2045 case IP_VERSION(10, 3, 0): 2046 case IP_VERSION(11, 0, 0): 2047 case IP_VERSION(11, 0, 1): 2048 case IP_VERSION(11, 0, 2): 2049 case IP_VERSION(11, 0, 3): 2050 *states = ATTR_STATE_SUPPORTED; 2051 break; 2052 default: 2053 *states = ATTR_STATE_UNSUPPORTED; 2054 } 2055 } else if (DEVICE_ATTR_IS(pp_features)) { 2056 if ((adev->flags & AMD_IS_APU && 2057 gc_ver != IP_VERSION(9, 4, 3)) || 2058 gc_ver < IP_VERSION(9, 0, 0)) 2059 *states = ATTR_STATE_UNSUPPORTED; 2060 } else if (DEVICE_ATTR_IS(gpu_metrics)) { 2061 if (gc_ver < IP_VERSION(9, 1, 0)) 2062 *states = ATTR_STATE_UNSUPPORTED; 2063 } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) { 2064 if (!(gc_ver == IP_VERSION(10, 3, 1) || 2065 gc_ver == IP_VERSION(10, 3, 0) || 2066 gc_ver == IP_VERSION(10, 1, 2) || 2067 gc_ver == IP_VERSION(11, 0, 0) || 2068 gc_ver == IP_VERSION(11, 0, 2) || 2069 gc_ver == IP_VERSION(11, 0, 3) || 2070 gc_ver == IP_VERSION(9, 4, 3))) 2071 *states = ATTR_STATE_UNSUPPORTED; 2072 } else if (DEVICE_ATTR_IS(pp_dpm_vclk1)) { 2073 if (!((gc_ver == IP_VERSION(10, 3, 1) || 2074 gc_ver == IP_VERSION(10, 3, 0) || 2075 gc_ver == IP_VERSION(11, 0, 2) || 2076 gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2)) 2077 *states = ATTR_STATE_UNSUPPORTED; 2078 } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) { 2079 if (!(gc_ver == IP_VERSION(10, 3, 1) || 2080 gc_ver == IP_VERSION(10, 3, 0) || 2081 gc_ver == IP_VERSION(10, 1, 2) || 2082 gc_ver == IP_VERSION(11, 0, 0) || 2083 gc_ver == IP_VERSION(11, 0, 2) || 2084 gc_ver == IP_VERSION(11, 0, 3) || 2085 gc_ver == IP_VERSION(9, 4, 3))) 2086 *states = ATTR_STATE_UNSUPPORTED; 2087 } else if (DEVICE_ATTR_IS(pp_dpm_dclk1)) { 2088 if (!((gc_ver == IP_VERSION(10, 3, 1) || 2089 gc_ver == IP_VERSION(10, 3, 0) || 2090 gc_ver == IP_VERSION(11, 0, 2) || 2091 gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2)) 2092 *states = ATTR_STATE_UNSUPPORTED; 2093 } else if (DEVICE_ATTR_IS(pp_power_profile_mode)) { 2094 if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == -EOPNOTSUPP) 2095 *states = ATTR_STATE_UNSUPPORTED; 2096 else if (gc_ver == IP_VERSION(10, 3, 0) && amdgpu_sriov_vf(adev)) 2097 *states = ATTR_STATE_UNSUPPORTED; 2098 } 2099 2100 switch (gc_ver) { 2101 case IP_VERSION(9, 4, 1): 2102 case IP_VERSION(9, 4, 2): 2103 /* the Mi series card does not support standalone mclk/socclk/fclk level setting */ 2104 if (DEVICE_ATTR_IS(pp_dpm_mclk) || 2105 DEVICE_ATTR_IS(pp_dpm_socclk) || 2106 DEVICE_ATTR_IS(pp_dpm_fclk)) { 2107 dev_attr->attr.mode &= ~S_IWUGO; 2108 dev_attr->store = NULL; 2109 } 2110 break; 2111 case IP_VERSION(10, 3, 0): 2112 if (DEVICE_ATTR_IS(power_dpm_force_performance_level) && 2113 amdgpu_sriov_vf(adev)) { 2114 dev_attr->attr.mode &= ~0222; 2115 dev_attr->store = NULL; 2116 } 2117 break; 2118 default: 2119 break; 2120 } 2121 2122 if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) { 2123 /* SMU MP1 does not support dcefclk level setting */ 2124 if (gc_ver >= IP_VERSION(10, 0, 0)) { 2125 dev_attr->attr.mode &= ~S_IWUGO; 2126 dev_attr->store = NULL; 2127 } 2128 } 2129 2130 /* setting should not be allowed from VF if not in one VF mode */ 2131 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 2132 dev_attr->attr.mode &= ~S_IWUGO; 2133 dev_attr->store = NULL; 2134 } 2135 2136 #undef DEVICE_ATTR_IS 2137 2138 return 0; 2139 } 2140 2141 2142 static int amdgpu_device_attr_create(struct amdgpu_device *adev, 2143 struct amdgpu_device_attr *attr, 2144 uint32_t mask, struct list_head *attr_list) 2145 { 2146 int ret = 0; 2147 enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED; 2148 struct amdgpu_device_attr_entry *attr_entry; 2149 struct device_attribute *dev_attr; 2150 const char *name; 2151 2152 int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2153 uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update; 2154 2155 if (!attr) 2156 return -EINVAL; 2157 2158 dev_attr = &attr->dev_attr; 2159 name = dev_attr->attr.name; 2160 2161 attr_update = attr->attr_update ? attr->attr_update : default_attr_update; 2162 2163 ret = attr_update(adev, attr, mask, &attr_states); 2164 if (ret) { 2165 dev_err(adev->dev, "failed to update device file %s, ret = %d\n", 2166 name, ret); 2167 return ret; 2168 } 2169 2170 if (attr_states == ATTR_STATE_UNSUPPORTED) 2171 return 0; 2172 2173 ret = device_create_file(adev->dev, dev_attr); 2174 if (ret) { 2175 dev_err(adev->dev, "failed to create device file %s, ret = %d\n", 2176 name, ret); 2177 } 2178 2179 attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL); 2180 if (!attr_entry) 2181 return -ENOMEM; 2182 2183 attr_entry->attr = attr; 2184 INIT_LIST_HEAD(&attr_entry->entry); 2185 2186 list_add_tail(&attr_entry->entry, attr_list); 2187 2188 return ret; 2189 } 2190 2191 static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr) 2192 { 2193 struct device_attribute *dev_attr = &attr->dev_attr; 2194 2195 device_remove_file(adev->dev, dev_attr); 2196 } 2197 2198 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev, 2199 struct list_head *attr_list); 2200 2201 static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev, 2202 struct amdgpu_device_attr *attrs, 2203 uint32_t counts, 2204 uint32_t mask, 2205 struct list_head *attr_list) 2206 { 2207 int ret = 0; 2208 uint32_t i = 0; 2209 2210 for (i = 0; i < counts; i++) { 2211 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list); 2212 if (ret) 2213 goto failed; 2214 } 2215 2216 return 0; 2217 2218 failed: 2219 amdgpu_device_attr_remove_groups(adev, attr_list); 2220 2221 return ret; 2222 } 2223 2224 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev, 2225 struct list_head *attr_list) 2226 { 2227 struct amdgpu_device_attr_entry *entry, *entry_tmp; 2228 2229 if (list_empty(attr_list)) 2230 return ; 2231 2232 list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) { 2233 amdgpu_device_attr_remove(adev, entry->attr); 2234 list_del(&entry->entry); 2235 kfree(entry); 2236 } 2237 } 2238 2239 static ssize_t amdgpu_hwmon_show_temp(struct device *dev, 2240 struct device_attribute *attr, 2241 char *buf) 2242 { 2243 struct amdgpu_device *adev = dev_get_drvdata(dev); 2244 int channel = to_sensor_dev_attr(attr)->index; 2245 int r, temp = 0; 2246 2247 if (channel >= PP_TEMP_MAX) 2248 return -EINVAL; 2249 2250 switch (channel) { 2251 case PP_TEMP_JUNCTION: 2252 /* get current junction temperature */ 2253 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 2254 (void *)&temp); 2255 break; 2256 case PP_TEMP_EDGE: 2257 /* get current edge temperature */ 2258 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_EDGE_TEMP, 2259 (void *)&temp); 2260 break; 2261 case PP_TEMP_MEM: 2262 /* get current memory temperature */ 2263 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_TEMP, 2264 (void *)&temp); 2265 break; 2266 default: 2267 r = -EINVAL; 2268 break; 2269 } 2270 2271 if (r) 2272 return r; 2273 2274 return sysfs_emit(buf, "%d\n", temp); 2275 } 2276 2277 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev, 2278 struct device_attribute *attr, 2279 char *buf) 2280 { 2281 struct amdgpu_device *adev = dev_get_drvdata(dev); 2282 int hyst = to_sensor_dev_attr(attr)->index; 2283 int temp; 2284 2285 if (hyst) 2286 temp = adev->pm.dpm.thermal.min_temp; 2287 else 2288 temp = adev->pm.dpm.thermal.max_temp; 2289 2290 return sysfs_emit(buf, "%d\n", temp); 2291 } 2292 2293 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev, 2294 struct device_attribute *attr, 2295 char *buf) 2296 { 2297 struct amdgpu_device *adev = dev_get_drvdata(dev); 2298 int hyst = to_sensor_dev_attr(attr)->index; 2299 int temp; 2300 2301 if (hyst) 2302 temp = adev->pm.dpm.thermal.min_hotspot_temp; 2303 else 2304 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp; 2305 2306 return sysfs_emit(buf, "%d\n", temp); 2307 } 2308 2309 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev, 2310 struct device_attribute *attr, 2311 char *buf) 2312 { 2313 struct amdgpu_device *adev = dev_get_drvdata(dev); 2314 int hyst = to_sensor_dev_attr(attr)->index; 2315 int temp; 2316 2317 if (hyst) 2318 temp = adev->pm.dpm.thermal.min_mem_temp; 2319 else 2320 temp = adev->pm.dpm.thermal.max_mem_crit_temp; 2321 2322 return sysfs_emit(buf, "%d\n", temp); 2323 } 2324 2325 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev, 2326 struct device_attribute *attr, 2327 char *buf) 2328 { 2329 int channel = to_sensor_dev_attr(attr)->index; 2330 2331 if (channel >= PP_TEMP_MAX) 2332 return -EINVAL; 2333 2334 return sysfs_emit(buf, "%s\n", temp_label[channel].label); 2335 } 2336 2337 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev, 2338 struct device_attribute *attr, 2339 char *buf) 2340 { 2341 struct amdgpu_device *adev = dev_get_drvdata(dev); 2342 int channel = to_sensor_dev_attr(attr)->index; 2343 int temp = 0; 2344 2345 if (channel >= PP_TEMP_MAX) 2346 return -EINVAL; 2347 2348 switch (channel) { 2349 case PP_TEMP_JUNCTION: 2350 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp; 2351 break; 2352 case PP_TEMP_EDGE: 2353 temp = adev->pm.dpm.thermal.max_edge_emergency_temp; 2354 break; 2355 case PP_TEMP_MEM: 2356 temp = adev->pm.dpm.thermal.max_mem_emergency_temp; 2357 break; 2358 } 2359 2360 return sysfs_emit(buf, "%d\n", temp); 2361 } 2362 2363 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev, 2364 struct device_attribute *attr, 2365 char *buf) 2366 { 2367 struct amdgpu_device *adev = dev_get_drvdata(dev); 2368 u32 pwm_mode = 0; 2369 int ret; 2370 2371 if (amdgpu_in_reset(adev)) 2372 return -EPERM; 2373 if (adev->in_suspend && !adev->in_runpm) 2374 return -EPERM; 2375 2376 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2377 if (ret < 0) { 2378 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2379 return ret; 2380 } 2381 2382 ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2383 2384 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2385 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2386 2387 if (ret) 2388 return -EINVAL; 2389 2390 return sysfs_emit(buf, "%u\n", pwm_mode); 2391 } 2392 2393 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev, 2394 struct device_attribute *attr, 2395 const char *buf, 2396 size_t count) 2397 { 2398 struct amdgpu_device *adev = dev_get_drvdata(dev); 2399 int err, ret; 2400 int value; 2401 2402 if (amdgpu_in_reset(adev)) 2403 return -EPERM; 2404 if (adev->in_suspend && !adev->in_runpm) 2405 return -EPERM; 2406 2407 err = kstrtoint(buf, 10, &value); 2408 if (err) 2409 return err; 2410 2411 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2412 if (ret < 0) { 2413 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2414 return ret; 2415 } 2416 2417 ret = amdgpu_dpm_set_fan_control_mode(adev, value); 2418 2419 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2420 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2421 2422 if (ret) 2423 return -EINVAL; 2424 2425 return count; 2426 } 2427 2428 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev, 2429 struct device_attribute *attr, 2430 char *buf) 2431 { 2432 return sysfs_emit(buf, "%i\n", 0); 2433 } 2434 2435 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev, 2436 struct device_attribute *attr, 2437 char *buf) 2438 { 2439 return sysfs_emit(buf, "%i\n", 255); 2440 } 2441 2442 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev, 2443 struct device_attribute *attr, 2444 const char *buf, size_t count) 2445 { 2446 struct amdgpu_device *adev = dev_get_drvdata(dev); 2447 int err; 2448 u32 value; 2449 u32 pwm_mode; 2450 2451 if (amdgpu_in_reset(adev)) 2452 return -EPERM; 2453 if (adev->in_suspend && !adev->in_runpm) 2454 return -EPERM; 2455 2456 err = kstrtou32(buf, 10, &value); 2457 if (err) 2458 return err; 2459 2460 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2461 if (err < 0) { 2462 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2463 return err; 2464 } 2465 2466 err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2467 if (err) 2468 goto out; 2469 2470 if (pwm_mode != AMD_FAN_CTRL_MANUAL) { 2471 pr_info("manual fan speed control should be enabled first\n"); 2472 err = -EINVAL; 2473 goto out; 2474 } 2475 2476 err = amdgpu_dpm_set_fan_speed_pwm(adev, value); 2477 2478 out: 2479 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2480 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2481 2482 if (err) 2483 return err; 2484 2485 return count; 2486 } 2487 2488 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev, 2489 struct device_attribute *attr, 2490 char *buf) 2491 { 2492 struct amdgpu_device *adev = dev_get_drvdata(dev); 2493 int err; 2494 u32 speed = 0; 2495 2496 if (amdgpu_in_reset(adev)) 2497 return -EPERM; 2498 if (adev->in_suspend && !adev->in_runpm) 2499 return -EPERM; 2500 2501 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2502 if (err < 0) { 2503 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2504 return err; 2505 } 2506 2507 err = amdgpu_dpm_get_fan_speed_pwm(adev, &speed); 2508 2509 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2510 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2511 2512 if (err) 2513 return err; 2514 2515 return sysfs_emit(buf, "%i\n", speed); 2516 } 2517 2518 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev, 2519 struct device_attribute *attr, 2520 char *buf) 2521 { 2522 struct amdgpu_device *adev = dev_get_drvdata(dev); 2523 int err; 2524 u32 speed = 0; 2525 2526 if (amdgpu_in_reset(adev)) 2527 return -EPERM; 2528 if (adev->in_suspend && !adev->in_runpm) 2529 return -EPERM; 2530 2531 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2532 if (err < 0) { 2533 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2534 return err; 2535 } 2536 2537 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed); 2538 2539 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2540 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2541 2542 if (err) 2543 return err; 2544 2545 return sysfs_emit(buf, "%i\n", speed); 2546 } 2547 2548 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev, 2549 struct device_attribute *attr, 2550 char *buf) 2551 { 2552 struct amdgpu_device *adev = dev_get_drvdata(dev); 2553 u32 min_rpm = 0; 2554 int r; 2555 2556 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM, 2557 (void *)&min_rpm); 2558 2559 if (r) 2560 return r; 2561 2562 return sysfs_emit(buf, "%d\n", min_rpm); 2563 } 2564 2565 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev, 2566 struct device_attribute *attr, 2567 char *buf) 2568 { 2569 struct amdgpu_device *adev = dev_get_drvdata(dev); 2570 u32 max_rpm = 0; 2571 int r; 2572 2573 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM, 2574 (void *)&max_rpm); 2575 2576 if (r) 2577 return r; 2578 2579 return sysfs_emit(buf, "%d\n", max_rpm); 2580 } 2581 2582 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev, 2583 struct device_attribute *attr, 2584 char *buf) 2585 { 2586 struct amdgpu_device *adev = dev_get_drvdata(dev); 2587 int err; 2588 u32 rpm = 0; 2589 2590 if (amdgpu_in_reset(adev)) 2591 return -EPERM; 2592 if (adev->in_suspend && !adev->in_runpm) 2593 return -EPERM; 2594 2595 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2596 if (err < 0) { 2597 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2598 return err; 2599 } 2600 2601 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm); 2602 2603 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2604 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2605 2606 if (err) 2607 return err; 2608 2609 return sysfs_emit(buf, "%i\n", rpm); 2610 } 2611 2612 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev, 2613 struct device_attribute *attr, 2614 const char *buf, size_t count) 2615 { 2616 struct amdgpu_device *adev = dev_get_drvdata(dev); 2617 int err; 2618 u32 value; 2619 u32 pwm_mode; 2620 2621 if (amdgpu_in_reset(adev)) 2622 return -EPERM; 2623 if (adev->in_suspend && !adev->in_runpm) 2624 return -EPERM; 2625 2626 err = kstrtou32(buf, 10, &value); 2627 if (err) 2628 return err; 2629 2630 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2631 if (err < 0) { 2632 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2633 return err; 2634 } 2635 2636 err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2637 if (err) 2638 goto out; 2639 2640 if (pwm_mode != AMD_FAN_CTRL_MANUAL) { 2641 err = -ENODATA; 2642 goto out; 2643 } 2644 2645 err = amdgpu_dpm_set_fan_speed_rpm(adev, value); 2646 2647 out: 2648 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2649 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2650 2651 if (err) 2652 return err; 2653 2654 return count; 2655 } 2656 2657 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev, 2658 struct device_attribute *attr, 2659 char *buf) 2660 { 2661 struct amdgpu_device *adev = dev_get_drvdata(dev); 2662 u32 pwm_mode = 0; 2663 int ret; 2664 2665 if (amdgpu_in_reset(adev)) 2666 return -EPERM; 2667 if (adev->in_suspend && !adev->in_runpm) 2668 return -EPERM; 2669 2670 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2671 if (ret < 0) { 2672 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2673 return ret; 2674 } 2675 2676 ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2677 2678 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2679 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2680 2681 if (ret) 2682 return -EINVAL; 2683 2684 return sysfs_emit(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1); 2685 } 2686 2687 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev, 2688 struct device_attribute *attr, 2689 const char *buf, 2690 size_t count) 2691 { 2692 struct amdgpu_device *adev = dev_get_drvdata(dev); 2693 int err; 2694 int value; 2695 u32 pwm_mode; 2696 2697 if (amdgpu_in_reset(adev)) 2698 return -EPERM; 2699 if (adev->in_suspend && !adev->in_runpm) 2700 return -EPERM; 2701 2702 err = kstrtoint(buf, 10, &value); 2703 if (err) 2704 return err; 2705 2706 if (value == 0) 2707 pwm_mode = AMD_FAN_CTRL_AUTO; 2708 else if (value == 1) 2709 pwm_mode = AMD_FAN_CTRL_MANUAL; 2710 else 2711 return -EINVAL; 2712 2713 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2714 if (err < 0) { 2715 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2716 return err; 2717 } 2718 2719 err = amdgpu_dpm_set_fan_control_mode(adev, pwm_mode); 2720 2721 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2722 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2723 2724 if (err) 2725 return -EINVAL; 2726 2727 return count; 2728 } 2729 2730 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev, 2731 struct device_attribute *attr, 2732 char *buf) 2733 { 2734 struct amdgpu_device *adev = dev_get_drvdata(dev); 2735 u32 vddgfx; 2736 int r; 2737 2738 /* get the voltage */ 2739 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDGFX, 2740 (void *)&vddgfx); 2741 if (r) 2742 return r; 2743 2744 return sysfs_emit(buf, "%d\n", vddgfx); 2745 } 2746 2747 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev, 2748 struct device_attribute *attr, 2749 char *buf) 2750 { 2751 return sysfs_emit(buf, "vddgfx\n"); 2752 } 2753 2754 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev, 2755 struct device_attribute *attr, 2756 char *buf) 2757 { 2758 struct amdgpu_device *adev = dev_get_drvdata(dev); 2759 u32 vddnb; 2760 int r; 2761 2762 /* only APUs have vddnb */ 2763 if (!(adev->flags & AMD_IS_APU)) 2764 return -EINVAL; 2765 2766 /* get the voltage */ 2767 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDNB, 2768 (void *)&vddnb); 2769 if (r) 2770 return r; 2771 2772 return sysfs_emit(buf, "%d\n", vddnb); 2773 } 2774 2775 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev, 2776 struct device_attribute *attr, 2777 char *buf) 2778 { 2779 return sysfs_emit(buf, "vddnb\n"); 2780 } 2781 2782 static unsigned int amdgpu_hwmon_get_power(struct device *dev, 2783 enum amd_pp_sensors sensor) 2784 { 2785 struct amdgpu_device *adev = dev_get_drvdata(dev); 2786 unsigned int uw; 2787 u32 query = 0; 2788 int r; 2789 2790 r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&query); 2791 if (r) 2792 return r; 2793 2794 /* convert to microwatts */ 2795 uw = (query >> 8) * 1000000 + (query & 0xff) * 1000; 2796 2797 return uw; 2798 } 2799 2800 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev, 2801 struct device_attribute *attr, 2802 char *buf) 2803 { 2804 unsigned int val; 2805 2806 val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_AVG_POWER); 2807 if (val < 0) 2808 return val; 2809 2810 return sysfs_emit(buf, "%u\n", val); 2811 } 2812 2813 static ssize_t amdgpu_hwmon_show_power_input(struct device *dev, 2814 struct device_attribute *attr, 2815 char *buf) 2816 { 2817 unsigned int val; 2818 2819 val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER); 2820 if (val < 0) 2821 return val; 2822 2823 return sysfs_emit(buf, "%u\n", val); 2824 } 2825 2826 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev, 2827 struct device_attribute *attr, 2828 char *buf) 2829 { 2830 return sysfs_emit(buf, "%i\n", 0); 2831 } 2832 2833 2834 static ssize_t amdgpu_hwmon_show_power_cap_generic(struct device *dev, 2835 struct device_attribute *attr, 2836 char *buf, 2837 enum pp_power_limit_level pp_limit_level) 2838 { 2839 struct amdgpu_device *adev = dev_get_drvdata(dev); 2840 enum pp_power_type power_type = to_sensor_dev_attr(attr)->index; 2841 uint32_t limit; 2842 ssize_t size; 2843 int r; 2844 2845 if (amdgpu_in_reset(adev)) 2846 return -EPERM; 2847 if (adev->in_suspend && !adev->in_runpm) 2848 return -EPERM; 2849 2850 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2851 if (r < 0) { 2852 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2853 return r; 2854 } 2855 2856 r = amdgpu_dpm_get_power_limit(adev, &limit, 2857 pp_limit_level, power_type); 2858 2859 if (!r) 2860 size = sysfs_emit(buf, "%u\n", limit * 1000000); 2861 else 2862 size = sysfs_emit(buf, "\n"); 2863 2864 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2865 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2866 2867 return size; 2868 } 2869 2870 2871 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev, 2872 struct device_attribute *attr, 2873 char *buf) 2874 { 2875 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MAX); 2876 2877 } 2878 2879 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev, 2880 struct device_attribute *attr, 2881 char *buf) 2882 { 2883 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_CURRENT); 2884 2885 } 2886 2887 static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev, 2888 struct device_attribute *attr, 2889 char *buf) 2890 { 2891 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_DEFAULT); 2892 2893 } 2894 2895 static ssize_t amdgpu_hwmon_show_power_label(struct device *dev, 2896 struct device_attribute *attr, 2897 char *buf) 2898 { 2899 struct amdgpu_device *adev = dev_get_drvdata(dev); 2900 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; 2901 2902 if (gc_ver == IP_VERSION(10, 3, 1)) 2903 return sysfs_emit(buf, "%s\n", 2904 to_sensor_dev_attr(attr)->index == PP_PWR_TYPE_FAST ? 2905 "fastPPT" : "slowPPT"); 2906 else 2907 return sysfs_emit(buf, "PPT\n"); 2908 } 2909 2910 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev, 2911 struct device_attribute *attr, 2912 const char *buf, 2913 size_t count) 2914 { 2915 struct amdgpu_device *adev = dev_get_drvdata(dev); 2916 int limit_type = to_sensor_dev_attr(attr)->index; 2917 int err; 2918 u32 value; 2919 2920 if (amdgpu_in_reset(adev)) 2921 return -EPERM; 2922 if (adev->in_suspend && !adev->in_runpm) 2923 return -EPERM; 2924 2925 if (amdgpu_sriov_vf(adev)) 2926 return -EINVAL; 2927 2928 err = kstrtou32(buf, 10, &value); 2929 if (err) 2930 return err; 2931 2932 value = value / 1000000; /* convert to Watt */ 2933 value |= limit_type << 24; 2934 2935 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2936 if (err < 0) { 2937 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2938 return err; 2939 } 2940 2941 err = amdgpu_dpm_set_power_limit(adev, value); 2942 2943 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2944 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2945 2946 if (err) 2947 return err; 2948 2949 return count; 2950 } 2951 2952 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev, 2953 struct device_attribute *attr, 2954 char *buf) 2955 { 2956 struct amdgpu_device *adev = dev_get_drvdata(dev); 2957 uint32_t sclk; 2958 int r; 2959 2960 /* get the sclk */ 2961 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_SCLK, 2962 (void *)&sclk); 2963 if (r) 2964 return r; 2965 2966 return sysfs_emit(buf, "%u\n", sclk * 10 * 1000); 2967 } 2968 2969 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev, 2970 struct device_attribute *attr, 2971 char *buf) 2972 { 2973 return sysfs_emit(buf, "sclk\n"); 2974 } 2975 2976 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev, 2977 struct device_attribute *attr, 2978 char *buf) 2979 { 2980 struct amdgpu_device *adev = dev_get_drvdata(dev); 2981 uint32_t mclk; 2982 int r; 2983 2984 /* get the sclk */ 2985 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_MCLK, 2986 (void *)&mclk); 2987 if (r) 2988 return r; 2989 2990 return sysfs_emit(buf, "%u\n", mclk * 10 * 1000); 2991 } 2992 2993 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev, 2994 struct device_attribute *attr, 2995 char *buf) 2996 { 2997 return sysfs_emit(buf, "mclk\n"); 2998 } 2999 3000 /** 3001 * DOC: hwmon 3002 * 3003 * The amdgpu driver exposes the following sensor interfaces: 3004 * 3005 * - GPU temperature (via the on-die sensor) 3006 * 3007 * - GPU voltage 3008 * 3009 * - Northbridge voltage (APUs only) 3010 * 3011 * - GPU power 3012 * 3013 * - GPU fan 3014 * 3015 * - GPU gfx/compute engine clock 3016 * 3017 * - GPU memory clock (dGPU only) 3018 * 3019 * hwmon interfaces for GPU temperature: 3020 * 3021 * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius 3022 * - temp2_input and temp3_input are supported on SOC15 dGPUs only 3023 * 3024 * - temp[1-3]_label: temperature channel label 3025 * - temp2_label and temp3_label are supported on SOC15 dGPUs only 3026 * 3027 * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius 3028 * - temp2_crit and temp3_crit are supported on SOC15 dGPUs only 3029 * 3030 * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius 3031 * - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only 3032 * 3033 * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius 3034 * - these are supported on SOC15 dGPUs only 3035 * 3036 * hwmon interfaces for GPU voltage: 3037 * 3038 * - in0_input: the voltage on the GPU in millivolts 3039 * 3040 * - in1_input: the voltage on the Northbridge in millivolts 3041 * 3042 * hwmon interfaces for GPU power: 3043 * 3044 * - power1_average: average power used by the SoC in microWatts. On APUs this includes the CPU. 3045 * 3046 * - power1_input: instantaneous power used by the SoC in microWatts. On APUs this includes the CPU. 3047 * 3048 * - power1_cap_min: minimum cap supported in microWatts 3049 * 3050 * - power1_cap_max: maximum cap supported in microWatts 3051 * 3052 * - power1_cap: selected power cap in microWatts 3053 * 3054 * hwmon interfaces for GPU fan: 3055 * 3056 * - pwm1: pulse width modulation fan level (0-255) 3057 * 3058 * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control) 3059 * 3060 * - pwm1_min: pulse width modulation fan control minimum level (0) 3061 * 3062 * - pwm1_max: pulse width modulation fan control maximum level (255) 3063 * 3064 * - fan1_min: a minimum value Unit: revolution/min (RPM) 3065 * 3066 * - fan1_max: a maximum value Unit: revolution/max (RPM) 3067 * 3068 * - fan1_input: fan speed in RPM 3069 * 3070 * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM) 3071 * 3072 * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable 3073 * 3074 * NOTE: DO NOT set the fan speed via "pwm1" and "fan[1-\*]_target" interfaces at the same time. 3075 * That will get the former one overridden. 3076 * 3077 * hwmon interfaces for GPU clocks: 3078 * 3079 * - freq1_input: the gfx/compute clock in hertz 3080 * 3081 * - freq2_input: the memory clock in hertz 3082 * 3083 * You can use hwmon tools like sensors to view this information on your system. 3084 * 3085 */ 3086 3087 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE); 3088 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0); 3089 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1); 3090 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE); 3091 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION); 3092 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0); 3093 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1); 3094 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION); 3095 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM); 3096 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0); 3097 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1); 3098 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM); 3099 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE); 3100 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION); 3101 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM); 3102 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0); 3103 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0); 3104 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0); 3105 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0); 3106 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0); 3107 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0); 3108 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0); 3109 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0); 3110 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0); 3111 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0); 3112 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0); 3113 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0); 3114 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0); 3115 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0); 3116 static SENSOR_DEVICE_ATTR(power1_input, S_IRUGO, amdgpu_hwmon_show_power_input, NULL, 0); 3117 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0); 3118 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0); 3119 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0); 3120 static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0); 3121 static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0); 3122 static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1); 3123 static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1); 3124 static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1); 3125 static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1); 3126 static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1); 3127 static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1); 3128 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0); 3129 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0); 3130 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0); 3131 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0); 3132 3133 static struct attribute *hwmon_attributes[] = { 3134 &sensor_dev_attr_temp1_input.dev_attr.attr, 3135 &sensor_dev_attr_temp1_crit.dev_attr.attr, 3136 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, 3137 &sensor_dev_attr_temp2_input.dev_attr.attr, 3138 &sensor_dev_attr_temp2_crit.dev_attr.attr, 3139 &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr, 3140 &sensor_dev_attr_temp3_input.dev_attr.attr, 3141 &sensor_dev_attr_temp3_crit.dev_attr.attr, 3142 &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr, 3143 &sensor_dev_attr_temp1_emergency.dev_attr.attr, 3144 &sensor_dev_attr_temp2_emergency.dev_attr.attr, 3145 &sensor_dev_attr_temp3_emergency.dev_attr.attr, 3146 &sensor_dev_attr_temp1_label.dev_attr.attr, 3147 &sensor_dev_attr_temp2_label.dev_attr.attr, 3148 &sensor_dev_attr_temp3_label.dev_attr.attr, 3149 &sensor_dev_attr_pwm1.dev_attr.attr, 3150 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 3151 &sensor_dev_attr_pwm1_min.dev_attr.attr, 3152 &sensor_dev_attr_pwm1_max.dev_attr.attr, 3153 &sensor_dev_attr_fan1_input.dev_attr.attr, 3154 &sensor_dev_attr_fan1_min.dev_attr.attr, 3155 &sensor_dev_attr_fan1_max.dev_attr.attr, 3156 &sensor_dev_attr_fan1_target.dev_attr.attr, 3157 &sensor_dev_attr_fan1_enable.dev_attr.attr, 3158 &sensor_dev_attr_in0_input.dev_attr.attr, 3159 &sensor_dev_attr_in0_label.dev_attr.attr, 3160 &sensor_dev_attr_in1_input.dev_attr.attr, 3161 &sensor_dev_attr_in1_label.dev_attr.attr, 3162 &sensor_dev_attr_power1_average.dev_attr.attr, 3163 &sensor_dev_attr_power1_input.dev_attr.attr, 3164 &sensor_dev_attr_power1_cap_max.dev_attr.attr, 3165 &sensor_dev_attr_power1_cap_min.dev_attr.attr, 3166 &sensor_dev_attr_power1_cap.dev_attr.attr, 3167 &sensor_dev_attr_power1_cap_default.dev_attr.attr, 3168 &sensor_dev_attr_power1_label.dev_attr.attr, 3169 &sensor_dev_attr_power2_average.dev_attr.attr, 3170 &sensor_dev_attr_power2_cap_max.dev_attr.attr, 3171 &sensor_dev_attr_power2_cap_min.dev_attr.attr, 3172 &sensor_dev_attr_power2_cap.dev_attr.attr, 3173 &sensor_dev_attr_power2_cap_default.dev_attr.attr, 3174 &sensor_dev_attr_power2_label.dev_attr.attr, 3175 &sensor_dev_attr_freq1_input.dev_attr.attr, 3176 &sensor_dev_attr_freq1_label.dev_attr.attr, 3177 &sensor_dev_attr_freq2_input.dev_attr.attr, 3178 &sensor_dev_attr_freq2_label.dev_attr.attr, 3179 NULL 3180 }; 3181 3182 static umode_t hwmon_attributes_visible(struct kobject *kobj, 3183 struct attribute *attr, int index) 3184 { 3185 struct device *dev = kobj_to_dev(kobj); 3186 struct amdgpu_device *adev = dev_get_drvdata(dev); 3187 umode_t effective_mode = attr->mode; 3188 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; 3189 uint32_t tmp; 3190 3191 /* under multi-vf mode, the hwmon attributes are all not supported */ 3192 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 3193 return 0; 3194 3195 /* under pp one vf mode manage of hwmon attributes is not supported */ 3196 if (amdgpu_sriov_is_pp_one_vf(adev)) 3197 effective_mode &= ~S_IWUSR; 3198 3199 /* Skip fan attributes if fan is not present */ 3200 if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3201 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3202 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3203 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3204 attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3205 attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3206 attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3207 attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3208 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3209 return 0; 3210 3211 /* Skip fan attributes on APU */ 3212 if ((adev->flags & AMD_IS_APU) && 3213 (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3214 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3215 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3216 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3217 attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3218 attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3219 attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3220 attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3221 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3222 return 0; 3223 3224 /* Skip crit temp on APU */ 3225 if ((((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ)) || 3226 (gc_ver == IP_VERSION(9, 4, 3))) && 3227 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 3228 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr)) 3229 return 0; 3230 3231 /* Skip limit attributes if DPM is not enabled */ 3232 if (!adev->pm.dpm_enabled && 3233 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 3234 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr || 3235 attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3236 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3237 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3238 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3239 attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3240 attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3241 attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3242 attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3243 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3244 return 0; 3245 3246 /* mask fan attributes if we have no bindings for this asic to expose */ 3247 if (((amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) && 3248 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */ 3249 ((amdgpu_dpm_get_fan_control_mode(adev, NULL) == -EOPNOTSUPP) && 3250 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */ 3251 effective_mode &= ~S_IRUGO; 3252 3253 if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) && 3254 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */ 3255 ((amdgpu_dpm_set_fan_control_mode(adev, U32_MAX) == -EOPNOTSUPP) && 3256 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ 3257 effective_mode &= ~S_IWUSR; 3258 3259 /* not implemented yet for APUs other than GC 10.3.1 (vangogh) and 9.4.3 */ 3260 if (((adev->family == AMDGPU_FAMILY_SI) || 3261 ((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(10, 3, 1)) && 3262 (gc_ver != IP_VERSION(9, 4, 3)))) && 3263 (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr || 3264 attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr || 3265 attr == &sensor_dev_attr_power1_cap.dev_attr.attr || 3266 attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr)) 3267 return 0; 3268 3269 /* not implemented yet for APUs having < GC 9.3.0 (Renoir) */ 3270 if (((adev->family == AMDGPU_FAMILY_SI) || 3271 ((adev->flags & AMD_IS_APU) && (gc_ver < IP_VERSION(9, 3, 0)))) && 3272 (attr == &sensor_dev_attr_power1_average.dev_attr.attr)) 3273 return 0; 3274 3275 /* not all products support both average and instantaneous */ 3276 if (attr == &sensor_dev_attr_power1_average.dev_attr.attr && 3277 amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&tmp) == -EOPNOTSUPP) 3278 return 0; 3279 if (attr == &sensor_dev_attr_power1_input.dev_attr.attr && 3280 amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&tmp) == -EOPNOTSUPP) 3281 return 0; 3282 3283 /* hide max/min values if we can't both query and manage the fan */ 3284 if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) && 3285 (amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) && 3286 (amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) && 3287 (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP)) && 3288 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3289 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 3290 return 0; 3291 3292 if ((amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) && 3293 (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP) && 3294 (attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3295 attr == &sensor_dev_attr_fan1_min.dev_attr.attr)) 3296 return 0; 3297 3298 if ((adev->family == AMDGPU_FAMILY_SI || /* not implemented yet */ 3299 adev->family == AMDGPU_FAMILY_KV || /* not implemented yet */ 3300 (gc_ver == IP_VERSION(9, 4, 3))) && 3301 (attr == &sensor_dev_attr_in0_input.dev_attr.attr || 3302 attr == &sensor_dev_attr_in0_label.dev_attr.attr)) 3303 return 0; 3304 3305 /* only APUs other than gc 9,4,3 have vddnb */ 3306 if ((!(adev->flags & AMD_IS_APU) || (gc_ver == IP_VERSION(9, 4, 3))) && 3307 (attr == &sensor_dev_attr_in1_input.dev_attr.attr || 3308 attr == &sensor_dev_attr_in1_label.dev_attr.attr)) 3309 return 0; 3310 3311 /* no mclk on APUs other than gc 9,4,3*/ 3312 if (((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(9, 4, 3))) && 3313 (attr == &sensor_dev_attr_freq2_input.dev_attr.attr || 3314 attr == &sensor_dev_attr_freq2_label.dev_attr.attr)) 3315 return 0; 3316 3317 if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) && 3318 (gc_ver != IP_VERSION(9, 4, 3)) && 3319 (attr == &sensor_dev_attr_temp2_input.dev_attr.attr || 3320 attr == &sensor_dev_attr_temp2_label.dev_attr.attr || 3321 attr == &sensor_dev_attr_temp2_crit.dev_attr.attr || 3322 attr == &sensor_dev_attr_temp3_input.dev_attr.attr || 3323 attr == &sensor_dev_attr_temp3_label.dev_attr.attr || 3324 attr == &sensor_dev_attr_temp3_crit.dev_attr.attr)) 3325 return 0; 3326 3327 /* hotspot temperature for gc 9,4,3*/ 3328 if ((gc_ver == IP_VERSION(9, 4, 3)) && 3329 (attr == &sensor_dev_attr_temp1_input.dev_attr.attr || 3330 attr == &sensor_dev_attr_temp1_label.dev_attr.attr)) 3331 return 0; 3332 3333 /* only SOC15 dGPUs support hotspot and mem temperatures */ 3334 if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0) || 3335 (gc_ver == IP_VERSION(9, 4, 3))) && 3336 (attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr || 3337 attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr || 3338 attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr || 3339 attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr || 3340 attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr)) 3341 return 0; 3342 3343 /* only Vangogh has fast PPT limit and power labels */ 3344 if (!(gc_ver == IP_VERSION(10, 3, 1)) && 3345 (attr == &sensor_dev_attr_power2_average.dev_attr.attr || 3346 attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr || 3347 attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr || 3348 attr == &sensor_dev_attr_power2_cap.dev_attr.attr || 3349 attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr || 3350 attr == &sensor_dev_attr_power2_label.dev_attr.attr)) 3351 return 0; 3352 3353 return effective_mode; 3354 } 3355 3356 static const struct attribute_group hwmon_attrgroup = { 3357 .attrs = hwmon_attributes, 3358 .is_visible = hwmon_attributes_visible, 3359 }; 3360 3361 static const struct attribute_group *hwmon_groups[] = { 3362 &hwmon_attrgroup, 3363 NULL 3364 }; 3365 3366 #endif /* __linux__ */ 3367 3368 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) 3369 { 3370 return 0; 3371 #ifdef __linux__ 3372 int ret; 3373 uint32_t mask = 0; 3374 3375 if (adev->pm.sysfs_initialized) 3376 return 0; 3377 3378 INIT_LIST_HEAD(&adev->pm.pm_attr_list); 3379 3380 if (adev->pm.dpm_enabled == 0) 3381 return 0; 3382 3383 adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev, 3384 DRIVER_NAME, adev, 3385 hwmon_groups); 3386 if (IS_ERR(adev->pm.int_hwmon_dev)) { 3387 ret = PTR_ERR(adev->pm.int_hwmon_dev); 3388 dev_err(adev->dev, 3389 "Unable to register hwmon device: %d\n", ret); 3390 return ret; 3391 } 3392 3393 switch (amdgpu_virt_get_sriov_vf_mode(adev)) { 3394 case SRIOV_VF_MODE_ONE_VF: 3395 mask = ATTR_FLAG_ONEVF; 3396 break; 3397 case SRIOV_VF_MODE_MULTI_VF: 3398 mask = 0; 3399 break; 3400 case SRIOV_VF_MODE_BARE_METAL: 3401 default: 3402 mask = ATTR_FLAG_MASK_ALL; 3403 break; 3404 } 3405 3406 ret = amdgpu_device_attr_create_groups(adev, 3407 amdgpu_device_attrs, 3408 ARRAY_SIZE(amdgpu_device_attrs), 3409 mask, 3410 &adev->pm.pm_attr_list); 3411 if (ret) 3412 return ret; 3413 3414 adev->pm.sysfs_initialized = true; 3415 3416 return 0; 3417 #endif 3418 } 3419 3420 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev) 3421 { 3422 #ifdef __linux__ 3423 if (adev->pm.int_hwmon_dev) 3424 hwmon_device_unregister(adev->pm.int_hwmon_dev); 3425 3426 amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list); 3427 #endif 3428 } 3429 3430 /* 3431 * Debugfs info 3432 */ 3433 #if defined(CONFIG_DEBUG_FS) 3434 3435 static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m, 3436 struct amdgpu_device *adev) 3437 { 3438 uint16_t *p_val; 3439 uint32_t size; 3440 int i; 3441 uint32_t num_cpu_cores = amdgpu_dpm_get_num_cpu_cores(adev); 3442 3443 if (amdgpu_dpm_is_cclk_dpm_supported(adev)) { 3444 p_val = kcalloc(num_cpu_cores, sizeof(uint16_t), 3445 GFP_KERNEL); 3446 3447 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK, 3448 (void *)p_val, &size)) { 3449 for (i = 0; i < num_cpu_cores; i++) 3450 seq_printf(m, "\t%u MHz (CPU%d)\n", 3451 *(p_val + i), i); 3452 } 3453 3454 kfree(p_val); 3455 } 3456 } 3457 3458 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev) 3459 { 3460 uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0]; 3461 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; 3462 uint32_t value; 3463 uint64_t value64 = 0; 3464 uint32_t query = 0; 3465 int size; 3466 3467 /* GPU Clocks */ 3468 size = sizeof(value); 3469 seq_printf(m, "GFX Clocks and Power:\n"); 3470 3471 amdgpu_debugfs_prints_cpu_info(m, adev); 3472 3473 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size)) 3474 seq_printf(m, "\t%u MHz (MCLK)\n", value/100); 3475 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size)) 3476 seq_printf(m, "\t%u MHz (SCLK)\n", value/100); 3477 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size)) 3478 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100); 3479 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size)) 3480 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100); 3481 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size)) 3482 seq_printf(m, "\t%u mV (VDDGFX)\n", value); 3483 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size)) 3484 seq_printf(m, "\t%u mV (VDDNB)\n", value); 3485 size = sizeof(uint32_t); 3486 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&query, &size)) 3487 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff); 3488 size = sizeof(uint32_t); 3489 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&query, &size)) 3490 seq_printf(m, "\t%u.%u W (current GPU)\n", query >> 8, query & 0xff); 3491 size = sizeof(value); 3492 seq_printf(m, "\n"); 3493 3494 /* GPU Temp */ 3495 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size)) 3496 seq_printf(m, "GPU Temperature: %u C\n", value/1000); 3497 3498 /* GPU Load */ 3499 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size)) 3500 seq_printf(m, "GPU Load: %u %%\n", value); 3501 /* MEM Load */ 3502 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size)) 3503 seq_printf(m, "MEM Load: %u %%\n", value); 3504 3505 seq_printf(m, "\n"); 3506 3507 /* SMC feature mask */ 3508 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size)) 3509 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64); 3510 3511 /* ASICs greater than CHIP_VEGA20 supports these sensors */ 3512 if (gc_ver != IP_VERSION(9, 4, 0) && mp1_ver > IP_VERSION(9, 0, 0)) { 3513 /* VCN clocks */ 3514 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) { 3515 if (!value) { 3516 seq_printf(m, "VCN: Disabled\n"); 3517 } else { 3518 seq_printf(m, "VCN: Enabled\n"); 3519 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) 3520 seq_printf(m, "\t%u MHz (DCLK)\n", value/100); 3521 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) 3522 seq_printf(m, "\t%u MHz (VCLK)\n", value/100); 3523 } 3524 } 3525 seq_printf(m, "\n"); 3526 } else { 3527 /* UVD clocks */ 3528 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) { 3529 if (!value) { 3530 seq_printf(m, "UVD: Disabled\n"); 3531 } else { 3532 seq_printf(m, "UVD: Enabled\n"); 3533 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) 3534 seq_printf(m, "\t%u MHz (DCLK)\n", value/100); 3535 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) 3536 seq_printf(m, "\t%u MHz (VCLK)\n", value/100); 3537 } 3538 } 3539 seq_printf(m, "\n"); 3540 3541 /* VCE clocks */ 3542 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) { 3543 if (!value) { 3544 seq_printf(m, "VCE: Disabled\n"); 3545 } else { 3546 seq_printf(m, "VCE: Enabled\n"); 3547 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size)) 3548 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100); 3549 } 3550 } 3551 } 3552 3553 return 0; 3554 } 3555 3556 static const struct cg_flag_name clocks[] = { 3557 {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"}, 3558 {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"}, 3559 {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"}, 3560 {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"}, 3561 {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"}, 3562 {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"}, 3563 {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"}, 3564 {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"}, 3565 {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"}, 3566 {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"}, 3567 {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"}, 3568 {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"}, 3569 {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"}, 3570 {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"}, 3571 {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"}, 3572 {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"}, 3573 {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"}, 3574 {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"}, 3575 {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"}, 3576 {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"}, 3577 {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"}, 3578 {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"}, 3579 {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"}, 3580 {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"}, 3581 {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"}, 3582 {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"}, 3583 {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"}, 3584 {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"}, 3585 {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"}, 3586 {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"}, 3587 {AMD_CG_SUPPORT_REPEATER_FGCG, "Repeater Fine Grain Clock Gating"}, 3588 {AMD_CG_SUPPORT_GFX_PERF_CLK, "Perfmon Clock Gating"}, 3589 {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"}, 3590 {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"}, 3591 {0, NULL}, 3592 }; 3593 3594 static void amdgpu_parse_cg_state(struct seq_file *m, u64 flags) 3595 { 3596 int i; 3597 3598 for (i = 0; clocks[i].flag; i++) 3599 seq_printf(m, "\t%s: %s\n", clocks[i].name, 3600 (flags & clocks[i].flag) ? "On" : "Off"); 3601 } 3602 3603 static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused) 3604 { 3605 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 3606 struct drm_device *dev = adev_to_drm(adev); 3607 u64 flags = 0; 3608 int r; 3609 3610 if (amdgpu_in_reset(adev)) 3611 return -EPERM; 3612 if (adev->in_suspend && !adev->in_runpm) 3613 return -EPERM; 3614 3615 r = pm_runtime_get_sync(dev->dev); 3616 if (r < 0) { 3617 pm_runtime_put_autosuspend(dev->dev); 3618 return r; 3619 } 3620 3621 if (amdgpu_dpm_debugfs_print_current_performance_level(adev, m)) { 3622 r = amdgpu_debugfs_pm_info_pp(m, adev); 3623 if (r) 3624 goto out; 3625 } 3626 3627 amdgpu_device_ip_get_clockgating_state(adev, &flags); 3628 3629 seq_printf(m, "Clock Gating Flags Mask: 0x%llx\n", flags); 3630 amdgpu_parse_cg_state(m, flags); 3631 seq_printf(m, "\n"); 3632 3633 out: 3634 pm_runtime_mark_last_busy(dev->dev); 3635 pm_runtime_put_autosuspend(dev->dev); 3636 3637 return r; 3638 } 3639 3640 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info); 3641 3642 /* 3643 * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW 3644 * 3645 * Reads debug memory region allocated to PMFW 3646 */ 3647 static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf, 3648 size_t size, loff_t *pos) 3649 { 3650 struct amdgpu_device *adev = file_inode(f)->i_private; 3651 size_t smu_prv_buf_size; 3652 void *smu_prv_buf; 3653 int ret = 0; 3654 3655 if (amdgpu_in_reset(adev)) 3656 return -EPERM; 3657 if (adev->in_suspend && !adev->in_runpm) 3658 return -EPERM; 3659 3660 ret = amdgpu_dpm_get_smu_prv_buf_details(adev, &smu_prv_buf, &smu_prv_buf_size); 3661 if (ret) 3662 return ret; 3663 3664 if (!smu_prv_buf || !smu_prv_buf_size) 3665 return -EINVAL; 3666 3667 return simple_read_from_buffer(buf, size, pos, smu_prv_buf, 3668 smu_prv_buf_size); 3669 } 3670 3671 static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = { 3672 .owner = THIS_MODULE, 3673 .open = simple_open, 3674 .read = amdgpu_pm_prv_buffer_read, 3675 .llseek = default_llseek, 3676 }; 3677 3678 #endif 3679 3680 void amdgpu_debugfs_pm_init(struct amdgpu_device *adev) 3681 { 3682 #if defined(CONFIG_DEBUG_FS) 3683 struct drm_minor *minor = adev_to_drm(adev)->primary; 3684 struct dentry *root = minor->debugfs_root; 3685 3686 if (!adev->pm.dpm_enabled) 3687 return; 3688 3689 debugfs_create_file("amdgpu_pm_info", 0444, root, adev, 3690 &amdgpu_debugfs_pm_info_fops); 3691 3692 if (adev->pm.smu_prv_buffer_size > 0) 3693 debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root, 3694 adev, 3695 &amdgpu_debugfs_pm_prv_buffer_fops, 3696 adev->pm.smu_prv_buffer_size); 3697 3698 amdgpu_dpm_stb_debug_fs_init(adev); 3699 #endif 3700 } 3701