xref: /openbsd-src/sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h (revision 1bb76ff151c0aba8e3312a604e4cd2e5195cf4b7)
1fb4d8502Sjsg /*
2fb4d8502Sjsg  * Copyright 2016 Advanced Micro Devices, Inc.
3fb4d8502Sjsg  *
4fb4d8502Sjsg  * Permission is hereby granted, free of charge, to any person obtaining a
5fb4d8502Sjsg  * copy of this software and associated documentation files (the "Software"),
6fb4d8502Sjsg  * to deal in the Software without restriction, including without limitation
7fb4d8502Sjsg  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8fb4d8502Sjsg  * and/or sell copies of the Software, and to permit persons to whom the
9fb4d8502Sjsg  * Software is furnished to do so, subject to the following conditions:
10fb4d8502Sjsg  *
11fb4d8502Sjsg  * The above copyright notice and this permission notice shall be included in
12fb4d8502Sjsg  * all copies or substantial portions of the Software.
13fb4d8502Sjsg  *
14fb4d8502Sjsg  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15fb4d8502Sjsg  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16fb4d8502Sjsg  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17fb4d8502Sjsg  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18fb4d8502Sjsg  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19fb4d8502Sjsg  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20fb4d8502Sjsg  * OTHER DEALINGS IN THE SOFTWARE.
21fb4d8502Sjsg  *
22fb4d8502Sjsg  * Authors: AMD
23fb4d8502Sjsg  *
24fb4d8502Sjsg  */
25fb4d8502Sjsg 
26fb4d8502Sjsg 
27fb4d8502Sjsg 
28fb4d8502Sjsg 
29fb4d8502Sjsg /*
30fb4d8502Sjsg  * Copyright 2016 Advanced Micro Devices, Inc.
31fb4d8502Sjsg  *
32fb4d8502Sjsg  * Permission is hereby granted, free of charge, to any person obtaining a
33fb4d8502Sjsg  * copy of this software and associated documentation files (the "Software"),
34fb4d8502Sjsg  * to deal in the Software without restriction, including without limitation
35fb4d8502Sjsg  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
36fb4d8502Sjsg  * and/or sell copies of the Software, and to permit persons to whom the
37fb4d8502Sjsg  * Software is furnished to do so, subject to the following conditions:
38fb4d8502Sjsg  *
39fb4d8502Sjsg  * The above copyright notice and this permission notice shall be included in
40fb4d8502Sjsg  * all copies or substantial portions of the Software.
41fb4d8502Sjsg  *
42fb4d8502Sjsg  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
43fb4d8502Sjsg  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
44fb4d8502Sjsg  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
45fb4d8502Sjsg  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
46fb4d8502Sjsg  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
47fb4d8502Sjsg  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
48fb4d8502Sjsg  * OTHER DEALINGS IN THE SOFTWARE.
49fb4d8502Sjsg  *
50fb4d8502Sjsg  * Authors: AMD
51fb4d8502Sjsg  *
52fb4d8502Sjsg  */
53fb4d8502Sjsg 
54fb4d8502Sjsg #ifndef MOD_FREESYNC_H_
55fb4d8502Sjsg #define MOD_FREESYNC_H_
56fb4d8502Sjsg 
57c349dbc7Sjsg #include "mod_shared.h"
58fb4d8502Sjsg 
59c349dbc7Sjsg // Access structures
60fb4d8502Sjsg struct mod_freesync {
61fb4d8502Sjsg 	int dummy;
62fb4d8502Sjsg };
63fb4d8502Sjsg 
64c349dbc7Sjsg // TODO: References to this should be removed
65fb4d8502Sjsg struct mod_freesync_caps {
66fb4d8502Sjsg 	bool supported;
67fb4d8502Sjsg 	unsigned int min_refresh_in_micro_hz;
68fb4d8502Sjsg 	unsigned int max_refresh_in_micro_hz;
69fb4d8502Sjsg };
70fb4d8502Sjsg 
71c349dbc7Sjsg enum mod_vrr_state {
72c349dbc7Sjsg 	VRR_STATE_UNSUPPORTED = 0,
73c349dbc7Sjsg 	VRR_STATE_DISABLED,
74c349dbc7Sjsg 	VRR_STATE_INACTIVE,
75c349dbc7Sjsg 	VRR_STATE_ACTIVE_VARIABLE,
76c349dbc7Sjsg 	VRR_STATE_ACTIVE_FIXED
77fb4d8502Sjsg };
78fb4d8502Sjsg 
79c349dbc7Sjsg struct mod_freesync_config {
80c349dbc7Sjsg 	enum mod_vrr_state state;
81c349dbc7Sjsg 	bool vsif_supported;
82c349dbc7Sjsg 	bool ramping;
83c349dbc7Sjsg 	bool btr;
84c349dbc7Sjsg 	unsigned int min_refresh_in_uhz;
85c349dbc7Sjsg 	unsigned int max_refresh_in_uhz;
86ad8b1aafSjsg 	unsigned int fixed_refresh_in_uhz;
87ad8b1aafSjsg 
88c349dbc7Sjsg };
89fb4d8502Sjsg 
90c349dbc7Sjsg struct mod_vrr_params_btr {
91c349dbc7Sjsg 	bool btr_enabled;
92c349dbc7Sjsg 	bool btr_active;
93c349dbc7Sjsg 	uint32_t mid_point_in_us;
94c349dbc7Sjsg 	uint32_t inserted_duration_in_us;
95c349dbc7Sjsg 	uint32_t frames_to_insert;
96c349dbc7Sjsg 	uint32_t frame_counter;
97c349dbc7Sjsg 	uint32_t margin_in_us;
98c349dbc7Sjsg };
99fb4d8502Sjsg 
100c349dbc7Sjsg struct mod_vrr_params_fixed_refresh {
101c349dbc7Sjsg 	bool fixed_active;
102c349dbc7Sjsg 	bool ramping_active;
103c349dbc7Sjsg 	bool ramping_done;
104c349dbc7Sjsg 	uint32_t target_refresh_in_uhz;
105c349dbc7Sjsg 	uint32_t frame_counter;
106c349dbc7Sjsg };
107fb4d8502Sjsg 
108*1bb76ff1Sjsg struct mod_vrr_params_flip_interval {
109*1bb76ff1Sjsg 	bool flip_interval_workaround_active;
110*1bb76ff1Sjsg 	bool program_flip_interval_workaround;
111*1bb76ff1Sjsg 	bool do_flip_interval_workaround_cleanup;
112*1bb76ff1Sjsg 	uint32_t flip_interval_detect_counter;
113*1bb76ff1Sjsg 	uint32_t vsyncs_between_flip;
114*1bb76ff1Sjsg 	uint32_t vsync_to_flip_in_us;
115*1bb76ff1Sjsg 	uint32_t v_update_timestamp_in_us;
116*1bb76ff1Sjsg };
117*1bb76ff1Sjsg 
118c349dbc7Sjsg struct mod_vrr_params {
119c349dbc7Sjsg 	bool supported;
120c349dbc7Sjsg 	bool send_info_frame;
121c349dbc7Sjsg 	enum mod_vrr_state state;
122fb4d8502Sjsg 
123c349dbc7Sjsg 	uint32_t min_refresh_in_uhz;
124c349dbc7Sjsg 	uint32_t max_duration_in_us;
125c349dbc7Sjsg 	uint32_t max_refresh_in_uhz;
126c349dbc7Sjsg 	uint32_t min_duration_in_us;
127ad8b1aafSjsg 	uint32_t fixed_refresh_in_uhz;
128fb4d8502Sjsg 
129c349dbc7Sjsg 	struct dc_crtc_timing_adjust adjust;
130fb4d8502Sjsg 
131c349dbc7Sjsg 	struct mod_vrr_params_fixed_refresh fixed;
132fb4d8502Sjsg 
133c349dbc7Sjsg 	struct mod_vrr_params_btr btr;
134*1bb76ff1Sjsg 
135*1bb76ff1Sjsg 	struct mod_vrr_params_flip_interval flip_interval;
136c349dbc7Sjsg };
137fb4d8502Sjsg 
138c349dbc7Sjsg struct mod_freesync *mod_freesync_create(struct dc *dc);
139c349dbc7Sjsg void mod_freesync_destroy(struct mod_freesync *mod_freesync);
140fb4d8502Sjsg 
141fb4d8502Sjsg bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync,
142c349dbc7Sjsg 		const struct dc_stream_state *stream,
143fb4d8502Sjsg 		unsigned int *vmin,
144fb4d8502Sjsg 		unsigned int *vmax);
145fb4d8502Sjsg 
146fb4d8502Sjsg bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync,
147fb4d8502Sjsg 		struct dc_stream_state *stream,
148fb4d8502Sjsg 		unsigned int *nom_v_pos,
149fb4d8502Sjsg 		unsigned int *v_pos);
150fb4d8502Sjsg 
151fb4d8502Sjsg void mod_freesync_get_settings(struct mod_freesync *mod_freesync,
152c349dbc7Sjsg 		const struct mod_vrr_params *vrr,
153fb4d8502Sjsg 		unsigned int *v_total_min, unsigned int *v_total_max,
154fb4d8502Sjsg 		unsigned int *event_triggers,
155fb4d8502Sjsg 		unsigned int *window_min, unsigned int *window_max,
156fb4d8502Sjsg 		unsigned int *lfc_mid_point_in_us,
157fb4d8502Sjsg 		unsigned int *inserted_frames,
158fb4d8502Sjsg 		unsigned int *inserted_duration_in_us);
159fb4d8502Sjsg 
160c349dbc7Sjsg void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,
161c349dbc7Sjsg 		const struct dc_stream_state *stream,
162c349dbc7Sjsg 		const struct mod_vrr_params *vrr,
163c349dbc7Sjsg 		enum vrr_packet_type packet_type,
164c349dbc7Sjsg 		enum color_transfer_func app_tf,
1655ca02815Sjsg 		struct dc_info_packet *infopacket,
1665ca02815Sjsg 		bool pack_sdp_v1_3);
167c349dbc7Sjsg 
168c349dbc7Sjsg void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
169c349dbc7Sjsg 		const struct dc_stream_state *stream,
170c349dbc7Sjsg 		struct mod_freesync_config *in_config,
171c349dbc7Sjsg 		struct mod_vrr_params *in_out_vrr);
172c349dbc7Sjsg 
173c349dbc7Sjsg void mod_freesync_handle_preflip(struct mod_freesync *mod_freesync,
174c349dbc7Sjsg 		const struct dc_plane_state *plane,
175c349dbc7Sjsg 		const struct dc_stream_state *stream,
176c349dbc7Sjsg 		unsigned int curr_time_stamp_in_us,
177c349dbc7Sjsg 		struct mod_vrr_params *in_out_vrr);
178c349dbc7Sjsg 
179c349dbc7Sjsg void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
180c349dbc7Sjsg 		const struct dc_stream_state *stream,
181c349dbc7Sjsg 		struct mod_vrr_params *in_out_vrr);
182c349dbc7Sjsg 
183c349dbc7Sjsg unsigned long long mod_freesync_calc_nominal_field_rate(
184c349dbc7Sjsg 			const struct dc_stream_state *stream);
185c349dbc7Sjsg 
1865ca02815Sjsg unsigned long long mod_freesync_calc_field_rate_from_timing(
1875ca02815Sjsg 		unsigned int vtotal, unsigned int htotal, unsigned int pix_clk);
1885ca02815Sjsg 
189ad8b1aafSjsg bool mod_freesync_is_valid_range(uint32_t min_refresh_cap_in_uhz,
190c349dbc7Sjsg 		uint32_t max_refresh_cap_in_uhz,
191ad8b1aafSjsg 		uint32_t nominal_field_rate_in_uhz);
192c349dbc7Sjsg 
1935ca02815Sjsg unsigned int mod_freesync_calc_v_total_from_refresh(
1945ca02815Sjsg 		const struct dc_stream_state *stream,
1955ca02815Sjsg 		unsigned int refresh_in_uhz);
196c349dbc7Sjsg 
197*1bb76ff1Sjsg // Returns true when FreeSync is supported and enabled (even if it is inactive)
198*1bb76ff1Sjsg bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr);
199*1bb76ff1Sjsg 
200fb4d8502Sjsg #endif
201