1fb4d8502Sjsg /*
2fb4d8502Sjsg * Copyright 2012-15 Advanced Micro Devices, Inc.
3fb4d8502Sjsg *
4fb4d8502Sjsg * Permission is hereby granted, free of charge, to any person obtaining a
5fb4d8502Sjsg * copy of this software and associated documentation files (the "Software"),
6fb4d8502Sjsg * to deal in the Software without restriction, including without limitation
7fb4d8502Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8fb4d8502Sjsg * and/or sell copies of the Software, and to permit persons to whom the
9fb4d8502Sjsg * Software is furnished to do so, subject to the following conditions:
10fb4d8502Sjsg *
11fb4d8502Sjsg * The above copyright notice and this permission notice shall be included in
12fb4d8502Sjsg * all copies or substantial portions of the Software.
13fb4d8502Sjsg *
14fb4d8502Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15fb4d8502Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16fb4d8502Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17fb4d8502Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18fb4d8502Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19fb4d8502Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20fb4d8502Sjsg * OTHER DEALINGS IN THE SOFTWARE.
21fb4d8502Sjsg *
22fb4d8502Sjsg * Authors: AMD
23fb4d8502Sjsg *
24fb4d8502Sjsg */
25fb4d8502Sjsg
26fb4d8502Sjsg #ifndef __DAL_GRPH_OBJECT_ID_H__
27fb4d8502Sjsg #define __DAL_GRPH_OBJECT_ID_H__
28fb4d8502Sjsg
29fb4d8502Sjsg /* Types of graphics objects */
30fb4d8502Sjsg enum object_type {
31fb4d8502Sjsg OBJECT_TYPE_UNKNOWN = 0,
32fb4d8502Sjsg
33fb4d8502Sjsg /* Direct ATOM BIOS translation */
34fb4d8502Sjsg OBJECT_TYPE_GPU,
35fb4d8502Sjsg OBJECT_TYPE_ENCODER,
36fb4d8502Sjsg OBJECT_TYPE_CONNECTOR,
37fb4d8502Sjsg OBJECT_TYPE_ROUTER,
38fb4d8502Sjsg OBJECT_TYPE_GENERIC,
39fb4d8502Sjsg
40fb4d8502Sjsg /* Driver specific */
41fb4d8502Sjsg OBJECT_TYPE_AUDIO,
42fb4d8502Sjsg OBJECT_TYPE_CONTROLLER,
43fb4d8502Sjsg OBJECT_TYPE_CLOCK_SOURCE,
44fb4d8502Sjsg OBJECT_TYPE_ENGINE,
45fb4d8502Sjsg
46fb4d8502Sjsg OBJECT_TYPE_COUNT
47fb4d8502Sjsg };
48fb4d8502Sjsg
49fb4d8502Sjsg /* Enumeration inside one type of graphics objects */
50fb4d8502Sjsg enum object_enum_id {
51fb4d8502Sjsg ENUM_ID_UNKNOWN = 0,
52fb4d8502Sjsg ENUM_ID_1,
53fb4d8502Sjsg ENUM_ID_2,
54fb4d8502Sjsg ENUM_ID_3,
55fb4d8502Sjsg ENUM_ID_4,
56fb4d8502Sjsg ENUM_ID_5,
57fb4d8502Sjsg ENUM_ID_6,
58fb4d8502Sjsg ENUM_ID_7,
59fb4d8502Sjsg
60fb4d8502Sjsg ENUM_ID_COUNT
61fb4d8502Sjsg };
62fb4d8502Sjsg
63fb4d8502Sjsg /* Generic object ids */
64fb4d8502Sjsg enum generic_id {
65fb4d8502Sjsg GENERIC_ID_UNKNOWN = 0,
66fb4d8502Sjsg GENERIC_ID_MXM_OPM,
67fb4d8502Sjsg GENERIC_ID_GLSYNC,
68fb4d8502Sjsg GENERIC_ID_STEREO,
69fb4d8502Sjsg
70fb4d8502Sjsg GENERIC_ID_COUNT
71fb4d8502Sjsg };
72fb4d8502Sjsg
73fb4d8502Sjsg /* Controller object ids */
74fb4d8502Sjsg enum controller_id {
75fb4d8502Sjsg CONTROLLER_ID_UNDEFINED = 0,
76fb4d8502Sjsg CONTROLLER_ID_D0,
77fb4d8502Sjsg CONTROLLER_ID_D1,
78fb4d8502Sjsg CONTROLLER_ID_D2,
79fb4d8502Sjsg CONTROLLER_ID_D3,
80fb4d8502Sjsg CONTROLLER_ID_D4,
81fb4d8502Sjsg CONTROLLER_ID_D5,
82fb4d8502Sjsg CONTROLLER_ID_UNDERLAY0,
83fb4d8502Sjsg CONTROLLER_ID_MAX = CONTROLLER_ID_UNDERLAY0
84fb4d8502Sjsg };
85fb4d8502Sjsg
86fb4d8502Sjsg #define IS_UNDERLAY_CONTROLLER(ctrlr_id) (ctrlr_id >= CONTROLLER_ID_UNDERLAY0)
87fb4d8502Sjsg
88fb4d8502Sjsg /*
89fb4d8502Sjsg * ClockSource object ids.
90fb4d8502Sjsg * We maintain the order matching (more or less) ATOM BIOS
91fb4d8502Sjsg * to improve optimized acquire
92fb4d8502Sjsg */
93fb4d8502Sjsg enum clock_source_id {
94fb4d8502Sjsg CLOCK_SOURCE_ID_UNDEFINED = 0,
95fb4d8502Sjsg CLOCK_SOURCE_ID_PLL0,
96fb4d8502Sjsg CLOCK_SOURCE_ID_PLL1,
97fb4d8502Sjsg CLOCK_SOURCE_ID_PLL2,
98fb4d8502Sjsg CLOCK_SOURCE_ID_EXTERNAL, /* ID (Phy) ref. clk. for DP */
99fb4d8502Sjsg CLOCK_SOURCE_ID_DCPLL,
100fb4d8502Sjsg CLOCK_SOURCE_ID_DFS, /* DENTIST */
101fb4d8502Sjsg CLOCK_SOURCE_ID_VCE, /* VCE does not need a real PLL */
102fb4d8502Sjsg /* Used to distinguish between programming pixel clock and ID (Phy) clock */
103fb4d8502Sjsg CLOCK_SOURCE_ID_DP_DTO,
104fb4d8502Sjsg
105fb4d8502Sjsg CLOCK_SOURCE_COMBO_PHY_PLL0, /*combo PHY PLL defines (DC 11.2 and up)*/
106fb4d8502Sjsg CLOCK_SOURCE_COMBO_PHY_PLL1,
107fb4d8502Sjsg CLOCK_SOURCE_COMBO_PHY_PLL2,
108fb4d8502Sjsg CLOCK_SOURCE_COMBO_PHY_PLL3,
109fb4d8502Sjsg CLOCK_SOURCE_COMBO_PHY_PLL4,
110fb4d8502Sjsg CLOCK_SOURCE_COMBO_PHY_PLL5,
111fb4d8502Sjsg CLOCK_SOURCE_COMBO_DISPLAY_PLL0
112fb4d8502Sjsg };
113fb4d8502Sjsg
114fb4d8502Sjsg /* Encoder object ids */
115fb4d8502Sjsg enum encoder_id {
116fb4d8502Sjsg ENCODER_ID_UNKNOWN = 0,
117fb4d8502Sjsg
118fb4d8502Sjsg /* Radeon Class Display Hardware */
119fb4d8502Sjsg ENCODER_ID_INTERNAL_LVDS,
120fb4d8502Sjsg ENCODER_ID_INTERNAL_TMDS1,
121fb4d8502Sjsg ENCODER_ID_INTERNAL_TMDS2,
122fb4d8502Sjsg ENCODER_ID_INTERNAL_DAC1,
123fb4d8502Sjsg ENCODER_ID_INTERNAL_DAC2, /* TV/CV DAC */
124fb4d8502Sjsg
125fb4d8502Sjsg /* External Third Party Encoders */
126fb4d8502Sjsg ENCODER_ID_INTERNAL_LVTM1, /* not used for Radeon */
127fb4d8502Sjsg ENCODER_ID_INTERNAL_HDMI,
128fb4d8502Sjsg
129fb4d8502Sjsg /* Kaledisope (KLDSCP) Class Display Hardware */
130fb4d8502Sjsg ENCODER_ID_INTERNAL_KLDSCP_TMDS1,
131fb4d8502Sjsg ENCODER_ID_INTERNAL_KLDSCP_DAC1,
132fb4d8502Sjsg ENCODER_ID_INTERNAL_KLDSCP_DAC2, /* Shared with CV/TV and CRT */
133fb4d8502Sjsg /* External TMDS (dual link) */
134fb4d8502Sjsg ENCODER_ID_EXTERNAL_MVPU_FPGA, /* MVPU FPGA chip */
135fb4d8502Sjsg ENCODER_ID_INTERNAL_DDI,
136fb4d8502Sjsg ENCODER_ID_INTERNAL_UNIPHY,
137fb4d8502Sjsg ENCODER_ID_INTERNAL_KLDSCP_LVTMA,
138fb4d8502Sjsg ENCODER_ID_INTERNAL_UNIPHY1,
139fb4d8502Sjsg ENCODER_ID_INTERNAL_UNIPHY2,
140fb4d8502Sjsg ENCODER_ID_EXTERNAL_NUTMEG,
141fb4d8502Sjsg ENCODER_ID_EXTERNAL_TRAVIS,
142fb4d8502Sjsg
143fb4d8502Sjsg ENCODER_ID_INTERNAL_WIRELESS, /* Internal wireless display encoder */
144fb4d8502Sjsg ENCODER_ID_INTERNAL_UNIPHY3,
145fb4d8502Sjsg ENCODER_ID_INTERNAL_VIRTUAL,
146fb4d8502Sjsg };
147fb4d8502Sjsg
148fb4d8502Sjsg /* Connector object ids */
149fb4d8502Sjsg enum connector_id {
150fb4d8502Sjsg CONNECTOR_ID_UNKNOWN = 0,
151fb4d8502Sjsg CONNECTOR_ID_SINGLE_LINK_DVII = 1,
152fb4d8502Sjsg CONNECTOR_ID_DUAL_LINK_DVII = 2,
153fb4d8502Sjsg CONNECTOR_ID_SINGLE_LINK_DVID = 3,
154fb4d8502Sjsg CONNECTOR_ID_DUAL_LINK_DVID = 4,
155fb4d8502Sjsg CONNECTOR_ID_VGA = 5,
156fb4d8502Sjsg CONNECTOR_ID_HDMI_TYPE_A = 12,
157fb4d8502Sjsg CONNECTOR_ID_LVDS = 14,
158fb4d8502Sjsg CONNECTOR_ID_PCIE = 16,
159fb4d8502Sjsg CONNECTOR_ID_HARDCODE_DVI = 18,
160fb4d8502Sjsg CONNECTOR_ID_DISPLAY_PORT = 19,
161fb4d8502Sjsg CONNECTOR_ID_EDP = 20,
162fb4d8502Sjsg CONNECTOR_ID_MXM = 21,
163fb4d8502Sjsg CONNECTOR_ID_WIRELESS = 22,
164fb4d8502Sjsg CONNECTOR_ID_MIRACAST = 23,
165*1bb76ff1Sjsg CONNECTOR_ID_USBC = 24,
166fb4d8502Sjsg
167fb4d8502Sjsg CONNECTOR_ID_VIRTUAL = 100
168fb4d8502Sjsg };
169fb4d8502Sjsg
170fb4d8502Sjsg /* Audio object ids */
171fb4d8502Sjsg enum audio_id {
172fb4d8502Sjsg AUDIO_ID_UNKNOWN = 0,
173fb4d8502Sjsg AUDIO_ID_INTERNAL_AZALIA
174fb4d8502Sjsg };
175fb4d8502Sjsg
176fb4d8502Sjsg /* Engine object ids */
177fb4d8502Sjsg enum engine_id {
178fb4d8502Sjsg ENGINE_ID_DIGA,
179fb4d8502Sjsg ENGINE_ID_DIGB,
180fb4d8502Sjsg ENGINE_ID_DIGC,
181fb4d8502Sjsg ENGINE_ID_DIGD,
182fb4d8502Sjsg ENGINE_ID_DIGE,
183fb4d8502Sjsg ENGINE_ID_DIGF,
184fb4d8502Sjsg ENGINE_ID_DIGG,
185fb4d8502Sjsg ENGINE_ID_DACA,
186fb4d8502Sjsg ENGINE_ID_DACB,
187fb4d8502Sjsg ENGINE_ID_VCE, /* wireless display pseudo-encoder */
188*1bb76ff1Sjsg ENGINE_ID_HPO_0,
189*1bb76ff1Sjsg ENGINE_ID_HPO_1,
190*1bb76ff1Sjsg ENGINE_ID_HPO_DP_0,
191*1bb76ff1Sjsg ENGINE_ID_HPO_DP_1,
192*1bb76ff1Sjsg ENGINE_ID_HPO_DP_2,
193*1bb76ff1Sjsg ENGINE_ID_HPO_DP_3,
194fb4d8502Sjsg ENGINE_ID_VIRTUAL,
195fb4d8502Sjsg
196fb4d8502Sjsg ENGINE_ID_COUNT,
197fb4d8502Sjsg ENGINE_ID_UNKNOWN = (-1L)
198fb4d8502Sjsg };
199fb4d8502Sjsg
200fb4d8502Sjsg enum transmitter_color_depth {
201fb4d8502Sjsg TRANSMITTER_COLOR_DEPTH_24 = 0, /* 8 bits */
202fb4d8502Sjsg TRANSMITTER_COLOR_DEPTH_30, /* 10 bits */
203fb4d8502Sjsg TRANSMITTER_COLOR_DEPTH_36, /* 12 bits */
204fb4d8502Sjsg TRANSMITTER_COLOR_DEPTH_48 /* 16 bits */
205fb4d8502Sjsg };
206fb4d8502Sjsg
207fb4d8502Sjsg enum dp_alt_mode {
208fb4d8502Sjsg DP_Alt_mode__Unknown = 0,
209fb4d8502Sjsg DP_Alt_mode__Connect,
210fb4d8502Sjsg DP_Alt_mode__NoConnect,
211fb4d8502Sjsg };
212fb4d8502Sjsg /*
213fb4d8502Sjsg *****************************************************************************
214fb4d8502Sjsg * graphics_object_id struct
215fb4d8502Sjsg *
216fb4d8502Sjsg * graphics_object_id is a very simple struct wrapping 32bit Graphics
217fb4d8502Sjsg * Object identication
218fb4d8502Sjsg *
219fb4d8502Sjsg * This struct should stay very simple
220fb4d8502Sjsg * No dependencies at all (no includes)
221fb4d8502Sjsg * No debug messages or asserts
222fb4d8502Sjsg * No #ifndef and preprocessor directives
223fb4d8502Sjsg * No grow in space (no more data member)
224fb4d8502Sjsg *****************************************************************************
225fb4d8502Sjsg */
226fb4d8502Sjsg
227fb4d8502Sjsg struct graphics_object_id {
228fb4d8502Sjsg uint32_t id:8;
229fb4d8502Sjsg uint32_t enum_id:4;
230fb4d8502Sjsg uint32_t type:4;
231fb4d8502Sjsg uint32_t reserved:16; /* for padding. total size should be u32 */
232fb4d8502Sjsg };
233fb4d8502Sjsg
234fb4d8502Sjsg /* some simple functions for convenient graphics_object_id handle */
235fb4d8502Sjsg
dal_graphics_object_id_init(uint32_t id,enum object_enum_id enum_id,enum object_type type)236fb4d8502Sjsg static inline struct graphics_object_id dal_graphics_object_id_init(
237fb4d8502Sjsg uint32_t id,
238fb4d8502Sjsg enum object_enum_id enum_id,
239fb4d8502Sjsg enum object_type type)
240fb4d8502Sjsg {
241fb4d8502Sjsg struct graphics_object_id result = {
242fb4d8502Sjsg id, enum_id, type, 0
243fb4d8502Sjsg };
244fb4d8502Sjsg
245fb4d8502Sjsg return result;
246fb4d8502Sjsg }
247fb4d8502Sjsg
248fb4d8502Sjsg /* Based on internal data members memory layout */
dal_graphics_object_id_to_uint(struct graphics_object_id id)249fb4d8502Sjsg static inline uint32_t dal_graphics_object_id_to_uint(
250fb4d8502Sjsg struct graphics_object_id id)
251fb4d8502Sjsg {
252fb4d8502Sjsg return id.id + (id.enum_id << 0x8) + (id.type << 0xc);
253fb4d8502Sjsg }
254fb4d8502Sjsg
dal_graphics_object_id_get_controller_id(struct graphics_object_id id)255fb4d8502Sjsg static inline enum controller_id dal_graphics_object_id_get_controller_id(
256fb4d8502Sjsg struct graphics_object_id id)
257fb4d8502Sjsg {
258fb4d8502Sjsg if (id.type == OBJECT_TYPE_CONTROLLER)
259fb4d8502Sjsg return (enum controller_id) id.id;
260fb4d8502Sjsg return CONTROLLER_ID_UNDEFINED;
261fb4d8502Sjsg }
262fb4d8502Sjsg
dal_graphics_object_id_get_clock_source_id(struct graphics_object_id id)263fb4d8502Sjsg static inline enum clock_source_id dal_graphics_object_id_get_clock_source_id(
264fb4d8502Sjsg struct graphics_object_id id)
265fb4d8502Sjsg {
266fb4d8502Sjsg if (id.type == OBJECT_TYPE_CLOCK_SOURCE)
267fb4d8502Sjsg return (enum clock_source_id) id.id;
268fb4d8502Sjsg return CLOCK_SOURCE_ID_UNDEFINED;
269fb4d8502Sjsg }
270fb4d8502Sjsg
dal_graphics_object_id_get_encoder_id(struct graphics_object_id id)271fb4d8502Sjsg static inline enum encoder_id dal_graphics_object_id_get_encoder_id(
272fb4d8502Sjsg struct graphics_object_id id)
273fb4d8502Sjsg {
274fb4d8502Sjsg if (id.type == OBJECT_TYPE_ENCODER)
275fb4d8502Sjsg return (enum encoder_id) id.id;
276fb4d8502Sjsg return ENCODER_ID_UNKNOWN;
277fb4d8502Sjsg }
278fb4d8502Sjsg
dal_graphics_object_id_get_connector_id(struct graphics_object_id id)279fb4d8502Sjsg static inline enum connector_id dal_graphics_object_id_get_connector_id(
280fb4d8502Sjsg struct graphics_object_id id)
281fb4d8502Sjsg {
282fb4d8502Sjsg if (id.type == OBJECT_TYPE_CONNECTOR)
283fb4d8502Sjsg return (enum connector_id) id.id;
284fb4d8502Sjsg return CONNECTOR_ID_UNKNOWN;
285fb4d8502Sjsg }
286fb4d8502Sjsg
dal_graphics_object_id_get_audio_id(struct graphics_object_id id)287fb4d8502Sjsg static inline enum audio_id dal_graphics_object_id_get_audio_id(
288fb4d8502Sjsg struct graphics_object_id id)
289fb4d8502Sjsg {
290fb4d8502Sjsg if (id.type == OBJECT_TYPE_AUDIO)
291fb4d8502Sjsg return (enum audio_id) id.id;
292fb4d8502Sjsg return AUDIO_ID_UNKNOWN;
293fb4d8502Sjsg }
294fb4d8502Sjsg
dal_graphics_object_id_get_engine_id(struct graphics_object_id id)295fb4d8502Sjsg static inline enum engine_id dal_graphics_object_id_get_engine_id(
296fb4d8502Sjsg struct graphics_object_id id)
297fb4d8502Sjsg {
298fb4d8502Sjsg if (id.type == OBJECT_TYPE_ENGINE)
299fb4d8502Sjsg return (enum engine_id) id.id;
300fb4d8502Sjsg return ENGINE_ID_UNKNOWN;
301fb4d8502Sjsg }
302fb4d8502Sjsg
dal_graphics_object_id_equal(struct graphics_object_id id_1,struct graphics_object_id id_2)303fb4d8502Sjsg static inline bool dal_graphics_object_id_equal(
304fb4d8502Sjsg struct graphics_object_id id_1,
305fb4d8502Sjsg struct graphics_object_id id_2)
306fb4d8502Sjsg {
307fb4d8502Sjsg if ((id_1.id == id_2.id) && (id_1.enum_id == id_2.enum_id) &&
308fb4d8502Sjsg (id_1.type == id_2.type)) {
309fb4d8502Sjsg return true;
310fb4d8502Sjsg }
311fb4d8502Sjsg return false;
312fb4d8502Sjsg }
313fb4d8502Sjsg #endif
314