1fb4d8502Sjsg /* 2fb4d8502Sjsg * Copyright 2012-15 Advanced Micro Devices, Inc. 3fb4d8502Sjsg * 4fb4d8502Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5fb4d8502Sjsg * copy of this software and associated documentation files (the "Software"), 6fb4d8502Sjsg * to deal in the Software without restriction, including without limitation 7fb4d8502Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8fb4d8502Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9fb4d8502Sjsg * Software is furnished to do so, subject to the following conditions: 10fb4d8502Sjsg * 11fb4d8502Sjsg * The above copyright notice and this permission notice shall be included in 12fb4d8502Sjsg * all copies or substantial portions of the Software. 13fb4d8502Sjsg * 14fb4d8502Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15fb4d8502Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16fb4d8502Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17fb4d8502Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18fb4d8502Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19fb4d8502Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20fb4d8502Sjsg * OTHER DEALINGS IN THE SOFTWARE. 21fb4d8502Sjsg * 22fb4d8502Sjsg * Authors: AMD 23fb4d8502Sjsg * 24fb4d8502Sjsg */ 25fb4d8502Sjsg 26fb4d8502Sjsg #ifndef __DAL_GRPH_OBJECT_DEFS_H__ 27fb4d8502Sjsg #define __DAL_GRPH_OBJECT_DEFS_H__ 28fb4d8502Sjsg 29fb4d8502Sjsg #include "grph_object_id.h" 30fb4d8502Sjsg 31fb4d8502Sjsg /* ******************************************************************** 32fb4d8502Sjsg * ******************************************************************** 33fb4d8502Sjsg * 34fb4d8502Sjsg * These defines shared between All Graphics Objects 35fb4d8502Sjsg * 36fb4d8502Sjsg * ******************************************************************** 37fb4d8502Sjsg * ******************************************************************** 38fb4d8502Sjsg */ 39fb4d8502Sjsg 40fb4d8502Sjsg #define MAX_CONNECTOR_NUMBER_PER_SLOT (16) 41fb4d8502Sjsg #define MAX_BOARD_SLOTS (4) 42fb4d8502Sjsg #define INVALID_CONNECTOR_INDEX ((unsigned int)(-1)) 43fb4d8502Sjsg 44fb4d8502Sjsg /* HPD unit id - HW direct translation */ 45fb4d8502Sjsg enum hpd_source_id { 46fb4d8502Sjsg HPD_SOURCEID1 = 0, 47fb4d8502Sjsg HPD_SOURCEID2, 48fb4d8502Sjsg HPD_SOURCEID3, 49fb4d8502Sjsg HPD_SOURCEID4, 50fb4d8502Sjsg HPD_SOURCEID5, 51fb4d8502Sjsg HPD_SOURCEID6, 52fb4d8502Sjsg 53fb4d8502Sjsg HPD_SOURCEID_COUNT, 54fb4d8502Sjsg HPD_SOURCEID_UNKNOWN 55fb4d8502Sjsg }; 56fb4d8502Sjsg 57fb4d8502Sjsg /* DDC unit id - HW direct translation */ 58fb4d8502Sjsg enum channel_id { 59fb4d8502Sjsg CHANNEL_ID_UNKNOWN = 0, 60fb4d8502Sjsg CHANNEL_ID_DDC1, 61fb4d8502Sjsg CHANNEL_ID_DDC2, 62fb4d8502Sjsg CHANNEL_ID_DDC3, 63fb4d8502Sjsg CHANNEL_ID_DDC4, 64fb4d8502Sjsg CHANNEL_ID_DDC5, 65fb4d8502Sjsg CHANNEL_ID_DDC6, 66fb4d8502Sjsg CHANNEL_ID_DDC_VGA, 67fb4d8502Sjsg CHANNEL_ID_I2C_PAD, 68fb4d8502Sjsg CHANNEL_ID_COUNT 69fb4d8502Sjsg }; 70fb4d8502Sjsg 71fb4d8502Sjsg #define DECODE_CHANNEL_ID(ch_id) \ 72fb4d8502Sjsg (ch_id) == CHANNEL_ID_DDC1 ? "CHANNEL_ID_DDC1" : \ 73fb4d8502Sjsg (ch_id) == CHANNEL_ID_DDC2 ? "CHANNEL_ID_DDC2" : \ 74fb4d8502Sjsg (ch_id) == CHANNEL_ID_DDC3 ? "CHANNEL_ID_DDC3" : \ 75fb4d8502Sjsg (ch_id) == CHANNEL_ID_DDC4 ? "CHANNEL_ID_DDC4" : \ 76fb4d8502Sjsg (ch_id) == CHANNEL_ID_DDC5 ? "CHANNEL_ID_DDC5" : \ 77fb4d8502Sjsg (ch_id) == CHANNEL_ID_DDC6 ? "CHANNEL_ID_DDC6" : \ 78fb4d8502Sjsg (ch_id) == CHANNEL_ID_DDC_VGA ? "CHANNEL_ID_DDC_VGA" : \ 79fb4d8502Sjsg (ch_id) == CHANNEL_ID_I2C_PAD ? "CHANNEL_ID_I2C_PAD" : "Invalid" 80fb4d8502Sjsg 81fb4d8502Sjsg enum transmitter { 82fb4d8502Sjsg TRANSMITTER_UNKNOWN = (-1L), 83fb4d8502Sjsg TRANSMITTER_UNIPHY_A, 84fb4d8502Sjsg TRANSMITTER_UNIPHY_B, 85fb4d8502Sjsg TRANSMITTER_UNIPHY_C, 86fb4d8502Sjsg TRANSMITTER_UNIPHY_D, 87fb4d8502Sjsg TRANSMITTER_UNIPHY_E, 88fb4d8502Sjsg TRANSMITTER_UNIPHY_F, 89fb4d8502Sjsg TRANSMITTER_NUTMEG_CRT, 90fb4d8502Sjsg TRANSMITTER_TRAVIS_CRT, 91fb4d8502Sjsg TRANSMITTER_TRAVIS_LCD, 92fb4d8502Sjsg TRANSMITTER_UNIPHY_G, 93fb4d8502Sjsg TRANSMITTER_COUNT 94fb4d8502Sjsg }; 95fb4d8502Sjsg 96fb4d8502Sjsg /* Generic source of the synchronisation input/output signal */ 97fb4d8502Sjsg /* Can be used for flow control, stereo sync, timing sync, frame sync, etc */ 98fb4d8502Sjsg enum sync_source { 99fb4d8502Sjsg SYNC_SOURCE_NONE = 0, 100fb4d8502Sjsg 101fb4d8502Sjsg /* Source based on controllers */ 102fb4d8502Sjsg SYNC_SOURCE_CONTROLLER0, 103fb4d8502Sjsg SYNC_SOURCE_CONTROLLER1, 104fb4d8502Sjsg SYNC_SOURCE_CONTROLLER2, 105fb4d8502Sjsg SYNC_SOURCE_CONTROLLER3, 106fb4d8502Sjsg SYNC_SOURCE_CONTROLLER4, 107fb4d8502Sjsg SYNC_SOURCE_CONTROLLER5, 108fb4d8502Sjsg 109fb4d8502Sjsg /* Source based on GSL group */ 110fb4d8502Sjsg SYNC_SOURCE_GSL_GROUP0, 111fb4d8502Sjsg SYNC_SOURCE_GSL_GROUP1, 112fb4d8502Sjsg SYNC_SOURCE_GSL_GROUP2, 113fb4d8502Sjsg 114fb4d8502Sjsg /* Source based on GSL IOs */ 115fb4d8502Sjsg /* These IOs normally used as GSL input/output */ 116fb4d8502Sjsg SYNC_SOURCE_GSL_IO_FIRST, 117fb4d8502Sjsg SYNC_SOURCE_GSL_IO_GENLOCK_CLOCK = SYNC_SOURCE_GSL_IO_FIRST, 118fb4d8502Sjsg SYNC_SOURCE_GSL_IO_GENLOCK_VSYNC, 119fb4d8502Sjsg SYNC_SOURCE_GSL_IO_SWAPLOCK_A, 120fb4d8502Sjsg SYNC_SOURCE_GSL_IO_SWAPLOCK_B, 121fb4d8502Sjsg SYNC_SOURCE_GSL_IO_LAST = SYNC_SOURCE_GSL_IO_SWAPLOCK_B, 122fb4d8502Sjsg 123fb4d8502Sjsg /* Source based on regular IOs */ 124fb4d8502Sjsg SYNC_SOURCE_IO_FIRST, 125fb4d8502Sjsg SYNC_SOURCE_IO_GENERIC_A = SYNC_SOURCE_IO_FIRST, 126fb4d8502Sjsg SYNC_SOURCE_IO_GENERIC_B, 127fb4d8502Sjsg SYNC_SOURCE_IO_GENERIC_C, 128fb4d8502Sjsg SYNC_SOURCE_IO_GENERIC_D, 129fb4d8502Sjsg SYNC_SOURCE_IO_GENERIC_E, 130fb4d8502Sjsg SYNC_SOURCE_IO_GENERIC_F, 131fb4d8502Sjsg SYNC_SOURCE_IO_HPD1, 132fb4d8502Sjsg SYNC_SOURCE_IO_HPD2, 133fb4d8502Sjsg SYNC_SOURCE_IO_HSYNC_A, 134fb4d8502Sjsg SYNC_SOURCE_IO_VSYNC_A, 135fb4d8502Sjsg SYNC_SOURCE_IO_HSYNC_B, 136fb4d8502Sjsg SYNC_SOURCE_IO_VSYNC_B, 137fb4d8502Sjsg SYNC_SOURCE_IO_LAST = SYNC_SOURCE_IO_VSYNC_B, 138fb4d8502Sjsg 139fb4d8502Sjsg /* Misc. flow control sources */ 140fb4d8502Sjsg SYNC_SOURCE_DUAL_GPU_PIN 141fb4d8502Sjsg }; 142fb4d8502Sjsg 143*1bb76ff1Sjsg enum tx_ffe_id { 144*1bb76ff1Sjsg TX_FFE0 = 0, 145*1bb76ff1Sjsg TX_FFE1, 146*1bb76ff1Sjsg TX_FFE2, 147*1bb76ff1Sjsg TX_FFE3, 148*1bb76ff1Sjsg TX_FFE_DeEmphasis_Only, 149*1bb76ff1Sjsg TX_FFE_PreShoot_Only, 150*1bb76ff1Sjsg TX_FFE_No_FFE, 151*1bb76ff1Sjsg }; 152*1bb76ff1Sjsg 153fb4d8502Sjsg /* connector sizes in millimeters - from BiosParserTypes.hpp */ 154fb4d8502Sjsg #define CONNECTOR_SIZE_DVI 40 155fb4d8502Sjsg #define CONNECTOR_SIZE_VGA 32 156fb4d8502Sjsg #define CONNECTOR_SIZE_HDMI 16 157fb4d8502Sjsg #define CONNECTOR_SIZE_DP 16 158fb4d8502Sjsg #define CONNECTOR_SIZE_MINI_DP 9 159fb4d8502Sjsg #define CONNECTOR_SIZE_UNKNOWN 30 160fb4d8502Sjsg 161fb4d8502Sjsg enum connector_layout_type { 162fb4d8502Sjsg CONNECTOR_LAYOUT_TYPE_UNKNOWN, 163fb4d8502Sjsg CONNECTOR_LAYOUT_TYPE_DVI_D, 164fb4d8502Sjsg CONNECTOR_LAYOUT_TYPE_DVI_I, 165fb4d8502Sjsg CONNECTOR_LAYOUT_TYPE_VGA, 166fb4d8502Sjsg CONNECTOR_LAYOUT_TYPE_HDMI, 167fb4d8502Sjsg CONNECTOR_LAYOUT_TYPE_DP, 168fb4d8502Sjsg CONNECTOR_LAYOUT_TYPE_MINI_DP, 169fb4d8502Sjsg }; 170fb4d8502Sjsg struct connector_layout_info { 171fb4d8502Sjsg struct graphics_object_id connector_id; 172fb4d8502Sjsg enum connector_layout_type connector_type; 173fb4d8502Sjsg unsigned int length; 174fb4d8502Sjsg unsigned int position; /* offset in mm from right side of the board */ 175fb4d8502Sjsg }; 176fb4d8502Sjsg 177fb4d8502Sjsg /* length and width in mm */ 178fb4d8502Sjsg struct slot_layout_info { 179fb4d8502Sjsg unsigned int length; 180fb4d8502Sjsg unsigned int width; 181fb4d8502Sjsg unsigned int num_of_connectors; 182fb4d8502Sjsg struct connector_layout_info connectors[MAX_CONNECTOR_NUMBER_PER_SLOT]; 183fb4d8502Sjsg }; 184fb4d8502Sjsg 185fb4d8502Sjsg struct board_layout_info { 186fb4d8502Sjsg unsigned int num_of_slots; 187fb4d8502Sjsg 188fb4d8502Sjsg /* indicates valid information in bracket layout structure. */ 189fb4d8502Sjsg unsigned int is_number_of_slots_valid : 1; 190fb4d8502Sjsg unsigned int is_slots_size_valid : 1; 191fb4d8502Sjsg unsigned int is_connector_offsets_valid : 1; 192fb4d8502Sjsg unsigned int is_connector_lengths_valid : 1; 193fb4d8502Sjsg 194fb4d8502Sjsg struct slot_layout_info slots[MAX_BOARD_SLOTS]; 195fb4d8502Sjsg }; 196fb4d8502Sjsg #endif 197