1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 //<DMUB_TYPES>================================================================== 48 /* Basic type definitions. */ 49 50 #define __forceinline inline 51 52 /** 53 * Flag from driver to indicate that ABM should be disabled gradually 54 * by slowly reversing all backlight programming and pixel compensation. 55 */ 56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 57 58 /** 59 * Flag from driver to indicate that ABM should be disabled immediately 60 * and undo all backlight programming and pixel compensation. 61 */ 62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 63 64 /** 65 * Flag from driver to indicate that ABM should be disabled immediately 66 * and keep the current backlight programming and pixel compensation. 67 */ 68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 69 70 /** 71 * Flag from driver to set the current ABM pipe index or ABM operating level. 72 */ 73 #define SET_ABM_PIPE_NORMAL 1 74 75 /** 76 * Number of ambient light levels in ABM algorithm. 77 */ 78 #define NUM_AMBI_LEVEL 5 79 80 /** 81 * Number of operating/aggression levels in ABM algorithm. 82 */ 83 #define NUM_AGGR_LEVEL 4 84 85 /** 86 * Number of segments in the gamma curve. 87 */ 88 #define NUM_POWER_FN_SEGS 8 89 90 /** 91 * Number of segments in the backlight curve. 92 */ 93 #define NUM_BL_CURVE_SEGS 16 94 95 /* Maximum number of SubVP streams */ 96 #define DMUB_MAX_SUBVP_STREAMS 2 97 98 /* Maximum number of streams on any ASIC. */ 99 #define DMUB_MAX_STREAMS 6 100 101 /* Maximum number of planes on any ASIC. */ 102 #define DMUB_MAX_PLANES 6 103 104 /* Trace buffer offset for entry */ 105 #define TRACE_BUFFER_ENTRY_OFFSET 16 106 107 /** 108 * Maximum number of dirty rects supported by FW. 109 */ 110 #define DMUB_MAX_DIRTY_RECTS 3 111 112 /** 113 * 114 * PSR control version legacy 115 */ 116 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 117 /** 118 * PSR control version with multi edp support 119 */ 120 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 121 122 123 /** 124 * ABM control version legacy 125 */ 126 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 127 128 /** 129 * ABM control version with multi edp support 130 */ 131 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 132 133 /** 134 * Physical framebuffer address location, 64-bit. 135 */ 136 #ifndef PHYSICAL_ADDRESS_LOC 137 #define PHYSICAL_ADDRESS_LOC union large_integer 138 #endif 139 140 /** 141 * OS/FW agnostic memcpy 142 */ 143 #ifndef dmub_memcpy 144 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 145 #endif 146 147 /** 148 * OS/FW agnostic memset 149 */ 150 #ifndef dmub_memset 151 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 152 #endif 153 154 #if defined(__cplusplus) 155 extern "C" { 156 #endif 157 158 /** 159 * OS/FW agnostic udelay 160 */ 161 #ifndef dmub_udelay 162 #define dmub_udelay(microseconds) udelay(microseconds) 163 #endif 164 165 #pragma pack(push, 1) 166 /** 167 * union dmub_addr - DMUB physical/virtual 64-bit address. 168 */ 169 union dmub_addr { 170 struct { 171 uint32_t low_part; /**< Lower 32 bits */ 172 uint32_t high_part; /**< Upper 32 bits */ 173 } u; /*<< Low/high bit access */ 174 uint64_t quad_part; /*<< 64 bit address */ 175 }; 176 #pragma pack(pop) 177 178 /** 179 * Dirty rect definition. 180 */ 181 struct dmub_rect { 182 /** 183 * Dirty rect x offset. 184 */ 185 uint32_t x; 186 187 /** 188 * Dirty rect y offset. 189 */ 190 uint32_t y; 191 192 /** 193 * Dirty rect width. 194 */ 195 uint32_t width; 196 197 /** 198 * Dirty rect height. 199 */ 200 uint32_t height; 201 }; 202 203 /** 204 * Flags that can be set by driver to change some PSR behaviour. 205 */ 206 union dmub_psr_debug_flags { 207 /** 208 * Debug flags. 209 */ 210 struct { 211 /** 212 * Enable visual confirm in FW. 213 */ 214 uint32_t visual_confirm : 1; 215 216 /** 217 * Force all selective updates to bw full frame updates. 218 */ 219 uint32_t force_full_frame_update : 1; 220 221 /** 222 * Use HW Lock Mgr object to do HW locking in FW. 223 */ 224 uint32_t use_hw_lock_mgr : 1; 225 226 /** 227 * Use TPS3 signal when restore main link. 228 */ 229 uint32_t force_wakeup_by_tps3 : 1; 230 } bitfields; 231 232 /** 233 * Union for debug flags. 234 */ 235 uint32_t u32All; 236 }; 237 238 /** 239 * DMUB visual confirm color 240 */ 241 struct dmub_feature_caps { 242 /** 243 * Max PSR version supported by FW. 244 */ 245 uint8_t psr; 246 uint8_t fw_assisted_mclk_switch; 247 uint8_t reserved[6]; 248 }; 249 250 struct dmub_visual_confirm_color { 251 /** 252 * Maximum 10 bits color value 253 */ 254 uint16_t color_r_cr; 255 uint16_t color_g_y; 256 uint16_t color_b_cb; 257 uint16_t panel_inst; 258 }; 259 260 #if defined(__cplusplus) 261 } 262 #endif 263 264 //============================================================================== 265 //</DMUB_TYPES>================================================================= 266 //============================================================================== 267 //< DMUB_META>================================================================== 268 //============================================================================== 269 #pragma pack(push, 1) 270 271 /* Magic value for identifying dmub_fw_meta_info */ 272 #define DMUB_FW_META_MAGIC 0x444D5542 273 274 /* Offset from the end of the file to the dmub_fw_meta_info */ 275 #define DMUB_FW_META_OFFSET 0x24 276 277 /** 278 * struct dmub_fw_meta_info - metadata associated with fw binary 279 * 280 * NOTE: This should be considered a stable API. Fields should 281 * not be repurposed or reordered. New fields should be 282 * added instead to extend the structure. 283 * 284 * @magic_value: magic value identifying DMUB firmware meta info 285 * @fw_region_size: size of the firmware state region 286 * @trace_buffer_size: size of the tracebuffer region 287 * @fw_version: the firmware version information 288 * @dal_fw: 1 if the firmware is DAL 289 */ 290 struct dmub_fw_meta_info { 291 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 292 uint32_t fw_region_size; /**< size of the firmware state region */ 293 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 294 uint32_t fw_version; /**< the firmware version information */ 295 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 296 uint8_t reserved[3]; /**< padding bits */ 297 }; 298 299 /** 300 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 301 */ 302 union dmub_fw_meta { 303 struct dmub_fw_meta_info info; /**< metadata info */ 304 uint8_t reserved[64]; /**< padding bits */ 305 }; 306 307 #pragma pack(pop) 308 309 //============================================================================== 310 //< DMUB Trace Buffer>================================================================ 311 //============================================================================== 312 /** 313 * dmub_trace_code_t - firmware trace code, 32-bits 314 */ 315 typedef uint32_t dmub_trace_code_t; 316 317 /** 318 * struct dmcub_trace_buf_entry - Firmware trace entry 319 */ 320 struct dmcub_trace_buf_entry { 321 dmub_trace_code_t trace_code; /**< trace code for the event */ 322 uint32_t tick_count; /**< the tick count at time of trace */ 323 uint32_t param0; /**< trace defined parameter 0 */ 324 uint32_t param1; /**< trace defined parameter 1 */ 325 }; 326 327 //============================================================================== 328 //< DMUB_STATUS>================================================================ 329 //============================================================================== 330 331 /** 332 * DMCUB scratch registers can be used to determine firmware status. 333 * Current scratch register usage is as follows: 334 * 335 * SCRATCH0: FW Boot Status register 336 * SCRATCH5: LVTMA Status Register 337 * SCRATCH15: FW Boot Options register 338 */ 339 340 /** 341 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 342 */ 343 union dmub_fw_boot_status { 344 struct { 345 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 346 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 347 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 348 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 349 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 350 uint32_t reserved : 1; 351 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 352 353 } bits; /**< status bits */ 354 uint32_t all; /**< 32-bit access to status bits */ 355 }; 356 357 /** 358 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 359 */ 360 enum dmub_fw_boot_status_bit { 361 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 362 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 363 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 364 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 365 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 366 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 367 }; 368 369 /* Register bit definition for SCRATCH5 */ 370 union dmub_lvtma_status { 371 struct { 372 uint32_t psp_ok : 1; 373 uint32_t edp_on : 1; 374 uint32_t reserved : 30; 375 } bits; 376 uint32_t all; 377 }; 378 379 enum dmub_lvtma_status_bit { 380 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 381 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 382 }; 383 384 /** 385 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 386 */ 387 union dmub_fw_boot_options { 388 struct { 389 uint32_t pemu_env : 1; /**< 1 if PEMU */ 390 uint32_t fpga_env : 1; /**< 1 if FPGA */ 391 uint32_t optimized_init : 1; /**< 1 if optimized init */ 392 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 393 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 394 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 395 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 396 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 397 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 398 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 399 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 400 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 401 uint32_t power_optimization: 1; 402 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 403 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 404 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 405 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 406 407 uint32_t reserved : 16; /**< reserved */ 408 } bits; /**< boot bits */ 409 uint32_t all; /**< 32-bit access to bits */ 410 }; 411 412 enum dmub_fw_boot_options_bit { 413 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 414 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 415 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 416 }; 417 418 //============================================================================== 419 //</DMUB_STATUS>================================================================ 420 //============================================================================== 421 //< DMUB_VBIOS>================================================================= 422 //============================================================================== 423 424 /* 425 * enum dmub_cmd_vbios_type - VBIOS commands. 426 * 427 * Command IDs should be treated as stable ABI. 428 * Do not reuse or modify IDs. 429 */ 430 enum dmub_cmd_vbios_type { 431 /** 432 * Configures the DIG encoder. 433 */ 434 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 435 /** 436 * Controls the PHY. 437 */ 438 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 439 /** 440 * Sets the pixel clock/symbol clock. 441 */ 442 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 443 /** 444 * Enables or disables power gating. 445 */ 446 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 447 /** 448 * Controls embedded panels. 449 */ 450 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 451 /** 452 * Query DP alt status on a transmitter. 453 */ 454 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 455 /** 456 * Controls domain power gating 457 */ 458 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 459 }; 460 461 //============================================================================== 462 //</DMUB_VBIOS>================================================================= 463 //============================================================================== 464 //< DMUB_GPINT>================================================================= 465 //============================================================================== 466 467 /** 468 * The shifts and masks below may alternatively be used to format and read 469 * the command register bits. 470 */ 471 472 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 473 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 474 475 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 476 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 477 478 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 479 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 480 481 /** 482 * Command responses. 483 */ 484 485 /** 486 * Return response for DMUB_GPINT__STOP_FW command. 487 */ 488 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 489 490 /** 491 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 492 */ 493 union dmub_gpint_data_register { 494 struct { 495 uint32_t param : 16; /**< 16-bit parameter */ 496 uint32_t command_code : 12; /**< GPINT command */ 497 uint32_t status : 4; /**< Command status bit */ 498 } bits; /**< GPINT bit access */ 499 uint32_t all; /**< GPINT 32-bit access */ 500 }; 501 502 /* 503 * enum dmub_gpint_command - GPINT command to DMCUB FW 504 * 505 * Command IDs should be treated as stable ABI. 506 * Do not reuse or modify IDs. 507 */ 508 enum dmub_gpint_command { 509 /** 510 * Invalid command, ignored. 511 */ 512 DMUB_GPINT__INVALID_COMMAND = 0, 513 /** 514 * DESC: Queries the firmware version. 515 * RETURN: Firmware version. 516 */ 517 DMUB_GPINT__GET_FW_VERSION = 1, 518 /** 519 * DESC: Halts the firmware. 520 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 521 */ 522 DMUB_GPINT__STOP_FW = 2, 523 /** 524 * DESC: Get PSR state from FW. 525 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 526 */ 527 DMUB_GPINT__GET_PSR_STATE = 7, 528 /** 529 * DESC: Notifies DMCUB of the currently active streams. 530 * ARGS: Stream mask, 1 bit per active stream index. 531 */ 532 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 533 /** 534 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 535 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 536 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 537 * RETURN: PSR residency in milli-percent. 538 */ 539 DMUB_GPINT__PSR_RESIDENCY = 9, 540 541 /** 542 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 543 */ 544 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 545 }; 546 547 /** 548 * INBOX0 generic command definition 549 */ 550 union dmub_inbox0_cmd_common { 551 struct { 552 uint32_t command_code: 8; /**< INBOX0 command code */ 553 uint32_t param: 24; /**< 24-bit parameter */ 554 } bits; 555 uint32_t all; 556 }; 557 558 /** 559 * INBOX0 hw_lock command definition 560 */ 561 union dmub_inbox0_cmd_lock_hw { 562 struct { 563 uint32_t command_code: 8; 564 565 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 566 uint32_t hw_lock_client: 2; 567 568 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 569 uint32_t otg_inst: 3; 570 uint32_t opp_inst: 3; 571 uint32_t dig_inst: 3; 572 573 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 574 uint32_t lock_pipe: 1; 575 uint32_t lock_cursor: 1; 576 uint32_t lock_dig: 1; 577 uint32_t triple_buffer_lock: 1; 578 579 uint32_t lock: 1; /**< Lock */ 580 uint32_t should_release: 1; /**< Release */ 581 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 582 } bits; 583 uint32_t all; 584 }; 585 586 union dmub_inbox0_data_register { 587 union dmub_inbox0_cmd_common inbox0_cmd_common; 588 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 589 }; 590 591 enum dmub_inbox0_command { 592 /** 593 * DESC: Invalid command, ignored. 594 */ 595 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 596 /** 597 * DESC: Notification to acquire/release HW lock 598 * ARGS: 599 */ 600 DMUB_INBOX0_CMD__HW_LOCK = 1, 601 }; 602 //============================================================================== 603 //</DMUB_GPINT>================================================================= 604 //============================================================================== 605 //< DMUB_CMD>=================================================================== 606 //============================================================================== 607 608 /** 609 * Size in bytes of each DMUB command. 610 */ 611 #define DMUB_RB_CMD_SIZE 64 612 613 /** 614 * Maximum number of items in the DMUB ringbuffer. 615 */ 616 #define DMUB_RB_MAX_ENTRY 128 617 618 /** 619 * Ringbuffer size in bytes. 620 */ 621 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 622 623 /** 624 * REG_SET mask for reg offload. 625 */ 626 #define REG_SET_MASK 0xFFFF 627 628 /* 629 * enum dmub_cmd_type - DMUB inbox command. 630 * 631 * Command IDs should be treated as stable ABI. 632 * Do not reuse or modify IDs. 633 */ 634 enum dmub_cmd_type { 635 /** 636 * Invalid command. 637 */ 638 DMUB_CMD__NULL = 0, 639 /** 640 * Read modify write register sequence offload. 641 */ 642 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 643 /** 644 * Field update register sequence offload. 645 */ 646 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 647 /** 648 * Burst write sequence offload. 649 */ 650 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 651 /** 652 * Reg wait sequence offload. 653 */ 654 DMUB_CMD__REG_REG_WAIT = 4, 655 /** 656 * Workaround to avoid HUBP underflow during NV12 playback. 657 */ 658 DMUB_CMD__PLAT_54186_WA = 5, 659 /** 660 * Command type used to query FW feature caps. 661 */ 662 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 663 /** 664 * Command type used to get visual confirm color. 665 */ 666 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 667 /** 668 * Command type used for all PSR commands. 669 */ 670 DMUB_CMD__PSR = 64, 671 /** 672 * Command type used for all MALL commands. 673 */ 674 DMUB_CMD__MALL = 65, 675 /** 676 * Command type used for all ABM commands. 677 */ 678 DMUB_CMD__ABM = 66, 679 /** 680 * Command type used to update dirty rects in FW. 681 */ 682 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 683 /** 684 * Command type used to update cursor info in FW. 685 */ 686 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 687 /** 688 * Command type used for HW locking in FW. 689 */ 690 DMUB_CMD__HW_LOCK = 69, 691 /** 692 * Command type used to access DP AUX. 693 */ 694 DMUB_CMD__DP_AUX_ACCESS = 70, 695 /** 696 * Command type used for OUTBOX1 notification enable 697 */ 698 DMUB_CMD__OUTBOX1_ENABLE = 71, 699 700 /** 701 * Command type used for all idle optimization commands. 702 */ 703 DMUB_CMD__IDLE_OPT = 72, 704 /** 705 * Command type used for all clock manager commands. 706 */ 707 DMUB_CMD__CLK_MGR = 73, 708 /** 709 * Command type used for all panel control commands. 710 */ 711 DMUB_CMD__PANEL_CNTL = 74, 712 /** 713 * Command type used for <TODO:description> 714 */ 715 DMUB_CMD__CAB_FOR_SS = 75, 716 717 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 718 719 /** 720 * Command type used for interfacing with DPIA. 721 */ 722 DMUB_CMD__DPIA = 77, 723 /** 724 * Command type used for EDID CEA parsing 725 */ 726 DMUB_CMD__EDID_CEA = 79, 727 /** 728 * Command type used for getting usbc cable ID 729 */ 730 DMUB_CMD_GET_USBC_CABLE_ID = 81, 731 /** 732 * Command type used to query HPD state. 733 */ 734 DMUB_CMD__QUERY_HPD_STATE = 82, 735 /** 736 * Command type used for all VBIOS interface commands. 737 */ 738 739 /** 740 * Command type used to set DPIA HPD interrupt state 741 */ 742 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 743 744 DMUB_CMD__VBIOS = 128, 745 }; 746 747 /** 748 * enum dmub_out_cmd_type - DMUB outbox commands. 749 */ 750 enum dmub_out_cmd_type { 751 /** 752 * Invalid outbox command, ignored. 753 */ 754 DMUB_OUT_CMD__NULL = 0, 755 /** 756 * Command type used for DP AUX Reply data notification 757 */ 758 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 759 /** 760 * Command type used for DP HPD event notification 761 */ 762 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 763 /** 764 * Command type used for SET_CONFIG Reply notification 765 */ 766 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 767 }; 768 769 /* DMUB_CMD__DPIA command sub-types. */ 770 enum dmub_cmd_dpia_type { 771 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 772 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 773 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 774 }; 775 776 #pragma pack(push, 1) 777 778 /** 779 * struct dmub_cmd_header - Common command header fields. 780 */ 781 struct dmub_cmd_header { 782 unsigned int type : 8; /**< command type */ 783 unsigned int sub_type : 8; /**< command sub type */ 784 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 785 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 786 unsigned int reserved0 : 6; /**< reserved bits */ 787 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 788 unsigned int reserved1 : 2; /**< reserved bits */ 789 }; 790 791 /* 792 * struct dmub_cmd_read_modify_write_sequence - Read modify write 793 * 794 * 60 payload bytes can hold up to 5 sets of read modify writes, 795 * each take 3 dwords. 796 * 797 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 798 * 799 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 800 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 801 */ 802 struct dmub_cmd_read_modify_write_sequence { 803 uint32_t addr; /**< register address */ 804 uint32_t modify_mask; /**< modify mask */ 805 uint32_t modify_value; /**< modify value */ 806 }; 807 808 /** 809 * Maximum number of ops in read modify write sequence. 810 */ 811 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 812 813 /** 814 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 815 */ 816 struct dmub_rb_cmd_read_modify_write { 817 struct dmub_cmd_header header; /**< command header */ 818 /** 819 * Read modify write sequence. 820 */ 821 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 822 }; 823 824 /* 825 * Update a register with specified masks and values sequeunce 826 * 827 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 828 * 829 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 830 * 831 * 832 * USE CASE: 833 * 1. auto-increment register where additional read would update pointer and produce wrong result 834 * 2. toggle a bit without read in the middle 835 */ 836 837 struct dmub_cmd_reg_field_update_sequence { 838 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 839 uint32_t modify_value; /**< value to update with */ 840 }; 841 842 /** 843 * Maximum number of ops in field update sequence. 844 */ 845 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 846 847 /** 848 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 849 */ 850 struct dmub_rb_cmd_reg_field_update_sequence { 851 struct dmub_cmd_header header; /**< command header */ 852 uint32_t addr; /**< register address */ 853 /** 854 * Field update sequence. 855 */ 856 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 857 }; 858 859 860 /** 861 * Maximum number of burst write values. 862 */ 863 #define DMUB_BURST_WRITE_VALUES__MAX 14 864 865 /* 866 * struct dmub_rb_cmd_burst_write - Burst write 867 * 868 * support use case such as writing out LUTs. 869 * 870 * 60 payload bytes can hold up to 14 values to write to given address 871 * 872 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 873 */ 874 struct dmub_rb_cmd_burst_write { 875 struct dmub_cmd_header header; /**< command header */ 876 uint32_t addr; /**< register start address */ 877 /** 878 * Burst write register values. 879 */ 880 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 881 }; 882 883 /** 884 * struct dmub_rb_cmd_common - Common command header 885 */ 886 struct dmub_rb_cmd_common { 887 struct dmub_cmd_header header; /**< command header */ 888 /** 889 * Padding to RB_CMD_SIZE 890 */ 891 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 892 }; 893 894 /** 895 * struct dmub_cmd_reg_wait_data - Register wait data 896 */ 897 struct dmub_cmd_reg_wait_data { 898 uint32_t addr; /**< Register address */ 899 uint32_t mask; /**< Mask for register bits */ 900 uint32_t condition_field_value; /**< Value to wait for */ 901 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 902 }; 903 904 /** 905 * struct dmub_rb_cmd_reg_wait - Register wait command 906 */ 907 struct dmub_rb_cmd_reg_wait { 908 struct dmub_cmd_header header; /**< Command header */ 909 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 910 }; 911 912 /** 913 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 914 * 915 * Reprograms surface parameters to avoid underflow. 916 */ 917 struct dmub_cmd_PLAT_54186_wa { 918 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 919 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 920 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 921 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 922 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 923 struct { 924 uint8_t hubp_inst : 4; /**< HUBP instance */ 925 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 926 uint8_t immediate :1; /**< Immediate flip */ 927 uint8_t vmid : 4; /**< VMID */ 928 uint8_t grph_stereo : 1; /**< 1 if stereo */ 929 uint32_t reserved : 21; /**< Reserved */ 930 } flip_params; /**< Pageflip parameters */ 931 uint32_t reserved[9]; /**< Reserved bits */ 932 }; 933 934 /** 935 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 936 */ 937 struct dmub_rb_cmd_PLAT_54186_wa { 938 struct dmub_cmd_header header; /**< Command header */ 939 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 940 }; 941 942 /** 943 * struct dmub_rb_cmd_mall - MALL command data. 944 */ 945 struct dmub_rb_cmd_mall { 946 struct dmub_cmd_header header; /**< Common command header */ 947 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 948 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 949 uint32_t tmr_delay; /**< Timer delay */ 950 uint32_t tmr_scale; /**< Timer scale */ 951 uint16_t cursor_width; /**< Cursor width in pixels */ 952 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 953 uint16_t cursor_height; /**< Cursor height in pixels */ 954 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 955 uint8_t debug_bits; /**< Debug bits */ 956 957 uint8_t reserved1; /**< Reserved bits */ 958 uint8_t reserved2; /**< Reserved bits */ 959 }; 960 961 /** 962 * enum dmub_cmd_cab_type - TODO: 963 */ 964 enum dmub_cmd_cab_type { 965 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 966 DMUB_CMD__CAB_NO_DCN_REQ = 1, 967 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 968 }; 969 970 /** 971 * struct dmub_rb_cmd_cab_for_ss - TODO: 972 */ 973 struct dmub_rb_cmd_cab_for_ss { 974 struct dmub_cmd_header header; 975 uint8_t cab_alloc_ways; /* total number of ways */ 976 uint8_t debug_bits; /* debug bits */ 977 }; 978 979 enum mclk_switch_mode { 980 NONE = 0, 981 FPO = 1, 982 SUBVP = 2, 983 VBLANK = 3, 984 }; 985 986 /* Per pipe struct which stores the MCLK switch mode 987 * data to be sent to DMUB. 988 * Named "v2" for now -- once FPO and SUBVP are fully merged 989 * the type name can be updated 990 */ 991 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 992 union { 993 struct { 994 uint32_t pix_clk_100hz; 995 uint16_t main_vblank_start; 996 uint16_t main_vblank_end; 997 uint16_t mall_region_lines; 998 uint16_t prefetch_lines; 999 uint16_t prefetch_to_mall_start_lines; 1000 uint16_t processing_delay_lines; 1001 uint16_t htotal; // required to calculate line time for multi-display cases 1002 uint16_t vtotal; 1003 uint8_t main_pipe_index; 1004 uint8_t phantom_pipe_index; 1005 /* Since the microschedule is calculated in terms of OTG lines, 1006 * include any scaling factors to make sure when we get accurate 1007 * conversion when programming MALL_START_LINE (which is in terms 1008 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1009 * is 1/2 (numerator = 1, denominator = 2). 1010 */ 1011 uint8_t scale_factor_numerator; 1012 uint8_t scale_factor_denominator; 1013 uint8_t is_drr; 1014 uint8_t main_split_pipe_index; 1015 uint8_t phantom_split_pipe_index; 1016 } subvp_data; 1017 1018 struct { 1019 uint32_t pix_clk_100hz; 1020 uint16_t vblank_start; 1021 uint16_t vblank_end; 1022 uint16_t vstartup_start; 1023 uint16_t vtotal; 1024 uint16_t htotal; 1025 uint8_t vblank_pipe_index; 1026 uint8_t padding[2]; 1027 struct { 1028 uint8_t drr_in_use; 1029 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1030 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1031 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1032 uint8_t use_ramping; // Use ramping or not 1033 } drr_info; // DRR considered as part of SubVP + VBLANK case 1034 } vblank_data; 1035 } pipe_config; 1036 1037 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1038 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1039 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1040 */ 1041 uint8_t mode; // enum mclk_switch_mode 1042 }; 1043 1044 /** 1045 * Config data for Sub-VP and FPO 1046 * Named "v2" for now -- once FPO and SUBVP are fully merged 1047 * the type name can be updated 1048 */ 1049 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1050 uint16_t watermark_a_cache; 1051 uint8_t vertical_int_margin_us; 1052 uint8_t pstate_allow_width_us; 1053 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1054 }; 1055 1056 /** 1057 * DMUB rb command definition for Sub-VP and FPO 1058 * Named "v2" for now -- once FPO and SUBVP are fully merged 1059 * the type name can be updated 1060 */ 1061 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1062 struct dmub_cmd_header header; 1063 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1064 }; 1065 1066 /** 1067 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1068 */ 1069 enum dmub_cmd_idle_opt_type { 1070 /** 1071 * DCN hardware restore. 1072 */ 1073 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1074 1075 /** 1076 * DCN hardware save. 1077 */ 1078 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 1079 }; 1080 1081 /** 1082 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1083 */ 1084 struct dmub_rb_cmd_idle_opt_dcn_restore { 1085 struct dmub_cmd_header header; /**< header */ 1086 }; 1087 1088 /** 1089 * struct dmub_clocks - Clock update notification. 1090 */ 1091 struct dmub_clocks { 1092 uint32_t dispclk_khz; /**< dispclk kHz */ 1093 uint32_t dppclk_khz; /**< dppclk kHz */ 1094 uint32_t dcfclk_khz; /**< dcfclk kHz */ 1095 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1096 }; 1097 1098 /** 1099 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1100 */ 1101 enum dmub_cmd_clk_mgr_type { 1102 /** 1103 * Notify DMCUB of clock update. 1104 */ 1105 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1106 }; 1107 1108 /** 1109 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1110 */ 1111 struct dmub_rb_cmd_clk_mgr_notify_clocks { 1112 struct dmub_cmd_header header; /**< header */ 1113 struct dmub_clocks clocks; /**< clock data */ 1114 }; 1115 1116 /** 1117 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1118 */ 1119 struct dmub_cmd_digx_encoder_control_data { 1120 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1121 }; 1122 1123 /** 1124 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1125 */ 1126 struct dmub_rb_cmd_digx_encoder_control { 1127 struct dmub_cmd_header header; /**< header */ 1128 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1129 }; 1130 1131 /** 1132 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1133 */ 1134 struct dmub_cmd_set_pixel_clock_data { 1135 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1136 }; 1137 1138 /** 1139 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1140 */ 1141 struct dmub_rb_cmd_set_pixel_clock { 1142 struct dmub_cmd_header header; /**< header */ 1143 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1144 }; 1145 1146 /** 1147 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1148 */ 1149 struct dmub_cmd_enable_disp_power_gating_data { 1150 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1151 }; 1152 1153 /** 1154 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1155 */ 1156 struct dmub_rb_cmd_enable_disp_power_gating { 1157 struct dmub_cmd_header header; /**< header */ 1158 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1159 }; 1160 1161 /** 1162 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1163 */ 1164 struct dmub_dig_transmitter_control_data_v1_7 { 1165 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1166 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1167 union { 1168 uint8_t digmode; /**< enum atom_encode_mode_def */ 1169 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1170 } mode_laneset; 1171 uint8_t lanenum; /**< Number of lanes */ 1172 union { 1173 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1174 } symclk_units; 1175 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1176 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1177 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1178 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1179 uint8_t reserved1; /**< For future use */ 1180 uint8_t reserved2[3]; /**< For future use */ 1181 uint32_t reserved3[11]; /**< For future use */ 1182 }; 1183 1184 /** 1185 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1186 */ 1187 union dmub_cmd_dig1_transmitter_control_data { 1188 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1189 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1190 }; 1191 1192 /** 1193 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1194 */ 1195 struct dmub_rb_cmd_dig1_transmitter_control { 1196 struct dmub_cmd_header header; /**< header */ 1197 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1198 }; 1199 1200 /** 1201 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 1202 */ 1203 struct dmub_rb_cmd_domain_control_data { 1204 uint8_t inst : 6; /**< DOMAIN instance to control */ 1205 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 1206 uint8_t reserved[3]; /**< Reserved for future use */ 1207 }; 1208 1209 /** 1210 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 1211 */ 1212 struct dmub_rb_cmd_domain_control { 1213 struct dmub_cmd_header header; /**< header */ 1214 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 1215 }; 1216 1217 /** 1218 * DPIA tunnel command parameters. 1219 */ 1220 struct dmub_cmd_dig_dpia_control_data { 1221 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1222 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1223 union { 1224 uint8_t digmode; /** enum atom_encode_mode_def */ 1225 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1226 } mode_laneset; 1227 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1228 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1229 uint8_t hpdsel; /** =0: HPD is not assigned */ 1230 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1231 uint8_t dpia_id; /** Index of DPIA */ 1232 uint8_t fec_rdy : 1; 1233 uint8_t reserved : 7; 1234 uint32_t reserved1; 1235 }; 1236 1237 /** 1238 * DMUB command for DPIA tunnel control. 1239 */ 1240 struct dmub_rb_cmd_dig1_dpia_control { 1241 struct dmub_cmd_header header; 1242 struct dmub_cmd_dig_dpia_control_data dpia_control; 1243 }; 1244 1245 /** 1246 * SET_CONFIG Command Payload 1247 */ 1248 struct set_config_cmd_payload { 1249 uint8_t msg_type; /* set config message type */ 1250 uint8_t msg_data; /* set config message data */ 1251 }; 1252 1253 /** 1254 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1255 */ 1256 struct dmub_cmd_set_config_control_data { 1257 struct set_config_cmd_payload cmd_pkt; 1258 uint8_t instance; /* DPIA instance */ 1259 uint8_t immed_status; /* Immediate status returned in case of error */ 1260 }; 1261 1262 /** 1263 * DMUB command structure for SET_CONFIG command. 1264 */ 1265 struct dmub_rb_cmd_set_config_access { 1266 struct dmub_cmd_header header; /* header */ 1267 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1268 }; 1269 1270 /** 1271 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1272 */ 1273 struct dmub_cmd_mst_alloc_slots_control_data { 1274 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1275 uint8_t instance; /* DPIA instance */ 1276 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1277 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1278 }; 1279 1280 /** 1281 * DMUB command structure for SET_ command. 1282 */ 1283 struct dmub_rb_cmd_set_mst_alloc_slots { 1284 struct dmub_cmd_header header; /* header */ 1285 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1286 }; 1287 1288 /** 1289 * DMUB command structure for DPIA HPD int enable control. 1290 */ 1291 struct dmub_rb_cmd_dpia_hpd_int_enable { 1292 struct dmub_cmd_header header; /* header */ 1293 uint32_t enable; /* dpia hpd interrupt enable */ 1294 }; 1295 1296 /** 1297 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1298 */ 1299 struct dmub_rb_cmd_dpphy_init { 1300 struct dmub_cmd_header header; /**< header */ 1301 uint8_t reserved[60]; /**< reserved bits */ 1302 }; 1303 1304 /** 1305 * enum dp_aux_request_action - DP AUX request command listing. 1306 * 1307 * 4 AUX request command bits are shifted to high nibble. 1308 */ 1309 enum dp_aux_request_action { 1310 /** I2C-over-AUX write request */ 1311 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1312 /** I2C-over-AUX read request */ 1313 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1314 /** I2C-over-AUX write status request */ 1315 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1316 /** I2C-over-AUX write request with MOT=1 */ 1317 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1318 /** I2C-over-AUX read request with MOT=1 */ 1319 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1320 /** I2C-over-AUX write status request with MOT=1 */ 1321 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1322 /** Native AUX write request */ 1323 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1324 /** Native AUX read request */ 1325 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1326 }; 1327 1328 /** 1329 * enum aux_return_code_type - DP AUX process return code listing. 1330 */ 1331 enum aux_return_code_type { 1332 /** AUX process succeeded */ 1333 AUX_RET_SUCCESS = 0, 1334 /** AUX process failed with unknown reason */ 1335 AUX_RET_ERROR_UNKNOWN, 1336 /** AUX process completed with invalid reply */ 1337 AUX_RET_ERROR_INVALID_REPLY, 1338 /** AUX process timed out */ 1339 AUX_RET_ERROR_TIMEOUT, 1340 /** HPD was low during AUX process */ 1341 AUX_RET_ERROR_HPD_DISCON, 1342 /** Failed to acquire AUX engine */ 1343 AUX_RET_ERROR_ENGINE_ACQUIRE, 1344 /** AUX request not supported */ 1345 AUX_RET_ERROR_INVALID_OPERATION, 1346 /** AUX process not available */ 1347 AUX_RET_ERROR_PROTOCOL_ERROR, 1348 }; 1349 1350 /** 1351 * enum aux_channel_type - DP AUX channel type listing. 1352 */ 1353 enum aux_channel_type { 1354 /** AUX thru Legacy DP AUX */ 1355 AUX_CHANNEL_LEGACY_DDC, 1356 /** AUX thru DPIA DP tunneling */ 1357 AUX_CHANNEL_DPIA 1358 }; 1359 1360 /** 1361 * struct aux_transaction_parameters - DP AUX request transaction data 1362 */ 1363 struct aux_transaction_parameters { 1364 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1365 uint8_t action; /**< enum dp_aux_request_action */ 1366 uint8_t length; /**< DP AUX request data length */ 1367 uint8_t reserved; /**< For future use */ 1368 uint32_t address; /**< DP AUX address */ 1369 uint8_t data[16]; /**< DP AUX write data */ 1370 }; 1371 1372 /** 1373 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1374 */ 1375 struct dmub_cmd_dp_aux_control_data { 1376 uint8_t instance; /**< AUX instance or DPIA instance */ 1377 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1378 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1379 uint8_t reserved0; /**< For future use */ 1380 uint16_t timeout; /**< timeout time in us */ 1381 uint16_t reserved1; /**< For future use */ 1382 enum aux_channel_type type; /**< enum aux_channel_type */ 1383 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1384 }; 1385 1386 /** 1387 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1388 */ 1389 struct dmub_rb_cmd_dp_aux_access { 1390 /** 1391 * Command header. 1392 */ 1393 struct dmub_cmd_header header; 1394 /** 1395 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1396 */ 1397 struct dmub_cmd_dp_aux_control_data aux_control; 1398 }; 1399 1400 /** 1401 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1402 */ 1403 struct dmub_rb_cmd_outbox1_enable { 1404 /** 1405 * Command header. 1406 */ 1407 struct dmub_cmd_header header; 1408 /** 1409 * enable: 0x0 -> disable outbox1 notification (default value) 1410 * 0x1 -> enable outbox1 notification 1411 */ 1412 uint32_t enable; 1413 }; 1414 1415 /* DP AUX Reply command - OutBox Cmd */ 1416 /** 1417 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1418 */ 1419 struct aux_reply_data { 1420 /** 1421 * Aux cmd 1422 */ 1423 uint8_t command; 1424 /** 1425 * Aux reply data length (max: 16 bytes) 1426 */ 1427 uint8_t length; 1428 /** 1429 * Alignment only 1430 */ 1431 uint8_t pad[2]; 1432 /** 1433 * Aux reply data 1434 */ 1435 uint8_t data[16]; 1436 }; 1437 1438 /** 1439 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1440 */ 1441 struct aux_reply_control_data { 1442 /** 1443 * Reserved for future use 1444 */ 1445 uint32_t handle; 1446 /** 1447 * Aux Instance 1448 */ 1449 uint8_t instance; 1450 /** 1451 * Aux transaction result: definition in enum aux_return_code_type 1452 */ 1453 uint8_t result; 1454 /** 1455 * Alignment only 1456 */ 1457 uint16_t pad; 1458 }; 1459 1460 /** 1461 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1462 */ 1463 struct dmub_rb_cmd_dp_aux_reply { 1464 /** 1465 * Command header. 1466 */ 1467 struct dmub_cmd_header header; 1468 /** 1469 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1470 */ 1471 struct aux_reply_control_data control; 1472 /** 1473 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1474 */ 1475 struct aux_reply_data reply_data; 1476 }; 1477 1478 /* DP HPD Notify command - OutBox Cmd */ 1479 /** 1480 * DP HPD Type 1481 */ 1482 enum dp_hpd_type { 1483 /** 1484 * Normal DP HPD 1485 */ 1486 DP_HPD = 0, 1487 /** 1488 * DP HPD short pulse 1489 */ 1490 DP_IRQ 1491 }; 1492 1493 /** 1494 * DP HPD Status 1495 */ 1496 enum dp_hpd_status { 1497 /** 1498 * DP_HPD status low 1499 */ 1500 DP_HPD_UNPLUG = 0, 1501 /** 1502 * DP_HPD status high 1503 */ 1504 DP_HPD_PLUG 1505 }; 1506 1507 /** 1508 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1509 */ 1510 struct dp_hpd_data { 1511 /** 1512 * DP HPD instance 1513 */ 1514 uint8_t instance; 1515 /** 1516 * HPD type 1517 */ 1518 uint8_t hpd_type; 1519 /** 1520 * HPD status: only for type: DP_HPD to indicate status 1521 */ 1522 uint8_t hpd_status; 1523 /** 1524 * Alignment only 1525 */ 1526 uint8_t pad; 1527 }; 1528 1529 /** 1530 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1531 */ 1532 struct dmub_rb_cmd_dp_hpd_notify { 1533 /** 1534 * Command header. 1535 */ 1536 struct dmub_cmd_header header; 1537 /** 1538 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1539 */ 1540 struct dp_hpd_data hpd_data; 1541 }; 1542 1543 /** 1544 * Definition of a SET_CONFIG reply from DPOA. 1545 */ 1546 enum set_config_status { 1547 SET_CONFIG_PENDING = 0, 1548 SET_CONFIG_ACK_RECEIVED, 1549 SET_CONFIG_RX_TIMEOUT, 1550 SET_CONFIG_UNKNOWN_ERROR, 1551 }; 1552 1553 /** 1554 * Definition of a set_config reply 1555 */ 1556 struct set_config_reply_control_data { 1557 uint8_t instance; /* DPIA Instance */ 1558 uint8_t status; /* Set Config reply */ 1559 uint16_t pad; /* Alignment */ 1560 }; 1561 1562 /** 1563 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1564 */ 1565 struct dmub_rb_cmd_dp_set_config_reply { 1566 struct dmub_cmd_header header; 1567 struct set_config_reply_control_data set_config_reply_control; 1568 }; 1569 1570 /** 1571 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1572 */ 1573 struct dmub_cmd_hpd_state_query_data { 1574 uint8_t instance; /**< HPD instance or DPIA instance */ 1575 uint8_t result; /**< For returning HPD state */ 1576 uint16_t pad; /** < Alignment */ 1577 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1578 enum aux_return_code_type status; /**< for returning the status of command */ 1579 }; 1580 1581 /** 1582 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1583 */ 1584 struct dmub_rb_cmd_query_hpd_state { 1585 /** 1586 * Command header. 1587 */ 1588 struct dmub_cmd_header header; 1589 /** 1590 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1591 */ 1592 struct dmub_cmd_hpd_state_query_data data; 1593 }; 1594 1595 /* 1596 * Command IDs should be treated as stable ABI. 1597 * Do not reuse or modify IDs. 1598 */ 1599 1600 /** 1601 * PSR command sub-types. 1602 */ 1603 enum dmub_cmd_psr_type { 1604 /** 1605 * Set PSR version support. 1606 */ 1607 DMUB_CMD__PSR_SET_VERSION = 0, 1608 /** 1609 * Copy driver-calculated parameters to PSR state. 1610 */ 1611 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1612 /** 1613 * Enable PSR. 1614 */ 1615 DMUB_CMD__PSR_ENABLE = 2, 1616 1617 /** 1618 * Disable PSR. 1619 */ 1620 DMUB_CMD__PSR_DISABLE = 3, 1621 1622 /** 1623 * Set PSR level. 1624 * PSR level is a 16-bit value dicated by driver that 1625 * will enable/disable different functionality. 1626 */ 1627 DMUB_CMD__PSR_SET_LEVEL = 4, 1628 1629 /** 1630 * Forces PSR enabled until an explicit PSR disable call. 1631 */ 1632 DMUB_CMD__PSR_FORCE_STATIC = 5, 1633 /** 1634 * Set vtotal in psr active for FreeSync PSR. 1635 */ 1636 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 1637 /** 1638 * Set PSR power option 1639 */ 1640 DMUB_CMD__SET_PSR_POWER_OPT = 7, 1641 }; 1642 1643 enum dmub_cmd_fams_type { 1644 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 1645 DMUB_CMD__FAMS_DRR_UPDATE = 1, 1646 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 1647 /** 1648 * For SubVP set manual trigger in FW because it 1649 * triggers DRR_UPDATE_PENDING which SubVP relies 1650 * on (for any SubVP cases that use a DRR display) 1651 */ 1652 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 1653 }; 1654 1655 /** 1656 * PSR versions. 1657 */ 1658 enum psr_version { 1659 /** 1660 * PSR version 1. 1661 */ 1662 PSR_VERSION_1 = 0, 1663 /** 1664 * Freesync PSR SU. 1665 */ 1666 PSR_VERSION_SU_1 = 1, 1667 /** 1668 * PSR not supported. 1669 */ 1670 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1671 }; 1672 1673 /** 1674 * enum dmub_cmd_mall_type - MALL commands 1675 */ 1676 enum dmub_cmd_mall_type { 1677 /** 1678 * Allows display refresh from MALL. 1679 */ 1680 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1681 /** 1682 * Disallows display refresh from MALL. 1683 */ 1684 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1685 /** 1686 * Cursor copy for MALL. 1687 */ 1688 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1689 /** 1690 * Controls DF requests. 1691 */ 1692 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1693 }; 1694 1695 /** 1696 * PHY Link rate for DP. 1697 */ 1698 enum phy_link_rate { 1699 /** 1700 * not supported. 1701 */ 1702 PHY_RATE_UNKNOWN = 0, 1703 /** 1704 * Rate_1 (RBR) - 1.62 Gbps/Lane 1705 */ 1706 PHY_RATE_162 = 1, 1707 /** 1708 * Rate_2 - 2.16 Gbps/Lane 1709 */ 1710 PHY_RATE_216 = 2, 1711 /** 1712 * Rate_3 - 2.43 Gbps/Lane 1713 */ 1714 PHY_RATE_243 = 3, 1715 /** 1716 * Rate_4 (HBR) - 2.70 Gbps/Lane 1717 */ 1718 PHY_RATE_270 = 4, 1719 /** 1720 * Rate_5 (RBR2)- 3.24 Gbps/Lane 1721 */ 1722 PHY_RATE_324 = 5, 1723 /** 1724 * Rate_6 - 4.32 Gbps/Lane 1725 */ 1726 PHY_RATE_432 = 6, 1727 /** 1728 * Rate_7 (HBR2)- 5.40 Gbps/Lane 1729 */ 1730 PHY_RATE_540 = 7, 1731 /** 1732 * Rate_8 (HBR3)- 8.10 Gbps/Lane 1733 */ 1734 PHY_RATE_810 = 8, 1735 /** 1736 * UHBR10 - 10.0 Gbps/Lane 1737 */ 1738 PHY_RATE_1000 = 9, 1739 /** 1740 * UHBR13.5 - 13.5 Gbps/Lane 1741 */ 1742 PHY_RATE_1350 = 10, 1743 /** 1744 * UHBR10 - 20.0 Gbps/Lane 1745 */ 1746 PHY_RATE_2000 = 11, 1747 }; 1748 1749 /** 1750 * enum dmub_phy_fsm_state - PHY FSM states. 1751 * PHY FSM state to transit to during PSR enable/disable. 1752 */ 1753 enum dmub_phy_fsm_state { 1754 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 1755 DMUB_PHY_FSM_RESET, 1756 DMUB_PHY_FSM_RESET_RELEASED, 1757 DMUB_PHY_FSM_SRAM_LOAD_DONE, 1758 DMUB_PHY_FSM_INITIALIZED, 1759 DMUB_PHY_FSM_CALIBRATED, 1760 DMUB_PHY_FSM_CALIBRATED_LP, 1761 DMUB_PHY_FSM_CALIBRATED_PG, 1762 DMUB_PHY_FSM_POWER_DOWN, 1763 DMUB_PHY_FSM_PLL_EN, 1764 DMUB_PHY_FSM_TX_EN, 1765 DMUB_PHY_FSM_FAST_LP, 1766 }; 1767 1768 /** 1769 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1770 */ 1771 struct dmub_cmd_psr_copy_settings_data { 1772 /** 1773 * Flags that can be set by driver to change some PSR behaviour. 1774 */ 1775 union dmub_psr_debug_flags debug; 1776 /** 1777 * 16-bit value dicated by driver that will enable/disable different functionality. 1778 */ 1779 uint16_t psr_level; 1780 /** 1781 * DPP HW instance. 1782 */ 1783 uint8_t dpp_inst; 1784 /** 1785 * MPCC HW instance. 1786 * Not used in dmub fw, 1787 * dmub fw will get active opp by reading odm registers. 1788 */ 1789 uint8_t mpcc_inst; 1790 /** 1791 * OPP HW instance. 1792 * Not used in dmub fw, 1793 * dmub fw will get active opp by reading odm registers. 1794 */ 1795 uint8_t opp_inst; 1796 /** 1797 * OTG HW instance. 1798 */ 1799 uint8_t otg_inst; 1800 /** 1801 * DIG FE HW instance. 1802 */ 1803 uint8_t digfe_inst; 1804 /** 1805 * DIG BE HW instance. 1806 */ 1807 uint8_t digbe_inst; 1808 /** 1809 * DP PHY HW instance. 1810 */ 1811 uint8_t dpphy_inst; 1812 /** 1813 * AUX HW instance. 1814 */ 1815 uint8_t aux_inst; 1816 /** 1817 * Determines if SMU optimzations are enabled/disabled. 1818 */ 1819 uint8_t smu_optimizations_en; 1820 /** 1821 * Unused. 1822 * TODO: Remove. 1823 */ 1824 uint8_t frame_delay; 1825 /** 1826 * If RFB setup time is greater than the total VBLANK time, 1827 * it is not possible for the sink to capture the video frame 1828 * in the same frame the SDP is sent. In this case, 1829 * the frame capture indication bit should be set and an extra 1830 * static frame should be transmitted to the sink. 1831 */ 1832 uint8_t frame_cap_ind; 1833 /** 1834 * Granularity of Y offset supported by sink. 1835 */ 1836 uint8_t su_y_granularity; 1837 /** 1838 * Indicates whether sink should start capturing 1839 * immediately following active scan line, 1840 * or starting with the 2nd active scan line. 1841 */ 1842 uint8_t line_capture_indication; 1843 /** 1844 * Multi-display optimizations are implemented on certain ASICs. 1845 */ 1846 uint8_t multi_disp_optimizations_en; 1847 /** 1848 * The last possible line SDP may be transmitted without violating 1849 * the RFB setup time or entering the active video frame. 1850 */ 1851 uint16_t init_sdp_deadline; 1852 /** 1853 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 1854 */ 1855 uint8_t rate_control_caps ; 1856 /* 1857 * Force PSRSU always doing full frame update 1858 */ 1859 uint8_t force_ffu_mode; 1860 /** 1861 * Length of each horizontal line in us. 1862 */ 1863 uint32_t line_time_in_us; 1864 /** 1865 * FEC enable status in driver 1866 */ 1867 uint8_t fec_enable_status; 1868 /** 1869 * FEC re-enable delay when PSR exit. 1870 * unit is 100us, range form 0~255(0xFF). 1871 */ 1872 uint8_t fec_enable_delay_in100us; 1873 /** 1874 * PSR control version. 1875 */ 1876 uint8_t cmd_version; 1877 /** 1878 * Panel Instance. 1879 * Panel isntance to identify which psr_state to use 1880 * Currently the support is only for 0 or 1 1881 */ 1882 uint8_t panel_inst; 1883 /* 1884 * DSC enable status in driver 1885 */ 1886 uint8_t dsc_enable_status; 1887 /* 1888 * Use FSM state for PSR power up/down 1889 */ 1890 uint8_t use_phy_fsm; 1891 /** 1892 * Explicit padding to 2 byte boundary. 1893 */ 1894 uint8_t pad3[2]; 1895 }; 1896 1897 /** 1898 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1899 */ 1900 struct dmub_rb_cmd_psr_copy_settings { 1901 /** 1902 * Command header. 1903 */ 1904 struct dmub_cmd_header header; 1905 /** 1906 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1907 */ 1908 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1909 }; 1910 1911 /** 1912 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1913 */ 1914 struct dmub_cmd_psr_set_level_data { 1915 /** 1916 * 16-bit value dicated by driver that will enable/disable different functionality. 1917 */ 1918 uint16_t psr_level; 1919 /** 1920 * PSR control version. 1921 */ 1922 uint8_t cmd_version; 1923 /** 1924 * Panel Instance. 1925 * Panel isntance to identify which psr_state to use 1926 * Currently the support is only for 0 or 1 1927 */ 1928 uint8_t panel_inst; 1929 }; 1930 1931 /** 1932 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1933 */ 1934 struct dmub_rb_cmd_psr_set_level { 1935 /** 1936 * Command header. 1937 */ 1938 struct dmub_cmd_header header; 1939 /** 1940 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1941 */ 1942 struct dmub_cmd_psr_set_level_data psr_set_level_data; 1943 }; 1944 1945 struct dmub_rb_cmd_psr_enable_data { 1946 /** 1947 * PSR control version. 1948 */ 1949 uint8_t cmd_version; 1950 /** 1951 * Panel Instance. 1952 * Panel isntance to identify which psr_state to use 1953 * Currently the support is only for 0 or 1 1954 */ 1955 uint8_t panel_inst; 1956 /** 1957 * Phy state to enter. 1958 * Values to use are defined in dmub_phy_fsm_state 1959 */ 1960 uint8_t phy_fsm_state; 1961 /** 1962 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 1963 * Set this using enum phy_link_rate. 1964 * This does not support HDMI/DP2 for now. 1965 */ 1966 uint8_t phy_rate; 1967 }; 1968 1969 /** 1970 * Definition of a DMUB_CMD__PSR_ENABLE command. 1971 * PSR enable/disable is controlled using the sub_type. 1972 */ 1973 struct dmub_rb_cmd_psr_enable { 1974 /** 1975 * Command header. 1976 */ 1977 struct dmub_cmd_header header; 1978 1979 struct dmub_rb_cmd_psr_enable_data data; 1980 }; 1981 1982 /** 1983 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1984 */ 1985 struct dmub_cmd_psr_set_version_data { 1986 /** 1987 * PSR version that FW should implement. 1988 */ 1989 enum psr_version version; 1990 /** 1991 * PSR control version. 1992 */ 1993 uint8_t cmd_version; 1994 /** 1995 * Panel Instance. 1996 * Panel isntance to identify which psr_state to use 1997 * Currently the support is only for 0 or 1 1998 */ 1999 uint8_t panel_inst; 2000 /** 2001 * Explicit padding to 4 byte boundary. 2002 */ 2003 uint8_t pad[2]; 2004 }; 2005 2006 /** 2007 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2008 */ 2009 struct dmub_rb_cmd_psr_set_version { 2010 /** 2011 * Command header. 2012 */ 2013 struct dmub_cmd_header header; 2014 /** 2015 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2016 */ 2017 struct dmub_cmd_psr_set_version_data psr_set_version_data; 2018 }; 2019 2020 struct dmub_cmd_psr_force_static_data { 2021 /** 2022 * PSR control version. 2023 */ 2024 uint8_t cmd_version; 2025 /** 2026 * Panel Instance. 2027 * Panel isntance to identify which psr_state to use 2028 * Currently the support is only for 0 or 1 2029 */ 2030 uint8_t panel_inst; 2031 /** 2032 * Explicit padding to 4 byte boundary. 2033 */ 2034 uint8_t pad[2]; 2035 }; 2036 2037 /** 2038 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2039 */ 2040 struct dmub_rb_cmd_psr_force_static { 2041 /** 2042 * Command header. 2043 */ 2044 struct dmub_cmd_header header; 2045 /** 2046 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2047 */ 2048 struct dmub_cmd_psr_force_static_data psr_force_static_data; 2049 }; 2050 2051 /** 2052 * PSR SU debug flags. 2053 */ 2054 union dmub_psr_su_debug_flags { 2055 /** 2056 * PSR SU debug flags. 2057 */ 2058 struct { 2059 /** 2060 * Update dirty rect in SW only. 2061 */ 2062 uint8_t update_dirty_rect_only : 1; 2063 /** 2064 * Reset the cursor/plane state before processing the call. 2065 */ 2066 uint8_t reset_state : 1; 2067 } bitfields; 2068 2069 /** 2070 * Union for debug flags. 2071 */ 2072 uint32_t u32All; 2073 }; 2074 2075 /** 2076 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2077 * This triggers a selective update for PSR SU. 2078 */ 2079 struct dmub_cmd_update_dirty_rect_data { 2080 /** 2081 * Dirty rects from OS. 2082 */ 2083 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 2084 /** 2085 * PSR SU debug flags. 2086 */ 2087 union dmub_psr_su_debug_flags debug_flags; 2088 /** 2089 * OTG HW instance. 2090 */ 2091 uint8_t pipe_idx; 2092 /** 2093 * Number of dirty rects. 2094 */ 2095 uint8_t dirty_rect_count; 2096 /** 2097 * PSR control version. 2098 */ 2099 uint8_t cmd_version; 2100 /** 2101 * Panel Instance. 2102 * Panel isntance to identify which psr_state to use 2103 * Currently the support is only for 0 or 1 2104 */ 2105 uint8_t panel_inst; 2106 }; 2107 2108 /** 2109 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 2110 */ 2111 struct dmub_rb_cmd_update_dirty_rect { 2112 /** 2113 * Command header. 2114 */ 2115 struct dmub_cmd_header header; 2116 /** 2117 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2118 */ 2119 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 2120 }; 2121 2122 /** 2123 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2124 */ 2125 union dmub_reg_cursor_control_cfg { 2126 struct { 2127 uint32_t cur_enable: 1; 2128 uint32_t reser0: 3; 2129 uint32_t cur_2x_magnify: 1; 2130 uint32_t reser1: 3; 2131 uint32_t mode: 3; 2132 uint32_t reser2: 5; 2133 uint32_t pitch: 2; 2134 uint32_t reser3: 6; 2135 uint32_t line_per_chunk: 5; 2136 uint32_t reser4: 3; 2137 } bits; 2138 uint32_t raw; 2139 }; 2140 struct dmub_cursor_position_cache_hubp { 2141 union dmub_reg_cursor_control_cfg cur_ctl; 2142 union dmub_reg_position_cfg { 2143 struct { 2144 uint32_t cur_x_pos: 16; 2145 uint32_t cur_y_pos: 16; 2146 } bits; 2147 uint32_t raw; 2148 } position; 2149 union dmub_reg_hot_spot_cfg { 2150 struct { 2151 uint32_t hot_x: 16; 2152 uint32_t hot_y: 16; 2153 } bits; 2154 uint32_t raw; 2155 } hot_spot; 2156 union dmub_reg_dst_offset_cfg { 2157 struct { 2158 uint32_t dst_x_offset: 13; 2159 uint32_t reserved: 19; 2160 } bits; 2161 uint32_t raw; 2162 } dst_offset; 2163 }; 2164 2165 union dmub_reg_cur0_control_cfg { 2166 struct { 2167 uint32_t cur0_enable: 1; 2168 uint32_t expansion_mode: 1; 2169 uint32_t reser0: 1; 2170 uint32_t cur0_rom_en: 1; 2171 uint32_t mode: 3; 2172 uint32_t reserved: 25; 2173 } bits; 2174 uint32_t raw; 2175 }; 2176 struct dmub_cursor_position_cache_dpp { 2177 union dmub_reg_cur0_control_cfg cur0_ctl; 2178 }; 2179 struct dmub_cursor_position_cfg { 2180 struct dmub_cursor_position_cache_hubp pHubp; 2181 struct dmub_cursor_position_cache_dpp pDpp; 2182 uint8_t pipe_idx; 2183 /* 2184 * Padding is required. To be 4 Bytes Aligned. 2185 */ 2186 uint8_t padding[3]; 2187 }; 2188 2189 struct dmub_cursor_attribute_cache_hubp { 2190 uint32_t SURFACE_ADDR_HIGH; 2191 uint32_t SURFACE_ADDR; 2192 union dmub_reg_cursor_control_cfg cur_ctl; 2193 union dmub_reg_cursor_size_cfg { 2194 struct { 2195 uint32_t width: 16; 2196 uint32_t height: 16; 2197 } bits; 2198 uint32_t raw; 2199 } size; 2200 union dmub_reg_cursor_settings_cfg { 2201 struct { 2202 uint32_t dst_y_offset: 8; 2203 uint32_t chunk_hdl_adjust: 2; 2204 uint32_t reserved: 22; 2205 } bits; 2206 uint32_t raw; 2207 } settings; 2208 }; 2209 struct dmub_cursor_attribute_cache_dpp { 2210 union dmub_reg_cur0_control_cfg cur0_ctl; 2211 }; 2212 struct dmub_cursor_attributes_cfg { 2213 struct dmub_cursor_attribute_cache_hubp aHubp; 2214 struct dmub_cursor_attribute_cache_dpp aDpp; 2215 }; 2216 2217 struct dmub_cmd_update_cursor_payload0 { 2218 /** 2219 * Cursor dirty rects. 2220 */ 2221 struct dmub_rect cursor_rect; 2222 /** 2223 * PSR SU debug flags. 2224 */ 2225 union dmub_psr_su_debug_flags debug_flags; 2226 /** 2227 * Cursor enable/disable. 2228 */ 2229 uint8_t enable; 2230 /** 2231 * OTG HW instance. 2232 */ 2233 uint8_t pipe_idx; 2234 /** 2235 * PSR control version. 2236 */ 2237 uint8_t cmd_version; 2238 /** 2239 * Panel Instance. 2240 * Panel isntance to identify which psr_state to use 2241 * Currently the support is only for 0 or 1 2242 */ 2243 uint8_t panel_inst; 2244 /** 2245 * Cursor Position Register. 2246 * Registers contains Hubp & Dpp modules 2247 */ 2248 struct dmub_cursor_position_cfg position_cfg; 2249 }; 2250 2251 struct dmub_cmd_update_cursor_payload1 { 2252 struct dmub_cursor_attributes_cfg attribute_cfg; 2253 }; 2254 2255 union dmub_cmd_update_cursor_info_data { 2256 struct dmub_cmd_update_cursor_payload0 payload0; 2257 struct dmub_cmd_update_cursor_payload1 payload1; 2258 }; 2259 /** 2260 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 2261 */ 2262 struct dmub_rb_cmd_update_cursor_info { 2263 /** 2264 * Command header. 2265 */ 2266 struct dmub_cmd_header header; 2267 /** 2268 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2269 */ 2270 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 2271 }; 2272 2273 /** 2274 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2275 */ 2276 struct dmub_cmd_psr_set_vtotal_data { 2277 /** 2278 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 2279 */ 2280 uint16_t psr_vtotal_idle; 2281 /** 2282 * PSR control version. 2283 */ 2284 uint8_t cmd_version; 2285 /** 2286 * Panel Instance. 2287 * Panel isntance to identify which psr_state to use 2288 * Currently the support is only for 0 or 1 2289 */ 2290 uint8_t panel_inst; 2291 /* 2292 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 2293 */ 2294 uint16_t psr_vtotal_su; 2295 /** 2296 * Explicit padding to 4 byte boundary. 2297 */ 2298 uint8_t pad2[2]; 2299 }; 2300 2301 /** 2302 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2303 */ 2304 struct dmub_rb_cmd_psr_set_vtotal { 2305 /** 2306 * Command header. 2307 */ 2308 struct dmub_cmd_header header; 2309 /** 2310 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2311 */ 2312 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 2313 }; 2314 2315 /** 2316 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2317 */ 2318 struct dmub_cmd_psr_set_power_opt_data { 2319 /** 2320 * PSR control version. 2321 */ 2322 uint8_t cmd_version; 2323 /** 2324 * Panel Instance. 2325 * Panel isntance to identify which psr_state to use 2326 * Currently the support is only for 0 or 1 2327 */ 2328 uint8_t panel_inst; 2329 /** 2330 * Explicit padding to 4 byte boundary. 2331 */ 2332 uint8_t pad[2]; 2333 /** 2334 * PSR power option 2335 */ 2336 uint32_t power_opt; 2337 }; 2338 2339 /** 2340 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2341 */ 2342 struct dmub_rb_cmd_psr_set_power_opt { 2343 /** 2344 * Command header. 2345 */ 2346 struct dmub_cmd_header header; 2347 /** 2348 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2349 */ 2350 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2351 }; 2352 2353 /** 2354 * Set of HW components that can be locked. 2355 * 2356 * Note: If updating with more HW components, fields 2357 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2358 */ 2359 union dmub_hw_lock_flags { 2360 /** 2361 * Set of HW components that can be locked. 2362 */ 2363 struct { 2364 /** 2365 * Lock/unlock OTG master update lock. 2366 */ 2367 uint8_t lock_pipe : 1; 2368 /** 2369 * Lock/unlock cursor. 2370 */ 2371 uint8_t lock_cursor : 1; 2372 /** 2373 * Lock/unlock global update lock. 2374 */ 2375 uint8_t lock_dig : 1; 2376 /** 2377 * Triple buffer lock requires additional hw programming to usual OTG master lock. 2378 */ 2379 uint8_t triple_buffer_lock : 1; 2380 } bits; 2381 2382 /** 2383 * Union for HW Lock flags. 2384 */ 2385 uint8_t u8All; 2386 }; 2387 2388 /** 2389 * Instances of HW to be locked. 2390 * 2391 * Note: If updating with more HW components, fields 2392 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2393 */ 2394 struct dmub_hw_lock_inst_flags { 2395 /** 2396 * OTG HW instance for OTG master update lock. 2397 */ 2398 uint8_t otg_inst; 2399 /** 2400 * OPP instance for cursor lock. 2401 */ 2402 uint8_t opp_inst; 2403 /** 2404 * OTG HW instance for global update lock. 2405 * TODO: Remove, and re-use otg_inst. 2406 */ 2407 uint8_t dig_inst; 2408 /** 2409 * Explicit pad to 4 byte boundary. 2410 */ 2411 uint8_t pad; 2412 }; 2413 2414 /** 2415 * Clients that can acquire the HW Lock Manager. 2416 * 2417 * Note: If updating with more clients, fields in 2418 * dmub_inbox0_cmd_lock_hw must be updated to match. 2419 */ 2420 enum hw_lock_client { 2421 /** 2422 * Driver is the client of HW Lock Manager. 2423 */ 2424 HW_LOCK_CLIENT_DRIVER = 0, 2425 /** 2426 * PSR SU is the client of HW Lock Manager. 2427 */ 2428 HW_LOCK_CLIENT_PSR_SU = 1, 2429 /** 2430 * Invalid client. 2431 */ 2432 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 2433 }; 2434 2435 /** 2436 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2437 */ 2438 struct dmub_cmd_lock_hw_data { 2439 /** 2440 * Specifies the client accessing HW Lock Manager. 2441 */ 2442 enum hw_lock_client client; 2443 /** 2444 * HW instances to be locked. 2445 */ 2446 struct dmub_hw_lock_inst_flags inst_flags; 2447 /** 2448 * Which components to be locked. 2449 */ 2450 union dmub_hw_lock_flags hw_locks; 2451 /** 2452 * Specifies lock/unlock. 2453 */ 2454 uint8_t lock; 2455 /** 2456 * HW can be unlocked separately from releasing the HW Lock Mgr. 2457 * This flag is set if the client wishes to release the object. 2458 */ 2459 uint8_t should_release; 2460 /** 2461 * Explicit padding to 4 byte boundary. 2462 */ 2463 uint8_t pad; 2464 }; 2465 2466 /** 2467 * Definition of a DMUB_CMD__HW_LOCK command. 2468 * Command is used by driver and FW. 2469 */ 2470 struct dmub_rb_cmd_lock_hw { 2471 /** 2472 * Command header. 2473 */ 2474 struct dmub_cmd_header header; 2475 /** 2476 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2477 */ 2478 struct dmub_cmd_lock_hw_data lock_hw_data; 2479 }; 2480 2481 /** 2482 * ABM command sub-types. 2483 */ 2484 enum dmub_cmd_abm_type { 2485 /** 2486 * Initialize parameters for ABM algorithm. 2487 * Data is passed through an indirect buffer. 2488 */ 2489 DMUB_CMD__ABM_INIT_CONFIG = 0, 2490 /** 2491 * Set OTG and panel HW instance. 2492 */ 2493 DMUB_CMD__ABM_SET_PIPE = 1, 2494 /** 2495 * Set user requested backklight level. 2496 */ 2497 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 2498 /** 2499 * Set ABM operating/aggression level. 2500 */ 2501 DMUB_CMD__ABM_SET_LEVEL = 3, 2502 /** 2503 * Set ambient light level. 2504 */ 2505 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 2506 /** 2507 * Enable/disable fractional duty cycle for backlight PWM. 2508 */ 2509 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 2510 2511 /** 2512 * unregister vertical interrupt after steady state is reached 2513 */ 2514 DMUB_CMD__ABM_PAUSE = 6, 2515 }; 2516 2517 /** 2518 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 2519 * Requirements: 2520 * - Padded explicitly to 32-bit boundary. 2521 * - Must ensure this structure matches the one on driver-side, 2522 * otherwise it won't be aligned. 2523 */ 2524 struct abm_config_table { 2525 /** 2526 * Gamma curve thresholds, used for crgb conversion. 2527 */ 2528 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 2529 /** 2530 * Gamma curve offsets, used for crgb conversion. 2531 */ 2532 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 2533 /** 2534 * Gamma curve slopes, used for crgb conversion. 2535 */ 2536 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 2537 /** 2538 * Custom backlight curve thresholds. 2539 */ 2540 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 2541 /** 2542 * Custom backlight curve offsets. 2543 */ 2544 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 2545 /** 2546 * Ambient light thresholds. 2547 */ 2548 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 2549 /** 2550 * Minimum programmable backlight. 2551 */ 2552 uint16_t min_abm_backlight; // 122B 2553 /** 2554 * Minimum reduction values. 2555 */ 2556 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 2557 /** 2558 * Maximum reduction values. 2559 */ 2560 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 2561 /** 2562 * Bright positive gain. 2563 */ 2564 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 2565 /** 2566 * Dark negative gain. 2567 */ 2568 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 2569 /** 2570 * Hybrid factor. 2571 */ 2572 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 2573 /** 2574 * Contrast factor. 2575 */ 2576 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 2577 /** 2578 * Deviation gain. 2579 */ 2580 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 2581 /** 2582 * Minimum knee. 2583 */ 2584 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 2585 /** 2586 * Maximum knee. 2587 */ 2588 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 2589 /** 2590 * Unused. 2591 */ 2592 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 2593 /** 2594 * Explicit padding to 4 byte boundary. 2595 */ 2596 uint8_t pad3[3]; // 229B 2597 /** 2598 * Backlight ramp reduction. 2599 */ 2600 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 2601 /** 2602 * Backlight ramp start. 2603 */ 2604 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 2605 }; 2606 2607 /** 2608 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2609 */ 2610 struct dmub_cmd_abm_set_pipe_data { 2611 /** 2612 * OTG HW instance. 2613 */ 2614 uint8_t otg_inst; 2615 2616 /** 2617 * Panel Control HW instance. 2618 */ 2619 uint8_t panel_inst; 2620 2621 /** 2622 * Controls how ABM will interpret a set pipe or set level command. 2623 */ 2624 uint8_t set_pipe_option; 2625 2626 /** 2627 * Unused. 2628 * TODO: Remove. 2629 */ 2630 uint8_t ramping_boundary; 2631 }; 2632 2633 /** 2634 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2635 */ 2636 struct dmub_rb_cmd_abm_set_pipe { 2637 /** 2638 * Command header. 2639 */ 2640 struct dmub_cmd_header header; 2641 2642 /** 2643 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2644 */ 2645 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2646 }; 2647 2648 /** 2649 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2650 */ 2651 struct dmub_cmd_abm_set_backlight_data { 2652 /** 2653 * Number of frames to ramp to backlight user level. 2654 */ 2655 uint32_t frame_ramp; 2656 2657 /** 2658 * Requested backlight level from user. 2659 */ 2660 uint32_t backlight_user_level; 2661 2662 /** 2663 * ABM control version. 2664 */ 2665 uint8_t version; 2666 2667 /** 2668 * Panel Control HW instance mask. 2669 * Bit 0 is Panel Control HW instance 0. 2670 * Bit 1 is Panel Control HW instance 1. 2671 */ 2672 uint8_t panel_mask; 2673 2674 /** 2675 * Explicit padding to 4 byte boundary. 2676 */ 2677 uint8_t pad[2]; 2678 }; 2679 2680 /** 2681 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2682 */ 2683 struct dmub_rb_cmd_abm_set_backlight { 2684 /** 2685 * Command header. 2686 */ 2687 struct dmub_cmd_header header; 2688 2689 /** 2690 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2691 */ 2692 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2693 }; 2694 2695 /** 2696 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2697 */ 2698 struct dmub_cmd_abm_set_level_data { 2699 /** 2700 * Set current ABM operating/aggression level. 2701 */ 2702 uint32_t level; 2703 2704 /** 2705 * ABM control version. 2706 */ 2707 uint8_t version; 2708 2709 /** 2710 * Panel Control HW instance mask. 2711 * Bit 0 is Panel Control HW instance 0. 2712 * Bit 1 is Panel Control HW instance 1. 2713 */ 2714 uint8_t panel_mask; 2715 2716 /** 2717 * Explicit padding to 4 byte boundary. 2718 */ 2719 uint8_t pad[2]; 2720 }; 2721 2722 /** 2723 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2724 */ 2725 struct dmub_rb_cmd_abm_set_level { 2726 /** 2727 * Command header. 2728 */ 2729 struct dmub_cmd_header header; 2730 2731 /** 2732 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2733 */ 2734 struct dmub_cmd_abm_set_level_data abm_set_level_data; 2735 }; 2736 2737 /** 2738 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2739 */ 2740 struct dmub_cmd_abm_set_ambient_level_data { 2741 /** 2742 * Ambient light sensor reading from OS. 2743 */ 2744 uint32_t ambient_lux; 2745 2746 /** 2747 * ABM control version. 2748 */ 2749 uint8_t version; 2750 2751 /** 2752 * Panel Control HW instance mask. 2753 * Bit 0 is Panel Control HW instance 0. 2754 * Bit 1 is Panel Control HW instance 1. 2755 */ 2756 uint8_t panel_mask; 2757 2758 /** 2759 * Explicit padding to 4 byte boundary. 2760 */ 2761 uint8_t pad[2]; 2762 }; 2763 2764 /** 2765 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2766 */ 2767 struct dmub_rb_cmd_abm_set_ambient_level { 2768 /** 2769 * Command header. 2770 */ 2771 struct dmub_cmd_header header; 2772 2773 /** 2774 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2775 */ 2776 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2777 }; 2778 2779 /** 2780 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2781 */ 2782 struct dmub_cmd_abm_set_pwm_frac_data { 2783 /** 2784 * Enable/disable fractional duty cycle for backlight PWM. 2785 * TODO: Convert to uint8_t. 2786 */ 2787 uint32_t fractional_pwm; 2788 2789 /** 2790 * ABM control version. 2791 */ 2792 uint8_t version; 2793 2794 /** 2795 * Panel Control HW instance mask. 2796 * Bit 0 is Panel Control HW instance 0. 2797 * Bit 1 is Panel Control HW instance 1. 2798 */ 2799 uint8_t panel_mask; 2800 2801 /** 2802 * Explicit padding to 4 byte boundary. 2803 */ 2804 uint8_t pad[2]; 2805 }; 2806 2807 /** 2808 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2809 */ 2810 struct dmub_rb_cmd_abm_set_pwm_frac { 2811 /** 2812 * Command header. 2813 */ 2814 struct dmub_cmd_header header; 2815 2816 /** 2817 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2818 */ 2819 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2820 }; 2821 2822 /** 2823 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2824 */ 2825 struct dmub_cmd_abm_init_config_data { 2826 /** 2827 * Location of indirect buffer used to pass init data to ABM. 2828 */ 2829 union dmub_addr src; 2830 2831 /** 2832 * Indirect buffer length. 2833 */ 2834 uint16_t bytes; 2835 2836 2837 /** 2838 * ABM control version. 2839 */ 2840 uint8_t version; 2841 2842 /** 2843 * Panel Control HW instance mask. 2844 * Bit 0 is Panel Control HW instance 0. 2845 * Bit 1 is Panel Control HW instance 1. 2846 */ 2847 uint8_t panel_mask; 2848 2849 /** 2850 * Explicit padding to 4 byte boundary. 2851 */ 2852 uint8_t pad[2]; 2853 }; 2854 2855 /** 2856 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2857 */ 2858 struct dmub_rb_cmd_abm_init_config { 2859 /** 2860 * Command header. 2861 */ 2862 struct dmub_cmd_header header; 2863 2864 /** 2865 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2866 */ 2867 struct dmub_cmd_abm_init_config_data abm_init_config_data; 2868 }; 2869 2870 /** 2871 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2872 */ 2873 2874 struct dmub_cmd_abm_pause_data { 2875 2876 /** 2877 * Panel Control HW instance mask. 2878 * Bit 0 is Panel Control HW instance 0. 2879 * Bit 1 is Panel Control HW instance 1. 2880 */ 2881 uint8_t panel_mask; 2882 2883 /** 2884 * OTG hw instance 2885 */ 2886 uint8_t otg_inst; 2887 2888 /** 2889 * Enable or disable ABM pause 2890 */ 2891 uint8_t enable; 2892 2893 /** 2894 * Explicit padding to 4 byte boundary. 2895 */ 2896 uint8_t pad[1]; 2897 }; 2898 2899 /** 2900 * Definition of a DMUB_CMD__ABM_PAUSE command. 2901 */ 2902 struct dmub_rb_cmd_abm_pause { 2903 /** 2904 * Command header. 2905 */ 2906 struct dmub_cmd_header header; 2907 2908 /** 2909 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2910 */ 2911 struct dmub_cmd_abm_pause_data abm_pause_data; 2912 }; 2913 2914 /** 2915 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2916 */ 2917 struct dmub_cmd_query_feature_caps_data { 2918 /** 2919 * DMUB feature capabilities. 2920 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2921 */ 2922 struct dmub_feature_caps feature_caps; 2923 }; 2924 2925 /** 2926 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2927 */ 2928 struct dmub_rb_cmd_query_feature_caps { 2929 /** 2930 * Command header. 2931 */ 2932 struct dmub_cmd_header header; 2933 /** 2934 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2935 */ 2936 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 2937 }; 2938 2939 /** 2940 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 2941 */ 2942 struct dmub_cmd_visual_confirm_color_data { 2943 /** 2944 * DMUB feature capabilities. 2945 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2946 */ 2947 struct dmub_visual_confirm_color visual_confirm_color; 2948 }; 2949 2950 /** 2951 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 2952 */ 2953 struct dmub_rb_cmd_get_visual_confirm_color { 2954 /** 2955 * Command header. 2956 */ 2957 struct dmub_cmd_header header; 2958 /** 2959 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 2960 */ 2961 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 2962 }; 2963 2964 struct dmub_optc_state { 2965 uint32_t v_total_max; 2966 uint32_t v_total_min; 2967 uint32_t tg_inst; 2968 }; 2969 2970 struct dmub_rb_cmd_drr_update { 2971 struct dmub_cmd_header header; 2972 struct dmub_optc_state dmub_optc_state_req; 2973 }; 2974 2975 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 2976 uint32_t pix_clk_100hz; 2977 uint8_t max_ramp_step; 2978 uint8_t pipes; 2979 uint8_t min_refresh_in_hz; 2980 uint8_t padding[1]; 2981 }; 2982 2983 struct dmub_cmd_fw_assisted_mclk_switch_config { 2984 uint8_t fams_enabled; 2985 uint8_t visual_confirm_enabled; 2986 uint8_t padding[2]; 2987 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_STREAMS]; 2988 }; 2989 2990 struct dmub_rb_cmd_fw_assisted_mclk_switch { 2991 struct dmub_cmd_header header; 2992 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 2993 }; 2994 2995 /** 2996 * enum dmub_cmd_panel_cntl_type - Panel control command. 2997 */ 2998 enum dmub_cmd_panel_cntl_type { 2999 /** 3000 * Initializes embedded panel hardware blocks. 3001 */ 3002 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 3003 /** 3004 * Queries backlight info for the embedded panel. 3005 */ 3006 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 3007 }; 3008 3009 /** 3010 * struct dmub_cmd_panel_cntl_data - Panel control data. 3011 */ 3012 struct dmub_cmd_panel_cntl_data { 3013 uint32_t inst; /**< panel instance */ 3014 uint32_t current_backlight; /* in/out */ 3015 uint32_t bl_pwm_cntl; /* in/out */ 3016 uint32_t bl_pwm_period_cntl; /* in/out */ 3017 uint32_t bl_pwm_ref_div1; /* in/out */ 3018 uint8_t is_backlight_on : 1; /* in/out */ 3019 uint8_t is_powered_on : 1; /* in/out */ 3020 uint8_t padding[3]; 3021 uint32_t bl_pwm_ref_div2; /* in/out */ 3022 uint8_t reserved[4]; 3023 }; 3024 3025 /** 3026 * struct dmub_rb_cmd_panel_cntl - Panel control command. 3027 */ 3028 struct dmub_rb_cmd_panel_cntl { 3029 struct dmub_cmd_header header; /**< header */ 3030 struct dmub_cmd_panel_cntl_data data; /**< payload */ 3031 }; 3032 3033 /** 3034 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3035 */ 3036 struct dmub_cmd_lvtma_control_data { 3037 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 3038 uint8_t reserved_0[3]; /**< For future use */ 3039 uint8_t panel_inst; /**< LVTMA control instance */ 3040 uint8_t reserved_1[3]; /**< For future use */ 3041 }; 3042 3043 /** 3044 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3045 */ 3046 struct dmub_rb_cmd_lvtma_control { 3047 /** 3048 * Command header. 3049 */ 3050 struct dmub_cmd_header header; 3051 /** 3052 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3053 */ 3054 struct dmub_cmd_lvtma_control_data data; 3055 }; 3056 3057 /** 3058 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3059 */ 3060 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 3061 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 3062 uint8_t is_usb; /**< is phy is usb */ 3063 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 3064 uint8_t is_dp4; /**< is dp in 4 lane */ 3065 }; 3066 3067 /** 3068 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3069 */ 3070 struct dmub_rb_cmd_transmitter_query_dp_alt { 3071 struct dmub_cmd_header header; /**< header */ 3072 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 3073 }; 3074 3075 /** 3076 * Maximum number of bytes a chunk sent to DMUB for parsing 3077 */ 3078 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 3079 3080 /** 3081 * Represent a chunk of CEA blocks sent to DMUB for parsing 3082 */ 3083 struct dmub_cmd_send_edid_cea { 3084 uint16_t offset; /**< offset into the CEA block */ 3085 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 3086 uint16_t cea_total_length; /**< total length of the CEA block */ 3087 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 3088 uint8_t pad[3]; /**< padding and for future expansion */ 3089 }; 3090 3091 /** 3092 * Result of VSDB parsing from CEA block 3093 */ 3094 struct dmub_cmd_edid_cea_amd_vsdb { 3095 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 3096 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 3097 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 3098 uint16_t min_frame_rate; /**< Maximum frame rate */ 3099 uint16_t max_frame_rate; /**< Minimum frame rate */ 3100 }; 3101 3102 /** 3103 * Result of sending a CEA chunk 3104 */ 3105 struct dmub_cmd_edid_cea_ack { 3106 uint16_t offset; /**< offset of the chunk into the CEA block */ 3107 uint8_t success; /**< 1 if this sending of chunk succeeded */ 3108 uint8_t pad; /**< padding and for future expansion */ 3109 }; 3110 3111 /** 3112 * Specify whether the result is an ACK/NACK or the parsing has finished 3113 */ 3114 enum dmub_cmd_edid_cea_reply_type { 3115 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 3116 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 3117 }; 3118 3119 /** 3120 * Definition of a DMUB_CMD__EDID_CEA command. 3121 */ 3122 struct dmub_rb_cmd_edid_cea { 3123 struct dmub_cmd_header header; /**< Command header */ 3124 union dmub_cmd_edid_cea_data { 3125 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 3126 struct dmub_cmd_edid_cea_output { /**< output with results */ 3127 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 3128 union { 3129 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 3130 struct dmub_cmd_edid_cea_ack ack; 3131 }; 3132 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 3133 } data; /**< Command data */ 3134 3135 }; 3136 3137 /** 3138 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 3139 */ 3140 struct dmub_cmd_cable_id_input { 3141 uint8_t phy_inst; /**< phy inst for cable id data */ 3142 }; 3143 3144 /** 3145 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 3146 */ 3147 struct dmub_cmd_cable_id_output { 3148 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 3149 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 3150 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 3151 uint8_t RESERVED :2; /**< reserved means not defined */ 3152 }; 3153 3154 /** 3155 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 3156 */ 3157 struct dmub_rb_cmd_get_usbc_cable_id { 3158 struct dmub_cmd_header header; /**< Command header */ 3159 /** 3160 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 3161 */ 3162 union dmub_cmd_cable_id_data { 3163 struct dmub_cmd_cable_id_input input; /**< Input */ 3164 struct dmub_cmd_cable_id_output output; /**< Output */ 3165 uint8_t output_raw; /**< Raw data output */ 3166 } data; 3167 }; 3168 3169 /** 3170 * union dmub_rb_cmd - DMUB inbox command. 3171 */ 3172 union dmub_rb_cmd { 3173 /** 3174 * Elements shared with all commands. 3175 */ 3176 struct dmub_rb_cmd_common cmd_common; 3177 /** 3178 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 3179 */ 3180 struct dmub_rb_cmd_read_modify_write read_modify_write; 3181 /** 3182 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 3183 */ 3184 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 3185 /** 3186 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 3187 */ 3188 struct dmub_rb_cmd_burst_write burst_write; 3189 /** 3190 * Definition of a DMUB_CMD__REG_REG_WAIT command. 3191 */ 3192 struct dmub_rb_cmd_reg_wait reg_wait; 3193 /** 3194 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 3195 */ 3196 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 3197 /** 3198 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 3199 */ 3200 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3201 /** 3202 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 3203 */ 3204 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3205 /** 3206 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 3207 */ 3208 struct dmub_rb_cmd_dpphy_init dpphy_init; 3209 /** 3210 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 3211 */ 3212 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 3213 /** 3214 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 3215 */ 3216 struct dmub_rb_cmd_domain_control domain_control; 3217 /** 3218 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3219 */ 3220 struct dmub_rb_cmd_psr_set_version psr_set_version; 3221 /** 3222 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3223 */ 3224 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 3225 /** 3226 * Definition of a DMUB_CMD__PSR_ENABLE command. 3227 */ 3228 struct dmub_rb_cmd_psr_enable psr_enable; 3229 /** 3230 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3231 */ 3232 struct dmub_rb_cmd_psr_set_level psr_set_level; 3233 /** 3234 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3235 */ 3236 struct dmub_rb_cmd_psr_force_static psr_force_static; 3237 /** 3238 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3239 */ 3240 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 3241 /** 3242 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3243 */ 3244 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 3245 /** 3246 * Definition of a DMUB_CMD__HW_LOCK command. 3247 * Command is used by driver and FW. 3248 */ 3249 struct dmub_rb_cmd_lock_hw lock_hw; 3250 /** 3251 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3252 */ 3253 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 3254 /** 3255 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3256 */ 3257 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 3258 /** 3259 * Definition of a DMUB_CMD__PLAT_54186_WA command. 3260 */ 3261 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 3262 /** 3263 * Definition of a DMUB_CMD__MALL command. 3264 */ 3265 struct dmub_rb_cmd_mall mall; 3266 /** 3267 * Definition of a DMUB_CMD__CAB command. 3268 */ 3269 struct dmub_rb_cmd_cab_for_ss cab; 3270 3271 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 3272 3273 /** 3274 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 3275 */ 3276 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 3277 3278 /** 3279 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 3280 */ 3281 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 3282 3283 /** 3284 * Definition of DMUB_CMD__PANEL_CNTL commands. 3285 */ 3286 struct dmub_rb_cmd_panel_cntl panel_cntl; 3287 /** 3288 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 3289 */ 3290 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 3291 3292 /** 3293 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 3294 */ 3295 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 3296 3297 /** 3298 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 3299 */ 3300 struct dmub_rb_cmd_abm_set_level abm_set_level; 3301 3302 /** 3303 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3304 */ 3305 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 3306 3307 /** 3308 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 3309 */ 3310 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 3311 3312 /** 3313 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 3314 */ 3315 struct dmub_rb_cmd_abm_init_config abm_init_config; 3316 3317 /** 3318 * Definition of a DMUB_CMD__ABM_PAUSE command. 3319 */ 3320 struct dmub_rb_cmd_abm_pause abm_pause; 3321 3322 /** 3323 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 3324 */ 3325 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 3326 3327 /** 3328 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3329 */ 3330 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 3331 3332 /** 3333 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3334 */ 3335 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 3336 3337 /** 3338 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3339 */ 3340 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 3341 struct dmub_rb_cmd_drr_update drr_update; 3342 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 3343 3344 /** 3345 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3346 */ 3347 struct dmub_rb_cmd_lvtma_control lvtma_control; 3348 /** 3349 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3350 */ 3351 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 3352 /** 3353 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 3354 */ 3355 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 3356 /** 3357 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 3358 */ 3359 struct dmub_rb_cmd_set_config_access set_config_access; 3360 /** 3361 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3362 */ 3363 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 3364 /** 3365 * Definition of a DMUB_CMD__EDID_CEA command. 3366 */ 3367 struct dmub_rb_cmd_edid_cea edid_cea; 3368 /** 3369 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 3370 */ 3371 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 3372 3373 /** 3374 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3375 */ 3376 struct dmub_rb_cmd_query_hpd_state query_hpd; 3377 /** 3378 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 3379 */ 3380 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 3381 }; 3382 3383 /** 3384 * union dmub_rb_out_cmd - Outbox command 3385 */ 3386 union dmub_rb_out_cmd { 3387 /** 3388 * Parameters common to every command. 3389 */ 3390 struct dmub_rb_cmd_common cmd_common; 3391 /** 3392 * AUX reply command. 3393 */ 3394 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 3395 /** 3396 * HPD notify command. 3397 */ 3398 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 3399 /** 3400 * SET_CONFIG reply command. 3401 */ 3402 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 3403 }; 3404 #pragma pack(pop) 3405 3406 3407 //============================================================================== 3408 //</DMUB_CMD>=================================================================== 3409 //============================================================================== 3410 //< DMUB_RB>==================================================================== 3411 //============================================================================== 3412 3413 #if defined(__cplusplus) 3414 extern "C" { 3415 #endif 3416 3417 /** 3418 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 3419 */ 3420 struct dmub_rb_init_params { 3421 void *ctx; /**< Caller provided context pointer */ 3422 void *base_address; /**< CPU base address for ring's data */ 3423 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3424 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 3425 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 3426 }; 3427 3428 /** 3429 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 3430 */ 3431 struct dmub_rb { 3432 void *base_address; /**< CPU address for the ring's data */ 3433 uint32_t rptr; /**< Read pointer for consumer in bytes */ 3434 uint32_t wrpt; /**< Write pointer for producer in bytes */ 3435 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3436 3437 void *ctx; /**< Caller provided context pointer */ 3438 void *dmub; /**< Pointer to the DMUB interface */ 3439 }; 3440 3441 /** 3442 * @brief Checks if the ringbuffer is empty. 3443 * 3444 * @param rb DMUB Ringbuffer 3445 * @return true if empty 3446 * @return false otherwise 3447 */ 3448 static inline bool dmub_rb_empty(struct dmub_rb *rb) 3449 { 3450 return (rb->wrpt == rb->rptr); 3451 } 3452 3453 /** 3454 * @brief Checks if the ringbuffer is full 3455 * 3456 * @param rb DMUB Ringbuffer 3457 * @return true if full 3458 * @return false otherwise 3459 */ 3460 static inline bool dmub_rb_full(struct dmub_rb *rb) 3461 { 3462 uint32_t data_count; 3463 3464 if (rb->wrpt >= rb->rptr) 3465 data_count = rb->wrpt - rb->rptr; 3466 else 3467 data_count = rb->capacity - (rb->rptr - rb->wrpt); 3468 3469 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 3470 } 3471 3472 /** 3473 * @brief Pushes a command into the ringbuffer 3474 * 3475 * @param rb DMUB ringbuffer 3476 * @param cmd The command to push 3477 * @return true if the ringbuffer was not full 3478 * @return false otherwise 3479 */ 3480 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 3481 const union dmub_rb_cmd *cmd) 3482 { 3483 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 3484 const uint64_t *src = (const uint64_t *)cmd; 3485 uint8_t i; 3486 3487 if (dmub_rb_full(rb)) 3488 return false; 3489 3490 // copying data 3491 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3492 *dst++ = *src++; 3493 3494 rb->wrpt += DMUB_RB_CMD_SIZE; 3495 3496 if (rb->wrpt >= rb->capacity) 3497 rb->wrpt %= rb->capacity; 3498 3499 return true; 3500 } 3501 3502 /** 3503 * @brief Pushes a command into the DMUB outbox ringbuffer 3504 * 3505 * @param rb DMUB outbox ringbuffer 3506 * @param cmd Outbox command 3507 * @return true if not full 3508 * @return false otherwise 3509 */ 3510 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 3511 const union dmub_rb_out_cmd *cmd) 3512 { 3513 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 3514 const uint8_t *src = (const uint8_t *)cmd; 3515 3516 if (dmub_rb_full(rb)) 3517 return false; 3518 3519 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 3520 3521 rb->wrpt += DMUB_RB_CMD_SIZE; 3522 3523 if (rb->wrpt >= rb->capacity) 3524 rb->wrpt %= rb->capacity; 3525 3526 return true; 3527 } 3528 3529 /** 3530 * @brief Returns the next unprocessed command in the ringbuffer. 3531 * 3532 * @param rb DMUB ringbuffer 3533 * @param cmd The command to return 3534 * @return true if not empty 3535 * @return false otherwise 3536 */ 3537 static inline bool dmub_rb_front(struct dmub_rb *rb, 3538 union dmub_rb_cmd **cmd) 3539 { 3540 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 3541 3542 if (dmub_rb_empty(rb)) 3543 return false; 3544 3545 *cmd = (union dmub_rb_cmd *)rb_cmd; 3546 3547 return true; 3548 } 3549 3550 /** 3551 * @brief Determines the next ringbuffer offset. 3552 * 3553 * @param rb DMUB inbox ringbuffer 3554 * @param num_cmds Number of commands 3555 * @param next_rptr The next offset in the ringbuffer 3556 */ 3557 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 3558 uint32_t num_cmds, 3559 uint32_t *next_rptr) 3560 { 3561 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 3562 3563 if (*next_rptr >= rb->capacity) 3564 *next_rptr %= rb->capacity; 3565 } 3566 3567 /** 3568 * @brief Returns a pointer to a command in the inbox. 3569 * 3570 * @param rb DMUB inbox ringbuffer 3571 * @param cmd The inbox command to return 3572 * @param rptr The ringbuffer offset 3573 * @return true if not empty 3574 * @return false otherwise 3575 */ 3576 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 3577 union dmub_rb_cmd **cmd, 3578 uint32_t rptr) 3579 { 3580 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 3581 3582 if (dmub_rb_empty(rb)) 3583 return false; 3584 3585 *cmd = (union dmub_rb_cmd *)rb_cmd; 3586 3587 return true; 3588 } 3589 3590 /** 3591 * @brief Returns the next unprocessed command in the outbox. 3592 * 3593 * @param rb DMUB outbox ringbuffer 3594 * @param cmd The outbox command to return 3595 * @return true if not empty 3596 * @return false otherwise 3597 */ 3598 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 3599 union dmub_rb_out_cmd *cmd) 3600 { 3601 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 3602 uint64_t *dst = (uint64_t *)cmd; 3603 uint8_t i; 3604 3605 if (dmub_rb_empty(rb)) 3606 return false; 3607 3608 // copying data 3609 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3610 *dst++ = *src++; 3611 3612 return true; 3613 } 3614 3615 /** 3616 * @brief Removes the front entry in the ringbuffer. 3617 * 3618 * @param rb DMUB ringbuffer 3619 * @return true if the command was removed 3620 * @return false if there were no commands 3621 */ 3622 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 3623 { 3624 if (dmub_rb_empty(rb)) 3625 return false; 3626 3627 rb->rptr += DMUB_RB_CMD_SIZE; 3628 3629 if (rb->rptr >= rb->capacity) 3630 rb->rptr %= rb->capacity; 3631 3632 return true; 3633 } 3634 3635 /** 3636 * @brief Flushes commands in the ringbuffer to framebuffer memory. 3637 * 3638 * Avoids a race condition where DMCUB accesses memory while 3639 * there are still writes in flight to framebuffer. 3640 * 3641 * @param rb DMUB ringbuffer 3642 */ 3643 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 3644 { 3645 uint32_t rptr = rb->rptr; 3646 uint32_t wptr = rb->wrpt; 3647 3648 while (rptr != wptr) { 3649 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 3650 uint8_t i; 3651 3652 /* Don't remove this. 3653 * The contents need to actually be read from the ring buffer 3654 * for this function to be effective. 3655 */ 3656 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3657 (void)READ_ONCE(*data++); 3658 3659 rptr += DMUB_RB_CMD_SIZE; 3660 if (rptr >= rb->capacity) 3661 rptr %= rb->capacity; 3662 } 3663 } 3664 3665 /** 3666 * @brief Initializes a DMCUB ringbuffer 3667 * 3668 * @param rb DMUB ringbuffer 3669 * @param init_params initial configuration for the ringbuffer 3670 */ 3671 static inline void dmub_rb_init(struct dmub_rb *rb, 3672 struct dmub_rb_init_params *init_params) 3673 { 3674 rb->base_address = init_params->base_address; 3675 rb->capacity = init_params->capacity; 3676 rb->rptr = init_params->read_ptr; 3677 rb->wrpt = init_params->write_ptr; 3678 } 3679 3680 /** 3681 * @brief Copies output data from in/out commands into the given command. 3682 * 3683 * @param rb DMUB ringbuffer 3684 * @param cmd Command to copy data into 3685 */ 3686 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 3687 union dmub_rb_cmd *cmd) 3688 { 3689 // Copy rb entry back into command 3690 uint8_t *rd_ptr = (rb->rptr == 0) ? 3691 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 3692 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 3693 3694 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 3695 } 3696 3697 #if defined(__cplusplus) 3698 } 3699 #endif 3700 3701 //============================================================================== 3702 //</DMUB_RB>==================================================================== 3703 //============================================================================== 3704 3705 #endif /* _DMUB_CMD_H_ */ 3706