1ad8b1aafSjsg /* 2ad8b1aafSjsg * Copyright 2019 Advanced Micro Devices, Inc. 3ad8b1aafSjsg * 4ad8b1aafSjsg * Permission is hereby granted, free of charge, to any person obtaining a 5ad8b1aafSjsg * copy of this software and associated documentation files (the "Software"), 6ad8b1aafSjsg * to deal in the Software without restriction, including without limitation 7ad8b1aafSjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8ad8b1aafSjsg * and/or sell copies of the Software, and to permit persons to whom the 9ad8b1aafSjsg * Software is furnished to do so, subject to the following conditions: 10ad8b1aafSjsg * 11ad8b1aafSjsg * The above copyright notice and this permission notice shall be included in 12ad8b1aafSjsg * all copies or substantial portions of the Software. 13ad8b1aafSjsg * 14ad8b1aafSjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15ad8b1aafSjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16ad8b1aafSjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17ad8b1aafSjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18ad8b1aafSjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19ad8b1aafSjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20ad8b1aafSjsg * OTHER DEALINGS IN THE SOFTWARE. 21ad8b1aafSjsg * 22ad8b1aafSjsg * Authors: AMD 23ad8b1aafSjsg * 24ad8b1aafSjsg */ 25ad8b1aafSjsg 26ad8b1aafSjsg #ifndef _DMUB_SRV_H_ 27ad8b1aafSjsg #define _DMUB_SRV_H_ 28ad8b1aafSjsg 29ad8b1aafSjsg /** 30ad8b1aafSjsg * DOC: DMUB interface and operation 31ad8b1aafSjsg * 32ad8b1aafSjsg * DMUB is the interface to the display DMCUB microcontroller on DCN hardware. 33ad8b1aafSjsg * It delegates hardware initialization and command submission to the 34ad8b1aafSjsg * microcontroller. DMUB is the shortname for DMCUB. 35ad8b1aafSjsg * 36ad8b1aafSjsg * This interface is not thread-safe. Ensure that all access to the interface 37ad8b1aafSjsg * is properly synchronized by the caller. 38ad8b1aafSjsg * 39ad8b1aafSjsg * Initialization and usage of the DMUB service should be done in the 40ad8b1aafSjsg * steps given below: 41ad8b1aafSjsg * 42ad8b1aafSjsg * 1. dmub_srv_create() 43ad8b1aafSjsg * 2. dmub_srv_has_hw_support() 44ad8b1aafSjsg * 3. dmub_srv_calc_region_info() 45ad8b1aafSjsg * 4. dmub_srv_hw_init() 46ad8b1aafSjsg * 47ad8b1aafSjsg * The call to dmub_srv_create() is required to use the server. 48ad8b1aafSjsg * 49ad8b1aafSjsg * The calls to dmub_srv_has_hw_support() and dmub_srv_calc_region_info() 50ad8b1aafSjsg * are helpers to query cache window size and allocate framebuffer(s) 51ad8b1aafSjsg * for the cache windows. 52ad8b1aafSjsg * 53ad8b1aafSjsg * The call to dmub_srv_hw_init() programs the DMCUB registers to prepare 54ad8b1aafSjsg * for command submission. Commands can be queued via dmub_srv_cmd_queue() 55ad8b1aafSjsg * and executed via dmub_srv_cmd_execute(). 56ad8b1aafSjsg * 57ad8b1aafSjsg * If the queue is full the dmub_srv_wait_for_idle() call can be used to 58ad8b1aafSjsg * wait until the queue has been cleared. 59ad8b1aafSjsg * 60ad8b1aafSjsg * Destroying the DMUB service can be done by calling dmub_srv_destroy(). 61ad8b1aafSjsg * This does not clear DMUB hardware state, only software state. 62ad8b1aafSjsg * 63ad8b1aafSjsg * The interface is intended to be standalone and should not depend on any 64ad8b1aafSjsg * other component within DAL. 65ad8b1aafSjsg */ 66ad8b1aafSjsg 67ad8b1aafSjsg #include "inc/dmub_cmd.h" 68ad8b1aafSjsg 69ad8b1aafSjsg #if defined(__cplusplus) 70ad8b1aafSjsg extern "C" { 71ad8b1aafSjsg #endif 72ad8b1aafSjsg 73ad8b1aafSjsg /* Forward declarations */ 74ad8b1aafSjsg struct dmub_srv; 75ad8b1aafSjsg struct dmub_srv_common_regs; 765ca02815Sjsg struct dmub_srv_dcn31_regs; 775ca02815Sjsg 785ca02815Sjsg struct dmcub_trace_buf_entry; 79ad8b1aafSjsg 80ad8b1aafSjsg /* enum dmub_status - return code for dmcub functions */ 81ad8b1aafSjsg enum dmub_status { 82ad8b1aafSjsg DMUB_STATUS_OK = 0, 83ad8b1aafSjsg DMUB_STATUS_NO_CTX, 84ad8b1aafSjsg DMUB_STATUS_QUEUE_FULL, 85ad8b1aafSjsg DMUB_STATUS_TIMEOUT, 86ad8b1aafSjsg DMUB_STATUS_INVALID, 871bb76ff1Sjsg DMUB_STATUS_HW_FAILURE, 88ad8b1aafSjsg }; 89ad8b1aafSjsg 90ad8b1aafSjsg /* enum dmub_asic - dmub asic identifier */ 91ad8b1aafSjsg enum dmub_asic { 92ad8b1aafSjsg DMUB_ASIC_NONE = 0, 93ad8b1aafSjsg DMUB_ASIC_DCN20, 94ad8b1aafSjsg DMUB_ASIC_DCN21, 95ad8b1aafSjsg DMUB_ASIC_DCN30, 965ca02815Sjsg DMUB_ASIC_DCN301, 975ca02815Sjsg DMUB_ASIC_DCN302, 985ca02815Sjsg DMUB_ASIC_DCN303, 995ca02815Sjsg DMUB_ASIC_DCN31, 1001bb76ff1Sjsg DMUB_ASIC_DCN31B, 1011bb76ff1Sjsg DMUB_ASIC_DCN314, 1021bb76ff1Sjsg DMUB_ASIC_DCN315, 1031bb76ff1Sjsg DMUB_ASIC_DCN316, 1041bb76ff1Sjsg DMUB_ASIC_DCN32, 1051bb76ff1Sjsg DMUB_ASIC_DCN321, 106ad8b1aafSjsg DMUB_ASIC_MAX, 107ad8b1aafSjsg }; 108ad8b1aafSjsg 109ad8b1aafSjsg /* enum dmub_window_id - dmub window identifier */ 110ad8b1aafSjsg enum dmub_window_id { 111ad8b1aafSjsg DMUB_WINDOW_0_INST_CONST = 0, 112ad8b1aafSjsg DMUB_WINDOW_1_STACK, 113ad8b1aafSjsg DMUB_WINDOW_2_BSS_DATA, 114ad8b1aafSjsg DMUB_WINDOW_3_VBIOS, 115ad8b1aafSjsg DMUB_WINDOW_4_MAILBOX, 116ad8b1aafSjsg DMUB_WINDOW_5_TRACEBUFF, 117ad8b1aafSjsg DMUB_WINDOW_6_FW_STATE, 118ad8b1aafSjsg DMUB_WINDOW_7_SCRATCH_MEM, 119ad8b1aafSjsg DMUB_WINDOW_TOTAL, 120ad8b1aafSjsg }; 121ad8b1aafSjsg 1225ca02815Sjsg /* enum dmub_notification_type - dmub outbox notification identifier */ 1235ca02815Sjsg enum dmub_notification_type { 1245ca02815Sjsg DMUB_NOTIFICATION_NO_DATA = 0, 1255ca02815Sjsg DMUB_NOTIFICATION_AUX_REPLY, 1265ca02815Sjsg DMUB_NOTIFICATION_HPD, 1275ca02815Sjsg DMUB_NOTIFICATION_HPD_IRQ, 1281bb76ff1Sjsg DMUB_NOTIFICATION_SET_CONFIG_REPLY, 129*f005ef32Sjsg DMUB_NOTIFICATION_DPIA_NOTIFICATION, 1305ca02815Sjsg DMUB_NOTIFICATION_MAX 1315ca02815Sjsg }; 1325ca02815Sjsg 133ad8b1aafSjsg /** 134*f005ef32Sjsg * DPIA NOTIFICATION Response Type 135*f005ef32Sjsg */ 136*f005ef32Sjsg enum dpia_notify_bw_alloc_status { 137*f005ef32Sjsg 138*f005ef32Sjsg DPIA_BW_REQ_FAILED = 0, 139*f005ef32Sjsg DPIA_BW_REQ_SUCCESS, 140*f005ef32Sjsg DPIA_EST_BW_CHANGED, 141*f005ef32Sjsg DPIA_BW_ALLOC_CAPS_CHANGED 142*f005ef32Sjsg }; 143*f005ef32Sjsg 144*f005ef32Sjsg /** 145ad8b1aafSjsg * struct dmub_region - dmub hw memory region 146ad8b1aafSjsg * @base: base address for region, must be 256 byte aligned 147ad8b1aafSjsg * @top: top address for region 148ad8b1aafSjsg */ 149ad8b1aafSjsg struct dmub_region { 150ad8b1aafSjsg uint32_t base; 151ad8b1aafSjsg uint32_t top; 152ad8b1aafSjsg }; 153ad8b1aafSjsg 154ad8b1aafSjsg /** 155ad8b1aafSjsg * struct dmub_window - dmub hw cache window 156ad8b1aafSjsg * @off: offset to the fb memory in gpu address space 157ad8b1aafSjsg * @r: region in uc address space for cache window 158ad8b1aafSjsg */ 159ad8b1aafSjsg struct dmub_window { 160ad8b1aafSjsg union dmub_addr offset; 161ad8b1aafSjsg struct dmub_region region; 162ad8b1aafSjsg }; 163ad8b1aafSjsg 164ad8b1aafSjsg /** 165ad8b1aafSjsg * struct dmub_fb - defines a dmub framebuffer memory region 166ad8b1aafSjsg * @cpu_addr: cpu virtual address for the region, NULL if invalid 167ad8b1aafSjsg * @gpu_addr: gpu virtual address for the region, NULL if invalid 168ad8b1aafSjsg * @size: size of the region in bytes, zero if invalid 169ad8b1aafSjsg */ 170ad8b1aafSjsg struct dmub_fb { 171ad8b1aafSjsg void *cpu_addr; 172ad8b1aafSjsg uint64_t gpu_addr; 173ad8b1aafSjsg uint32_t size; 174ad8b1aafSjsg }; 175ad8b1aafSjsg 176ad8b1aafSjsg /** 177ad8b1aafSjsg * struct dmub_srv_region_params - params used for calculating dmub regions 178ad8b1aafSjsg * @inst_const_size: size of the fw inst const section 179ad8b1aafSjsg * @bss_data_size: size of the fw bss data section 180ad8b1aafSjsg * @vbios_size: size of the vbios data 181ad8b1aafSjsg * @fw_bss_data: raw firmware bss data section 182ad8b1aafSjsg */ 183ad8b1aafSjsg struct dmub_srv_region_params { 184ad8b1aafSjsg uint32_t inst_const_size; 185ad8b1aafSjsg uint32_t bss_data_size; 186ad8b1aafSjsg uint32_t vbios_size; 187ad8b1aafSjsg const uint8_t *fw_inst_const; 188ad8b1aafSjsg const uint8_t *fw_bss_data; 189cf95312aSjsg bool is_mailbox_in_inbox; 190ad8b1aafSjsg }; 191ad8b1aafSjsg 192ad8b1aafSjsg /** 193ad8b1aafSjsg * struct dmub_srv_region_info - output region info from the dmub service 194ad8b1aafSjsg * @fb_size: required minimum fb size for all regions, aligned to 4096 bytes 195ad8b1aafSjsg * @num_regions: number of regions used by the dmub service 196ad8b1aafSjsg * @regions: region info 197ad8b1aafSjsg * 198ad8b1aafSjsg * The regions are aligned such that they can be all placed within the 199ad8b1aafSjsg * same framebuffer but they can also be placed into different framebuffers. 200ad8b1aafSjsg * 201ad8b1aafSjsg * The size of each region can be calculated by the caller: 202ad8b1aafSjsg * size = reg.top - reg.base 203ad8b1aafSjsg * 204ad8b1aafSjsg * Care must be taken when performing custom allocations to ensure that each 205ad8b1aafSjsg * region base address is 256 byte aligned. 206ad8b1aafSjsg */ 207ad8b1aafSjsg struct dmub_srv_region_info { 208ad8b1aafSjsg uint32_t fb_size; 209cf95312aSjsg uint32_t inbox_size; 210ad8b1aafSjsg uint8_t num_regions; 211ad8b1aafSjsg struct dmub_region regions[DMUB_WINDOW_TOTAL]; 212ad8b1aafSjsg }; 213ad8b1aafSjsg 214ad8b1aafSjsg /** 215cf95312aSjsg * struct dmub_srv_memory_params - parameters used for driver fb setup 216ad8b1aafSjsg * @region_info: region info calculated by dmub service 217cf95312aSjsg * @cpu_fb_addr: base cpu address for the framebuffer 218cf95312aSjsg * @cpu_inbox_addr: base cpu address for the gart 219cf95312aSjsg * @gpu_fb_addr: base gpu virtual address for the framebuffer 220cf95312aSjsg * @gpu_inbox_addr: base gpu virtual address for the gart 221ad8b1aafSjsg */ 222cf95312aSjsg struct dmub_srv_memory_params { 223ad8b1aafSjsg const struct dmub_srv_region_info *region_info; 224cf95312aSjsg void *cpu_fb_addr; 225cf95312aSjsg void *cpu_inbox_addr; 226cf95312aSjsg uint64_t gpu_fb_addr; 227cf95312aSjsg uint64_t gpu_inbox_addr; 228ad8b1aafSjsg }; 229ad8b1aafSjsg 230ad8b1aafSjsg /** 231ad8b1aafSjsg * struct dmub_srv_fb_info - output fb info from the dmub service 232ad8b1aafSjsg * @num_fbs: number of required dmub framebuffers 233ad8b1aafSjsg * @fbs: fb data for each region 234ad8b1aafSjsg * 235ad8b1aafSjsg * Output from the dmub service helper that can be used by the 236ad8b1aafSjsg * driver to prepare dmub_fb that can be passed into the dmub 237ad8b1aafSjsg * hw init service. 238ad8b1aafSjsg * 239ad8b1aafSjsg * Assumes that all regions are within the same framebuffer 240ad8b1aafSjsg * and have been setup according to the region_info generated 241ad8b1aafSjsg * by the dmub service. 242ad8b1aafSjsg */ 243ad8b1aafSjsg struct dmub_srv_fb_info { 244ad8b1aafSjsg uint8_t num_fb; 245ad8b1aafSjsg struct dmub_fb fb[DMUB_WINDOW_TOTAL]; 246ad8b1aafSjsg }; 247ad8b1aafSjsg 2485ca02815Sjsg /* 2495ca02815Sjsg * struct dmub_srv_hw_params - params for dmub hardware initialization 2505ca02815Sjsg * @fb: framebuffer info for each region 2515ca02815Sjsg * @fb_base: base of the framebuffer aperture 2525ca02815Sjsg * @fb_offset: offset of the framebuffer aperture 2535ca02815Sjsg * @psp_version: psp version to pass for DMCU init 2545ca02815Sjsg * @load_inst_const: true if DMUB should load inst const fw 2555ca02815Sjsg */ 2565ca02815Sjsg struct dmub_srv_hw_params { 2575ca02815Sjsg struct dmub_fb *fb[DMUB_WINDOW_TOTAL]; 2585ca02815Sjsg uint64_t fb_base; 2595ca02815Sjsg uint64_t fb_offset; 2605ca02815Sjsg uint32_t psp_version; 2615ca02815Sjsg bool load_inst_const; 2625ca02815Sjsg bool skip_panel_power_sequence; 2635ca02815Sjsg bool disable_z10; 2641bb76ff1Sjsg bool power_optimization; 2651bb76ff1Sjsg bool dpia_supported; 2661bb76ff1Sjsg bool disable_dpia; 2671bb76ff1Sjsg bool usb4_cm_version; 2681bb76ff1Sjsg bool fw_in_system_memory; 2691bb76ff1Sjsg bool dpia_hpd_int_enable_supported; 270*f005ef32Sjsg bool disable_clock_gate; 271*f005ef32Sjsg bool disallow_dispclk_dppclk_ds; 2725ca02815Sjsg }; 2735ca02815Sjsg 2745ca02815Sjsg /** 2755ca02815Sjsg * struct dmub_diagnostic_data - Diagnostic data retrieved from DMCUB for 2765ca02815Sjsg * debugging purposes, including logging, crash analysis, etc. 2775ca02815Sjsg */ 2785ca02815Sjsg struct dmub_diagnostic_data { 2795ca02815Sjsg uint32_t dmcub_version; 280*f005ef32Sjsg uint32_t scratch[17]; 2815ca02815Sjsg uint32_t pc; 2825ca02815Sjsg uint32_t undefined_address_fault_addr; 2835ca02815Sjsg uint32_t inst_fetch_fault_addr; 2845ca02815Sjsg uint32_t data_write_fault_addr; 2855ca02815Sjsg uint32_t inbox1_rptr; 2865ca02815Sjsg uint32_t inbox1_wptr; 2875ca02815Sjsg uint32_t inbox1_size; 2885ca02815Sjsg uint32_t inbox0_rptr; 2895ca02815Sjsg uint32_t inbox0_wptr; 2905ca02815Sjsg uint32_t inbox0_size; 291*f005ef32Sjsg uint32_t gpint_datain0; 2925ca02815Sjsg uint8_t is_dmcub_enabled : 1; 2935ca02815Sjsg uint8_t is_dmcub_soft_reset : 1; 2945ca02815Sjsg uint8_t is_dmcub_secure_reset : 1; 2955ca02815Sjsg uint8_t is_traceport_en : 1; 2965ca02815Sjsg uint8_t is_cw0_enabled : 1; 2975ca02815Sjsg uint8_t is_cw6_enabled : 1; 2985ca02815Sjsg }; 2995ca02815Sjsg 300ad8b1aafSjsg /** 301ad8b1aafSjsg * struct dmub_srv_base_funcs - Driver specific base callbacks 302ad8b1aafSjsg */ 303ad8b1aafSjsg struct dmub_srv_base_funcs { 304ad8b1aafSjsg /** 305ad8b1aafSjsg * @reg_read: 306ad8b1aafSjsg * 307ad8b1aafSjsg * Hook for reading a register. 308ad8b1aafSjsg * 309ad8b1aafSjsg * Return: The 32-bit register value from the given address. 310ad8b1aafSjsg */ 311ad8b1aafSjsg uint32_t (*reg_read)(void *ctx, uint32_t address); 312ad8b1aafSjsg 313ad8b1aafSjsg /** 314ad8b1aafSjsg * @reg_write: 315ad8b1aafSjsg * 316ad8b1aafSjsg * Hook for writing a value to the register specified by address. 317ad8b1aafSjsg */ 318ad8b1aafSjsg void (*reg_write)(void *ctx, uint32_t address, uint32_t value); 319ad8b1aafSjsg }; 320ad8b1aafSjsg 321ad8b1aafSjsg /** 322ad8b1aafSjsg * struct dmub_srv_hw_funcs - hardware sequencer funcs for dmub 323ad8b1aafSjsg */ 324ad8b1aafSjsg struct dmub_srv_hw_funcs { 325ad8b1aafSjsg /* private: internal use only */ 326ad8b1aafSjsg 327ad8b1aafSjsg void (*init)(struct dmub_srv *dmub); 328ad8b1aafSjsg 329ad8b1aafSjsg void (*reset)(struct dmub_srv *dmub); 330ad8b1aafSjsg 331ad8b1aafSjsg void (*reset_release)(struct dmub_srv *dmub); 332ad8b1aafSjsg 333ad8b1aafSjsg void (*backdoor_load)(struct dmub_srv *dmub, 334ad8b1aafSjsg const struct dmub_window *cw0, 335ad8b1aafSjsg const struct dmub_window *cw1); 336ad8b1aafSjsg 3371bb76ff1Sjsg void (*backdoor_load_zfb_mode)(struct dmub_srv *dmub, 3381bb76ff1Sjsg const struct dmub_window *cw0, 3391bb76ff1Sjsg const struct dmub_window *cw1); 340ad8b1aafSjsg void (*setup_windows)(struct dmub_srv *dmub, 341ad8b1aafSjsg const struct dmub_window *cw2, 342ad8b1aafSjsg const struct dmub_window *cw3, 343ad8b1aafSjsg const struct dmub_window *cw4, 344ad8b1aafSjsg const struct dmub_window *cw5, 345ad8b1aafSjsg const struct dmub_window *cw6); 346ad8b1aafSjsg 347ad8b1aafSjsg void (*setup_mailbox)(struct dmub_srv *dmub, 348ad8b1aafSjsg const struct dmub_region *inbox1); 349ad8b1aafSjsg 35069703a93Sjsg uint32_t (*get_inbox1_wptr)(struct dmub_srv *dmub); 35169703a93Sjsg 352ad8b1aafSjsg uint32_t (*get_inbox1_rptr)(struct dmub_srv *dmub); 353ad8b1aafSjsg 354ad8b1aafSjsg void (*set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset); 355ad8b1aafSjsg 3565ca02815Sjsg void (*setup_out_mailbox)(struct dmub_srv *dmub, 3575ca02815Sjsg const struct dmub_region *outbox1); 3585ca02815Sjsg 3595ca02815Sjsg uint32_t (*get_outbox1_wptr)(struct dmub_srv *dmub); 3605ca02815Sjsg 3615ca02815Sjsg void (*set_outbox1_rptr)(struct dmub_srv *dmub, uint32_t rptr_offset); 3625ca02815Sjsg 3635ca02815Sjsg void (*setup_outbox0)(struct dmub_srv *dmub, 3645ca02815Sjsg const struct dmub_region *outbox0); 3655ca02815Sjsg 3665ca02815Sjsg uint32_t (*get_outbox0_wptr)(struct dmub_srv *dmub); 3675ca02815Sjsg 3685ca02815Sjsg void (*set_outbox0_rptr)(struct dmub_srv *dmub, uint32_t rptr_offset); 3695ca02815Sjsg 370ad8b1aafSjsg uint32_t (*emul_get_inbox1_rptr)(struct dmub_srv *dmub); 371ad8b1aafSjsg 372ad8b1aafSjsg void (*emul_set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset); 373ad8b1aafSjsg 374ad8b1aafSjsg bool (*is_supported)(struct dmub_srv *dmub); 375ad8b1aafSjsg 3765dce7169Sjsg bool (*is_psrsu_supported)(struct dmub_srv *dmub); 3775dce7169Sjsg 378ad8b1aafSjsg bool (*is_hw_init)(struct dmub_srv *dmub); 379ad8b1aafSjsg 3805ca02815Sjsg void (*enable_dmub_boot_options)(struct dmub_srv *dmub, 3815ca02815Sjsg const struct dmub_srv_hw_params *params); 382ad8b1aafSjsg 3835ca02815Sjsg void (*skip_dmub_panel_power_sequence)(struct dmub_srv *dmub, bool skip); 3845ca02815Sjsg 3855ca02815Sjsg union dmub_fw_boot_status (*get_fw_status)(struct dmub_srv *dmub); 3865ca02815Sjsg 387*f005ef32Sjsg union dmub_fw_boot_options (*get_fw_boot_option)(struct dmub_srv *dmub); 388ad8b1aafSjsg 389ad8b1aafSjsg void (*set_gpint)(struct dmub_srv *dmub, 390ad8b1aafSjsg union dmub_gpint_data_register reg); 391ad8b1aafSjsg 392ad8b1aafSjsg bool (*is_gpint_acked)(struct dmub_srv *dmub, 393ad8b1aafSjsg union dmub_gpint_data_register reg); 394ad8b1aafSjsg 395ad8b1aafSjsg uint32_t (*get_gpint_response)(struct dmub_srv *dmub); 3965ca02815Sjsg 3975ca02815Sjsg uint32_t (*get_gpint_dataout)(struct dmub_srv *dmub); 3985ca02815Sjsg 3991bb76ff1Sjsg void (*configure_dmub_in_system_memory)(struct dmub_srv *dmub); 4001bb76ff1Sjsg void (*clear_inbox0_ack_register)(struct dmub_srv *dmub); 4011bb76ff1Sjsg uint32_t (*read_inbox0_ack_register)(struct dmub_srv *dmub); 4025ca02815Sjsg void (*send_inbox0_cmd)(struct dmub_srv *dmub, union dmub_inbox0_data_register data); 4035ca02815Sjsg uint32_t (*get_current_time)(struct dmub_srv *dmub); 4045ca02815Sjsg 4055ca02815Sjsg void (*get_diagnostic_data)(struct dmub_srv *dmub, struct dmub_diagnostic_data *dmub_oca); 4061bb76ff1Sjsg 4071bb76ff1Sjsg bool (*should_detect)(struct dmub_srv *dmub); 408ad8b1aafSjsg }; 409ad8b1aafSjsg 410ad8b1aafSjsg /** 411ad8b1aafSjsg * struct dmub_srv_create_params - params for dmub service creation 412ad8b1aafSjsg * @base_funcs: driver supplied base routines 413ad8b1aafSjsg * @hw_funcs: optional overrides for hw funcs 414ad8b1aafSjsg * @user_ctx: context data for callback funcs 415ad8b1aafSjsg * @asic: driver supplied asic 416ad8b1aafSjsg * @fw_version: the current firmware version, if any 417ad8b1aafSjsg * @is_virtual: false for hw support only 418ad8b1aafSjsg */ 419ad8b1aafSjsg struct dmub_srv_create_params { 420ad8b1aafSjsg struct dmub_srv_base_funcs funcs; 421ad8b1aafSjsg struct dmub_srv_hw_funcs *hw_funcs; 422ad8b1aafSjsg void *user_ctx; 423ad8b1aafSjsg enum dmub_asic asic; 424ad8b1aafSjsg uint32_t fw_version; 425ad8b1aafSjsg bool is_virtual; 426ad8b1aafSjsg }; 427ad8b1aafSjsg 428ad8b1aafSjsg /** 429ad8b1aafSjsg * struct dmub_srv - software state for dmcub 430ad8b1aafSjsg * @asic: dmub asic identifier 431ad8b1aafSjsg * @user_ctx: user provided context for the dmub_srv 432ad8b1aafSjsg * @fw_version: the current firmware version, if any 433ad8b1aafSjsg * @is_virtual: false if hardware support only 434ad8b1aafSjsg * @fw_state: dmub firmware state pointer 435ad8b1aafSjsg */ 436ad8b1aafSjsg struct dmub_srv { 437ad8b1aafSjsg enum dmub_asic asic; 438ad8b1aafSjsg void *user_ctx; 439ad8b1aafSjsg uint32_t fw_version; 440ad8b1aafSjsg bool is_virtual; 441ad8b1aafSjsg struct dmub_fb scratch_mem_fb; 442ad8b1aafSjsg volatile const struct dmub_fw_state *fw_state; 443ad8b1aafSjsg 444ad8b1aafSjsg /* private: internal use only */ 445ad8b1aafSjsg const struct dmub_srv_common_regs *regs; 4465ca02815Sjsg const struct dmub_srv_dcn31_regs *regs_dcn31; 4471bb76ff1Sjsg const struct dmub_srv_dcn32_regs *regs_dcn32; 448ad8b1aafSjsg 449ad8b1aafSjsg struct dmub_srv_base_funcs funcs; 450ad8b1aafSjsg struct dmub_srv_hw_funcs hw_funcs; 451ad8b1aafSjsg struct dmub_rb inbox1_rb; 4521bb76ff1Sjsg uint32_t inbox1_last_wptr; 4535ca02815Sjsg /** 4545ca02815Sjsg * outbox1_rb is accessed without locks (dal & dc) 4555ca02815Sjsg * and to be used only in dmub_srv_stat_get_notification() 4565ca02815Sjsg */ 4575ca02815Sjsg struct dmub_rb outbox1_rb; 4585ca02815Sjsg 4595ca02815Sjsg struct dmub_rb outbox0_rb; 460ad8b1aafSjsg 461ad8b1aafSjsg bool sw_init; 462ad8b1aafSjsg bool hw_init; 463ad8b1aafSjsg 464ad8b1aafSjsg uint64_t fb_base; 465ad8b1aafSjsg uint64_t fb_offset; 466ad8b1aafSjsg uint32_t psp_version; 4675ca02815Sjsg 4685ca02815Sjsg /* Feature capabilities reported by fw */ 4695ca02815Sjsg struct dmub_feature_caps feature_caps; 4701bb76ff1Sjsg struct dmub_visual_confirm_color visual_confirm_color; 4715ca02815Sjsg }; 4725ca02815Sjsg 4735ca02815Sjsg /** 4745ca02815Sjsg * struct dmub_notification - dmub notification data 4755ca02815Sjsg * @type: dmub notification type 4765ca02815Sjsg * @link_index: link index to identify aux connection 4775ca02815Sjsg * @result: USB4 status returned from dmub 4785ca02815Sjsg * @pending_notification: Indicates there are other pending notifications 4795ca02815Sjsg * @aux_reply: aux reply 4805ca02815Sjsg * @hpd_status: hpd status 481*f005ef32Sjsg * @bw_alloc_reply: BW Allocation reply from CM/DPIA 4825ca02815Sjsg */ 4835ca02815Sjsg struct dmub_notification { 4845ca02815Sjsg enum dmub_notification_type type; 4855ca02815Sjsg uint8_t link_index; 4865ca02815Sjsg uint8_t result; 4875ca02815Sjsg bool pending_notification; 4885ca02815Sjsg union { 4895ca02815Sjsg struct aux_reply_data aux_reply; 4905ca02815Sjsg enum dp_hpd_status hpd_status; 4911bb76ff1Sjsg enum set_config_status sc_status; 492*f005ef32Sjsg /** 493*f005ef32Sjsg * DPIA notification command. 494*f005ef32Sjsg */ 495*f005ef32Sjsg struct dmub_rb_cmd_dpia_notification dpia_notification; 4965ca02815Sjsg }; 497ad8b1aafSjsg }; 498ad8b1aafSjsg 499ad8b1aafSjsg /** 500ad8b1aafSjsg * DMUB firmware version helper macro - useful for checking if the version 501ad8b1aafSjsg * of a firmware to know if feature or functionality is supported or present. 502ad8b1aafSjsg */ 503ad8b1aafSjsg #define DMUB_FW_VERSION(major, minor, revision) \ 504a63848d0Sjsg ((((major) & 0xFF) << 24) | (((minor) & 0xFF) << 16) | (((revision) & 0xFF) << 8)) 505ad8b1aafSjsg 506ad8b1aafSjsg /** 507ad8b1aafSjsg * dmub_srv_create() - creates the DMUB service. 508ad8b1aafSjsg * @dmub: the dmub service 509ad8b1aafSjsg * @params: creation parameters for the service 510ad8b1aafSjsg * 511ad8b1aafSjsg * Return: 512ad8b1aafSjsg * DMUB_STATUS_OK - success 513ad8b1aafSjsg * DMUB_STATUS_INVALID - unspecified error 514ad8b1aafSjsg */ 515ad8b1aafSjsg enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 516ad8b1aafSjsg const struct dmub_srv_create_params *params); 517ad8b1aafSjsg 518ad8b1aafSjsg /** 519ad8b1aafSjsg * dmub_srv_destroy() - destroys the DMUB service. 520ad8b1aafSjsg * @dmub: the dmub service 521ad8b1aafSjsg */ 522ad8b1aafSjsg void dmub_srv_destroy(struct dmub_srv *dmub); 523ad8b1aafSjsg 524ad8b1aafSjsg /** 525ad8b1aafSjsg * dmub_srv_calc_region_info() - retreives region info from the dmub service 526ad8b1aafSjsg * @dmub: the dmub service 527ad8b1aafSjsg * @params: parameters used to calculate region locations 528ad8b1aafSjsg * @info_out: the output region info from dmub 529ad8b1aafSjsg * 530ad8b1aafSjsg * Calculates the base and top address for all relevant dmub regions 531ad8b1aafSjsg * using the parameters given (if any). 532ad8b1aafSjsg * 533ad8b1aafSjsg * Return: 534ad8b1aafSjsg * DMUB_STATUS_OK - success 535ad8b1aafSjsg * DMUB_STATUS_INVALID - unspecified error 536ad8b1aafSjsg */ 537ad8b1aafSjsg enum dmub_status 538ad8b1aafSjsg dmub_srv_calc_region_info(struct dmub_srv *dmub, 539ad8b1aafSjsg const struct dmub_srv_region_params *params, 540ad8b1aafSjsg struct dmub_srv_region_info *out); 541ad8b1aafSjsg 542ad8b1aafSjsg /** 543ad8b1aafSjsg * dmub_srv_calc_region_info() - retreives fb info from the dmub service 544ad8b1aafSjsg * @dmub: the dmub service 545ad8b1aafSjsg * @params: parameters used to calculate fb locations 546ad8b1aafSjsg * @info_out: the output fb info from dmub 547ad8b1aafSjsg * 548ad8b1aafSjsg * Calculates the base and top address for all relevant dmub regions 549ad8b1aafSjsg * using the parameters given (if any). 550ad8b1aafSjsg * 551ad8b1aafSjsg * Return: 552ad8b1aafSjsg * DMUB_STATUS_OK - success 553ad8b1aafSjsg * DMUB_STATUS_INVALID - unspecified error 554ad8b1aafSjsg */ 555cf95312aSjsg enum dmub_status dmub_srv_calc_mem_info(struct dmub_srv *dmub, 556cf95312aSjsg const struct dmub_srv_memory_params *params, 557ad8b1aafSjsg struct dmub_srv_fb_info *out); 558ad8b1aafSjsg 559ad8b1aafSjsg /** 560ad8b1aafSjsg * dmub_srv_has_hw_support() - returns hw support state for dmcub 561ad8b1aafSjsg * @dmub: the dmub service 562ad8b1aafSjsg * @is_supported: hw support state 563ad8b1aafSjsg * 564ad8b1aafSjsg * Queries the hardware for DMCUB support and returns the result. 565ad8b1aafSjsg * 566ad8b1aafSjsg * Can be called before dmub_srv_hw_init(). 567ad8b1aafSjsg * 568ad8b1aafSjsg * Return: 569ad8b1aafSjsg * DMUB_STATUS_OK - success 570ad8b1aafSjsg * DMUB_STATUS_INVALID - unspecified error 571ad8b1aafSjsg */ 572ad8b1aafSjsg enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 573ad8b1aafSjsg bool *is_supported); 574ad8b1aafSjsg 575ad8b1aafSjsg /** 576ad8b1aafSjsg * dmub_srv_is_hw_init() - returns hardware init state 577ad8b1aafSjsg * 578ad8b1aafSjsg * Return: 579ad8b1aafSjsg * DMUB_STATUS_OK - success 580ad8b1aafSjsg * DMUB_STATUS_INVALID - unspecified error 581ad8b1aafSjsg */ 582ad8b1aafSjsg enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init); 583ad8b1aafSjsg 584ad8b1aafSjsg /** 585ad8b1aafSjsg * dmub_srv_hw_init() - initializes the underlying DMUB hardware 586ad8b1aafSjsg * @dmub: the dmub service 587ad8b1aafSjsg * @params: params for hardware initialization 588ad8b1aafSjsg * 589ad8b1aafSjsg * Resets the DMUB hardware and performs backdoor loading of the 590ad8b1aafSjsg * required cache regions based on the input framebuffer regions. 591ad8b1aafSjsg * 592ad8b1aafSjsg * Return: 593ad8b1aafSjsg * DMUB_STATUS_OK - success 594ad8b1aafSjsg * DMUB_STATUS_NO_CTX - dmcub context not initialized 595ad8b1aafSjsg * DMUB_STATUS_INVALID - unspecified error 596ad8b1aafSjsg */ 597ad8b1aafSjsg enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 598ad8b1aafSjsg const struct dmub_srv_hw_params *params); 599ad8b1aafSjsg 600ad8b1aafSjsg /** 601ad8b1aafSjsg * dmub_srv_hw_reset() - puts the DMUB hardware in reset state if initialized 602ad8b1aafSjsg * @dmub: the dmub service 603ad8b1aafSjsg * 604ad8b1aafSjsg * Before destroying the DMUB service or releasing the backing framebuffer 605ad8b1aafSjsg * memory we'll need to put the DMCUB into reset first. 606ad8b1aafSjsg * 607ad8b1aafSjsg * A subsequent call to dmub_srv_hw_init() will re-enable the DMCUB. 608ad8b1aafSjsg * 609ad8b1aafSjsg * Return: 610ad8b1aafSjsg * DMUB_STATUS_OK - success 611ad8b1aafSjsg * DMUB_STATUS_INVALID - unspecified error 612ad8b1aafSjsg */ 613ad8b1aafSjsg enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub); 614ad8b1aafSjsg 615ad8b1aafSjsg /** 61669703a93Sjsg * dmub_srv_sync_inbox1() - sync sw state with hw state 61769703a93Sjsg * @dmub: the dmub service 61869703a93Sjsg * 61969703a93Sjsg * Sync sw state with hw state when resume from S0i3 62069703a93Sjsg * 62169703a93Sjsg * Return: 62269703a93Sjsg * DMUB_STATUS_OK - success 62369703a93Sjsg * DMUB_STATUS_INVALID - unspecified error 62469703a93Sjsg */ 62569703a93Sjsg enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub); 62669703a93Sjsg 62769703a93Sjsg /** 628ad8b1aafSjsg * dmub_srv_cmd_queue() - queues a command to the DMUB 629ad8b1aafSjsg * @dmub: the dmub service 630ad8b1aafSjsg * @cmd: the command to queue 631ad8b1aafSjsg * 632ad8b1aafSjsg * Queues a command to the DMUB service but does not begin execution 633ad8b1aafSjsg * immediately. 634ad8b1aafSjsg * 635ad8b1aafSjsg * Return: 636ad8b1aafSjsg * DMUB_STATUS_OK - success 637ad8b1aafSjsg * DMUB_STATUS_QUEUE_FULL - no remaining room in queue 638ad8b1aafSjsg * DMUB_STATUS_INVALID - unspecified error 639ad8b1aafSjsg */ 640ad8b1aafSjsg enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub, 641ad8b1aafSjsg const union dmub_rb_cmd *cmd); 642ad8b1aafSjsg 643ad8b1aafSjsg /** 644ad8b1aafSjsg * dmub_srv_cmd_execute() - Executes a queued sequence to the dmub 645ad8b1aafSjsg * @dmub: the dmub service 646ad8b1aafSjsg * 647ad8b1aafSjsg * Begins execution of queued commands on the dmub. 648ad8b1aafSjsg * 649ad8b1aafSjsg * Return: 650ad8b1aafSjsg * DMUB_STATUS_OK - success 651ad8b1aafSjsg * DMUB_STATUS_INVALID - unspecified error 652ad8b1aafSjsg */ 653ad8b1aafSjsg enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub); 654ad8b1aafSjsg 655ad8b1aafSjsg /** 656ad8b1aafSjsg * dmub_srv_wait_for_auto_load() - Waits for firmware auto load to complete 657ad8b1aafSjsg * @dmub: the dmub service 658ad8b1aafSjsg * @timeout_us: the maximum number of microseconds to wait 659ad8b1aafSjsg * 660ad8b1aafSjsg * Waits until firmware has been autoloaded by the DMCUB. The maximum 661ad8b1aafSjsg * wait time is given in microseconds to prevent spinning forever. 662ad8b1aafSjsg * 663ad8b1aafSjsg * On ASICs without firmware autoload support this function will return 664ad8b1aafSjsg * immediately. 665ad8b1aafSjsg * 666ad8b1aafSjsg * Return: 667ad8b1aafSjsg * DMUB_STATUS_OK - success 668ad8b1aafSjsg * DMUB_STATUS_TIMEOUT - wait for phy init timed out 669ad8b1aafSjsg * DMUB_STATUS_INVALID - unspecified error 670ad8b1aafSjsg */ 671ad8b1aafSjsg enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 672ad8b1aafSjsg uint32_t timeout_us); 673ad8b1aafSjsg 674ad8b1aafSjsg /** 675ad8b1aafSjsg * dmub_srv_wait_for_phy_init() - Waits for DMUB PHY init to complete 676ad8b1aafSjsg * @dmub: the dmub service 677ad8b1aafSjsg * @timeout_us: the maximum number of microseconds to wait 678ad8b1aafSjsg * 679ad8b1aafSjsg * Waits until the PHY has been initialized by the DMUB. The maximum 680ad8b1aafSjsg * wait time is given in microseconds to prevent spinning forever. 681ad8b1aafSjsg * 682ad8b1aafSjsg * On ASICs without PHY init support this function will return 683ad8b1aafSjsg * immediately. 684ad8b1aafSjsg * 685ad8b1aafSjsg * Return: 686ad8b1aafSjsg * DMUB_STATUS_OK - success 687ad8b1aafSjsg * DMUB_STATUS_TIMEOUT - wait for phy init timed out 688ad8b1aafSjsg * DMUB_STATUS_INVALID - unspecified error 689ad8b1aafSjsg */ 690ad8b1aafSjsg enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub, 691ad8b1aafSjsg uint32_t timeout_us); 692ad8b1aafSjsg 693ad8b1aafSjsg /** 694ad8b1aafSjsg * dmub_srv_wait_for_idle() - Waits for the DMUB to be idle 695ad8b1aafSjsg * @dmub: the dmub service 696ad8b1aafSjsg * @timeout_us: the maximum number of microseconds to wait 697ad8b1aafSjsg * 698ad8b1aafSjsg * Waits until the DMUB buffer is empty and all commands have 699ad8b1aafSjsg * finished processing. The maximum wait time is given in 700ad8b1aafSjsg * microseconds to prevent spinning forever. 701ad8b1aafSjsg * 702ad8b1aafSjsg * Return: 703ad8b1aafSjsg * DMUB_STATUS_OK - success 704ad8b1aafSjsg * DMUB_STATUS_TIMEOUT - wait for buffer to flush timed out 705ad8b1aafSjsg * DMUB_STATUS_INVALID - unspecified error 706ad8b1aafSjsg */ 707ad8b1aafSjsg enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 708ad8b1aafSjsg uint32_t timeout_us); 709ad8b1aafSjsg 710ad8b1aafSjsg /** 711ad8b1aafSjsg * dmub_srv_send_gpint_command() - Sends a GPINT based command. 712ad8b1aafSjsg * @dmub: the dmub service 713ad8b1aafSjsg * @command_code: the command code to send 714ad8b1aafSjsg * @param: the command parameter to send 715ad8b1aafSjsg * @timeout_us: the maximum number of microseconds to wait 716ad8b1aafSjsg * 717ad8b1aafSjsg * Sends a command via the general purpose interrupt (GPINT). 718ad8b1aafSjsg * Waits for the number of microseconds specified by timeout_us 719ad8b1aafSjsg * for the command ACK before returning. 720ad8b1aafSjsg * 721ad8b1aafSjsg * Can be called after software initialization. 722ad8b1aafSjsg * 723ad8b1aafSjsg * Return: 724ad8b1aafSjsg * DMUB_STATUS_OK - success 725ad8b1aafSjsg * DMUB_STATUS_TIMEOUT - wait for ACK timed out 726ad8b1aafSjsg * DMUB_STATUS_INVALID - unspecified error 727ad8b1aafSjsg */ 728ad8b1aafSjsg enum dmub_status 729ad8b1aafSjsg dmub_srv_send_gpint_command(struct dmub_srv *dmub, 730ad8b1aafSjsg enum dmub_gpint_command command_code, 731ad8b1aafSjsg uint16_t param, uint32_t timeout_us); 732ad8b1aafSjsg 733ad8b1aafSjsg /** 734ad8b1aafSjsg * dmub_srv_get_gpint_response() - Queries the GPINT response. 735ad8b1aafSjsg * @dmub: the dmub service 736ad8b1aafSjsg * @response: the response for the last GPINT 737ad8b1aafSjsg * 738ad8b1aafSjsg * Returns the response code for the last GPINT interrupt. 739ad8b1aafSjsg * 740ad8b1aafSjsg * Can be called after software initialization. 741ad8b1aafSjsg * 742ad8b1aafSjsg * Return: 743ad8b1aafSjsg * DMUB_STATUS_OK - success 744ad8b1aafSjsg * DMUB_STATUS_INVALID - unspecified error 745ad8b1aafSjsg */ 746ad8b1aafSjsg enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 747ad8b1aafSjsg uint32_t *response); 748ad8b1aafSjsg 749ad8b1aafSjsg /** 7505ca02815Sjsg * dmub_srv_get_gpint_dataout() - Queries the GPINT DATAOUT. 7515ca02815Sjsg * @dmub: the dmub service 7525ca02815Sjsg * @dataout: the data for the GPINT DATAOUT 7535ca02815Sjsg * 7545ca02815Sjsg * Returns the response code for the last GPINT DATAOUT interrupt. 7555ca02815Sjsg * 7565ca02815Sjsg * Can be called after software initialization. 7575ca02815Sjsg * 7585ca02815Sjsg * Return: 7595ca02815Sjsg * DMUB_STATUS_OK - success 7605ca02815Sjsg * DMUB_STATUS_INVALID - unspecified error 7615ca02815Sjsg */ 7625ca02815Sjsg enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub, 7635ca02815Sjsg uint32_t *dataout); 7645ca02815Sjsg 7655ca02815Sjsg /** 766ad8b1aafSjsg * dmub_flush_buffer_mem() - Read back entire frame buffer region. 767ad8b1aafSjsg * This ensures that the write from x86 has been flushed and will not 768ad8b1aafSjsg * hang the DMCUB. 769ad8b1aafSjsg * @fb: frame buffer to flush 770ad8b1aafSjsg * 771ad8b1aafSjsg * Can be called after software initialization. 772ad8b1aafSjsg */ 773ad8b1aafSjsg void dmub_flush_buffer_mem(const struct dmub_fb *fb); 774ad8b1aafSjsg 7755ca02815Sjsg /** 7765ca02815Sjsg * dmub_srv_get_fw_boot_status() - Returns the DMUB boot status bits. 7775ca02815Sjsg * 7785ca02815Sjsg * @dmub: the dmub service 7795ca02815Sjsg * @status: out pointer for firmware status 7805ca02815Sjsg * 7815ca02815Sjsg * Return: 7825ca02815Sjsg * DMUB_STATUS_OK - success 7835ca02815Sjsg * DMUB_STATUS_INVALID - unspecified error, unsupported 7845ca02815Sjsg */ 7855ca02815Sjsg enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub, 7865ca02815Sjsg union dmub_fw_boot_status *status); 7875ca02815Sjsg 788*f005ef32Sjsg enum dmub_status dmub_srv_get_fw_boot_option(struct dmub_srv *dmub, 789*f005ef32Sjsg union dmub_fw_boot_options *option); 790*f005ef32Sjsg 7915ca02815Sjsg enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub, 7925ca02815Sjsg union dmub_rb_cmd *cmd); 7935ca02815Sjsg 794*f005ef32Sjsg enum dmub_status dmub_srv_set_skip_panel_power_sequence(struct dmub_srv *dmub, 795*f005ef32Sjsg bool skip); 796*f005ef32Sjsg 7975ca02815Sjsg bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry); 7985ca02815Sjsg 7995ca02815Sjsg bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data); 8005ca02815Sjsg 8011bb76ff1Sjsg bool dmub_srv_should_detect(struct dmub_srv *dmub); 8021bb76ff1Sjsg 8031bb76ff1Sjsg /** 8041bb76ff1Sjsg * dmub_srv_send_inbox0_cmd() - Send command to DMUB using INBOX0 8051bb76ff1Sjsg * @dmub: the dmub service 8061bb76ff1Sjsg * @data: the data to be sent in the INBOX0 command 8071bb76ff1Sjsg * 8081bb76ff1Sjsg * Send command by writing directly to INBOX0 WPTR 8091bb76ff1Sjsg * 8101bb76ff1Sjsg * Return: 8111bb76ff1Sjsg * DMUB_STATUS_OK - success 8121bb76ff1Sjsg * DMUB_STATUS_INVALID - hw_init false or hw function does not exist 8131bb76ff1Sjsg */ 8141bb76ff1Sjsg enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data); 8151bb76ff1Sjsg 8161bb76ff1Sjsg /** 8171bb76ff1Sjsg * dmub_srv_wait_for_inbox0_ack() - wait for DMUB to ACK INBOX0 command 8181bb76ff1Sjsg * @dmub: the dmub service 8191bb76ff1Sjsg * @timeout_us: the maximum number of microseconds to wait 8201bb76ff1Sjsg * 8211bb76ff1Sjsg * Wait for DMUB to ACK the INBOX0 message 8221bb76ff1Sjsg * 8231bb76ff1Sjsg * Return: 8241bb76ff1Sjsg * DMUB_STATUS_OK - success 8251bb76ff1Sjsg * DMUB_STATUS_INVALID - hw_init false or hw function does not exist 8261bb76ff1Sjsg * DMUB_STATUS_TIMEOUT - wait for ack timed out 8271bb76ff1Sjsg */ 8281bb76ff1Sjsg enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us); 8291bb76ff1Sjsg 8301bb76ff1Sjsg /** 8311bb76ff1Sjsg * dmub_srv_wait_for_inbox0_ack() - clear ACK register for INBOX0 8321bb76ff1Sjsg * @dmub: the dmub service 8331bb76ff1Sjsg * 8341bb76ff1Sjsg * Clear ACK register for INBOX0 8351bb76ff1Sjsg * 8361bb76ff1Sjsg * Return: 8371bb76ff1Sjsg * DMUB_STATUS_OK - success 8381bb76ff1Sjsg * DMUB_STATUS_INVALID - hw_init false or hw function does not exist 8391bb76ff1Sjsg */ 8401bb76ff1Sjsg enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub); 8411bb76ff1Sjsg 842ad8b1aafSjsg #if defined(__cplusplus) 843ad8b1aafSjsg } 844ad8b1aafSjsg #endif 845ad8b1aafSjsg 846ad8b1aafSjsg #endif /* _DMUB_SRV_H_ */ 847