xref: /openbsd-src/sys/dev/pci/drm/amd/display/dc/inc/link.h (revision f005ef32267c16bdb134f0e9fa4477dbe07c263a)
1*f005ef32Sjsg /*
2*f005ef32Sjsg  * Copyright 2022 Advanced Micro Devices, Inc.
3*f005ef32Sjsg  *
4*f005ef32Sjsg  * Permission is hereby granted, free of charge, to any person obtaining a
5*f005ef32Sjsg  * copy of this software and associated documentation files (the "Software"),
6*f005ef32Sjsg  * to deal in the Software without restriction, including without limitation
7*f005ef32Sjsg  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*f005ef32Sjsg  * and/or sell copies of the Software, and to permit persons to whom the
9*f005ef32Sjsg  * Software is furnished to do so, subject to the following conditions:
10*f005ef32Sjsg  *
11*f005ef32Sjsg  * The above copyright notice and this permission notice shall be included in
12*f005ef32Sjsg  * all copies or substantial portions of the Software.
13*f005ef32Sjsg  *
14*f005ef32Sjsg  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*f005ef32Sjsg  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*f005ef32Sjsg  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17*f005ef32Sjsg  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*f005ef32Sjsg  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*f005ef32Sjsg  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*f005ef32Sjsg  * OTHER DEALINGS IN THE SOFTWARE.
21*f005ef32Sjsg  *
22*f005ef32Sjsg  * Authors: AMD
23*f005ef32Sjsg  *
24*f005ef32Sjsg  */
25*f005ef32Sjsg 
26*f005ef32Sjsg #ifndef __DC_LINK_H__
27*f005ef32Sjsg #define __DC_LINK_H__
28*f005ef32Sjsg 
29*f005ef32Sjsg /* FILE POLICY AND INTENDED USAGE:
30*f005ef32Sjsg  *
31*f005ef32Sjsg  * This header defines link component function interfaces aka link_service.
32*f005ef32Sjsg  * link_service provides the only entry point to link functions with function
33*f005ef32Sjsg  * pointer style. This header is strictly private in dc and should never be
34*f005ef32Sjsg  * included by DM because it exposes too much dc detail including all dc
35*f005ef32Sjsg  * private types defined in core_types.h. Otherwise it will break DM - DC
36*f005ef32Sjsg  * encapsulation and turn DM into a maintenance nightmare.
37*f005ef32Sjsg  *
38*f005ef32Sjsg  * The following shows a link component relation map.
39*f005ef32Sjsg  *
40*f005ef32Sjsg  * DM to DC:
41*f005ef32Sjsg  * DM includes dc.h
42*f005ef32Sjsg  * dc_link_exports.c or other dc files implement dc.h
43*f005ef32Sjsg  *
44*f005ef32Sjsg  * DC to Link:
45*f005ef32Sjsg  * dc_link_exports.c or other dc files include link.h
46*f005ef32Sjsg  * link_factory.c implements link.h
47*f005ef32Sjsg  *
48*f005ef32Sjsg  * Link sub-component to Link sub-component:
49*f005ef32Sjsg  * link_factory.c includes --> link_xxx.h
50*f005ef32Sjsg  * link_xxx.c implements link_xxx.h
51*f005ef32Sjsg 
52*f005ef32Sjsg  * As you can see if you ever need to add a new dc link function and call it on
53*f005ef32Sjsg  * DM/dc side, it is very difficult because you will need layers of translation.
54*f005ef32Sjsg  * The most appropriate approach to implement new requirements on DM/dc side is
55*f005ef32Sjsg  * to extend or generalize the functionality of existing link function
56*f005ef32Sjsg  * interfaces so minimal modification is needed outside link component to
57*f005ef32Sjsg  * achieve your new requirements. This approach reduces or even eliminates the
58*f005ef32Sjsg  * effort needed outside link component to support a new link feature. This also
59*f005ef32Sjsg  * reduces code discrepancy among DMs to support the same link feature. If we
60*f005ef32Sjsg  * test full code path on one version of DM, and there is no feature specific
61*f005ef32Sjsg  * modification required on other DMs, then we can have higher confidence that
62*f005ef32Sjsg  * the feature will run on other DMs and produce the same result. The following
63*f005ef32Sjsg  * are some good examples to start with:
64*f005ef32Sjsg  *
65*f005ef32Sjsg  * - detect_link --> to add new link detection or capability retrieval routines
66*f005ef32Sjsg  *
67*f005ef32Sjsg  * - validate_mode_timing --> to add new timing validation conditions
68*f005ef32Sjsg  *
69*f005ef32Sjsg  * - set_dpms_on/set_dpms_off --> to include new link enablement sequences
70*f005ef32Sjsg  *
71*f005ef32Sjsg  * If you must add new link functions, you will need to:
72*f005ef32Sjsg  * 1. declare the function pointer here under the suitable commented category.
73*f005ef32Sjsg  * 2. Implement your function in the suitable link_xxx.c file.
74*f005ef32Sjsg  * 3. Assign the function to link_service in link_factory.c
75*f005ef32Sjsg  * 4. NEVER include link_xxx.h headers outside link component.
76*f005ef32Sjsg  * 5. NEVER include link.h on DM side.
77*f005ef32Sjsg  */
78*f005ef32Sjsg #include "core_types.h"
79*f005ef32Sjsg 
80*f005ef32Sjsg struct link_service *link_create_link_service(void);
81*f005ef32Sjsg void link_destroy_link_service(struct link_service **link_srv);
82*f005ef32Sjsg 
83*f005ef32Sjsg struct link_init_data {
84*f005ef32Sjsg 	const struct dc *dc;
85*f005ef32Sjsg 	struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */
86*f005ef32Sjsg 	uint32_t connector_index; /* this will be mapped to the HPD pins */
87*f005ef32Sjsg 	uint32_t link_index; /* this is mapped to DAL display_index
88*f005ef32Sjsg 				TODO: remove it when DC is complete. */
89*f005ef32Sjsg 	bool is_dpia_link;
90*f005ef32Sjsg };
91*f005ef32Sjsg 
92*f005ef32Sjsg struct ddc_service_init_data {
93*f005ef32Sjsg 	struct graphics_object_id id;
94*f005ef32Sjsg 	struct dc_context *ctx;
95*f005ef32Sjsg 	struct dc_link *link;
96*f005ef32Sjsg 	bool is_dpia_link;
97*f005ef32Sjsg };
98*f005ef32Sjsg 
99*f005ef32Sjsg struct link_service {
100*f005ef32Sjsg 	/************************** Factory ***********************************/
101*f005ef32Sjsg 	struct dc_link *(*create_link)(
102*f005ef32Sjsg 			const struct link_init_data *init_params);
103*f005ef32Sjsg 	void (*destroy_link)(struct dc_link **link);
104*f005ef32Sjsg 
105*f005ef32Sjsg 
106*f005ef32Sjsg 	/************************** Detection *********************************/
107*f005ef32Sjsg 	bool (*detect_link)(struct dc_link *link, enum dc_detect_reason reason);
108*f005ef32Sjsg 	bool (*detect_connection_type)(struct dc_link *link,
109*f005ef32Sjsg 			enum dc_connection_type *type);
110*f005ef32Sjsg 	struct dc_sink *(*add_remote_sink)(
111*f005ef32Sjsg 			struct dc_link *link,
112*f005ef32Sjsg 			const uint8_t *edid,
113*f005ef32Sjsg 			int len,
114*f005ef32Sjsg 			struct dc_sink_init_data *init_data);
115*f005ef32Sjsg 	void (*remove_remote_sink)(struct dc_link *link, struct dc_sink *sink);
116*f005ef32Sjsg 	bool (*get_hpd_state)(struct dc_link *link);
117*f005ef32Sjsg 	struct gpio *(*get_hpd_gpio)(struct dc_bios *dcb,
118*f005ef32Sjsg 			struct graphics_object_id link_id,
119*f005ef32Sjsg 			struct gpio_service *gpio_service);
120*f005ef32Sjsg 	void (*enable_hpd)(const struct dc_link *link);
121*f005ef32Sjsg 	void (*disable_hpd)(const struct dc_link *link);
122*f005ef32Sjsg 	void (*enable_hpd_filter)(struct dc_link *link, bool enable);
123*f005ef32Sjsg 	bool (*reset_cur_dp_mst_topology)(struct dc_link *link);
124*f005ef32Sjsg 	const struct dc_link_status *(*get_status)(const struct dc_link *link);
125*f005ef32Sjsg 	bool (*is_hdcp1x_supported)(struct dc_link *link,
126*f005ef32Sjsg 			enum amd_signal_type signal);
127*f005ef32Sjsg 	bool (*is_hdcp2x_supported)(struct dc_link *link,
128*f005ef32Sjsg 			enum amd_signal_type signal);
129*f005ef32Sjsg 	void (*clear_dprx_states)(struct dc_link *link);
130*f005ef32Sjsg 
131*f005ef32Sjsg 
132*f005ef32Sjsg 	/*************************** Resource *********************************/
133*f005ef32Sjsg 	void (*get_cur_res_map)(const struct dc *dc, uint32_t *map);
134*f005ef32Sjsg 	void (*restore_res_map)(const struct dc *dc, uint32_t *map);
135*f005ef32Sjsg 	void (*get_cur_link_res)(const struct dc_link *link,
136*f005ef32Sjsg 			struct link_resource *link_res);
137*f005ef32Sjsg 
138*f005ef32Sjsg 
139*f005ef32Sjsg 	/*************************** Validation *******************************/
140*f005ef32Sjsg 	enum dc_status (*validate_mode_timing)(
141*f005ef32Sjsg 			const struct dc_stream_state *stream,
142*f005ef32Sjsg 			struct dc_link *link,
143*f005ef32Sjsg 			const struct dc_crtc_timing *timing);
144*f005ef32Sjsg 	uint32_t (*dp_link_bandwidth_kbps)(
145*f005ef32Sjsg 		const struct dc_link *link,
146*f005ef32Sjsg 		const struct dc_link_settings *link_settings);
147*f005ef32Sjsg 	bool (*validate_dpia_bandwidth)(
148*f005ef32Sjsg 			const struct dc_stream_state *stream,
149*f005ef32Sjsg 			const unsigned int num_streams);
150*f005ef32Sjsg 
151*f005ef32Sjsg 
152*f005ef32Sjsg 	/*************************** DPMS *************************************/
153*f005ef32Sjsg 	void (*set_dpms_on)(struct dc_state *state, struct pipe_ctx *pipe_ctx);
154*f005ef32Sjsg 	void (*set_dpms_off)(struct pipe_ctx *pipe_ctx);
155*f005ef32Sjsg 	void (*resume)(struct dc_link *link);
156*f005ef32Sjsg 	void (*blank_all_dp_displays)(struct dc *dc);
157*f005ef32Sjsg 	void (*blank_all_edp_displays)(struct dc *dc);
158*f005ef32Sjsg 	void (*blank_dp_stream)(struct dc_link *link, bool hw_init);
159*f005ef32Sjsg 	enum dc_status (*increase_mst_payload)(
160*f005ef32Sjsg 			struct pipe_ctx *pipe_ctx, uint32_t req_pbn);
161*f005ef32Sjsg 	enum dc_status (*reduce_mst_payload)(
162*f005ef32Sjsg 			struct pipe_ctx *pipe_ctx, uint32_t req_pbn);
163*f005ef32Sjsg 	void (*set_dsc_on_stream)(struct pipe_ctx *pipe_ctx, bool enable);
164*f005ef32Sjsg 	bool (*set_dsc_enable)(struct pipe_ctx *pipe_ctx, bool enable);
165*f005ef32Sjsg 	bool (*update_dsc_config)(struct pipe_ctx *pipe_ctx);
166*f005ef32Sjsg 
167*f005ef32Sjsg 
168*f005ef32Sjsg 	/*************************** DDC **************************************/
169*f005ef32Sjsg 	struct ddc_service *(*create_ddc_service)(
170*f005ef32Sjsg 			struct ddc_service_init_data *ddc_init_data);
171*f005ef32Sjsg 	void (*destroy_ddc_service)(struct ddc_service **ddc);
172*f005ef32Sjsg 	bool (*query_ddc_data)(
173*f005ef32Sjsg 			struct ddc_service *ddc,
174*f005ef32Sjsg 			uint32_t address,
175*f005ef32Sjsg 			uint8_t *write_buf,
176*f005ef32Sjsg 			uint32_t write_size,
177*f005ef32Sjsg 			uint8_t *read_buf,
178*f005ef32Sjsg 			uint32_t read_size);
179*f005ef32Sjsg 	int (*aux_transfer_raw)(struct ddc_service *ddc,
180*f005ef32Sjsg 			struct aux_payload *payload,
181*f005ef32Sjsg 			enum aux_return_code_type *operation_result);
182*f005ef32Sjsg 	bool (*configure_fixed_vs_pe_retimer)(
183*f005ef32Sjsg 			struct ddc_service *ddc,
184*f005ef32Sjsg 			const uint8_t *data,
185*f005ef32Sjsg 			uint32_t len);
186*f005ef32Sjsg 	bool (*aux_transfer_with_retries_no_mutex)(struct ddc_service *ddc,
187*f005ef32Sjsg 			struct aux_payload *payload);
188*f005ef32Sjsg 	bool (*is_in_aux_transaction_mode)(struct ddc_service *ddc);
189*f005ef32Sjsg 	uint32_t (*get_aux_defer_delay)(struct ddc_service *ddc);
190*f005ef32Sjsg 
191*f005ef32Sjsg 
192*f005ef32Sjsg 	/*************************** DP Capability ****************************/
193*f005ef32Sjsg 	bool (*dp_is_sink_present)(struct dc_link *link);
194*f005ef32Sjsg 	bool (*dp_is_fec_supported)(const struct dc_link *link);
195*f005ef32Sjsg 	bool (*dp_is_128b_132b_signal)(struct pipe_ctx *pipe_ctx);
196*f005ef32Sjsg 	bool (*dp_get_max_link_enc_cap)(const struct dc_link *link,
197*f005ef32Sjsg 			struct dc_link_settings *max_link_enc_cap);
198*f005ef32Sjsg 	const struct dc_link_settings *(*dp_get_verified_link_cap)(
199*f005ef32Sjsg 			const struct dc_link *link);
200*f005ef32Sjsg 	enum dp_link_encoding (*dp_get_encoding_format)(
201*f005ef32Sjsg 			const struct dc_link_settings *link_settings);
202*f005ef32Sjsg 	bool (*dp_should_enable_fec)(const struct dc_link *link);
203*f005ef32Sjsg 	bool (*dp_decide_link_settings)(
204*f005ef32Sjsg 		struct dc_stream_state *stream,
205*f005ef32Sjsg 		struct dc_link_settings *link_setting);
206*f005ef32Sjsg 	enum dp_link_encoding (*mst_decide_link_encoding_format)(
207*f005ef32Sjsg 			const struct dc_link *link);
208*f005ef32Sjsg 	bool (*edp_decide_link_settings)(struct dc_link *link,
209*f005ef32Sjsg 			struct dc_link_settings *link_setting, uint32_t req_bw);
210*f005ef32Sjsg 	uint32_t (*bw_kbps_from_raw_frl_link_rate_data)(uint8_t bw);
211*f005ef32Sjsg 	bool (*dp_overwrite_extended_receiver_cap)(struct dc_link *link);
212*f005ef32Sjsg 	enum lttpr_mode (*dp_decide_lttpr_mode)(struct dc_link *link,
213*f005ef32Sjsg 			struct dc_link_settings *link_setting);
214*f005ef32Sjsg 
215*f005ef32Sjsg 
216*f005ef32Sjsg 	/*************************** DP DPIA/PHY ******************************/
217*f005ef32Sjsg 	int (*dpia_handle_usb4_bandwidth_allocation_for_link)(
218*f005ef32Sjsg 			struct dc_link *link, int peak_bw);
219*f005ef32Sjsg 	void (*dpia_handle_bw_alloc_response)(
220*f005ef32Sjsg 			struct dc_link *link, uint8_t bw, uint8_t result);
221*f005ef32Sjsg 	void (*dp_set_drive_settings)(
222*f005ef32Sjsg 		struct dc_link *link,
223*f005ef32Sjsg 		const struct link_resource *link_res,
224*f005ef32Sjsg 		struct link_training_settings *lt_settings);
225*f005ef32Sjsg 	void (*dpcd_write_rx_power_ctrl)(struct dc_link *link, bool on);
226*f005ef32Sjsg 
227*f005ef32Sjsg 
228*f005ef32Sjsg 	/*************************** DP IRQ Handler ***************************/
229*f005ef32Sjsg 	bool (*dp_parse_link_loss_status)(
230*f005ef32Sjsg 		struct dc_link *link,
231*f005ef32Sjsg 		union hpd_irq_data *hpd_irq_dpcd_data);
232*f005ef32Sjsg 	bool (*dp_should_allow_hpd_rx_irq)(const struct dc_link *link);
233*f005ef32Sjsg 	void (*dp_handle_link_loss)(struct dc_link *link);
234*f005ef32Sjsg 	enum dc_status (*dp_read_hpd_rx_irq_data)(
235*f005ef32Sjsg 		struct dc_link *link,
236*f005ef32Sjsg 		union hpd_irq_data *irq_data);
237*f005ef32Sjsg 	bool (*dp_handle_hpd_rx_irq)(struct dc_link *link,
238*f005ef32Sjsg 			union hpd_irq_data *out_hpd_irq_dpcd_data,
239*f005ef32Sjsg 			bool *out_link_loss,
240*f005ef32Sjsg 			bool defer_handling, bool *has_left_work);
241*f005ef32Sjsg 
242*f005ef32Sjsg 
243*f005ef32Sjsg 	/*************************** eDP Panel Control ************************/
244*f005ef32Sjsg 	void (*edp_panel_backlight_power_on)(
245*f005ef32Sjsg 			struct dc_link *link, bool wait_for_hpd);
246*f005ef32Sjsg 	int (*edp_get_backlight_level)(const struct dc_link *link);
247*f005ef32Sjsg 	bool (*edp_get_backlight_level_nits)(struct dc_link *link,
248*f005ef32Sjsg 			uint32_t *backlight_millinits_avg,
249*f005ef32Sjsg 			uint32_t *backlight_millinits_peak);
250*f005ef32Sjsg 	bool (*edp_set_backlight_level)(const struct dc_link *link,
251*f005ef32Sjsg 			uint32_t backlight_pwm_u16_16,
252*f005ef32Sjsg 			uint32_t frame_ramp);
253*f005ef32Sjsg 	bool (*edp_set_backlight_level_nits)(struct dc_link *link,
254*f005ef32Sjsg 			bool isHDR,
255*f005ef32Sjsg 			uint32_t backlight_millinits,
256*f005ef32Sjsg 			uint32_t transition_time_in_ms);
257*f005ef32Sjsg 	int (*edp_get_target_backlight_pwm)(const struct dc_link *link);
258*f005ef32Sjsg 	bool (*edp_get_psr_state)(
259*f005ef32Sjsg 			const struct dc_link *link, enum dc_psr_state *state);
260*f005ef32Sjsg 	bool (*edp_set_psr_allow_active)(
261*f005ef32Sjsg 			struct dc_link *link,
262*f005ef32Sjsg 			const bool *allow_active,
263*f005ef32Sjsg 			bool wait,
264*f005ef32Sjsg 			bool force_static,
265*f005ef32Sjsg 			const unsigned int *power_opts);
266*f005ef32Sjsg 	bool (*edp_setup_psr)(struct dc_link *link,
267*f005ef32Sjsg 			const struct dc_stream_state *stream,
268*f005ef32Sjsg 			struct psr_config *psr_config,
269*f005ef32Sjsg 			struct psr_context *psr_context);
270*f005ef32Sjsg 	bool (*edp_set_sink_vtotal_in_psr_active)(
271*f005ef32Sjsg 			const struct dc_link *link,
272*f005ef32Sjsg 			uint16_t psr_vtotal_idle,
273*f005ef32Sjsg 			uint16_t psr_vtotal_su);
274*f005ef32Sjsg 	void (*edp_get_psr_residency)(
275*f005ef32Sjsg 			const struct dc_link *link, uint32_t *residency);
276*f005ef32Sjsg 
277*f005ef32Sjsg 	bool (*edp_get_replay_state)(
278*f005ef32Sjsg 			const struct dc_link *link, uint64_t *state);
279*f005ef32Sjsg 	bool (*edp_set_replay_allow_active)(struct dc_link *dc_link,
280*f005ef32Sjsg 			const bool *enable, bool wait, bool force_static,
281*f005ef32Sjsg 			const unsigned int *power_opts);
282*f005ef32Sjsg 	bool (*edp_setup_replay)(struct dc_link *link,
283*f005ef32Sjsg 			const struct dc_stream_state *stream);
284*f005ef32Sjsg 	bool (*edp_set_coasting_vtotal)(
285*f005ef32Sjsg 			struct dc_link *link, uint16_t coasting_vtotal);
286*f005ef32Sjsg 	bool (*edp_replay_residency)(const struct dc_link *link,
287*f005ef32Sjsg 			unsigned int *residency, const bool is_start,
288*f005ef32Sjsg 			const bool is_alpm);
289*f005ef32Sjsg 
290*f005ef32Sjsg 	bool (*edp_wait_for_t12)(struct dc_link *link);
291*f005ef32Sjsg 	bool (*edp_is_ilr_optimization_required)(struct dc_link *link,
292*f005ef32Sjsg 			struct dc_crtc_timing *crtc_timing);
293*f005ef32Sjsg 	bool (*edp_backlight_enable_aux)(struct dc_link *link, bool enable);
294*f005ef32Sjsg 	void (*edp_add_delay_for_T9)(struct dc_link *link);
295*f005ef32Sjsg 	bool (*edp_receiver_ready_T9)(struct dc_link *link);
296*f005ef32Sjsg 	bool (*edp_receiver_ready_T7)(struct dc_link *link);
297*f005ef32Sjsg 	bool (*edp_power_alpm_dpcd_enable)(struct dc_link *link, bool enable);
298*f005ef32Sjsg 	void (*edp_set_panel_power)(struct dc_link *link, bool powerOn);
299*f005ef32Sjsg 
300*f005ef32Sjsg 
301*f005ef32Sjsg 	/*************************** DP CTS ************************************/
302*f005ef32Sjsg 	void (*dp_handle_automated_test)(struct dc_link *link);
303*f005ef32Sjsg 	bool (*dp_set_test_pattern)(
304*f005ef32Sjsg 			struct dc_link *link,
305*f005ef32Sjsg 			enum dp_test_pattern test_pattern,
306*f005ef32Sjsg 			enum dp_test_pattern_color_space test_pattern_color_space,
307*f005ef32Sjsg 			const struct link_training_settings *p_link_settings,
308*f005ef32Sjsg 			const unsigned char *p_custom_pattern,
309*f005ef32Sjsg 			unsigned int cust_pattern_size);
310*f005ef32Sjsg 	void (*dp_set_preferred_link_settings)(struct dc *dc,
311*f005ef32Sjsg 			struct dc_link_settings *link_setting,
312*f005ef32Sjsg 			struct dc_link *link);
313*f005ef32Sjsg 	void (*dp_set_preferred_training_settings)(struct dc *dc,
314*f005ef32Sjsg 			struct dc_link_settings *link_setting,
315*f005ef32Sjsg 			struct dc_link_training_overrides *lt_overrides,
316*f005ef32Sjsg 			struct dc_link *link,
317*f005ef32Sjsg 			bool skip_immediate_retrain);
318*f005ef32Sjsg 
319*f005ef32Sjsg 
320*f005ef32Sjsg 	/*************************** DP Trace *********************************/
321*f005ef32Sjsg 	bool (*dp_trace_is_initialized)(struct dc_link *link);
322*f005ef32Sjsg 	void (*dp_trace_set_is_logged_flag)(struct dc_link *link,
323*f005ef32Sjsg 			bool in_detection,
324*f005ef32Sjsg 			bool is_logged);
325*f005ef32Sjsg 	bool (*dp_trace_is_logged)(struct dc_link *link, bool in_detection);
326*f005ef32Sjsg 	unsigned long long (*dp_trace_get_lt_end_timestamp)(
327*f005ef32Sjsg 			struct dc_link *link, bool in_detection);
328*f005ef32Sjsg 	const struct dp_trace_lt_counts *(*dp_trace_get_lt_counts)(
329*f005ef32Sjsg 			struct dc_link *link, bool in_detection);
330*f005ef32Sjsg 	unsigned int (*dp_trace_get_link_loss_count)(struct dc_link *link);
331*f005ef32Sjsg 	void (*dp_trace_set_edp_power_timestamp)(struct dc_link *link,
332*f005ef32Sjsg 			bool power_up);
333*f005ef32Sjsg 	uint64_t (*dp_trace_get_edp_poweron_timestamp)(struct dc_link *link);
334*f005ef32Sjsg 	uint64_t (*dp_trace_get_edp_poweroff_timestamp)(struct dc_link *link);
335*f005ef32Sjsg 	void (*dp_trace_source_sequence)(
336*f005ef32Sjsg 			struct dc_link *link, uint8_t dp_test_mode);
337*f005ef32Sjsg };
338*f005ef32Sjsg #endif /* __DC_LINK_HPD_H__ */
339