1*fb4d8502Sjsg /* 2*fb4d8502Sjsg * Copyright 2017 Advanced Micro Devices, Inc. 3*fb4d8502Sjsg * 4*fb4d8502Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5*fb4d8502Sjsg * copy of this software and associated documentation files (the "Software"), 6*fb4d8502Sjsg * to deal in the Software without restriction, including without limitation 7*fb4d8502Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*fb4d8502Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9*fb4d8502Sjsg * Software is furnished to do so, subject to the following conditions: 10*fb4d8502Sjsg * 11*fb4d8502Sjsg * The above copyright notice and this permission notice shall be included in 12*fb4d8502Sjsg * all copies or substantial portions of the Software. 13*fb4d8502Sjsg * 14*fb4d8502Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*fb4d8502Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*fb4d8502Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*fb4d8502Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*fb4d8502Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*fb4d8502Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*fb4d8502Sjsg * OTHER DEALINGS IN THE SOFTWARE. 21*fb4d8502Sjsg * 22*fb4d8502Sjsg * Authors: AMD 23*fb4d8502Sjsg * 24*fb4d8502Sjsg */ 25*fb4d8502Sjsg 26*fb4d8502Sjsg #ifndef __DAL_IPP_H__ 27*fb4d8502Sjsg #define __DAL_IPP_H__ 28*fb4d8502Sjsg 29*fb4d8502Sjsg #include "hw_shared.h" 30*fb4d8502Sjsg #include "dc_hw_types.h" 31*fb4d8502Sjsg 32*fb4d8502Sjsg #define MAXTRIX_COEFFICIENTS_NUMBER 12 33*fb4d8502Sjsg #define MAXTRIX_COEFFICIENTS_WRAP_NUMBER (MAXTRIX_COEFFICIENTS_NUMBER + 4) 34*fb4d8502Sjsg #define MAX_OVL_MATRIX_COUNT 12 35*fb4d8502Sjsg 36*fb4d8502Sjsg /* IPP RELATED */ 37*fb4d8502Sjsg struct input_pixel_processor { 38*fb4d8502Sjsg struct dc_context *ctx; 39*fb4d8502Sjsg unsigned int inst; 40*fb4d8502Sjsg const struct ipp_funcs *funcs; 41*fb4d8502Sjsg }; 42*fb4d8502Sjsg 43*fb4d8502Sjsg enum ipp_prescale_mode { 44*fb4d8502Sjsg IPP_PRESCALE_MODE_BYPASS, 45*fb4d8502Sjsg IPP_PRESCALE_MODE_FIXED_SIGNED, 46*fb4d8502Sjsg IPP_PRESCALE_MODE_FLOAT_SIGNED, 47*fb4d8502Sjsg IPP_PRESCALE_MODE_FIXED_UNSIGNED, 48*fb4d8502Sjsg IPP_PRESCALE_MODE_FLOAT_UNSIGNED 49*fb4d8502Sjsg }; 50*fb4d8502Sjsg 51*fb4d8502Sjsg struct ipp_prescale_params { 52*fb4d8502Sjsg enum ipp_prescale_mode mode; 53*fb4d8502Sjsg uint16_t bias; 54*fb4d8502Sjsg uint16_t scale; 55*fb4d8502Sjsg }; 56*fb4d8502Sjsg 57*fb4d8502Sjsg 58*fb4d8502Sjsg 59*fb4d8502Sjsg enum ovl_color_space { 60*fb4d8502Sjsg OVL_COLOR_SPACE_UNKNOWN = 0, 61*fb4d8502Sjsg OVL_COLOR_SPACE_RGB, 62*fb4d8502Sjsg OVL_COLOR_SPACE_YUV601, 63*fb4d8502Sjsg OVL_COLOR_SPACE_YUV709 64*fb4d8502Sjsg }; 65*fb4d8502Sjsg 66*fb4d8502Sjsg 67*fb4d8502Sjsg struct ipp_funcs { 68*fb4d8502Sjsg 69*fb4d8502Sjsg /*** cursor ***/ 70*fb4d8502Sjsg void (*ipp_cursor_set_position)( 71*fb4d8502Sjsg struct input_pixel_processor *ipp, 72*fb4d8502Sjsg const struct dc_cursor_position *position, 73*fb4d8502Sjsg const struct dc_cursor_mi_param *param); 74*fb4d8502Sjsg 75*fb4d8502Sjsg void (*ipp_cursor_set_attributes)( 76*fb4d8502Sjsg struct input_pixel_processor *ipp, 77*fb4d8502Sjsg const struct dc_cursor_attributes *attributes); 78*fb4d8502Sjsg 79*fb4d8502Sjsg /*** setup input pixel processing ***/ 80*fb4d8502Sjsg 81*fb4d8502Sjsg /* put the entire pixel processor to bypass */ 82*fb4d8502Sjsg void (*ipp_full_bypass)( 83*fb4d8502Sjsg struct input_pixel_processor *ipp); 84*fb4d8502Sjsg 85*fb4d8502Sjsg /* setup ipp to expand/convert input to pixel processor internal format */ 86*fb4d8502Sjsg void (*ipp_setup)( 87*fb4d8502Sjsg struct input_pixel_processor *ipp, 88*fb4d8502Sjsg enum surface_pixel_format format, 89*fb4d8502Sjsg enum expansion_mode mode, 90*fb4d8502Sjsg struct dc_csc_transform input_csc_color_matrix, 91*fb4d8502Sjsg enum dc_color_space input_color_space); 92*fb4d8502Sjsg 93*fb4d8502Sjsg /* DCE function to setup IPP. TODO: see if we can consolidate to setup */ 94*fb4d8502Sjsg void (*ipp_program_prescale)( 95*fb4d8502Sjsg struct input_pixel_processor *ipp, 96*fb4d8502Sjsg struct ipp_prescale_params *params); 97*fb4d8502Sjsg 98*fb4d8502Sjsg void (*ipp_program_input_lut)( 99*fb4d8502Sjsg struct input_pixel_processor *ipp, 100*fb4d8502Sjsg const struct dc_gamma *gamma); 101*fb4d8502Sjsg 102*fb4d8502Sjsg /*** DEGAMMA RELATED ***/ 103*fb4d8502Sjsg void (*ipp_set_degamma)( 104*fb4d8502Sjsg struct input_pixel_processor *ipp, 105*fb4d8502Sjsg enum ipp_degamma_mode mode); 106*fb4d8502Sjsg 107*fb4d8502Sjsg void (*ipp_program_degamma_pwl)( 108*fb4d8502Sjsg struct input_pixel_processor *ipp, 109*fb4d8502Sjsg const struct pwl_params *params); 110*fb4d8502Sjsg 111*fb4d8502Sjsg void (*ipp_destroy)(struct input_pixel_processor **ipp); 112*fb4d8502Sjsg }; 113*fb4d8502Sjsg 114*fb4d8502Sjsg #endif /* __DAL_IPP_H__ */ 115