xref: /openbsd-src/sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h (revision f005ef32267c16bdb134f0e9fa4477dbe07c263a)
1fb4d8502Sjsg /*
2fb4d8502Sjsg  * Copyright 2012-15 Advanced Micro Devices, Inc.
3fb4d8502Sjsg  *
4fb4d8502Sjsg  * Permission is hereby granted, free of charge, to any person obtaining a
5fb4d8502Sjsg  * copy of this software and associated documentation files (the "Software"),
6fb4d8502Sjsg  * to deal in the Software without restriction, including without limitation
7fb4d8502Sjsg  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8fb4d8502Sjsg  * and/or sell copies of the Software, and to permit persons to whom the
9fb4d8502Sjsg  * Software is furnished to do so, subject to the following conditions:
10fb4d8502Sjsg  *
11fb4d8502Sjsg  * The above copyright notice and this permission notice shall be included in
12fb4d8502Sjsg  * all copies or substantial portions of the Software.
13fb4d8502Sjsg  *
14fb4d8502Sjsg  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15fb4d8502Sjsg  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16fb4d8502Sjsg  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17fb4d8502Sjsg  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18fb4d8502Sjsg  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19fb4d8502Sjsg  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20fb4d8502Sjsg  * OTHER DEALINGS IN THE SOFTWARE.
21fb4d8502Sjsg  *
22fb4d8502Sjsg  * Authors: AMD
23fb4d8502Sjsg  *
24fb4d8502Sjsg  */
25fb4d8502Sjsg 
26fb4d8502Sjsg #ifndef __DAL_HUBP_H__
27fb4d8502Sjsg #define __DAL_HUBP_H__
28fb4d8502Sjsg 
29fb4d8502Sjsg #include "mem_input.h"
301bb76ff1Sjsg #include "cursor_reg_cache.h"
31fb4d8502Sjsg 
32c349dbc7Sjsg #define OPP_ID_INVALID 0xf
335ca02815Sjsg #define MAX_TTU 0xffffff
34c349dbc7Sjsg 
35fb4d8502Sjsg 
36fb4d8502Sjsg enum cursor_pitch {
37fb4d8502Sjsg 	CURSOR_PITCH_64_PIXELS = 0,
38fb4d8502Sjsg 	CURSOR_PITCH_128_PIXELS,
39fb4d8502Sjsg 	CURSOR_PITCH_256_PIXELS
40fb4d8502Sjsg };
41fb4d8502Sjsg 
42fb4d8502Sjsg enum cursor_lines_per_chunk {
43c349dbc7Sjsg 	CURSOR_LINE_PER_CHUNK_1 = 0, /* new for DCN2 */
44fb4d8502Sjsg 	CURSOR_LINE_PER_CHUNK_2 = 1,
45fb4d8502Sjsg 	CURSOR_LINE_PER_CHUNK_4,
46fb4d8502Sjsg 	CURSOR_LINE_PER_CHUNK_8,
47fb4d8502Sjsg 	CURSOR_LINE_PER_CHUNK_16
48fb4d8502Sjsg };
49fb4d8502Sjsg 
50c349dbc7Sjsg enum hubp_ind_block_size {
51c349dbc7Sjsg 	hubp_ind_block_unconstrained = 0,
52c349dbc7Sjsg 	hubp_ind_block_64b,
53ad8b1aafSjsg 	hubp_ind_block_128b,
54ad8b1aafSjsg 	hubp_ind_block_64b_no_128bcl,
55c349dbc7Sjsg };
56c349dbc7Sjsg 
57fb4d8502Sjsg struct hubp {
58fb4d8502Sjsg 	const struct hubp_funcs *funcs;
59fb4d8502Sjsg 	struct dc_context *ctx;
60fb4d8502Sjsg 	struct dc_plane_address request_address;
61fb4d8502Sjsg 	int inst;
62fb4d8502Sjsg 
63fb4d8502Sjsg 	/* run time states */
64fb4d8502Sjsg 	int opp_id;
65fb4d8502Sjsg 	int mpcc_id;
66fb4d8502Sjsg 	struct dc_cursor_attributes curs_attr;
671bb76ff1Sjsg 	struct dc_cursor_position curs_pos;
68fb4d8502Sjsg 	bool power_gated;
691bb76ff1Sjsg 
701bb76ff1Sjsg 	struct cursor_position_cache_hubp  pos;
711bb76ff1Sjsg 	struct cursor_attribute_cache_hubp att;
721bb76ff1Sjsg 	struct cursor_rect cur_rect;
73fb4d8502Sjsg };
74fb4d8502Sjsg 
75c349dbc7Sjsg struct surface_flip_registers {
76c349dbc7Sjsg 	uint32_t DCSURF_SURFACE_CONTROL;
77c349dbc7Sjsg 	uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH;
78c349dbc7Sjsg 	uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS;
79c349dbc7Sjsg 	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH;
80c349dbc7Sjsg 	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS;
81c349dbc7Sjsg 	uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C;
82c349dbc7Sjsg 	uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C;
83c349dbc7Sjsg 	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C;
84c349dbc7Sjsg 	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C;
85c349dbc7Sjsg 	uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH;
86c349dbc7Sjsg 	uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS;
87c349dbc7Sjsg 	uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH;
88c349dbc7Sjsg 	uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS;
89c349dbc7Sjsg 	bool tmz_surface;
90c349dbc7Sjsg 	bool immediate;
91c349dbc7Sjsg 	uint8_t vmid;
92c349dbc7Sjsg 	bool grph_stereo;
93c349dbc7Sjsg };
94c349dbc7Sjsg 
95fb4d8502Sjsg struct hubp_funcs {
96fb4d8502Sjsg 	void (*hubp_setup)(
97fb4d8502Sjsg 			struct hubp *hubp,
98fb4d8502Sjsg 			struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
99fb4d8502Sjsg 			struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
100fb4d8502Sjsg 			struct _vcs_dpi_display_rq_regs_st *rq_regs,
101fb4d8502Sjsg 			struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
102fb4d8502Sjsg 
103c349dbc7Sjsg 	void (*hubp_setup_interdependent)(
104c349dbc7Sjsg 			struct hubp *hubp,
105c349dbc7Sjsg 			struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
106c349dbc7Sjsg 			struct _vcs_dpi_display_ttu_regs_st *ttu_regs);
107c349dbc7Sjsg 
108fb4d8502Sjsg 	void (*dcc_control)(struct hubp *hubp, bool enable,
109c349dbc7Sjsg 			enum hubp_ind_block_size blk_size);
110c349dbc7Sjsg 
111fb4d8502Sjsg 	void (*mem_program_viewport)(
112fb4d8502Sjsg 			struct hubp *hubp,
113fb4d8502Sjsg 			const struct rect *viewport,
114fb4d8502Sjsg 			const struct rect *viewport_c);
115fb4d8502Sjsg 
116fb4d8502Sjsg 	bool (*hubp_program_surface_flip_and_addr)(
117fb4d8502Sjsg 		struct hubp *hubp,
118fb4d8502Sjsg 		const struct dc_plane_address *address,
119fb4d8502Sjsg 		bool flip_immediate);
120fb4d8502Sjsg 
121fb4d8502Sjsg 	void (*hubp_program_pte_vm)(
122fb4d8502Sjsg 		struct hubp *hubp,
123fb4d8502Sjsg 		enum surface_pixel_format format,
124fb4d8502Sjsg 		union dc_tiling_info *tiling_info,
125fb4d8502Sjsg 		enum dc_rotation_angle rotation);
126fb4d8502Sjsg 
127fb4d8502Sjsg 	void (*hubp_set_vm_system_aperture_settings)(
128fb4d8502Sjsg 			struct hubp *hubp,
129fb4d8502Sjsg 			struct vm_system_aperture_param *apt);
130fb4d8502Sjsg 
131fb4d8502Sjsg 	void (*hubp_set_vm_context0_settings)(
132fb4d8502Sjsg 			struct hubp *hubp,
133fb4d8502Sjsg 			const struct vm_context0_param *vm0);
134fb4d8502Sjsg 
135fb4d8502Sjsg 	void (*hubp_program_surface_config)(
136fb4d8502Sjsg 		struct hubp *hubp,
137fb4d8502Sjsg 		enum surface_pixel_format format,
138fb4d8502Sjsg 		union dc_tiling_info *tiling_info,
139c349dbc7Sjsg 		struct plane_size *plane_size,
140fb4d8502Sjsg 		enum dc_rotation_angle rotation,
141fb4d8502Sjsg 		struct dc_plane_dcc_param *dcc,
142c349dbc7Sjsg 		bool horizontal_mirror,
143c349dbc7Sjsg 		unsigned int compa_level);
144fb4d8502Sjsg 
145fb4d8502Sjsg 	bool (*hubp_is_flip_pending)(struct hubp *hubp);
146fb4d8502Sjsg 
147fb4d8502Sjsg 	void (*set_blank)(struct hubp *hubp, bool blank);
1481bb76ff1Sjsg 	void (*set_blank_regs)(struct hubp *hubp, bool blank);
149*f005ef32Sjsg #ifdef CONFIG_DRM_AMD_DC_FP
1501bb76ff1Sjsg 	void (*phantom_hubp_post_enable)(struct hubp *hubp);
1511bb76ff1Sjsg #endif
152fb4d8502Sjsg 	void (*set_hubp_blank_en)(struct hubp *hubp, bool blank);
153fb4d8502Sjsg 
154fb4d8502Sjsg 	void (*set_cursor_attributes)(
155fb4d8502Sjsg 			struct hubp *hubp,
156fb4d8502Sjsg 			const struct dc_cursor_attributes *attr);
157fb4d8502Sjsg 
158fb4d8502Sjsg 	void (*set_cursor_position)(
159fb4d8502Sjsg 			struct hubp *hubp,
160fb4d8502Sjsg 			const struct dc_cursor_position *pos,
161fb4d8502Sjsg 			const struct dc_cursor_mi_param *param);
162fb4d8502Sjsg 
163fb4d8502Sjsg 	void (*hubp_disconnect)(struct hubp *hubp);
164fb4d8502Sjsg 
165fb4d8502Sjsg 	void (*hubp_clk_cntl)(struct hubp *hubp, bool enable);
166fb4d8502Sjsg 	void (*hubp_vtg_sel)(struct hubp *hubp, uint32_t otg_inst);
167fb4d8502Sjsg 	void (*hubp_read_state)(struct hubp *hubp);
168c349dbc7Sjsg 	void (*hubp_clear_underflow)(struct hubp *hubp);
169fb4d8502Sjsg 	void (*hubp_disable_control)(struct hubp *hubp, bool disable_hubp);
170fb4d8502Sjsg 	unsigned int (*hubp_get_underflow_status)(struct hubp *hubp);
171c349dbc7Sjsg 	void (*hubp_init)(struct hubp *hubp);
172c349dbc7Sjsg 
173c349dbc7Sjsg 	void (*dmdata_set_attributes)(
174c349dbc7Sjsg 			struct hubp *hubp,
175c349dbc7Sjsg 			const struct dc_dmdata_attributes *attr);
176c349dbc7Sjsg 
177c349dbc7Sjsg 	void (*dmdata_load)(
178c349dbc7Sjsg 			struct hubp *hubp,
179c349dbc7Sjsg 			uint32_t dmdata_sw_size,
180c349dbc7Sjsg 			const uint32_t *dmdata_sw_data);
181c349dbc7Sjsg 	bool (*dmdata_status_done)(struct hubp *hubp);
182c349dbc7Sjsg 	void (*hubp_enable_tripleBuffer)(
183c349dbc7Sjsg 		struct hubp *hubp,
184c349dbc7Sjsg 		bool enable);
185c349dbc7Sjsg 
186c349dbc7Sjsg 	bool (*hubp_is_triplebuffer_enabled)(
187c349dbc7Sjsg 		struct hubp *hubp);
188c349dbc7Sjsg 
189c349dbc7Sjsg 	void (*hubp_set_flip_control_surface_gsl)(
190c349dbc7Sjsg 		struct hubp *hubp,
191c349dbc7Sjsg 		bool enable);
192c349dbc7Sjsg 
193c349dbc7Sjsg 	void (*validate_dml_output)(
194c349dbc7Sjsg 			struct hubp *hubp,
195c349dbc7Sjsg 			struct dc_context *ctx,
196c349dbc7Sjsg 			struct _vcs_dpi_display_rq_regs_st *dml_rq_regs,
197c349dbc7Sjsg 			struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr,
198c349dbc7Sjsg 			struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr);
1995ca02815Sjsg 	void (*set_unbounded_requesting)(
2005ca02815Sjsg 		struct hubp *hubp,
2015ca02815Sjsg 		bool enable);
2025ca02815Sjsg 	bool (*hubp_in_blank)(struct hubp *hubp);
2035ca02815Sjsg 	void (*hubp_soft_reset)(struct hubp *hubp, bool reset);
2045ca02815Sjsg 
2051bb76ff1Sjsg 	void (*hubp_update_force_pstate_disallow)(struct hubp *hubp, bool allow);
206*f005ef32Sjsg 	void (*hubp_update_force_cursor_pstate_disallow)(struct hubp *hubp, bool allow);
2071bb76ff1Sjsg 	void (*hubp_update_mall_sel)(struct hubp *hubp, uint32_t mall_sel, bool c_cursor);
2081bb76ff1Sjsg 	void (*hubp_prepare_subvp_buffering)(struct hubp *hubp, bool enable);
2091bb76ff1Sjsg 
2105ca02815Sjsg 	void (*hubp_set_flip_int)(struct hubp *hubp);
211fb4d8502Sjsg 
2121bb76ff1Sjsg 	void (*program_extended_blank)(struct hubp *hubp,
2131bb76ff1Sjsg 			unsigned int min_dst_y_next_start_optimized);
2141bb76ff1Sjsg 
2151bb76ff1Sjsg 	void (*hubp_wait_pipe_read_start)(struct hubp *hubp);
216fb4d8502Sjsg };
217fb4d8502Sjsg 
218fb4d8502Sjsg #endif
219