1fb4d8502Sjsg /* 2fb4d8502Sjsg * Copyright 2012-16 Advanced Micro Devices, Inc. 3fb4d8502Sjsg * 4fb4d8502Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5fb4d8502Sjsg * copy of this software and associated documentation files (the "Software"), 6fb4d8502Sjsg * to deal in the Software without restriction, including without limitation 7fb4d8502Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8fb4d8502Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9fb4d8502Sjsg * Software is furnished to do so, subject to the following conditions: 10fb4d8502Sjsg * 11fb4d8502Sjsg * The above copyright notice and this permission notice shall be included in 12fb4d8502Sjsg * all copies or substantial portions of the Software. 13fb4d8502Sjsg * 14fb4d8502Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15fb4d8502Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16fb4d8502Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17fb4d8502Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18fb4d8502Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19fb4d8502Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20fb4d8502Sjsg * OTHER DEALINGS IN THE SOFTWARE. 21fb4d8502Sjsg * 22fb4d8502Sjsg * Authors: AMD 23fb4d8502Sjsg * 24fb4d8502Sjsg */ 25fb4d8502Sjsg 26fb4d8502Sjsg #ifndef __DAL_GPIO_H__ 27fb4d8502Sjsg #define __DAL_GPIO_H__ 28fb4d8502Sjsg 29fb4d8502Sjsg #include "gpio_types.h" 30fb4d8502Sjsg 31*c349dbc7Sjsg 32*c349dbc7Sjsg union gpio_hw_container { 33*c349dbc7Sjsg struct hw_ddc *ddc; 34*c349dbc7Sjsg struct hw_generic *generic; 35*c349dbc7Sjsg struct hw_hpd *hpd; 36*c349dbc7Sjsg }; 37*c349dbc7Sjsg 38fb4d8502Sjsg struct gpio { 39fb4d8502Sjsg struct gpio_service *service; 40fb4d8502Sjsg struct hw_gpio_pin *pin; 41fb4d8502Sjsg enum gpio_id id; 42fb4d8502Sjsg uint32_t en; 43*c349dbc7Sjsg 44*c349dbc7Sjsg union gpio_hw_container hw_container; 45fb4d8502Sjsg enum gpio_mode mode; 46*c349dbc7Sjsg 47fb4d8502Sjsg /* when GPIO comes from VBIOS, it has defined output state */ 48fb4d8502Sjsg enum gpio_pin_output_state output_state; 49fb4d8502Sjsg }; 50fb4d8502Sjsg 51fb4d8502Sjsg #if 0 52fb4d8502Sjsg struct gpio_funcs { 53fb4d8502Sjsg 54fb4d8502Sjsg struct hw_gpio_pin *(*create_ddc_data)( 55fb4d8502Sjsg struct dc_context *ctx, 56fb4d8502Sjsg enum gpio_id id, 57fb4d8502Sjsg uint32_t en); 58fb4d8502Sjsg struct hw_gpio_pin *(*create_ddc_clock)( 59fb4d8502Sjsg struct dc_context *ctx, 60fb4d8502Sjsg enum gpio_id id, 61fb4d8502Sjsg uint32_t en); 62fb4d8502Sjsg struct hw_gpio_pin *(*create_generic)( 63fb4d8502Sjsg struct dc_context *ctx, 64fb4d8502Sjsg enum gpio_id id, 65fb4d8502Sjsg uint32_t en); 66fb4d8502Sjsg struct hw_gpio_pin *(*create_hpd)( 67fb4d8502Sjsg struct dc_context *ctx, 68fb4d8502Sjsg enum gpio_id id, 69fb4d8502Sjsg uint32_t en); 70fb4d8502Sjsg struct hw_gpio_pin *(*create_gpio_pad)( 71fb4d8502Sjsg struct dc_context *ctx, 72fb4d8502Sjsg enum gpio_id id, 73fb4d8502Sjsg uint32_t en); 74fb4d8502Sjsg struct hw_gpio_pin *(*create_sync)( 75fb4d8502Sjsg struct dc_context *ctx, 76fb4d8502Sjsg enum gpio_id id, 77fb4d8502Sjsg uint32_t en); 78fb4d8502Sjsg struct hw_gpio_pin *(*create_gsl)( 79fb4d8502Sjsg struct dc_context *ctx, 80fb4d8502Sjsg enum gpio_id id, 81fb4d8502Sjsg uint32_t en); 82fb4d8502Sjsg 83fb4d8502Sjsg /* HW translation */ 84fb4d8502Sjsg bool (*offset_to_id)( 85fb4d8502Sjsg uint32_t offset, 86fb4d8502Sjsg uint32_t mask, 87fb4d8502Sjsg enum gpio_id *id, 88fb4d8502Sjsg uint32_t *en); 89fb4d8502Sjsg bool (*id_to_offset)( 90fb4d8502Sjsg enum gpio_id id, 91fb4d8502Sjsg uint32_t en, 92fb4d8502Sjsg struct gpio_pin_info *info); 93fb4d8502Sjsg }; 94fb4d8502Sjsg #endif 95fb4d8502Sjsg 96fb4d8502Sjsg #endif /* __DAL_GPIO__ */ 97