1fb4d8502Sjsg /* Copyright 2012-15 Advanced Micro Devices, Inc. 2fb4d8502Sjsg * 3fb4d8502Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 4fb4d8502Sjsg * copy of this software and associated documentation files (the "Software"), 5fb4d8502Sjsg * to deal in the Software without restriction, including without limitation 6fb4d8502Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7fb4d8502Sjsg * and/or sell copies of the Software, and to permit persons to whom the 8fb4d8502Sjsg * Software is furnished to do so, subject to the following conditions: 9fb4d8502Sjsg * 10fb4d8502Sjsg * The above copyright notice and this permission notice shall be included in 11fb4d8502Sjsg * all copies or substantial portions of the Software. 12fb4d8502Sjsg * 13fb4d8502Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14fb4d8502Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15fb4d8502Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16fb4d8502Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17fb4d8502Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18fb4d8502Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19fb4d8502Sjsg * OTHER DEALINGS IN THE SOFTWARE. 20fb4d8502Sjsg * 21fb4d8502Sjsg * Authors: AMD 22fb4d8502Sjsg * 23fb4d8502Sjsg */ 24fb4d8502Sjsg 25fb4d8502Sjsg #ifndef __DC_DMCU_H__ 26fb4d8502Sjsg #define __DC_DMCU_H__ 27fb4d8502Sjsg 28fb4d8502Sjsg #include "dm_services_types.h" 29fb4d8502Sjsg 30c349dbc7Sjsg /* If HW itself ever powered down it will be 0. 31c349dbc7Sjsg * fwDmcuInit will write to 1. 32c349dbc7Sjsg * Driver will only call MCP init if current state is 1, 33c349dbc7Sjsg * and the MCP command will transition this to 2. 34c349dbc7Sjsg */ 35fb4d8502Sjsg enum dmcu_state { 36c349dbc7Sjsg DMCU_UNLOADED = 0, 37c349dbc7Sjsg DMCU_LOADED_UNINITIALIZED = 1, 38c349dbc7Sjsg DMCU_RUNNING = 2, 39c349dbc7Sjsg }; 40c349dbc7Sjsg 41c349dbc7Sjsg struct dmcu_version { 42c349dbc7Sjsg unsigned int interface_version; 43c349dbc7Sjsg unsigned int abm_version; 44c349dbc7Sjsg unsigned int psr_version; 45c349dbc7Sjsg unsigned int build_version; 46fb4d8502Sjsg }; 47fb4d8502Sjsg 48fb4d8502Sjsg struct dmcu { 49fb4d8502Sjsg struct dc_context *ctx; 50fb4d8502Sjsg const struct dmcu_funcs *funcs; 51fb4d8502Sjsg 52fb4d8502Sjsg enum dmcu_state dmcu_state; 53fb4d8502Sjsg struct dmcu_version dmcu_version; 54fb4d8502Sjsg unsigned int cached_wait_loop_number; 55c349dbc7Sjsg uint32_t psp_version; 56c349dbc7Sjsg bool auto_load_dmcu; 57fb4d8502Sjsg }; 58fb4d8502Sjsg 59fb4d8502Sjsg struct dmcu_funcs { 60fb4d8502Sjsg bool (*dmcu_init)(struct dmcu *dmcu); 61fb4d8502Sjsg bool (*load_iram)(struct dmcu *dmcu, 62fb4d8502Sjsg unsigned int start_offset, 63fb4d8502Sjsg const char *src, 64fb4d8502Sjsg unsigned int bytes); 65fb4d8502Sjsg void (*set_psr_enable)(struct dmcu *dmcu, bool enable, bool wait); 66fb4d8502Sjsg bool (*setup_psr)(struct dmcu *dmcu, 67fb4d8502Sjsg struct dc_link *link, 68fb4d8502Sjsg struct psr_context *psr_context); 695ca02815Sjsg void (*get_psr_state)(struct dmcu *dmcu, enum dc_psr_state *dc_psr_state); 70fb4d8502Sjsg void (*set_psr_wait_loop)(struct dmcu *dmcu, 71fb4d8502Sjsg unsigned int wait_loop_number); 72fb4d8502Sjsg void (*get_psr_wait_loop)(struct dmcu *dmcu, 73fb4d8502Sjsg unsigned int *psr_wait_loop_number); 74fb4d8502Sjsg bool (*is_dmcu_initialized)(struct dmcu *dmcu); 75c349dbc7Sjsg bool (*lock_phy)(struct dmcu *dmcu); 76c349dbc7Sjsg bool (*unlock_phy)(struct dmcu *dmcu); 775ca02815Sjsg bool (*send_edid_cea)(struct dmcu *dmcu, 785ca02815Sjsg int offset, 795ca02815Sjsg int total_length, 805ca02815Sjsg uint8_t *data, 815ca02815Sjsg int length); 825ca02815Sjsg bool (*recv_amd_vsdb)(struct dmcu *dmcu, 835ca02815Sjsg int *version, 845ca02815Sjsg int *min_frame_rate, 855ca02815Sjsg int *max_frame_rate); 865ca02815Sjsg bool (*recv_edid_cea_ack)(struct dmcu *dmcu, int *offset); 875ca02815Sjsg #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 885ca02815Sjsg void (*forward_crc_window)(struct dmcu *dmcu, 89*f005ef32Sjsg struct rect *rect, 905ca02815Sjsg struct otg_phy_mux *mux_mapping); 915ca02815Sjsg void (*stop_crc_win_update)(struct dmcu *dmcu, 925ca02815Sjsg struct otg_phy_mux *mux_mapping); 935ca02815Sjsg #endif 94fb4d8502Sjsg }; 95fb4d8502Sjsg 96fb4d8502Sjsg #endif 97