1*fb4d8502Sjsg /* 2*fb4d8502Sjsg * Copyright 2015-2017 Advanced Micro Devices, Inc. 3*fb4d8502Sjsg * 4*fb4d8502Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5*fb4d8502Sjsg * copy of this software and associated documentation files (the "Software"), 6*fb4d8502Sjsg * to deal in the Software without restriction, including without limitation 7*fb4d8502Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*fb4d8502Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9*fb4d8502Sjsg * Software is furnished to do so, subject to the following conditions: 10*fb4d8502Sjsg * 11*fb4d8502Sjsg * The above copyright notice and this permission notice shall be included in 12*fb4d8502Sjsg * all copies or substantial portions of the Software. 13*fb4d8502Sjsg * 14*fb4d8502Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*fb4d8502Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*fb4d8502Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*fb4d8502Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*fb4d8502Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*fb4d8502Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*fb4d8502Sjsg * OTHER DEALINGS IN THE SOFTWARE. 21*fb4d8502Sjsg * 22*fb4d8502Sjsg * Authors: AMD 23*fb4d8502Sjsg * 24*fb4d8502Sjsg */ 25*fb4d8502Sjsg 26*fb4d8502Sjsg /** 27*fb4d8502Sjsg * Bandwidth and Watermark calculations interface. 28*fb4d8502Sjsg * (Refer to "DCEx_mode_support.xlsm" from Perforce.) 29*fb4d8502Sjsg */ 30*fb4d8502Sjsg #ifndef __DCE_CALCS_H__ 31*fb4d8502Sjsg #define __DCE_CALCS_H__ 32*fb4d8502Sjsg 33*fb4d8502Sjsg #include "bw_fixed.h" 34*fb4d8502Sjsg 35*fb4d8502Sjsg struct pipe_ctx; 36*fb4d8502Sjsg struct dc; 37*fb4d8502Sjsg struct dc_state; 38*fb4d8502Sjsg struct dce_bw_output; 39*fb4d8502Sjsg 40*fb4d8502Sjsg enum bw_calcs_version { 41*fb4d8502Sjsg BW_CALCS_VERSION_INVALID, 42*fb4d8502Sjsg BW_CALCS_VERSION_CARRIZO, 43*fb4d8502Sjsg BW_CALCS_VERSION_POLARIS10, 44*fb4d8502Sjsg BW_CALCS_VERSION_POLARIS11, 45*fb4d8502Sjsg BW_CALCS_VERSION_POLARIS12, 46*fb4d8502Sjsg BW_CALCS_VERSION_VEGAM, 47*fb4d8502Sjsg BW_CALCS_VERSION_STONEY, 48*fb4d8502Sjsg BW_CALCS_VERSION_VEGA10 49*fb4d8502Sjsg }; 50*fb4d8502Sjsg 51*fb4d8502Sjsg /******************************************************************************* 52*fb4d8502Sjsg * There are three types of input into Calculations: 53*fb4d8502Sjsg * 1. per-DCE static values - these are "hardcoded" properties of the DCEIP 54*fb4d8502Sjsg * 2. board-level values - these are generally coming from VBIOS parser 55*fb4d8502Sjsg * 3. mode/configuration values - depending Mode, Scaling number of Displays etc. 56*fb4d8502Sjsg ******************************************************************************/ 57*fb4d8502Sjsg 58*fb4d8502Sjsg enum bw_defines { 59*fb4d8502Sjsg //Common 60*fb4d8502Sjsg bw_def_no = 0, 61*fb4d8502Sjsg bw_def_none = 0, 62*fb4d8502Sjsg bw_def_yes = 1, 63*fb4d8502Sjsg bw_def_ok = 1, 64*fb4d8502Sjsg bw_def_high = 2, 65*fb4d8502Sjsg bw_def_mid = 1, 66*fb4d8502Sjsg bw_def_low = 0, 67*fb4d8502Sjsg 68*fb4d8502Sjsg //Internal 69*fb4d8502Sjsg bw_defs_start = 255, 70*fb4d8502Sjsg bw_def_underlay422, 71*fb4d8502Sjsg bw_def_underlay420_luma, 72*fb4d8502Sjsg bw_def_underlay420_chroma, 73*fb4d8502Sjsg bw_def_underlay444, 74*fb4d8502Sjsg bw_def_graphics, 75*fb4d8502Sjsg bw_def_display_write_back420_luma, 76*fb4d8502Sjsg bw_def_display_write_back420_chroma, 77*fb4d8502Sjsg bw_def_portrait, 78*fb4d8502Sjsg bw_def_hsr_mtn_4, 79*fb4d8502Sjsg bw_def_hsr_mtn_h_taps, 80*fb4d8502Sjsg bw_def_ceiling__h_taps_div_4___meq_hsr, 81*fb4d8502Sjsg bw_def_invalid_linear_or_stereo_mode, 82*fb4d8502Sjsg bw_def_invalid_rotation_or_bpp_or_stereo, 83*fb4d8502Sjsg bw_def_vsr_mtn_v_taps, 84*fb4d8502Sjsg bw_def_vsr_mtn_4, 85*fb4d8502Sjsg bw_def_auto, 86*fb4d8502Sjsg bw_def_manual, 87*fb4d8502Sjsg bw_def_exceeded_allowed_maximum_sclk, 88*fb4d8502Sjsg bw_def_exceeded_allowed_page_close_open, 89*fb4d8502Sjsg bw_def_exceeded_allowed_outstanding_pte_req_queue_size, 90*fb4d8502Sjsg bw_def_exceeded_allowed_maximum_bw, 91*fb4d8502Sjsg bw_def_landscape, 92*fb4d8502Sjsg 93*fb4d8502Sjsg //Panning and bezel 94*fb4d8502Sjsg bw_def_any_lines, 95*fb4d8502Sjsg 96*fb4d8502Sjsg //Underlay mode 97*fb4d8502Sjsg bw_def_underlay_only, 98*fb4d8502Sjsg bw_def_blended, 99*fb4d8502Sjsg bw_def_blend, 100*fb4d8502Sjsg 101*fb4d8502Sjsg //Stereo mode 102*fb4d8502Sjsg bw_def_mono, 103*fb4d8502Sjsg bw_def_side_by_side, 104*fb4d8502Sjsg bw_def_top_bottom, 105*fb4d8502Sjsg 106*fb4d8502Sjsg //Underlay surface type 107*fb4d8502Sjsg bw_def_420, 108*fb4d8502Sjsg bw_def_422, 109*fb4d8502Sjsg bw_def_444, 110*fb4d8502Sjsg 111*fb4d8502Sjsg //Tiling mode 112*fb4d8502Sjsg bw_def_linear, 113*fb4d8502Sjsg bw_def_tiled, 114*fb4d8502Sjsg bw_def_array_linear_general, 115*fb4d8502Sjsg bw_def_array_linear_aligned, 116*fb4d8502Sjsg bw_def_rotated_micro_tiling, 117*fb4d8502Sjsg bw_def_display_micro_tiling, 118*fb4d8502Sjsg 119*fb4d8502Sjsg //Memory type 120*fb4d8502Sjsg bw_def_gddr5, 121*fb4d8502Sjsg bw_def_hbm, 122*fb4d8502Sjsg 123*fb4d8502Sjsg //Voltage 124*fb4d8502Sjsg bw_def_high_no_nbp_state_change, 125*fb4d8502Sjsg bw_def_0_72, 126*fb4d8502Sjsg bw_def_0_8, 127*fb4d8502Sjsg bw_def_0_9, 128*fb4d8502Sjsg 129*fb4d8502Sjsg bw_def_notok = -1, 130*fb4d8502Sjsg bw_def_na = -1 131*fb4d8502Sjsg }; 132*fb4d8502Sjsg 133*fb4d8502Sjsg struct bw_calcs_dceip { 134*fb4d8502Sjsg enum bw_calcs_version version; 135*fb4d8502Sjsg uint32_t percent_of_ideal_port_bw_received_after_urgent_latency; 136*fb4d8502Sjsg uint32_t max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation; 137*fb4d8502Sjsg uint32_t max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation; 138*fb4d8502Sjsg bool large_cursor; 139*fb4d8502Sjsg uint32_t cursor_max_outstanding_group_num; 140*fb4d8502Sjsg bool dmif_pipe_en_fbc_chunk_tracker; 141*fb4d8502Sjsg struct bw_fixed dmif_request_buffer_size; 142*fb4d8502Sjsg uint32_t lines_interleaved_into_lb; 143*fb4d8502Sjsg uint32_t low_power_tiling_mode; 144*fb4d8502Sjsg uint32_t chunk_width; 145*fb4d8502Sjsg uint32_t number_of_graphics_pipes; 146*fb4d8502Sjsg uint32_t number_of_underlay_pipes; 147*fb4d8502Sjsg bool display_write_back_supported; 148*fb4d8502Sjsg bool argb_compression_support; 149*fb4d8502Sjsg struct bw_fixed underlay_vscaler_efficiency6_bit_per_component; 150*fb4d8502Sjsg struct bw_fixed underlay_vscaler_efficiency8_bit_per_component; 151*fb4d8502Sjsg struct bw_fixed underlay_vscaler_efficiency10_bit_per_component; 152*fb4d8502Sjsg struct bw_fixed underlay_vscaler_efficiency12_bit_per_component; 153*fb4d8502Sjsg struct bw_fixed graphics_vscaler_efficiency6_bit_per_component; 154*fb4d8502Sjsg struct bw_fixed graphics_vscaler_efficiency8_bit_per_component; 155*fb4d8502Sjsg struct bw_fixed graphics_vscaler_efficiency10_bit_per_component; 156*fb4d8502Sjsg struct bw_fixed graphics_vscaler_efficiency12_bit_per_component; 157*fb4d8502Sjsg struct bw_fixed alpha_vscaler_efficiency; 158*fb4d8502Sjsg uint32_t max_dmif_buffer_allocated; 159*fb4d8502Sjsg uint32_t graphics_dmif_size; 160*fb4d8502Sjsg uint32_t underlay_luma_dmif_size; 161*fb4d8502Sjsg uint32_t underlay_chroma_dmif_size; 162*fb4d8502Sjsg bool pre_downscaler_enabled; 163*fb4d8502Sjsg bool underlay_downscale_prefetch_enabled; 164*fb4d8502Sjsg struct bw_fixed lb_write_pixels_per_dispclk; 165*fb4d8502Sjsg struct bw_fixed lb_size_per_component444; 166*fb4d8502Sjsg bool graphics_lb_nodownscaling_multi_line_prefetching; 167*fb4d8502Sjsg struct bw_fixed stutter_and_dram_clock_state_change_gated_before_cursor; 168*fb4d8502Sjsg struct bw_fixed underlay420_luma_lb_size_per_component; 169*fb4d8502Sjsg struct bw_fixed underlay420_chroma_lb_size_per_component; 170*fb4d8502Sjsg struct bw_fixed underlay422_lb_size_per_component; 171*fb4d8502Sjsg struct bw_fixed cursor_chunk_width; 172*fb4d8502Sjsg struct bw_fixed cursor_dcp_buffer_lines; 173*fb4d8502Sjsg struct bw_fixed underlay_maximum_width_efficient_for_tiling; 174*fb4d8502Sjsg struct bw_fixed underlay_maximum_height_efficient_for_tiling; 175*fb4d8502Sjsg struct bw_fixed peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display; 176*fb4d8502Sjsg struct bw_fixed peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation; 177*fb4d8502Sjsg struct bw_fixed minimum_outstanding_pte_request_limit; 178*fb4d8502Sjsg struct bw_fixed maximum_total_outstanding_pte_requests_allowed_by_saw; 179*fb4d8502Sjsg bool limit_excessive_outstanding_dmif_requests; 180*fb4d8502Sjsg struct bw_fixed linear_mode_line_request_alternation_slice; 181*fb4d8502Sjsg uint32_t scatter_gather_lines_of_pte_prefetching_in_linear_mode; 182*fb4d8502Sjsg uint32_t display_write_back420_luma_mcifwr_buffer_size; 183*fb4d8502Sjsg uint32_t display_write_back420_chroma_mcifwr_buffer_size; 184*fb4d8502Sjsg struct bw_fixed request_efficiency; 185*fb4d8502Sjsg struct bw_fixed dispclk_per_request; 186*fb4d8502Sjsg struct bw_fixed dispclk_ramping_factor; 187*fb4d8502Sjsg struct bw_fixed display_pipe_throughput_factor; 188*fb4d8502Sjsg uint32_t scatter_gather_pte_request_rows_in_tiling_mode; 189*fb4d8502Sjsg struct bw_fixed mcifwr_all_surfaces_burst_time; 190*fb4d8502Sjsg }; 191*fb4d8502Sjsg 192*fb4d8502Sjsg struct bw_calcs_vbios { 193*fb4d8502Sjsg enum bw_defines memory_type; 194*fb4d8502Sjsg uint32_t dram_channel_width_in_bits; 195*fb4d8502Sjsg uint32_t number_of_dram_channels; 196*fb4d8502Sjsg uint32_t number_of_dram_banks; 197*fb4d8502Sjsg struct bw_fixed low_yclk; /*m_hz*/ 198*fb4d8502Sjsg struct bw_fixed mid_yclk; /*m_hz*/ 199*fb4d8502Sjsg struct bw_fixed high_yclk; /*m_hz*/ 200*fb4d8502Sjsg struct bw_fixed low_sclk; /*m_hz*/ 201*fb4d8502Sjsg struct bw_fixed mid1_sclk; /*m_hz*/ 202*fb4d8502Sjsg struct bw_fixed mid2_sclk; /*m_hz*/ 203*fb4d8502Sjsg struct bw_fixed mid3_sclk; /*m_hz*/ 204*fb4d8502Sjsg struct bw_fixed mid4_sclk; /*m_hz*/ 205*fb4d8502Sjsg struct bw_fixed mid5_sclk; /*m_hz*/ 206*fb4d8502Sjsg struct bw_fixed mid6_sclk; /*m_hz*/ 207*fb4d8502Sjsg struct bw_fixed high_sclk; /*m_hz*/ 208*fb4d8502Sjsg struct bw_fixed low_voltage_max_dispclk; /*m_hz*/ 209*fb4d8502Sjsg struct bw_fixed mid_voltage_max_dispclk; /*m_hz*/ 210*fb4d8502Sjsg struct bw_fixed high_voltage_max_dispclk; /*m_hz*/ 211*fb4d8502Sjsg struct bw_fixed low_voltage_max_phyclk; 212*fb4d8502Sjsg struct bw_fixed mid_voltage_max_phyclk; 213*fb4d8502Sjsg struct bw_fixed high_voltage_max_phyclk; 214*fb4d8502Sjsg struct bw_fixed data_return_bus_width; 215*fb4d8502Sjsg struct bw_fixed trc; 216*fb4d8502Sjsg struct bw_fixed dmifmc_urgent_latency; 217*fb4d8502Sjsg struct bw_fixed stutter_self_refresh_exit_latency; 218*fb4d8502Sjsg struct bw_fixed stutter_self_refresh_entry_latency; 219*fb4d8502Sjsg struct bw_fixed nbp_state_change_latency; 220*fb4d8502Sjsg struct bw_fixed mcifwrmc_urgent_latency; 221*fb4d8502Sjsg bool scatter_gather_enable; 222*fb4d8502Sjsg struct bw_fixed down_spread_percentage; 223*fb4d8502Sjsg uint32_t cursor_width; 224*fb4d8502Sjsg uint32_t average_compression_rate; 225*fb4d8502Sjsg uint32_t number_of_request_slots_gmc_reserves_for_dmif_per_channel; 226*fb4d8502Sjsg struct bw_fixed blackout_duration; 227*fb4d8502Sjsg struct bw_fixed maximum_blackout_recovery_time; 228*fb4d8502Sjsg }; 229*fb4d8502Sjsg 230*fb4d8502Sjsg /******************************************************************************* 231*fb4d8502Sjsg * Temporary data structure(s). 232*fb4d8502Sjsg ******************************************************************************/ 233*fb4d8502Sjsg #define maximum_number_of_surfaces 12 234*fb4d8502Sjsg /*Units : MHz, us */ 235*fb4d8502Sjsg 236*fb4d8502Sjsg struct bw_calcs_data { 237*fb4d8502Sjsg /* data for all displays */ 238*fb4d8502Sjsg bool display_synchronization_enabled; 239*fb4d8502Sjsg uint32_t number_of_displays; 240*fb4d8502Sjsg enum bw_defines underlay_surface_type; 241*fb4d8502Sjsg enum bw_defines panning_and_bezel_adjustment; 242*fb4d8502Sjsg enum bw_defines graphics_tiling_mode; 243*fb4d8502Sjsg uint32_t graphics_lb_bpc; 244*fb4d8502Sjsg uint32_t underlay_lb_bpc; 245*fb4d8502Sjsg enum bw_defines underlay_tiling_mode; 246*fb4d8502Sjsg enum bw_defines d0_underlay_mode; 247*fb4d8502Sjsg bool d1_display_write_back_dwb_enable; 248*fb4d8502Sjsg enum bw_defines d1_underlay_mode; 249*fb4d8502Sjsg 250*fb4d8502Sjsg bool increase_voltage_to_support_mclk_switch; 251*fb4d8502Sjsg bool cpup_state_change_enable; 252*fb4d8502Sjsg bool cpuc_state_change_enable; 253*fb4d8502Sjsg bool nbp_state_change_enable; 254*fb4d8502Sjsg bool stutter_mode_enable; 255*fb4d8502Sjsg uint32_t y_clk_level; 256*fb4d8502Sjsg uint32_t sclk_level; 257*fb4d8502Sjsg uint32_t number_of_underlay_surfaces; 258*fb4d8502Sjsg uint32_t number_of_dram_wrchannels; 259*fb4d8502Sjsg uint32_t chunk_request_delay; 260*fb4d8502Sjsg uint32_t number_of_dram_channels; 261*fb4d8502Sjsg enum bw_defines underlay_micro_tile_mode; 262*fb4d8502Sjsg enum bw_defines graphics_micro_tile_mode; 263*fb4d8502Sjsg struct bw_fixed max_phyclk; 264*fb4d8502Sjsg struct bw_fixed dram_efficiency; 265*fb4d8502Sjsg struct bw_fixed src_width_after_surface_type; 266*fb4d8502Sjsg struct bw_fixed src_height_after_surface_type; 267*fb4d8502Sjsg struct bw_fixed hsr_after_surface_type; 268*fb4d8502Sjsg struct bw_fixed vsr_after_surface_type; 269*fb4d8502Sjsg struct bw_fixed src_width_after_rotation; 270*fb4d8502Sjsg struct bw_fixed src_height_after_rotation; 271*fb4d8502Sjsg struct bw_fixed hsr_after_rotation; 272*fb4d8502Sjsg struct bw_fixed vsr_after_rotation; 273*fb4d8502Sjsg struct bw_fixed source_height_pixels; 274*fb4d8502Sjsg struct bw_fixed hsr_after_stereo; 275*fb4d8502Sjsg struct bw_fixed vsr_after_stereo; 276*fb4d8502Sjsg struct bw_fixed source_width_in_lb; 277*fb4d8502Sjsg struct bw_fixed lb_line_pitch; 278*fb4d8502Sjsg struct bw_fixed underlay_maximum_source_efficient_for_tiling; 279*fb4d8502Sjsg struct bw_fixed num_lines_at_frame_start; 280*fb4d8502Sjsg struct bw_fixed min_dmif_size_in_time; 281*fb4d8502Sjsg struct bw_fixed min_mcifwr_size_in_time; 282*fb4d8502Sjsg struct bw_fixed total_requests_for_dmif_size; 283*fb4d8502Sjsg struct bw_fixed peak_pte_request_to_eviction_ratio_limiting; 284*fb4d8502Sjsg struct bw_fixed useful_pte_per_pte_request; 285*fb4d8502Sjsg struct bw_fixed scatter_gather_pte_request_rows; 286*fb4d8502Sjsg struct bw_fixed scatter_gather_row_height; 287*fb4d8502Sjsg struct bw_fixed scatter_gather_pte_requests_in_vblank; 288*fb4d8502Sjsg struct bw_fixed inefficient_linear_pitch_in_bytes; 289*fb4d8502Sjsg struct bw_fixed cursor_total_data; 290*fb4d8502Sjsg struct bw_fixed cursor_total_request_groups; 291*fb4d8502Sjsg struct bw_fixed scatter_gather_total_pte_requests; 292*fb4d8502Sjsg struct bw_fixed scatter_gather_total_pte_request_groups; 293*fb4d8502Sjsg struct bw_fixed tile_width_in_pixels; 294*fb4d8502Sjsg struct bw_fixed dmif_total_number_of_data_request_page_close_open; 295*fb4d8502Sjsg struct bw_fixed mcifwr_total_number_of_data_request_page_close_open; 296*fb4d8502Sjsg struct bw_fixed bytes_per_page_close_open; 297*fb4d8502Sjsg struct bw_fixed mcifwr_total_page_close_open_time; 298*fb4d8502Sjsg struct bw_fixed total_requests_for_adjusted_dmif_size; 299*fb4d8502Sjsg struct bw_fixed total_dmifmc_urgent_trips; 300*fb4d8502Sjsg struct bw_fixed total_dmifmc_urgent_latency; 301*fb4d8502Sjsg struct bw_fixed total_display_reads_required_data; 302*fb4d8502Sjsg struct bw_fixed total_display_reads_required_dram_access_data; 303*fb4d8502Sjsg struct bw_fixed total_display_writes_required_data; 304*fb4d8502Sjsg struct bw_fixed total_display_writes_required_dram_access_data; 305*fb4d8502Sjsg struct bw_fixed display_reads_required_data; 306*fb4d8502Sjsg struct bw_fixed display_reads_required_dram_access_data; 307*fb4d8502Sjsg struct bw_fixed dmif_total_page_close_open_time; 308*fb4d8502Sjsg struct bw_fixed min_cursor_memory_interface_buffer_size_in_time; 309*fb4d8502Sjsg struct bw_fixed min_read_buffer_size_in_time; 310*fb4d8502Sjsg struct bw_fixed display_reads_time_for_data_transfer; 311*fb4d8502Sjsg struct bw_fixed display_writes_time_for_data_transfer; 312*fb4d8502Sjsg struct bw_fixed dmif_required_dram_bandwidth; 313*fb4d8502Sjsg struct bw_fixed mcifwr_required_dram_bandwidth; 314*fb4d8502Sjsg struct bw_fixed required_dmifmc_urgent_latency_for_page_close_open; 315*fb4d8502Sjsg struct bw_fixed required_mcifmcwr_urgent_latency; 316*fb4d8502Sjsg struct bw_fixed required_dram_bandwidth_gbyte_per_second; 317*fb4d8502Sjsg struct bw_fixed dram_bandwidth; 318*fb4d8502Sjsg struct bw_fixed dmif_required_sclk; 319*fb4d8502Sjsg struct bw_fixed mcifwr_required_sclk; 320*fb4d8502Sjsg struct bw_fixed required_sclk; 321*fb4d8502Sjsg struct bw_fixed downspread_factor; 322*fb4d8502Sjsg struct bw_fixed v_scaler_efficiency; 323*fb4d8502Sjsg struct bw_fixed scaler_limits_factor; 324*fb4d8502Sjsg struct bw_fixed display_pipe_pixel_throughput; 325*fb4d8502Sjsg struct bw_fixed total_dispclk_required_with_ramping; 326*fb4d8502Sjsg struct bw_fixed total_dispclk_required_without_ramping; 327*fb4d8502Sjsg struct bw_fixed total_read_request_bandwidth; 328*fb4d8502Sjsg struct bw_fixed total_write_request_bandwidth; 329*fb4d8502Sjsg struct bw_fixed dispclk_required_for_total_read_request_bandwidth; 330*fb4d8502Sjsg struct bw_fixed total_dispclk_required_with_ramping_with_request_bandwidth; 331*fb4d8502Sjsg struct bw_fixed total_dispclk_required_without_ramping_with_request_bandwidth; 332*fb4d8502Sjsg struct bw_fixed dispclk; 333*fb4d8502Sjsg struct bw_fixed blackout_recovery_time; 334*fb4d8502Sjsg struct bw_fixed min_pixels_per_data_fifo_entry; 335*fb4d8502Sjsg struct bw_fixed sclk_deep_sleep; 336*fb4d8502Sjsg struct bw_fixed chunk_request_time; 337*fb4d8502Sjsg struct bw_fixed cursor_request_time; 338*fb4d8502Sjsg struct bw_fixed line_source_pixels_transfer_time; 339*fb4d8502Sjsg struct bw_fixed dmifdram_access_efficiency; 340*fb4d8502Sjsg struct bw_fixed mcifwrdram_access_efficiency; 341*fb4d8502Sjsg struct bw_fixed total_average_bandwidth_no_compression; 342*fb4d8502Sjsg struct bw_fixed total_average_bandwidth; 343*fb4d8502Sjsg struct bw_fixed total_stutter_cycle_duration; 344*fb4d8502Sjsg struct bw_fixed stutter_burst_time; 345*fb4d8502Sjsg struct bw_fixed time_in_self_refresh; 346*fb4d8502Sjsg struct bw_fixed stutter_efficiency; 347*fb4d8502Sjsg struct bw_fixed worst_number_of_trips_to_memory; 348*fb4d8502Sjsg struct bw_fixed immediate_flip_time; 349*fb4d8502Sjsg struct bw_fixed latency_for_non_dmif_clients; 350*fb4d8502Sjsg struct bw_fixed latency_for_non_mcifwr_clients; 351*fb4d8502Sjsg struct bw_fixed dmifmc_urgent_latency_supported_in_high_sclk_and_yclk; 352*fb4d8502Sjsg struct bw_fixed nbp_state_dram_speed_change_margin; 353*fb4d8502Sjsg struct bw_fixed display_reads_time_for_data_transfer_and_urgent_latency; 354*fb4d8502Sjsg struct bw_fixed dram_speed_change_margin; 355*fb4d8502Sjsg struct bw_fixed min_vblank_dram_speed_change_margin; 356*fb4d8502Sjsg struct bw_fixed min_stutter_refresh_duration; 357*fb4d8502Sjsg uint32_t total_stutter_dmif_buffer_size; 358*fb4d8502Sjsg uint32_t total_bytes_requested; 359*fb4d8502Sjsg uint32_t min_stutter_dmif_buffer_size; 360*fb4d8502Sjsg uint32_t num_stutter_bursts; 361*fb4d8502Sjsg struct bw_fixed v_blank_nbp_state_dram_speed_change_latency_supported; 362*fb4d8502Sjsg struct bw_fixed nbp_state_dram_speed_change_latency_supported; 363*fb4d8502Sjsg bool fbc_en[maximum_number_of_surfaces]; 364*fb4d8502Sjsg bool lpt_en[maximum_number_of_surfaces]; 365*fb4d8502Sjsg bool displays_match_flag[maximum_number_of_surfaces]; 366*fb4d8502Sjsg bool use_alpha[maximum_number_of_surfaces]; 367*fb4d8502Sjsg bool orthogonal_rotation[maximum_number_of_surfaces]; 368*fb4d8502Sjsg bool enable[maximum_number_of_surfaces]; 369*fb4d8502Sjsg bool access_one_channel_only[maximum_number_of_surfaces]; 370*fb4d8502Sjsg bool scatter_gather_enable_for_pipe[maximum_number_of_surfaces]; 371*fb4d8502Sjsg bool interlace_mode[maximum_number_of_surfaces]; 372*fb4d8502Sjsg bool display_pstate_change_enable[maximum_number_of_surfaces]; 373*fb4d8502Sjsg bool line_buffer_prefetch[maximum_number_of_surfaces]; 374*fb4d8502Sjsg uint32_t bytes_per_pixel[maximum_number_of_surfaces]; 375*fb4d8502Sjsg uint32_t max_chunks_non_fbc_mode[maximum_number_of_surfaces]; 376*fb4d8502Sjsg uint32_t lb_bpc[maximum_number_of_surfaces]; 377*fb4d8502Sjsg uint32_t output_bpphdmi[maximum_number_of_surfaces]; 378*fb4d8502Sjsg uint32_t output_bppdp4_lane_hbr[maximum_number_of_surfaces]; 379*fb4d8502Sjsg uint32_t output_bppdp4_lane_hbr2[maximum_number_of_surfaces]; 380*fb4d8502Sjsg uint32_t output_bppdp4_lane_hbr3[maximum_number_of_surfaces]; 381*fb4d8502Sjsg enum bw_defines stereo_mode[maximum_number_of_surfaces]; 382*fb4d8502Sjsg struct bw_fixed dmif_buffer_transfer_time[maximum_number_of_surfaces]; 383*fb4d8502Sjsg struct bw_fixed displays_with_same_mode[maximum_number_of_surfaces]; 384*fb4d8502Sjsg struct bw_fixed stutter_dmif_buffer_size[maximum_number_of_surfaces]; 385*fb4d8502Sjsg struct bw_fixed stutter_refresh_duration[maximum_number_of_surfaces]; 386*fb4d8502Sjsg struct bw_fixed stutter_exit_watermark[maximum_number_of_surfaces]; 387*fb4d8502Sjsg struct bw_fixed stutter_entry_watermark[maximum_number_of_surfaces]; 388*fb4d8502Sjsg struct bw_fixed h_total[maximum_number_of_surfaces]; 389*fb4d8502Sjsg struct bw_fixed v_total[maximum_number_of_surfaces]; 390*fb4d8502Sjsg struct bw_fixed pixel_rate[maximum_number_of_surfaces]; 391*fb4d8502Sjsg struct bw_fixed src_width[maximum_number_of_surfaces]; 392*fb4d8502Sjsg struct bw_fixed pitch_in_pixels[maximum_number_of_surfaces]; 393*fb4d8502Sjsg struct bw_fixed pitch_in_pixels_after_surface_type[maximum_number_of_surfaces]; 394*fb4d8502Sjsg struct bw_fixed src_height[maximum_number_of_surfaces]; 395*fb4d8502Sjsg struct bw_fixed scale_ratio[maximum_number_of_surfaces]; 396*fb4d8502Sjsg struct bw_fixed h_taps[maximum_number_of_surfaces]; 397*fb4d8502Sjsg struct bw_fixed v_taps[maximum_number_of_surfaces]; 398*fb4d8502Sjsg struct bw_fixed h_scale_ratio[maximum_number_of_surfaces]; 399*fb4d8502Sjsg struct bw_fixed v_scale_ratio[maximum_number_of_surfaces]; 400*fb4d8502Sjsg struct bw_fixed rotation_angle[maximum_number_of_surfaces]; 401*fb4d8502Sjsg struct bw_fixed compression_rate[maximum_number_of_surfaces]; 402*fb4d8502Sjsg struct bw_fixed hsr[maximum_number_of_surfaces]; 403*fb4d8502Sjsg struct bw_fixed vsr[maximum_number_of_surfaces]; 404*fb4d8502Sjsg struct bw_fixed source_width_rounded_up_to_chunks[maximum_number_of_surfaces]; 405*fb4d8502Sjsg struct bw_fixed source_width_pixels[maximum_number_of_surfaces]; 406*fb4d8502Sjsg struct bw_fixed source_height_rounded_up_to_chunks[maximum_number_of_surfaces]; 407*fb4d8502Sjsg struct bw_fixed display_bandwidth[maximum_number_of_surfaces]; 408*fb4d8502Sjsg struct bw_fixed request_bandwidth[maximum_number_of_surfaces]; 409*fb4d8502Sjsg struct bw_fixed bytes_per_request[maximum_number_of_surfaces]; 410*fb4d8502Sjsg struct bw_fixed useful_bytes_per_request[maximum_number_of_surfaces]; 411*fb4d8502Sjsg struct bw_fixed lines_interleaved_in_mem_access[maximum_number_of_surfaces]; 412*fb4d8502Sjsg struct bw_fixed latency_hiding_lines[maximum_number_of_surfaces]; 413*fb4d8502Sjsg struct bw_fixed lb_partitions[maximum_number_of_surfaces]; 414*fb4d8502Sjsg struct bw_fixed lb_partitions_max[maximum_number_of_surfaces]; 415*fb4d8502Sjsg struct bw_fixed dispclk_required_with_ramping[maximum_number_of_surfaces]; 416*fb4d8502Sjsg struct bw_fixed dispclk_required_without_ramping[maximum_number_of_surfaces]; 417*fb4d8502Sjsg struct bw_fixed data_buffer_size[maximum_number_of_surfaces]; 418*fb4d8502Sjsg struct bw_fixed outstanding_chunk_request_limit[maximum_number_of_surfaces]; 419*fb4d8502Sjsg struct bw_fixed urgent_watermark[maximum_number_of_surfaces]; 420*fb4d8502Sjsg struct bw_fixed nbp_state_change_watermark[maximum_number_of_surfaces]; 421*fb4d8502Sjsg struct bw_fixed v_filter_init[maximum_number_of_surfaces]; 422*fb4d8502Sjsg struct bw_fixed stutter_cycle_duration[maximum_number_of_surfaces]; 423*fb4d8502Sjsg struct bw_fixed average_bandwidth[maximum_number_of_surfaces]; 424*fb4d8502Sjsg struct bw_fixed average_bandwidth_no_compression[maximum_number_of_surfaces]; 425*fb4d8502Sjsg struct bw_fixed scatter_gather_pte_request_limit[maximum_number_of_surfaces]; 426*fb4d8502Sjsg struct bw_fixed lb_size_per_component[maximum_number_of_surfaces]; 427*fb4d8502Sjsg struct bw_fixed memory_chunk_size_in_bytes[maximum_number_of_surfaces]; 428*fb4d8502Sjsg struct bw_fixed pipe_chunk_size_in_bytes[maximum_number_of_surfaces]; 429*fb4d8502Sjsg struct bw_fixed number_of_trips_to_memory_for_getting_apte_row[maximum_number_of_surfaces]; 430*fb4d8502Sjsg struct bw_fixed adjusted_data_buffer_size[maximum_number_of_surfaces]; 431*fb4d8502Sjsg struct bw_fixed adjusted_data_buffer_size_in_memory[maximum_number_of_surfaces]; 432*fb4d8502Sjsg struct bw_fixed pixels_per_data_fifo_entry[maximum_number_of_surfaces]; 433*fb4d8502Sjsg struct bw_fixed scatter_gather_pte_requests_in_row[maximum_number_of_surfaces]; 434*fb4d8502Sjsg struct bw_fixed pte_request_per_chunk[maximum_number_of_surfaces]; 435*fb4d8502Sjsg struct bw_fixed scatter_gather_page_width[maximum_number_of_surfaces]; 436*fb4d8502Sjsg struct bw_fixed scatter_gather_page_height[maximum_number_of_surfaces]; 437*fb4d8502Sjsg struct bw_fixed lb_lines_in_per_line_out_in_beginning_of_frame[maximum_number_of_surfaces]; 438*fb4d8502Sjsg struct bw_fixed lb_lines_in_per_line_out_in_middle_of_frame[maximum_number_of_surfaces]; 439*fb4d8502Sjsg struct bw_fixed cursor_width_pixels[maximum_number_of_surfaces]; 440*fb4d8502Sjsg struct bw_fixed minimum_latency_hiding[maximum_number_of_surfaces]; 441*fb4d8502Sjsg struct bw_fixed maximum_latency_hiding[maximum_number_of_surfaces]; 442*fb4d8502Sjsg struct bw_fixed minimum_latency_hiding_with_cursor[maximum_number_of_surfaces]; 443*fb4d8502Sjsg struct bw_fixed maximum_latency_hiding_with_cursor[maximum_number_of_surfaces]; 444*fb4d8502Sjsg struct bw_fixed src_pixels_for_first_output_pixel[maximum_number_of_surfaces]; 445*fb4d8502Sjsg struct bw_fixed src_pixels_for_last_output_pixel[maximum_number_of_surfaces]; 446*fb4d8502Sjsg struct bw_fixed src_data_for_first_output_pixel[maximum_number_of_surfaces]; 447*fb4d8502Sjsg struct bw_fixed src_data_for_last_output_pixel[maximum_number_of_surfaces]; 448*fb4d8502Sjsg struct bw_fixed active_time[maximum_number_of_surfaces]; 449*fb4d8502Sjsg struct bw_fixed horizontal_blank_and_chunk_granularity_factor[maximum_number_of_surfaces]; 450*fb4d8502Sjsg struct bw_fixed cursor_latency_hiding[maximum_number_of_surfaces]; 451*fb4d8502Sjsg struct bw_fixed v_blank_dram_speed_change_margin[maximum_number_of_surfaces]; 452*fb4d8502Sjsg uint32_t num_displays_with_margin[3][8]; 453*fb4d8502Sjsg struct bw_fixed dmif_burst_time[3][8]; 454*fb4d8502Sjsg struct bw_fixed mcifwr_burst_time[3][8]; 455*fb4d8502Sjsg struct bw_fixed line_source_transfer_time[maximum_number_of_surfaces][3][8]; 456*fb4d8502Sjsg struct bw_fixed dram_speed_change_line_source_transfer_time[maximum_number_of_surfaces][3][8]; 457*fb4d8502Sjsg struct bw_fixed min_dram_speed_change_margin[3][8]; 458*fb4d8502Sjsg struct bw_fixed dispclk_required_for_dram_speed_change[3][8]; 459*fb4d8502Sjsg struct bw_fixed dispclk_required_for_dram_speed_change_pipe[3][8]; 460*fb4d8502Sjsg struct bw_fixed blackout_duration_margin[3][8]; 461*fb4d8502Sjsg struct bw_fixed dispclk_required_for_blackout_duration[3][8]; 462*fb4d8502Sjsg struct bw_fixed dispclk_required_for_blackout_recovery[3][8]; 463*fb4d8502Sjsg struct bw_fixed dmif_required_sclk_for_urgent_latency[6]; 464*fb4d8502Sjsg }; 465*fb4d8502Sjsg 466*fb4d8502Sjsg /** 467*fb4d8502Sjsg * Initialize structures with data which will NOT change at runtime. 468*fb4d8502Sjsg */ 469*fb4d8502Sjsg void bw_calcs_init( 470*fb4d8502Sjsg struct bw_calcs_dceip *bw_dceip, 471*fb4d8502Sjsg struct bw_calcs_vbios *bw_vbios, 472*fb4d8502Sjsg struct hw_asic_id asic_id); 473*fb4d8502Sjsg 474*fb4d8502Sjsg /** 475*fb4d8502Sjsg * Return: 476*fb4d8502Sjsg * true - Display(s) configuration supported. 477*fb4d8502Sjsg * In this case 'calcs_output' contains data for HW programming 478*fb4d8502Sjsg * false - Display(s) configuration not supported (not enough bandwidth). 479*fb4d8502Sjsg */ 480*fb4d8502Sjsg bool bw_calcs( 481*fb4d8502Sjsg struct dc_context *ctx, 482*fb4d8502Sjsg const struct bw_calcs_dceip *dceip, 483*fb4d8502Sjsg const struct bw_calcs_vbios *vbios, 484*fb4d8502Sjsg const struct pipe_ctx *pipe, 485*fb4d8502Sjsg int pipe_count, 486*fb4d8502Sjsg struct dce_bw_output *calcs_output); 487*fb4d8502Sjsg 488*fb4d8502Sjsg #endif /* __BANDWIDTH_CALCS_H__ */ 489*fb4d8502Sjsg 490