xref: /openbsd-src/sys/dev/pci/drm/amd/display/dc/inc/compressor.h (revision c349dbc7938c71a30e13c1be4acc1976165f4630)
1fb4d8502Sjsg /*
2fb4d8502Sjsg  * Copyright 2012-15 Advanced Micro Devices, Inc.
3fb4d8502Sjsg  *
4fb4d8502Sjsg  * Permission is hereby granted, free of charge, to any person obtaining a
5fb4d8502Sjsg  * copy of this software and associated documentation files (the "Software"),
6fb4d8502Sjsg  * to deal in the Software without restriction, including without limitation
7fb4d8502Sjsg  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8fb4d8502Sjsg  * and/or sell copies of the Software, and to permit persons to whom the
9fb4d8502Sjsg  * Software is furnished to do so, subject to the following conditions:
10fb4d8502Sjsg  *
11fb4d8502Sjsg  * The above copyright notice and this permission notice shall be included in
12fb4d8502Sjsg  * all copies or substantial portions of the Software.
13fb4d8502Sjsg  *
14fb4d8502Sjsg  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15fb4d8502Sjsg  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16fb4d8502Sjsg  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17fb4d8502Sjsg  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18fb4d8502Sjsg  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19fb4d8502Sjsg  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20fb4d8502Sjsg  * OTHER DEALINGS IN THE SOFTWARE.
21fb4d8502Sjsg  *
22fb4d8502Sjsg  * Authors: AMD
23fb4d8502Sjsg  *
24fb4d8502Sjsg  */
25fb4d8502Sjsg 
26fb4d8502Sjsg #ifndef __DAL_COMPRESSOR_H__
27fb4d8502Sjsg #define __DAL_COMPRESSOR_H__
28fb4d8502Sjsg 
29fb4d8502Sjsg #include "include/grph_object_id.h"
30fb4d8502Sjsg #include "bios_parser_interface.h"
31fb4d8502Sjsg 
32fb4d8502Sjsg enum fbc_compress_ratio {
33fb4d8502Sjsg 	FBC_COMPRESS_RATIO_INVALID = 0,
34fb4d8502Sjsg 	FBC_COMPRESS_RATIO_1TO1 = 1,
35fb4d8502Sjsg 	FBC_COMPRESS_RATIO_2TO1 = 2,
36fb4d8502Sjsg 	FBC_COMPRESS_RATIO_4TO1 = 4,
37fb4d8502Sjsg 	FBC_COMPRESS_RATIO_8TO1 = 8,
38fb4d8502Sjsg };
39fb4d8502Sjsg 
40fb4d8502Sjsg union fbc_physical_address {
41fb4d8502Sjsg 	struct {
42fb4d8502Sjsg 		uint32_t low_part;
43fb4d8502Sjsg 		int32_t high_part;
44fb4d8502Sjsg 	} addr;
45fb4d8502Sjsg 	uint64_t quad_part;
46fb4d8502Sjsg };
47fb4d8502Sjsg 
48fb4d8502Sjsg struct compr_addr_and_pitch_params {
49fb4d8502Sjsg 	/* enum controller_id controller_id; */
50fb4d8502Sjsg 	uint32_t inst;
51fb4d8502Sjsg 	uint32_t source_view_width;
52fb4d8502Sjsg 	uint32_t source_view_height;
53fb4d8502Sjsg };
54fb4d8502Sjsg 
55fb4d8502Sjsg enum fbc_hw_max_resolution_supported {
56fb4d8502Sjsg 	FBC_MAX_X = 3840,
57fb4d8502Sjsg 	FBC_MAX_Y = 2400,
58fb4d8502Sjsg 	FBC_MAX_X_SG = 1920,
59fb4d8502Sjsg 	FBC_MAX_Y_SG = 1080,
60fb4d8502Sjsg };
61fb4d8502Sjsg 
62fb4d8502Sjsg struct compressor;
63fb4d8502Sjsg 
64fb4d8502Sjsg struct compressor_funcs {
65fb4d8502Sjsg 
66fb4d8502Sjsg 	void (*power_up_fbc)(struct compressor *cp);
67fb4d8502Sjsg 	void (*enable_fbc)(struct compressor *cp,
68fb4d8502Sjsg 		struct compr_addr_and_pitch_params *params);
69fb4d8502Sjsg 	void (*disable_fbc)(struct compressor *cp);
70fb4d8502Sjsg 	void (*set_fbc_invalidation_triggers)(struct compressor *cp,
71fb4d8502Sjsg 		uint32_t fbc_trigger);
72fb4d8502Sjsg 	void (*surface_address_and_pitch)(
73fb4d8502Sjsg 		struct compressor *cp,
74fb4d8502Sjsg 		struct compr_addr_and_pitch_params *params);
75fb4d8502Sjsg 	bool (*is_fbc_enabled_in_hw)(struct compressor *cp,
76fb4d8502Sjsg 		uint32_t *fbc_mapped_crtc_id);
77fb4d8502Sjsg };
78fb4d8502Sjsg struct compressor {
79fb4d8502Sjsg 	struct dc_context *ctx;
80*c349dbc7Sjsg 	/* CONTROLLER_ID_D0 + instance, CONTROLLER_ID_UNDEFINED = 0 */
81fb4d8502Sjsg 	uint32_t attached_inst;
82fb4d8502Sjsg 	bool is_enabled;
83fb4d8502Sjsg 	const struct compressor_funcs *funcs;
84fb4d8502Sjsg 	union {
85fb4d8502Sjsg 		uint32_t raw;
86fb4d8502Sjsg 		struct {
87fb4d8502Sjsg 			uint32_t FBC_SUPPORT:1;
88fb4d8502Sjsg 			uint32_t FB_POOL:1;
89fb4d8502Sjsg 			uint32_t DYNAMIC_ALLOC:1;
90fb4d8502Sjsg 			uint32_t LPT_SUPPORT:1;
91fb4d8502Sjsg 			uint32_t LPT_MC_CONFIG:1;
92fb4d8502Sjsg 			uint32_t DUMMY_BACKEND:1;
93fb4d8502Sjsg 			uint32_t CLK_GATING_DISABLED:1;
94fb4d8502Sjsg 
95fb4d8502Sjsg 		} bits;
96fb4d8502Sjsg 	} options;
97fb4d8502Sjsg 
98fb4d8502Sjsg 	union fbc_physical_address compr_surface_address;
99fb4d8502Sjsg 
100fb4d8502Sjsg 	uint32_t embedded_panel_h_size;
101fb4d8502Sjsg 	uint32_t embedded_panel_v_size;
102fb4d8502Sjsg 	uint32_t memory_bus_width;
103fb4d8502Sjsg 	uint32_t banks_num;
104fb4d8502Sjsg 	uint32_t raw_size;
105fb4d8502Sjsg 	uint32_t channel_interleave_size;
106fb4d8502Sjsg 	uint32_t dram_channels_num;
107fb4d8502Sjsg 
108fb4d8502Sjsg 	uint32_t allocated_size;
109fb4d8502Sjsg 	uint32_t preferred_requested_size;
110fb4d8502Sjsg 	uint32_t lpt_channels_num;
111fb4d8502Sjsg 	enum fbc_compress_ratio min_compress_ratio;
112fb4d8502Sjsg };
113fb4d8502Sjsg 
114fb4d8502Sjsg struct fbc_input_info {
115fb4d8502Sjsg 	bool           dynamic_fbc_buffer_alloc;
116fb4d8502Sjsg 	unsigned int   source_view_width;
117fb4d8502Sjsg 	unsigned int   source_view_height;
118fb4d8502Sjsg 	unsigned int   num_of_active_targets;
119fb4d8502Sjsg };
120fb4d8502Sjsg 
121fb4d8502Sjsg 
122fb4d8502Sjsg struct fbc_requested_compressed_size {
123fb4d8502Sjsg 	unsigned int   preferred_size;
124fb4d8502Sjsg 	unsigned int   preferred_size_alignment;
125fb4d8502Sjsg 	unsigned int   min_size;
126fb4d8502Sjsg 	unsigned int   min_size_alignment;
127fb4d8502Sjsg 	union {
128fb4d8502Sjsg 		struct {
129fb4d8502Sjsg 			/* Above preferedSize must be allocated in FB pool */
130fb4d8502Sjsg 			unsigned int preferred_must_be_framebuffer_pool : 1;
131fb4d8502Sjsg 			/* Above minSize must be allocated in FB pool */
132fb4d8502Sjsg 			unsigned int min_must_be_framebuffer_pool : 1;
133fb4d8502Sjsg 		} bits;
134fb4d8502Sjsg 		unsigned int flags;
135fb4d8502Sjsg 	};
136fb4d8502Sjsg };
137fb4d8502Sjsg #endif
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