xref: /openbsd-src/sys/dev/pci/drm/amd/display/dc/gpio/hw_hpd.c (revision 1bb76ff151c0aba8e3312a604e4cd2e5195cf4b7)
1fb4d8502Sjsg /*
2fb4d8502Sjsg  * Copyright 2012-15 Advanced Micro Devices, Inc.
3fb4d8502Sjsg  *
4fb4d8502Sjsg  * Permission is hereby granted, free of charge, to any person obtaining a
5fb4d8502Sjsg  * copy of this software and associated documentation files (the "Software"),
6fb4d8502Sjsg  * to deal in the Software without restriction, including without limitation
7fb4d8502Sjsg  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8fb4d8502Sjsg  * and/or sell copies of the Software, and to permit persons to whom the
9fb4d8502Sjsg  * Software is furnished to do so, subject to the following conditions:
10fb4d8502Sjsg  *
11fb4d8502Sjsg  * The above copyright notice and this permission notice shall be included in
12fb4d8502Sjsg  * all copies or substantial portions of the Software.
13fb4d8502Sjsg  *
14fb4d8502Sjsg  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15fb4d8502Sjsg  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16fb4d8502Sjsg  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17fb4d8502Sjsg  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18fb4d8502Sjsg  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19fb4d8502Sjsg  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20fb4d8502Sjsg  * OTHER DEALINGS IN THE SOFTWARE.
21fb4d8502Sjsg  *
22fb4d8502Sjsg  * Authors: AMD
23fb4d8502Sjsg  *
24fb4d8502Sjsg  */
25fb4d8502Sjsg 
26fb4d8502Sjsg #include "dm_services.h"
27fb4d8502Sjsg 
28*c349dbc7Sjsg #include "include/gpio_interface.h"
29fb4d8502Sjsg #include "include/gpio_types.h"
30fb4d8502Sjsg #include "hw_gpio.h"
31fb4d8502Sjsg #include "hw_hpd.h"
32fb4d8502Sjsg 
33fb4d8502Sjsg #include "reg_helper.h"
34fb4d8502Sjsg #include "hpd_regs.h"
35fb4d8502Sjsg 
36fb4d8502Sjsg #undef FN
37fb4d8502Sjsg #define FN(reg_name, field_name) \
38fb4d8502Sjsg 	hpd->shifts->field_name, hpd->masks->field_name
39fb4d8502Sjsg 
40fb4d8502Sjsg #define CTX \
41fb4d8502Sjsg 	hpd->base.base.ctx
42fb4d8502Sjsg #define REG(reg)\
43fb4d8502Sjsg 	(hpd->regs->reg)
44fb4d8502Sjsg 
45*c349dbc7Sjsg struct gpio;
46fb4d8502Sjsg 
dal_hw_hpd_destruct(struct hw_hpd * pin)47fb4d8502Sjsg static void dal_hw_hpd_destruct(
48fb4d8502Sjsg 	struct hw_hpd *pin)
49fb4d8502Sjsg {
50fb4d8502Sjsg 	dal_hw_gpio_destruct(&pin->base);
51fb4d8502Sjsg }
52fb4d8502Sjsg 
dal_hw_hpd_destroy(struct hw_gpio_pin ** ptr)53*c349dbc7Sjsg static void dal_hw_hpd_destroy(
54fb4d8502Sjsg 	struct hw_gpio_pin **ptr)
55fb4d8502Sjsg {
56fb4d8502Sjsg 	struct hw_hpd *hpd = HW_HPD_FROM_BASE(*ptr);
57fb4d8502Sjsg 
58*c349dbc7Sjsg 	dal_hw_hpd_destruct(hpd);
59fb4d8502Sjsg 
60fb4d8502Sjsg 	kfree(hpd);
61fb4d8502Sjsg 
62fb4d8502Sjsg 	*ptr = NULL;
63fb4d8502Sjsg }
64fb4d8502Sjsg 
get_value(const struct hw_gpio_pin * ptr,uint32_t * value)65fb4d8502Sjsg static enum gpio_result get_value(
66fb4d8502Sjsg 	const struct hw_gpio_pin *ptr,
67fb4d8502Sjsg 	uint32_t *value)
68fb4d8502Sjsg {
69fb4d8502Sjsg 	struct hw_hpd *hpd = HW_HPD_FROM_BASE(ptr);
70fb4d8502Sjsg 	uint32_t hpd_delayed = 0;
71fb4d8502Sjsg 
72fb4d8502Sjsg 	/* in Interrupt mode we ask for SENSE bit */
73fb4d8502Sjsg 
74fb4d8502Sjsg 	if (ptr->mode == GPIO_MODE_INTERRUPT) {
75fb4d8502Sjsg 
76fb4d8502Sjsg 		REG_GET(int_status,
77fb4d8502Sjsg 			DC_HPD_SENSE_DELAYED, &hpd_delayed);
78fb4d8502Sjsg 
79fb4d8502Sjsg 		*value = hpd_delayed;
80fb4d8502Sjsg 		return GPIO_RESULT_OK;
81fb4d8502Sjsg 	}
82fb4d8502Sjsg 
83fb4d8502Sjsg 	/* in any other modes, operate as normal GPIO */
84fb4d8502Sjsg 
85fb4d8502Sjsg 	return dal_hw_gpio_get_value(ptr, value);
86fb4d8502Sjsg }
87fb4d8502Sjsg 
set_config(struct hw_gpio_pin * ptr,const struct gpio_config_data * config_data)88fb4d8502Sjsg static enum gpio_result set_config(
89fb4d8502Sjsg 	struct hw_gpio_pin *ptr,
90fb4d8502Sjsg 	const struct gpio_config_data *config_data)
91fb4d8502Sjsg {
92fb4d8502Sjsg 	struct hw_hpd *hpd = HW_HPD_FROM_BASE(ptr);
93fb4d8502Sjsg 
94fb4d8502Sjsg 	if (!config_data)
95fb4d8502Sjsg 		return GPIO_RESULT_INVALID_DATA;
96fb4d8502Sjsg 
97fb4d8502Sjsg 	REG_UPDATE_2(toggle_filt_cntl,
98fb4d8502Sjsg 		DC_HPD_CONNECT_INT_DELAY, config_data->config.hpd.delay_on_connect / 10,
99fb4d8502Sjsg 		DC_HPD_DISCONNECT_INT_DELAY, config_data->config.hpd.delay_on_disconnect / 10);
100fb4d8502Sjsg 
101fb4d8502Sjsg 	return GPIO_RESULT_OK;
102fb4d8502Sjsg }
103fb4d8502Sjsg 
104fb4d8502Sjsg static const struct hw_gpio_pin_funcs funcs = {
105*c349dbc7Sjsg 	.destroy = dal_hw_hpd_destroy,
106fb4d8502Sjsg 	.open = dal_hw_gpio_open,
107fb4d8502Sjsg 	.get_value = get_value,
108fb4d8502Sjsg 	.set_value = dal_hw_gpio_set_value,
109fb4d8502Sjsg 	.set_config = set_config,
110fb4d8502Sjsg 	.change_mode = dal_hw_gpio_change_mode,
111fb4d8502Sjsg 	.close = dal_hw_gpio_close,
112fb4d8502Sjsg };
113fb4d8502Sjsg 
dal_hw_hpd_construct(struct hw_hpd * pin,enum gpio_id id,uint32_t en,struct dc_context * ctx)114*c349dbc7Sjsg static void dal_hw_hpd_construct(
115*c349dbc7Sjsg 	struct hw_hpd *pin,
116fb4d8502Sjsg 	enum gpio_id id,
117fb4d8502Sjsg 	uint32_t en,
118fb4d8502Sjsg 	struct dc_context *ctx)
119fb4d8502Sjsg {
120*c349dbc7Sjsg 	dal_hw_gpio_construct(&pin->base, id, en, ctx);
121*c349dbc7Sjsg 	pin->base.base.funcs = &funcs;
122fb4d8502Sjsg }
123fb4d8502Sjsg 
dal_hw_hpd_init(struct hw_hpd ** hw_hpd,struct dc_context * ctx,enum gpio_id id,uint32_t en)124*c349dbc7Sjsg void dal_hw_hpd_init(
125*c349dbc7Sjsg 	struct hw_hpd **hw_hpd,
126fb4d8502Sjsg 	struct dc_context *ctx,
127fb4d8502Sjsg 	enum gpio_id id,
128fb4d8502Sjsg 	uint32_t en)
129fb4d8502Sjsg {
130*c349dbc7Sjsg 	if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) {
131fb4d8502Sjsg 		ASSERT_CRITICAL(false);
132*c349dbc7Sjsg 		*hw_hpd = NULL;
133fb4d8502Sjsg 	}
134fb4d8502Sjsg 
135*c349dbc7Sjsg 	*hw_hpd = kzalloc(sizeof(struct hw_hpd), GFP_KERNEL);
136*c349dbc7Sjsg 	if (!*hw_hpd) {
137fb4d8502Sjsg 		ASSERT_CRITICAL(false);
138*c349dbc7Sjsg 		return;
139fb4d8502Sjsg 	}
140fb4d8502Sjsg 
141*c349dbc7Sjsg 	dal_hw_hpd_construct(*hw_hpd, id, en, ctx);
142fb4d8502Sjsg }
143fb4d8502Sjsg 
dal_hw_hpd_get_pin(struct gpio * gpio)144*c349dbc7Sjsg struct hw_gpio_pin *dal_hw_hpd_get_pin(struct gpio *gpio)
145*c349dbc7Sjsg {
146*c349dbc7Sjsg 	struct hw_hpd *hw_hpd = dal_gpio_get_hpd(gpio);
147*c349dbc7Sjsg 
148*c349dbc7Sjsg 	return &hw_hpd->base.base;
149fb4d8502Sjsg }
150