1fb4d8502Sjsg /*
2fb4d8502Sjsg * Copyright 2012-15 Advanced Micro Devices, Inc.
3fb4d8502Sjsg *
4fb4d8502Sjsg * Permission is hereby granted, free of charge, to any person obtaining a
5fb4d8502Sjsg * copy of this software and associated documentation files (the "Software"),
6fb4d8502Sjsg * to deal in the Software without restriction, including without limitation
7fb4d8502Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8fb4d8502Sjsg * and/or sell copies of the Software, and to permit persons to whom the
9fb4d8502Sjsg * Software is furnished to do so, subject to the following conditions:
10fb4d8502Sjsg *
11fb4d8502Sjsg * The above copyright notice and this permission notice shall be included in
12fb4d8502Sjsg * all copies or substantial portions of the Software.
13fb4d8502Sjsg *
14fb4d8502Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15fb4d8502Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16fb4d8502Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17fb4d8502Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18fb4d8502Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19fb4d8502Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20fb4d8502Sjsg * OTHER DEALINGS IN THE SOFTWARE.
21fb4d8502Sjsg *
22fb4d8502Sjsg * Authors: AMD
23fb4d8502Sjsg *
24fb4d8502Sjsg */
25fb4d8502Sjsg
26fb4d8502Sjsg /*
27fb4d8502Sjsg * Pre-requisites: headers required by header of this unit
28fb4d8502Sjsg */
29fb4d8502Sjsg
30fb4d8502Sjsg #include "dm_services.h"
31fb4d8502Sjsg
32fb4d8502Sjsg #include "include/gpio_interface.h"
33fb4d8502Sjsg #include "include/gpio_service_interface.h"
34fb4d8502Sjsg #include "hw_gpio.h"
35fb4d8502Sjsg #include "hw_translate.h"
36fb4d8502Sjsg #include "hw_factory.h"
37fb4d8502Sjsg #include "gpio_service.h"
38fb4d8502Sjsg
39fb4d8502Sjsg /*
40fb4d8502Sjsg * Post-requisites: headers required by this unit
41fb4d8502Sjsg */
42fb4d8502Sjsg
43fb4d8502Sjsg /*
44fb4d8502Sjsg * This unit
45fb4d8502Sjsg */
46fb4d8502Sjsg
47fb4d8502Sjsg /*
48fb4d8502Sjsg * @brief
49fb4d8502Sjsg * Public API
50fb4d8502Sjsg */
51fb4d8502Sjsg
dal_gpio_open(struct gpio * gpio,enum gpio_mode mode)52fb4d8502Sjsg enum gpio_result dal_gpio_open(
53fb4d8502Sjsg struct gpio *gpio,
54fb4d8502Sjsg enum gpio_mode mode)
55fb4d8502Sjsg {
56fb4d8502Sjsg return dal_gpio_open_ex(gpio, mode);
57fb4d8502Sjsg }
58fb4d8502Sjsg
dal_gpio_open_ex(struct gpio * gpio,enum gpio_mode mode)59fb4d8502Sjsg enum gpio_result dal_gpio_open_ex(
60fb4d8502Sjsg struct gpio *gpio,
61fb4d8502Sjsg enum gpio_mode mode)
62fb4d8502Sjsg {
63fb4d8502Sjsg if (gpio->pin) {
64*ad8b1aafSjsg BREAK_TO_DEBUGGER();
65fb4d8502Sjsg return GPIO_RESULT_ALREADY_OPENED;
66fb4d8502Sjsg }
67fb4d8502Sjsg
68c349dbc7Sjsg // No action if allocation failed during gpio construct
69c349dbc7Sjsg if (!gpio->hw_container.ddc) {
70*ad8b1aafSjsg BREAK_TO_DEBUGGER();
71c349dbc7Sjsg return GPIO_RESULT_NON_SPECIFIC_ERROR;
72c349dbc7Sjsg }
73fb4d8502Sjsg gpio->mode = mode;
74fb4d8502Sjsg
75c349dbc7Sjsg return dal_gpio_service_open(gpio);
76fb4d8502Sjsg }
77fb4d8502Sjsg
dal_gpio_get_value(const struct gpio * gpio,uint32_t * value)78fb4d8502Sjsg enum gpio_result dal_gpio_get_value(
79fb4d8502Sjsg const struct gpio *gpio,
80fb4d8502Sjsg uint32_t *value)
81fb4d8502Sjsg {
82fb4d8502Sjsg if (!gpio->pin) {
83fb4d8502Sjsg BREAK_TO_DEBUGGER();
84fb4d8502Sjsg return GPIO_RESULT_NULL_HANDLE;
85fb4d8502Sjsg }
86fb4d8502Sjsg
87fb4d8502Sjsg return gpio->pin->funcs->get_value(gpio->pin, value);
88fb4d8502Sjsg }
89fb4d8502Sjsg
dal_gpio_set_value(const struct gpio * gpio,uint32_t value)90fb4d8502Sjsg enum gpio_result dal_gpio_set_value(
91fb4d8502Sjsg const struct gpio *gpio,
92fb4d8502Sjsg uint32_t value)
93fb4d8502Sjsg {
94fb4d8502Sjsg if (!gpio->pin) {
95fb4d8502Sjsg BREAK_TO_DEBUGGER();
96fb4d8502Sjsg return GPIO_RESULT_NULL_HANDLE;
97fb4d8502Sjsg }
98fb4d8502Sjsg
99fb4d8502Sjsg return gpio->pin->funcs->set_value(gpio->pin, value);
100fb4d8502Sjsg }
101fb4d8502Sjsg
dal_gpio_get_mode(const struct gpio * gpio)102fb4d8502Sjsg enum gpio_mode dal_gpio_get_mode(
103fb4d8502Sjsg const struct gpio *gpio)
104fb4d8502Sjsg {
105fb4d8502Sjsg return gpio->mode;
106fb4d8502Sjsg }
107fb4d8502Sjsg
dal_gpio_lock_pin(struct gpio * gpio)108c349dbc7Sjsg enum gpio_result dal_gpio_lock_pin(
109c349dbc7Sjsg struct gpio *gpio)
110c349dbc7Sjsg {
111c349dbc7Sjsg return dal_gpio_service_lock(gpio->service, gpio->id, gpio->en);
112c349dbc7Sjsg }
113c349dbc7Sjsg
dal_gpio_unlock_pin(struct gpio * gpio)114c349dbc7Sjsg enum gpio_result dal_gpio_unlock_pin(
115c349dbc7Sjsg struct gpio *gpio)
116c349dbc7Sjsg {
117c349dbc7Sjsg return dal_gpio_service_unlock(gpio->service, gpio->id, gpio->en);
118c349dbc7Sjsg }
119c349dbc7Sjsg
dal_gpio_change_mode(struct gpio * gpio,enum gpio_mode mode)120fb4d8502Sjsg enum gpio_result dal_gpio_change_mode(
121fb4d8502Sjsg struct gpio *gpio,
122fb4d8502Sjsg enum gpio_mode mode)
123fb4d8502Sjsg {
124fb4d8502Sjsg if (!gpio->pin) {
125fb4d8502Sjsg BREAK_TO_DEBUGGER();
126fb4d8502Sjsg return GPIO_RESULT_NULL_HANDLE;
127fb4d8502Sjsg }
128fb4d8502Sjsg
129fb4d8502Sjsg return gpio->pin->funcs->change_mode(gpio->pin, mode);
130fb4d8502Sjsg }
131fb4d8502Sjsg
dal_gpio_get_id(const struct gpio * gpio)132fb4d8502Sjsg enum gpio_id dal_gpio_get_id(
133fb4d8502Sjsg const struct gpio *gpio)
134fb4d8502Sjsg {
135fb4d8502Sjsg return gpio->id;
136fb4d8502Sjsg }
137fb4d8502Sjsg
dal_gpio_get_enum(const struct gpio * gpio)138fb4d8502Sjsg uint32_t dal_gpio_get_enum(
139fb4d8502Sjsg const struct gpio *gpio)
140fb4d8502Sjsg {
141fb4d8502Sjsg return gpio->en;
142fb4d8502Sjsg }
143fb4d8502Sjsg
dal_gpio_set_config(struct gpio * gpio,const struct gpio_config_data * config_data)144fb4d8502Sjsg enum gpio_result dal_gpio_set_config(
145fb4d8502Sjsg struct gpio *gpio,
146fb4d8502Sjsg const struct gpio_config_data *config_data)
147fb4d8502Sjsg {
148fb4d8502Sjsg if (!gpio->pin) {
149fb4d8502Sjsg BREAK_TO_DEBUGGER();
150fb4d8502Sjsg return GPIO_RESULT_NULL_HANDLE;
151fb4d8502Sjsg }
152fb4d8502Sjsg
153fb4d8502Sjsg return gpio->pin->funcs->set_config(gpio->pin, config_data);
154fb4d8502Sjsg }
155fb4d8502Sjsg
dal_gpio_get_pin_info(const struct gpio * gpio,struct gpio_pin_info * pin_info)156fb4d8502Sjsg enum gpio_result dal_gpio_get_pin_info(
157fb4d8502Sjsg const struct gpio *gpio,
158fb4d8502Sjsg struct gpio_pin_info *pin_info)
159fb4d8502Sjsg {
160fb4d8502Sjsg return gpio->service->translate.funcs->id_to_offset(
161fb4d8502Sjsg gpio->id, gpio->en, pin_info) ?
162fb4d8502Sjsg GPIO_RESULT_OK : GPIO_RESULT_INVALID_DATA;
163fb4d8502Sjsg }
164fb4d8502Sjsg
dal_gpio_get_sync_source(const struct gpio * gpio)165fb4d8502Sjsg enum sync_source dal_gpio_get_sync_source(
166fb4d8502Sjsg const struct gpio *gpio)
167fb4d8502Sjsg {
168fb4d8502Sjsg switch (gpio->id) {
169fb4d8502Sjsg case GPIO_ID_GENERIC:
170fb4d8502Sjsg switch (gpio->en) {
171fb4d8502Sjsg case GPIO_GENERIC_A:
172fb4d8502Sjsg return SYNC_SOURCE_IO_GENERIC_A;
173fb4d8502Sjsg case GPIO_GENERIC_B:
174fb4d8502Sjsg return SYNC_SOURCE_IO_GENERIC_B;
175fb4d8502Sjsg case GPIO_GENERIC_C:
176fb4d8502Sjsg return SYNC_SOURCE_IO_GENERIC_C;
177fb4d8502Sjsg case GPIO_GENERIC_D:
178fb4d8502Sjsg return SYNC_SOURCE_IO_GENERIC_D;
179fb4d8502Sjsg case GPIO_GENERIC_E:
180fb4d8502Sjsg return SYNC_SOURCE_IO_GENERIC_E;
181fb4d8502Sjsg case GPIO_GENERIC_F:
182fb4d8502Sjsg return SYNC_SOURCE_IO_GENERIC_F;
183fb4d8502Sjsg default:
184fb4d8502Sjsg return SYNC_SOURCE_NONE;
185fb4d8502Sjsg }
186fb4d8502Sjsg break;
187fb4d8502Sjsg case GPIO_ID_SYNC:
188fb4d8502Sjsg switch (gpio->en) {
189fb4d8502Sjsg case GPIO_SYNC_HSYNC_A:
190fb4d8502Sjsg return SYNC_SOURCE_IO_HSYNC_A;
191fb4d8502Sjsg case GPIO_SYNC_VSYNC_A:
192fb4d8502Sjsg return SYNC_SOURCE_IO_VSYNC_A;
193fb4d8502Sjsg case GPIO_SYNC_HSYNC_B:
194fb4d8502Sjsg return SYNC_SOURCE_IO_HSYNC_B;
195fb4d8502Sjsg case GPIO_SYNC_VSYNC_B:
196fb4d8502Sjsg return SYNC_SOURCE_IO_VSYNC_B;
197fb4d8502Sjsg default:
198fb4d8502Sjsg return SYNC_SOURCE_NONE;
199fb4d8502Sjsg }
200fb4d8502Sjsg break;
201fb4d8502Sjsg case GPIO_ID_HPD:
202fb4d8502Sjsg switch (gpio->en) {
203fb4d8502Sjsg case GPIO_HPD_1:
204fb4d8502Sjsg return SYNC_SOURCE_IO_HPD1;
205fb4d8502Sjsg case GPIO_HPD_2:
206fb4d8502Sjsg return SYNC_SOURCE_IO_HPD2;
207fb4d8502Sjsg default:
208fb4d8502Sjsg return SYNC_SOURCE_NONE;
209fb4d8502Sjsg }
210fb4d8502Sjsg break;
211fb4d8502Sjsg case GPIO_ID_GSL:
212fb4d8502Sjsg switch (gpio->en) {
213fb4d8502Sjsg case GPIO_GSL_GENLOCK_CLOCK:
214fb4d8502Sjsg return SYNC_SOURCE_GSL_IO_GENLOCK_CLOCK;
215fb4d8502Sjsg case GPIO_GSL_GENLOCK_VSYNC:
216fb4d8502Sjsg return SYNC_SOURCE_GSL_IO_GENLOCK_VSYNC;
217fb4d8502Sjsg case GPIO_GSL_SWAPLOCK_A:
218fb4d8502Sjsg return SYNC_SOURCE_GSL_IO_SWAPLOCK_A;
219fb4d8502Sjsg case GPIO_GSL_SWAPLOCK_B:
220fb4d8502Sjsg return SYNC_SOURCE_GSL_IO_SWAPLOCK_B;
221fb4d8502Sjsg default:
222fb4d8502Sjsg return SYNC_SOURCE_NONE;
223fb4d8502Sjsg }
224fb4d8502Sjsg break;
225fb4d8502Sjsg default:
226fb4d8502Sjsg return SYNC_SOURCE_NONE;
227fb4d8502Sjsg }
228fb4d8502Sjsg }
229fb4d8502Sjsg
dal_gpio_get_output_state(const struct gpio * gpio)230fb4d8502Sjsg enum gpio_pin_output_state dal_gpio_get_output_state(
231fb4d8502Sjsg const struct gpio *gpio)
232fb4d8502Sjsg {
233fb4d8502Sjsg return gpio->output_state;
234fb4d8502Sjsg }
235fb4d8502Sjsg
dal_gpio_get_ddc(struct gpio * gpio)236c349dbc7Sjsg struct hw_ddc *dal_gpio_get_ddc(struct gpio *gpio)
237c349dbc7Sjsg {
238c349dbc7Sjsg return gpio->hw_container.ddc;
239c349dbc7Sjsg }
240c349dbc7Sjsg
dal_gpio_get_hpd(struct gpio * gpio)241c349dbc7Sjsg struct hw_hpd *dal_gpio_get_hpd(struct gpio *gpio)
242c349dbc7Sjsg {
243c349dbc7Sjsg return gpio->hw_container.hpd;
244c349dbc7Sjsg }
245c349dbc7Sjsg
dal_gpio_get_generic(struct gpio * gpio)246c349dbc7Sjsg struct hw_generic *dal_gpio_get_generic(struct gpio *gpio)
247c349dbc7Sjsg {
248c349dbc7Sjsg return gpio->hw_container.generic;
249c349dbc7Sjsg }
250c349dbc7Sjsg
dal_gpio_close(struct gpio * gpio)251fb4d8502Sjsg void dal_gpio_close(
252fb4d8502Sjsg struct gpio *gpio)
253fb4d8502Sjsg {
254fb4d8502Sjsg if (!gpio)
255fb4d8502Sjsg return;
256fb4d8502Sjsg
257fb4d8502Sjsg dal_gpio_service_close(gpio->service, &gpio->pin);
258fb4d8502Sjsg
259fb4d8502Sjsg gpio->mode = GPIO_MODE_UNKNOWN;
260fb4d8502Sjsg }
261fb4d8502Sjsg
262fb4d8502Sjsg /*
263fb4d8502Sjsg * @brief
264fb4d8502Sjsg * Creation and destruction
265fb4d8502Sjsg */
266fb4d8502Sjsg
dal_gpio_create(struct gpio_service * service,enum gpio_id id,uint32_t en,enum gpio_pin_output_state output_state)267fb4d8502Sjsg struct gpio *dal_gpio_create(
268fb4d8502Sjsg struct gpio_service *service,
269fb4d8502Sjsg enum gpio_id id,
270fb4d8502Sjsg uint32_t en,
271fb4d8502Sjsg enum gpio_pin_output_state output_state)
272fb4d8502Sjsg {
273fb4d8502Sjsg struct gpio *gpio = kzalloc(sizeof(struct gpio), GFP_KERNEL);
274fb4d8502Sjsg
275fb4d8502Sjsg if (!gpio) {
276fb4d8502Sjsg ASSERT_CRITICAL(false);
277fb4d8502Sjsg return NULL;
278fb4d8502Sjsg }
279fb4d8502Sjsg
280fb4d8502Sjsg gpio->service = service;
281fb4d8502Sjsg gpio->pin = NULL;
282fb4d8502Sjsg gpio->id = id;
283fb4d8502Sjsg gpio->en = en;
284fb4d8502Sjsg gpio->mode = GPIO_MODE_UNKNOWN;
285fb4d8502Sjsg gpio->output_state = output_state;
286fb4d8502Sjsg
287c349dbc7Sjsg //initialize hw_container union based on id
288c349dbc7Sjsg switch (gpio->id) {
289c349dbc7Sjsg case GPIO_ID_DDC_DATA:
290c349dbc7Sjsg gpio->service->factory.funcs->init_ddc_data(&gpio->hw_container.ddc, service->ctx, id, en);
291c349dbc7Sjsg break;
292c349dbc7Sjsg case GPIO_ID_DDC_CLOCK:
293c349dbc7Sjsg gpio->service->factory.funcs->init_ddc_data(&gpio->hw_container.ddc, service->ctx, id, en);
294c349dbc7Sjsg break;
295c349dbc7Sjsg case GPIO_ID_GENERIC:
296c349dbc7Sjsg gpio->service->factory.funcs->init_generic(&gpio->hw_container.generic, service->ctx, id, en);
297c349dbc7Sjsg break;
298c349dbc7Sjsg case GPIO_ID_HPD:
299c349dbc7Sjsg gpio->service->factory.funcs->init_hpd(&gpio->hw_container.hpd, service->ctx, id, en);
300c349dbc7Sjsg break;
301c349dbc7Sjsg // TODO: currently gpio for sync and gsl does not get created, might need it later
302c349dbc7Sjsg case GPIO_ID_SYNC:
303c349dbc7Sjsg break;
304c349dbc7Sjsg case GPIO_ID_GSL:
305c349dbc7Sjsg break;
306c349dbc7Sjsg default:
307c349dbc7Sjsg ASSERT_CRITICAL(false);
308c349dbc7Sjsg gpio->pin = NULL;
309c349dbc7Sjsg }
310c349dbc7Sjsg
311fb4d8502Sjsg return gpio;
312fb4d8502Sjsg }
313fb4d8502Sjsg
dal_gpio_destroy(struct gpio ** gpio)314fb4d8502Sjsg void dal_gpio_destroy(
315fb4d8502Sjsg struct gpio **gpio)
316fb4d8502Sjsg {
317fb4d8502Sjsg if (!gpio || !*gpio) {
318fb4d8502Sjsg ASSERT_CRITICAL(false);
319fb4d8502Sjsg return;
320fb4d8502Sjsg }
321fb4d8502Sjsg
322c349dbc7Sjsg switch ((*gpio)->id) {
323c349dbc7Sjsg case GPIO_ID_DDC_DATA:
324c349dbc7Sjsg kfree((*gpio)->hw_container.ddc);
325c349dbc7Sjsg (*gpio)->hw_container.ddc = NULL;
326c349dbc7Sjsg break;
327c349dbc7Sjsg case GPIO_ID_DDC_CLOCK:
328c349dbc7Sjsg //TODO: might want to change it to init_ddc_clock
329c349dbc7Sjsg kfree((*gpio)->hw_container.ddc);
330c349dbc7Sjsg (*gpio)->hw_container.ddc = NULL;
331c349dbc7Sjsg break;
332c349dbc7Sjsg case GPIO_ID_GENERIC:
333c349dbc7Sjsg kfree((*gpio)->hw_container.generic);
334c349dbc7Sjsg (*gpio)->hw_container.generic = NULL;
335c349dbc7Sjsg break;
336c349dbc7Sjsg case GPIO_ID_HPD:
337c349dbc7Sjsg kfree((*gpio)->hw_container.hpd);
338c349dbc7Sjsg (*gpio)->hw_container.hpd = NULL;
339c349dbc7Sjsg break;
340c349dbc7Sjsg // TODO: currently gpio for sync and gsl does not get created, might need it later
341c349dbc7Sjsg case GPIO_ID_SYNC:
342c349dbc7Sjsg break;
343c349dbc7Sjsg case GPIO_ID_GSL:
344c349dbc7Sjsg break;
345c349dbc7Sjsg default:
346c349dbc7Sjsg break;
347c349dbc7Sjsg }
348fb4d8502Sjsg
349fb4d8502Sjsg kfree(*gpio);
350fb4d8502Sjsg
351fb4d8502Sjsg *gpio = NULL;
352fb4d8502Sjsg }
353