xref: /openbsd-src/sys/dev/pci/drm/amd/display/dc/dsc/rc_calc.c (revision f005ef32267c16bdb134f0e9fa4477dbe07c263a)
1c349dbc7Sjsg 
2c349dbc7Sjsg /*
3c349dbc7Sjsg  * Copyright 2017 Advanced Micro Devices, Inc.
4c349dbc7Sjsg  *
5c349dbc7Sjsg  * Permission is hereby granted, free of charge, to any person obtaining a
6c349dbc7Sjsg  * copy of this software and associated documentation files (the "Software"),
7c349dbc7Sjsg  * to deal in the Software without restriction, including without limitation
8c349dbc7Sjsg  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9c349dbc7Sjsg  * and/or sell copies of the Software, and to permit persons to whom the
10c349dbc7Sjsg  * Software is furnished to do so, subject to the following conditions:
11c349dbc7Sjsg  *
12c349dbc7Sjsg  * The above copyright notice and this permission notice shall be included in
13c349dbc7Sjsg  * all copies or substantial portions of the Software.
14c349dbc7Sjsg  *
15c349dbc7Sjsg  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16c349dbc7Sjsg  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17c349dbc7Sjsg  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18c349dbc7Sjsg  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19c349dbc7Sjsg  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20c349dbc7Sjsg  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21c349dbc7Sjsg  * OTHER DEALINGS IN THE SOFTWARE.
22c349dbc7Sjsg  *
23c349dbc7Sjsg  * Authors: AMD
24c349dbc7Sjsg  *
25c349dbc7Sjsg  */
26c349dbc7Sjsg #include "rc_calc.h"
27ad8b1aafSjsg 
28ad8b1aafSjsg /**
29ad8b1aafSjsg  * calc_rc_params - reads the user's cmdline mode
30ad8b1aafSjsg  * @rc: DC internal DSC parameters
31ad8b1aafSjsg  * @pps: DRM struct with all required DSC values
32ad8b1aafSjsg  *
33ad8b1aafSjsg  * This function expects a drm_dsc_config data struct with all the required DSC
34ad8b1aafSjsg  * values previously filled out by our driver and based on this information it
35ad8b1aafSjsg  * computes some of the DSC values.
36ad8b1aafSjsg  *
37ad8b1aafSjsg  * @note This calculation requires float point operation, most of it executes
38ad8b1aafSjsg  * under kernel_fpu_{begin,end}.
39ad8b1aafSjsg  */
calc_rc_params(struct rc_params * rc,const struct drm_dsc_config * pps)40ad8b1aafSjsg void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps)
41ad8b1aafSjsg {
42*f005ef32Sjsg #if defined(CONFIG_DRM_AMD_DC_FP)
43ad8b1aafSjsg 	enum colour_mode mode;
44ad8b1aafSjsg 	enum bits_per_comp bpc;
45ad8b1aafSjsg 	bool is_navite_422_or_420;
46ad8b1aafSjsg 	u16 drm_bpp = pps->bits_per_pixel;
47ad8b1aafSjsg 	int slice_width  = pps->slice_width;
48ad8b1aafSjsg 	int slice_height = pps->slice_height;
49ad8b1aafSjsg 
50ad8b1aafSjsg 	mode = pps->convert_rgb ? CM_RGB : (pps->simple_422  ? CM_444 :
51ad8b1aafSjsg 					   (pps->native_422  ? CM_422 :
52ad8b1aafSjsg 					    pps->native_420  ? CM_420 : CM_444));
53ad8b1aafSjsg 	bpc = (pps->bits_per_component == 8) ? BPC_8 : (pps->bits_per_component == 10)
54ad8b1aafSjsg 					     ? BPC_10 : BPC_12;
55ad8b1aafSjsg 
56ad8b1aafSjsg 	is_navite_422_or_420 = pps->native_422 || pps->native_420;
57ad8b1aafSjsg 
58ad8b1aafSjsg 	DC_FP_START();
59ad8b1aafSjsg 	_do_calc_rc_params(rc, mode, bpc, drm_bpp, is_navite_422_or_420,
60ad8b1aafSjsg 			   slice_width, slice_height,
61ad8b1aafSjsg 			   pps->dsc_version_minor);
62ad8b1aafSjsg 	DC_FP_END();
63*f005ef32Sjsg #endif
64ad8b1aafSjsg }
65