1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dce/dce_8_0_d.h" 27 #include "dce/dce_8_0_sh_mask.h" 28 29 #include "dm_services.h" 30 31 #include "link_encoder.h" 32 #include "stream_encoder.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "irq/dce80/irq_service_dce80.h" 37 #include "dce110/dce110_timing_generator.h" 38 #include "dce110/dce110_resource.h" 39 #include "dce80/dce80_timing_generator.h" 40 #include "dce/dce_mem_input.h" 41 #include "dce/dce_link_encoder.h" 42 #include "dce/dce_stream_encoder.h" 43 #include "dce/dce_mem_input.h" 44 #include "dce/dce_ipp.h" 45 #include "dce/dce_transform.h" 46 #include "dce/dce_opp.h" 47 #include "dce/dce_clocks.h" 48 #include "dce/dce_clock_source.h" 49 #include "dce/dce_audio.h" 50 #include "dce/dce_hwseq.h" 51 #include "dce80/dce80_hw_sequencer.h" 52 #include "dce100/dce100_resource.h" 53 54 #include "reg_helper.h" 55 56 #include "dce/dce_dmcu.h" 57 #include "dce/dce_aux.h" 58 #include "dce/dce_abm.h" 59 /* TODO remove this include */ 60 61 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 62 #include "gmc/gmc_7_1_d.h" 63 #include "gmc/gmc_7_1_sh_mask.h" 64 #endif 65 66 #ifndef mmDP_DPHY_INTERNAL_CTRL 67 #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE 68 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE 69 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE 70 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE 71 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE 72 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE 73 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE 74 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x4EDE 75 #endif 76 77 78 #ifndef mmBIOS_SCRATCH_2 79 #define mmBIOS_SCRATCH_2 0x05CB 80 #define mmBIOS_SCRATCH_6 0x05CF 81 #endif 82 83 #ifndef mmDP_DPHY_FAST_TRAINING 84 #define mmDP_DPHY_FAST_TRAINING 0x1CCE 85 #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE 86 #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE 87 #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE 88 #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE 89 #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE 90 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE 91 #define mmDP6_DP_DPHY_FAST_TRAINING 0x4ECE 92 #endif 93 94 95 #ifndef mmHPD_DC_HPD_CONTROL 96 #define mmHPD_DC_HPD_CONTROL 0x189A 97 #define mmHPD0_DC_HPD_CONTROL 0x189A 98 #define mmHPD1_DC_HPD_CONTROL 0x18A2 99 #define mmHPD2_DC_HPD_CONTROL 0x18AA 100 #define mmHPD3_DC_HPD_CONTROL 0x18B2 101 #define mmHPD4_DC_HPD_CONTROL 0x18BA 102 #define mmHPD5_DC_HPD_CONTROL 0x18C2 103 #endif 104 105 #define DCE11_DIG_FE_CNTL 0x4a00 106 #define DCE11_DIG_BE_CNTL 0x4a47 107 #define DCE11_DP_SEC 0x4ac3 108 109 static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = { 110 { 111 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 112 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL), 113 .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 114 - mmDPG_WATERMARK_MASK_CONTROL), 115 }, 116 { 117 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 118 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 119 .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 120 - mmDPG_WATERMARK_MASK_CONTROL), 121 }, 122 { 123 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 124 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 125 .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 126 - mmDPG_WATERMARK_MASK_CONTROL), 127 }, 128 { 129 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 130 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 131 .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 132 - mmDPG_WATERMARK_MASK_CONTROL), 133 }, 134 { 135 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 136 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 137 .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 138 - mmDPG_WATERMARK_MASK_CONTROL), 139 }, 140 { 141 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 142 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 143 .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 144 - mmDPG_WATERMARK_MASK_CONTROL), 145 } 146 }; 147 148 /* set register offset */ 149 #define SR(reg_name)\ 150 .reg_name = mm ## reg_name 151 152 /* set register offset with instance */ 153 #define SRI(reg_name, block, id)\ 154 .reg_name = mm ## block ## id ## _ ## reg_name 155 156 157 static const struct dccg_registers disp_clk_regs = { 158 CLK_COMMON_REG_LIST_DCE_BASE() 159 }; 160 161 static const struct dccg_shift disp_clk_shift = { 162 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 163 }; 164 165 static const struct dccg_mask disp_clk_mask = { 166 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 167 }; 168 169 #define ipp_regs(id)\ 170 [id] = {\ 171 IPP_COMMON_REG_LIST_DCE_BASE(id)\ 172 } 173 174 static const struct dce_ipp_registers ipp_regs[] = { 175 ipp_regs(0), 176 ipp_regs(1), 177 ipp_regs(2), 178 ipp_regs(3), 179 ipp_regs(4), 180 ipp_regs(5) 181 }; 182 183 static const struct dce_ipp_shift ipp_shift = { 184 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 185 }; 186 187 static const struct dce_ipp_mask ipp_mask = { 188 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 189 }; 190 191 #define transform_regs(id)\ 192 [id] = {\ 193 XFM_COMMON_REG_LIST_DCE80(id)\ 194 } 195 196 static const struct dce_transform_registers xfm_regs[] = { 197 transform_regs(0), 198 transform_regs(1), 199 transform_regs(2), 200 transform_regs(3), 201 transform_regs(4), 202 transform_regs(5) 203 }; 204 205 static const struct dce_transform_shift xfm_shift = { 206 XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT) 207 }; 208 209 static const struct dce_transform_mask xfm_mask = { 210 XFM_COMMON_MASK_SH_LIST_DCE80(_MASK) 211 }; 212 213 #define aux_regs(id)\ 214 [id] = {\ 215 AUX_REG_LIST(id)\ 216 } 217 218 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 219 aux_regs(0), 220 aux_regs(1), 221 aux_regs(2), 222 aux_regs(3), 223 aux_regs(4), 224 aux_regs(5) 225 }; 226 227 #define hpd_regs(id)\ 228 [id] = {\ 229 HPD_REG_LIST(id)\ 230 } 231 232 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 233 hpd_regs(0), 234 hpd_regs(1), 235 hpd_regs(2), 236 hpd_regs(3), 237 hpd_regs(4), 238 hpd_regs(5) 239 }; 240 241 #define link_regs(id)\ 242 [id] = {\ 243 LE_DCE80_REG_LIST(id)\ 244 } 245 246 static const struct dce110_link_enc_registers link_enc_regs[] = { 247 link_regs(0), 248 link_regs(1), 249 link_regs(2), 250 link_regs(3), 251 link_regs(4), 252 link_regs(5), 253 link_regs(6), 254 }; 255 256 #define stream_enc_regs(id)\ 257 [id] = {\ 258 SE_COMMON_REG_LIST_DCE_BASE(id),\ 259 .AFMT_CNTL = 0,\ 260 } 261 262 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 263 stream_enc_regs(0), 264 stream_enc_regs(1), 265 stream_enc_regs(2), 266 stream_enc_regs(3), 267 stream_enc_regs(4), 268 stream_enc_regs(5), 269 stream_enc_regs(6) 270 }; 271 272 static const struct dce_stream_encoder_shift se_shift = { 273 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) 274 }; 275 276 static const struct dce_stream_encoder_mask se_mask = { 277 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) 278 }; 279 280 #define opp_regs(id)\ 281 [id] = {\ 282 OPP_DCE_80_REG_LIST(id),\ 283 } 284 285 static const struct dce_opp_registers opp_regs[] = { 286 opp_regs(0), 287 opp_regs(1), 288 opp_regs(2), 289 opp_regs(3), 290 opp_regs(4), 291 opp_regs(5) 292 }; 293 294 static const struct dce_opp_shift opp_shift = { 295 OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT) 296 }; 297 298 static const struct dce_opp_mask opp_mask = { 299 OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK) 300 }; 301 302 #define aux_engine_regs(id)\ 303 [id] = {\ 304 AUX_COMMON_REG_LIST(id), \ 305 .AUX_RESET_MASK = 0 \ 306 } 307 308 static const struct dce110_aux_registers aux_engine_regs[] = { 309 aux_engine_regs(0), 310 aux_engine_regs(1), 311 aux_engine_regs(2), 312 aux_engine_regs(3), 313 aux_engine_regs(4), 314 aux_engine_regs(5) 315 }; 316 317 #define audio_regs(id)\ 318 [id] = {\ 319 AUD_COMMON_REG_LIST(id)\ 320 } 321 322 static const struct dce_audio_registers audio_regs[] = { 323 audio_regs(0), 324 audio_regs(1), 325 audio_regs(2), 326 audio_regs(3), 327 audio_regs(4), 328 audio_regs(5), 329 audio_regs(6), 330 }; 331 332 static const struct dce_audio_shift audio_shift = { 333 AUD_COMMON_MASK_SH_LIST(__SHIFT) 334 }; 335 336 static const struct dce_aduio_mask audio_mask = { 337 AUD_COMMON_MASK_SH_LIST(_MASK) 338 }; 339 340 #define clk_src_regs(id)\ 341 [id] = {\ 342 CS_COMMON_REG_LIST_DCE_80(id),\ 343 } 344 345 346 static const struct dce110_clk_src_regs clk_src_regs[] = { 347 clk_src_regs(0), 348 clk_src_regs(1), 349 clk_src_regs(2) 350 }; 351 352 static const struct dce110_clk_src_shift cs_shift = { 353 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 354 }; 355 356 static const struct dce110_clk_src_mask cs_mask = { 357 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 358 }; 359 360 static const struct bios_registers bios_regs = { 361 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 362 }; 363 364 static const struct resource_caps res_cap = { 365 .num_timing_generator = 6, 366 .num_audio = 6, 367 .num_stream_encoder = 6, 368 .num_pll = 3, 369 .num_ddc = 6, 370 }; 371 372 static const struct resource_caps res_cap_81 = { 373 .num_timing_generator = 4, 374 .num_audio = 7, 375 .num_stream_encoder = 7, 376 .num_pll = 3, 377 .num_ddc = 6, 378 }; 379 380 static const struct resource_caps res_cap_83 = { 381 .num_timing_generator = 2, 382 .num_audio = 6, 383 .num_stream_encoder = 6, 384 .num_pll = 2, 385 .num_ddc = 2, 386 }; 387 388 static const struct dce_dmcu_registers dmcu_regs = { 389 DMCU_DCE80_REG_LIST() 390 }; 391 392 static const struct dce_dmcu_shift dmcu_shift = { 393 DMCU_MASK_SH_LIST_DCE80(__SHIFT) 394 }; 395 396 static const struct dce_dmcu_mask dmcu_mask = { 397 DMCU_MASK_SH_LIST_DCE80(_MASK) 398 }; 399 static const struct dce_abm_registers abm_regs = { 400 ABM_DCE110_COMMON_REG_LIST() 401 }; 402 403 static const struct dce_abm_shift abm_shift = { 404 ABM_MASK_SH_LIST_DCE110(__SHIFT) 405 }; 406 407 static const struct dce_abm_mask abm_mask = { 408 ABM_MASK_SH_LIST_DCE110(_MASK) 409 }; 410 411 #define CTX ctx 412 #define REG(reg) mm ## reg 413 414 #ifndef mmCC_DC_HDMI_STRAPS 415 #define mmCC_DC_HDMI_STRAPS 0x1918 416 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 417 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 418 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 419 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 420 #endif 421 422 static void read_dce_straps( 423 struct dc_context *ctx, 424 struct resource_straps *straps) 425 { 426 REG_GET_2(CC_DC_HDMI_STRAPS, 427 HDMI_DISABLE, &straps->hdmi_disable, 428 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 429 430 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 431 } 432 433 static struct audio *create_audio( 434 struct dc_context *ctx, unsigned int inst) 435 { 436 return dce_audio_create(ctx, inst, 437 &audio_regs[inst], &audio_shift, &audio_mask); 438 } 439 440 static struct timing_generator *dce80_timing_generator_create( 441 struct dc_context *ctx, 442 uint32_t instance, 443 const struct dce110_timing_generator_offsets *offsets) 444 { 445 struct dce110_timing_generator *tg110 = 446 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 447 448 if (!tg110) 449 return NULL; 450 451 dce80_timing_generator_construct(tg110, ctx, instance, offsets); 452 return &tg110->base; 453 } 454 455 static struct output_pixel_processor *dce80_opp_create( 456 struct dc_context *ctx, 457 uint32_t inst) 458 { 459 struct dce110_opp *opp = 460 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 461 462 if (!opp) 463 return NULL; 464 465 dce110_opp_construct(opp, 466 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 467 return &opp->base; 468 } 469 470 struct aux_engine *dce80_aux_engine_create( 471 struct dc_context *ctx, 472 uint32_t inst) 473 { 474 struct aux_engine_dce110 *aux_engine = 475 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 476 477 if (!aux_engine) 478 return NULL; 479 480 dce110_aux_engine_construct(aux_engine, ctx, inst, 481 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 482 &aux_engine_regs[inst]); 483 484 return &aux_engine->base; 485 } 486 487 static struct stream_encoder *dce80_stream_encoder_create( 488 enum engine_id eng_id, 489 struct dc_context *ctx) 490 { 491 struct dce110_stream_encoder *enc110 = 492 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 493 494 if (!enc110) 495 return NULL; 496 497 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 498 &stream_enc_regs[eng_id], 499 &se_shift, &se_mask); 500 return &enc110->base; 501 } 502 503 #define SRII(reg_name, block, id)\ 504 .reg_name[id] = mm ## block ## id ## _ ## reg_name 505 506 static const struct dce_hwseq_registers hwseq_reg = { 507 HWSEQ_DCE8_REG_LIST() 508 }; 509 510 static const struct dce_hwseq_shift hwseq_shift = { 511 HWSEQ_DCE8_MASK_SH_LIST(__SHIFT) 512 }; 513 514 static const struct dce_hwseq_mask hwseq_mask = { 515 HWSEQ_DCE8_MASK_SH_LIST(_MASK) 516 }; 517 518 static struct dce_hwseq *dce80_hwseq_create( 519 struct dc_context *ctx) 520 { 521 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 522 523 if (hws) { 524 hws->ctx = ctx; 525 hws->regs = &hwseq_reg; 526 hws->shifts = &hwseq_shift; 527 hws->masks = &hwseq_mask; 528 } 529 return hws; 530 } 531 532 static const struct resource_create_funcs res_create_funcs = { 533 .read_dce_straps = read_dce_straps, 534 .create_audio = create_audio, 535 .create_stream_encoder = dce80_stream_encoder_create, 536 .create_hwseq = dce80_hwseq_create, 537 }; 538 539 #define mi_inst_regs(id) { \ 540 MI_DCE8_REG_LIST(id), \ 541 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 542 } 543 static const struct dce_mem_input_registers mi_regs[] = { 544 mi_inst_regs(0), 545 mi_inst_regs(1), 546 mi_inst_regs(2), 547 mi_inst_regs(3), 548 mi_inst_regs(4), 549 mi_inst_regs(5), 550 }; 551 552 static const struct dce_mem_input_shift mi_shifts = { 553 MI_DCE8_MASK_SH_LIST(__SHIFT), 554 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 555 }; 556 557 static const struct dce_mem_input_mask mi_masks = { 558 MI_DCE8_MASK_SH_LIST(_MASK), 559 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 560 }; 561 562 static struct mem_input *dce80_mem_input_create( 563 struct dc_context *ctx, 564 uint32_t inst) 565 { 566 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 567 GFP_KERNEL); 568 569 if (!dce_mi) { 570 BREAK_TO_DEBUGGER(); 571 return NULL; 572 } 573 574 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 575 dce_mi->wa.single_head_rdreq_dmif_limit = 2; 576 return &dce_mi->base; 577 } 578 579 static void dce80_transform_destroy(struct transform **xfm) 580 { 581 kfree(TO_DCE_TRANSFORM(*xfm)); 582 *xfm = NULL; 583 } 584 585 static struct transform *dce80_transform_create( 586 struct dc_context *ctx, 587 uint32_t inst) 588 { 589 struct dce_transform *transform = 590 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 591 592 if (!transform) 593 return NULL; 594 595 dce_transform_construct(transform, ctx, inst, 596 &xfm_regs[inst], &xfm_shift, &xfm_mask); 597 transform->prescaler_on = false; 598 return &transform->base; 599 } 600 601 static const struct encoder_feature_support link_enc_feature = { 602 .max_hdmi_deep_color = COLOR_DEPTH_121212, 603 .max_hdmi_pixel_clock = 297000, 604 .flags.bits.IS_HBR2_CAPABLE = true, 605 .flags.bits.IS_TPS3_CAPABLE = true, 606 .flags.bits.IS_YCBCR_CAPABLE = true 607 }; 608 609 struct link_encoder *dce80_link_encoder_create( 610 const struct encoder_init_data *enc_init_data) 611 { 612 struct dce110_link_encoder *enc110 = 613 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 614 615 if (!enc110) 616 return NULL; 617 618 dce110_link_encoder_construct(enc110, 619 enc_init_data, 620 &link_enc_feature, 621 &link_enc_regs[enc_init_data->transmitter], 622 &link_enc_aux_regs[enc_init_data->channel - 1], 623 &link_enc_hpd_regs[enc_init_data->hpd_source]); 624 return &enc110->base; 625 } 626 627 struct clock_source *dce80_clock_source_create( 628 struct dc_context *ctx, 629 struct dc_bios *bios, 630 enum clock_source_id id, 631 const struct dce110_clk_src_regs *regs, 632 bool dp_clk_src) 633 { 634 struct dce110_clk_src *clk_src = 635 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 636 637 if (!clk_src) 638 return NULL; 639 640 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 641 regs, &cs_shift, &cs_mask)) { 642 clk_src->base.dp_clk_src = dp_clk_src; 643 return &clk_src->base; 644 } 645 646 BREAK_TO_DEBUGGER(); 647 return NULL; 648 } 649 650 void dce80_clock_source_destroy(struct clock_source **clk_src) 651 { 652 kfree(TO_DCE110_CLK_SRC(*clk_src)); 653 *clk_src = NULL; 654 } 655 656 static struct input_pixel_processor *dce80_ipp_create( 657 struct dc_context *ctx, uint32_t inst) 658 { 659 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 660 661 if (!ipp) { 662 BREAK_TO_DEBUGGER(); 663 return NULL; 664 } 665 666 dce_ipp_construct(ipp, ctx, inst, 667 &ipp_regs[inst], &ipp_shift, &ipp_mask); 668 return &ipp->base; 669 } 670 671 static void destruct(struct dce110_resource_pool *pool) 672 { 673 unsigned int i; 674 675 for (i = 0; i < pool->base.pipe_count; i++) { 676 if (pool->base.opps[i] != NULL) 677 dce110_opp_destroy(&pool->base.opps[i]); 678 679 if (pool->base.transforms[i] != NULL) 680 dce80_transform_destroy(&pool->base.transforms[i]); 681 682 if (pool->base.ipps[i] != NULL) 683 dce_ipp_destroy(&pool->base.ipps[i]); 684 685 if (pool->base.mis[i] != NULL) { 686 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 687 pool->base.mis[i] = NULL; 688 } 689 690 if (pool->base.timing_generators[i] != NULL) { 691 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 692 pool->base.timing_generators[i] = NULL; 693 } 694 695 if (pool->base.engines[i] != NULL) 696 dce110_engine_destroy(&pool->base.engines[i]); 697 } 698 699 for (i = 0; i < pool->base.stream_enc_count; i++) { 700 if (pool->base.stream_enc[i] != NULL) 701 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 702 } 703 704 for (i = 0; i < pool->base.clk_src_count; i++) { 705 if (pool->base.clock_sources[i] != NULL) { 706 dce80_clock_source_destroy(&pool->base.clock_sources[i]); 707 } 708 } 709 710 if (pool->base.abm != NULL) 711 dce_abm_destroy(&pool->base.abm); 712 713 if (pool->base.dmcu != NULL) 714 dce_dmcu_destroy(&pool->base.dmcu); 715 716 if (pool->base.dp_clock_source != NULL) 717 dce80_clock_source_destroy(&pool->base.dp_clock_source); 718 719 for (i = 0; i < pool->base.audio_count; i++) { 720 if (pool->base.audios[i] != NULL) { 721 dce_aud_destroy(&pool->base.audios[i]); 722 } 723 } 724 725 if (pool->base.dccg != NULL) 726 dce_dccg_destroy(&pool->base.dccg); 727 728 if (pool->base.irqs != NULL) { 729 dal_irq_service_destroy(&pool->base.irqs); 730 } 731 } 732 733 bool dce80_validate_bandwidth( 734 struct dc *dc, 735 struct dc_state *context) 736 { 737 /* TODO implement when needed but for now hardcode max value*/ 738 context->bw.dce.dispclk_khz = 681000; 739 context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER; 740 741 return true; 742 } 743 744 static bool dce80_validate_surface_sets( 745 struct dc_state *context) 746 { 747 int i; 748 749 for (i = 0; i < context->stream_count; i++) { 750 if (context->stream_status[i].plane_count == 0) 751 continue; 752 753 if (context->stream_status[i].plane_count > 1) 754 return false; 755 756 if (context->stream_status[i].plane_states[0]->format 757 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 758 return false; 759 } 760 761 return true; 762 } 763 764 enum dc_status dce80_validate_global( 765 struct dc *dc, 766 struct dc_state *context) 767 { 768 if (!dce80_validate_surface_sets(context)) 769 return DC_FAIL_SURFACE_VALIDATE; 770 771 return DC_OK; 772 } 773 774 static void dce80_destroy_resource_pool(struct resource_pool **pool) 775 { 776 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 777 778 destruct(dce110_pool); 779 kfree(dce110_pool); 780 *pool = NULL; 781 } 782 783 static const struct resource_funcs dce80_res_pool_funcs = { 784 .destroy = dce80_destroy_resource_pool, 785 .link_enc_create = dce80_link_encoder_create, 786 .validate_bandwidth = dce80_validate_bandwidth, 787 .validate_plane = dce100_validate_plane, 788 .add_stream_to_ctx = dce100_add_stream_to_ctx, 789 .validate_global = dce80_validate_global 790 }; 791 792 static bool dce80_construct( 793 uint8_t num_virtual_links, 794 struct dc *dc, 795 struct dce110_resource_pool *pool) 796 { 797 unsigned int i; 798 struct dc_context *ctx = dc->ctx; 799 struct dc_firmware_info info; 800 struct dc_bios *bp; 801 struct dm_pp_static_clock_info static_clk_info = {0}; 802 803 ctx->dc_bios->regs = &bios_regs; 804 805 pool->base.res_cap = &res_cap; 806 pool->base.funcs = &dce80_res_pool_funcs; 807 808 809 /************************************************* 810 * Resource + asic cap harcoding * 811 *************************************************/ 812 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 813 pool->base.pipe_count = res_cap.num_timing_generator; 814 pool->base.timing_generator_count = res_cap.num_timing_generator; 815 dc->caps.max_downscale_ratio = 200; 816 dc->caps.i2c_speed_in_khz = 40; 817 dc->caps.max_cursor_size = 128; 818 dc->caps.dual_link_dvi = true; 819 820 /************************************************* 821 * Create resources * 822 *************************************************/ 823 824 bp = ctx->dc_bios; 825 826 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 827 info.external_clock_source_frequency_for_dp != 0) { 828 pool->base.dp_clock_source = 829 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 830 831 pool->base.clock_sources[0] = 832 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 833 pool->base.clock_sources[1] = 834 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 835 pool->base.clock_sources[2] = 836 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 837 pool->base.clk_src_count = 3; 838 839 } else { 840 pool->base.dp_clock_source = 841 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 842 843 pool->base.clock_sources[0] = 844 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 845 pool->base.clock_sources[1] = 846 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 847 pool->base.clk_src_count = 2; 848 } 849 850 if (pool->base.dp_clock_source == NULL) { 851 dm_error("DC: failed to create dp clock source!\n"); 852 BREAK_TO_DEBUGGER(); 853 goto res_create_fail; 854 } 855 856 for (i = 0; i < pool->base.clk_src_count; i++) { 857 if (pool->base.clock_sources[i] == NULL) { 858 dm_error("DC: failed to create clock sources!\n"); 859 BREAK_TO_DEBUGGER(); 860 goto res_create_fail; 861 } 862 } 863 864 pool->base.dccg = dce_dccg_create(ctx, 865 &disp_clk_regs, 866 &disp_clk_shift, 867 &disp_clk_mask); 868 if (pool->base.dccg == NULL) { 869 dm_error("DC: failed to create display clock!\n"); 870 BREAK_TO_DEBUGGER(); 871 goto res_create_fail; 872 } 873 874 pool->base.dmcu = dce_dmcu_create(ctx, 875 &dmcu_regs, 876 &dmcu_shift, 877 &dmcu_mask); 878 if (pool->base.dmcu == NULL) { 879 dm_error("DC: failed to create dmcu!\n"); 880 BREAK_TO_DEBUGGER(); 881 goto res_create_fail; 882 } 883 884 pool->base.abm = dce_abm_create(ctx, 885 &abm_regs, 886 &abm_shift, 887 &abm_mask); 888 if (pool->base.abm == NULL) { 889 dm_error("DC: failed to create abm!\n"); 890 BREAK_TO_DEBUGGER(); 891 goto res_create_fail; 892 } 893 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 894 pool->base.dccg->max_clks_state = 895 static_clk_info.max_clocks_state; 896 897 { 898 struct irq_service_init_data init_data; 899 init_data.ctx = dc->ctx; 900 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 901 if (!pool->base.irqs) 902 goto res_create_fail; 903 } 904 905 for (i = 0; i < pool->base.pipe_count; i++) { 906 pool->base.timing_generators[i] = dce80_timing_generator_create( 907 ctx, i, &dce80_tg_offsets[i]); 908 if (pool->base.timing_generators[i] == NULL) { 909 BREAK_TO_DEBUGGER(); 910 dm_error("DC: failed to create tg!\n"); 911 goto res_create_fail; 912 } 913 914 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 915 if (pool->base.mis[i] == NULL) { 916 BREAK_TO_DEBUGGER(); 917 dm_error("DC: failed to create memory input!\n"); 918 goto res_create_fail; 919 } 920 921 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 922 if (pool->base.ipps[i] == NULL) { 923 BREAK_TO_DEBUGGER(); 924 dm_error("DC: failed to create input pixel processor!\n"); 925 goto res_create_fail; 926 } 927 928 pool->base.transforms[i] = dce80_transform_create(ctx, i); 929 if (pool->base.transforms[i] == NULL) { 930 BREAK_TO_DEBUGGER(); 931 dm_error("DC: failed to create transform!\n"); 932 goto res_create_fail; 933 } 934 935 pool->base.opps[i] = dce80_opp_create(ctx, i); 936 if (pool->base.opps[i] == NULL) { 937 BREAK_TO_DEBUGGER(); 938 dm_error("DC: failed to create output pixel processor!\n"); 939 goto res_create_fail; 940 } 941 } 942 943 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 944 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 945 if (pool->base.engines[i] == NULL) { 946 BREAK_TO_DEBUGGER(); 947 dm_error( 948 "DC:failed to create aux engine!!\n"); 949 goto res_create_fail; 950 } 951 } 952 953 dc->caps.max_planes = pool->base.pipe_count; 954 dc->caps.disable_dp_clk_share = true; 955 956 if (!resource_construct(num_virtual_links, dc, &pool->base, 957 &res_create_funcs)) 958 goto res_create_fail; 959 960 /* Create hardware sequencer */ 961 dce80_hw_sequencer_construct(dc); 962 963 return true; 964 965 res_create_fail: 966 destruct(pool); 967 return false; 968 } 969 970 struct resource_pool *dce80_create_resource_pool( 971 uint8_t num_virtual_links, 972 struct dc *dc) 973 { 974 struct dce110_resource_pool *pool = 975 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 976 977 if (!pool) 978 return NULL; 979 980 if (dce80_construct(num_virtual_links, dc, pool)) 981 return &pool->base; 982 983 BREAK_TO_DEBUGGER(); 984 return NULL; 985 } 986 987 static bool dce81_construct( 988 uint8_t num_virtual_links, 989 struct dc *dc, 990 struct dce110_resource_pool *pool) 991 { 992 unsigned int i; 993 struct dc_context *ctx = dc->ctx; 994 struct dc_firmware_info info; 995 struct dc_bios *bp; 996 struct dm_pp_static_clock_info static_clk_info = {0}; 997 998 ctx->dc_bios->regs = &bios_regs; 999 1000 pool->base.res_cap = &res_cap_81; 1001 pool->base.funcs = &dce80_res_pool_funcs; 1002 1003 1004 /************************************************* 1005 * Resource + asic cap harcoding * 1006 *************************************************/ 1007 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1008 pool->base.pipe_count = res_cap_81.num_timing_generator; 1009 pool->base.timing_generator_count = res_cap_81.num_timing_generator; 1010 dc->caps.max_downscale_ratio = 200; 1011 dc->caps.i2c_speed_in_khz = 40; 1012 dc->caps.max_cursor_size = 128; 1013 dc->caps.is_apu = true; 1014 1015 /************************************************* 1016 * Create resources * 1017 *************************************************/ 1018 1019 bp = ctx->dc_bios; 1020 1021 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 1022 info.external_clock_source_frequency_for_dp != 0) { 1023 pool->base.dp_clock_source = 1024 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1025 1026 pool->base.clock_sources[0] = 1027 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 1028 pool->base.clock_sources[1] = 1029 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1030 pool->base.clock_sources[2] = 1031 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1032 pool->base.clk_src_count = 3; 1033 1034 } else { 1035 pool->base.dp_clock_source = 1036 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 1037 1038 pool->base.clock_sources[0] = 1039 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1040 pool->base.clock_sources[1] = 1041 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1042 pool->base.clk_src_count = 2; 1043 } 1044 1045 if (pool->base.dp_clock_source == NULL) { 1046 dm_error("DC: failed to create dp clock source!\n"); 1047 BREAK_TO_DEBUGGER(); 1048 goto res_create_fail; 1049 } 1050 1051 for (i = 0; i < pool->base.clk_src_count; i++) { 1052 if (pool->base.clock_sources[i] == NULL) { 1053 dm_error("DC: failed to create clock sources!\n"); 1054 BREAK_TO_DEBUGGER(); 1055 goto res_create_fail; 1056 } 1057 } 1058 1059 pool->base.dccg = dce_dccg_create(ctx, 1060 &disp_clk_regs, 1061 &disp_clk_shift, 1062 &disp_clk_mask); 1063 if (pool->base.dccg == NULL) { 1064 dm_error("DC: failed to create display clock!\n"); 1065 BREAK_TO_DEBUGGER(); 1066 goto res_create_fail; 1067 } 1068 1069 pool->base.dmcu = dce_dmcu_create(ctx, 1070 &dmcu_regs, 1071 &dmcu_shift, 1072 &dmcu_mask); 1073 if (pool->base.dmcu == NULL) { 1074 dm_error("DC: failed to create dmcu!\n"); 1075 BREAK_TO_DEBUGGER(); 1076 goto res_create_fail; 1077 } 1078 1079 pool->base.abm = dce_abm_create(ctx, 1080 &abm_regs, 1081 &abm_shift, 1082 &abm_mask); 1083 if (pool->base.abm == NULL) { 1084 dm_error("DC: failed to create abm!\n"); 1085 BREAK_TO_DEBUGGER(); 1086 goto res_create_fail; 1087 } 1088 1089 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 1090 pool->base.dccg->max_clks_state = 1091 static_clk_info.max_clocks_state; 1092 1093 { 1094 struct irq_service_init_data init_data; 1095 init_data.ctx = dc->ctx; 1096 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1097 if (!pool->base.irqs) 1098 goto res_create_fail; 1099 } 1100 1101 for (i = 0; i < pool->base.pipe_count; i++) { 1102 pool->base.timing_generators[i] = dce80_timing_generator_create( 1103 ctx, i, &dce80_tg_offsets[i]); 1104 if (pool->base.timing_generators[i] == NULL) { 1105 BREAK_TO_DEBUGGER(); 1106 dm_error("DC: failed to create tg!\n"); 1107 goto res_create_fail; 1108 } 1109 1110 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1111 if (pool->base.mis[i] == NULL) { 1112 BREAK_TO_DEBUGGER(); 1113 dm_error("DC: failed to create memory input!\n"); 1114 goto res_create_fail; 1115 } 1116 1117 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1118 if (pool->base.ipps[i] == NULL) { 1119 BREAK_TO_DEBUGGER(); 1120 dm_error("DC: failed to create input pixel processor!\n"); 1121 goto res_create_fail; 1122 } 1123 1124 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1125 if (pool->base.transforms[i] == NULL) { 1126 BREAK_TO_DEBUGGER(); 1127 dm_error("DC: failed to create transform!\n"); 1128 goto res_create_fail; 1129 } 1130 1131 pool->base.opps[i] = dce80_opp_create(ctx, i); 1132 if (pool->base.opps[i] == NULL) { 1133 BREAK_TO_DEBUGGER(); 1134 dm_error("DC: failed to create output pixel processor!\n"); 1135 goto res_create_fail; 1136 } 1137 } 1138 1139 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1140 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1141 if (pool->base.engines[i] == NULL) { 1142 BREAK_TO_DEBUGGER(); 1143 dm_error( 1144 "DC:failed to create aux engine!!\n"); 1145 goto res_create_fail; 1146 } 1147 } 1148 1149 dc->caps.max_planes = pool->base.pipe_count; 1150 dc->caps.disable_dp_clk_share = true; 1151 1152 if (!resource_construct(num_virtual_links, dc, &pool->base, 1153 &res_create_funcs)) 1154 goto res_create_fail; 1155 1156 /* Create hardware sequencer */ 1157 dce80_hw_sequencer_construct(dc); 1158 1159 return true; 1160 1161 res_create_fail: 1162 destruct(pool); 1163 return false; 1164 } 1165 1166 struct resource_pool *dce81_create_resource_pool( 1167 uint8_t num_virtual_links, 1168 struct dc *dc) 1169 { 1170 struct dce110_resource_pool *pool = 1171 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1172 1173 if (!pool) 1174 return NULL; 1175 1176 if (dce81_construct(num_virtual_links, dc, pool)) 1177 return &pool->base; 1178 1179 BREAK_TO_DEBUGGER(); 1180 return NULL; 1181 } 1182 1183 static bool dce83_construct( 1184 uint8_t num_virtual_links, 1185 struct dc *dc, 1186 struct dce110_resource_pool *pool) 1187 { 1188 unsigned int i; 1189 struct dc_context *ctx = dc->ctx; 1190 struct dc_firmware_info info; 1191 struct dc_bios *bp; 1192 struct dm_pp_static_clock_info static_clk_info = {0}; 1193 1194 ctx->dc_bios->regs = &bios_regs; 1195 1196 pool->base.res_cap = &res_cap_83; 1197 pool->base.funcs = &dce80_res_pool_funcs; 1198 1199 1200 /************************************************* 1201 * Resource + asic cap harcoding * 1202 *************************************************/ 1203 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1204 pool->base.pipe_count = res_cap_83.num_timing_generator; 1205 pool->base.timing_generator_count = res_cap_83.num_timing_generator; 1206 dc->caps.max_downscale_ratio = 200; 1207 dc->caps.i2c_speed_in_khz = 40; 1208 dc->caps.max_cursor_size = 128; 1209 dc->caps.is_apu = true; 1210 1211 /************************************************* 1212 * Create resources * 1213 *************************************************/ 1214 1215 bp = ctx->dc_bios; 1216 1217 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 1218 info.external_clock_source_frequency_for_dp != 0) { 1219 pool->base.dp_clock_source = 1220 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1221 1222 pool->base.clock_sources[0] = 1223 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false); 1224 pool->base.clock_sources[1] = 1225 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1226 pool->base.clk_src_count = 2; 1227 1228 } else { 1229 pool->base.dp_clock_source = 1230 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true); 1231 1232 pool->base.clock_sources[0] = 1233 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1234 pool->base.clk_src_count = 1; 1235 } 1236 1237 if (pool->base.dp_clock_source == NULL) { 1238 dm_error("DC: failed to create dp clock source!\n"); 1239 BREAK_TO_DEBUGGER(); 1240 goto res_create_fail; 1241 } 1242 1243 for (i = 0; i < pool->base.clk_src_count; i++) { 1244 if (pool->base.clock_sources[i] == NULL) { 1245 dm_error("DC: failed to create clock sources!\n"); 1246 BREAK_TO_DEBUGGER(); 1247 goto res_create_fail; 1248 } 1249 } 1250 1251 pool->base.dccg = dce_dccg_create(ctx, 1252 &disp_clk_regs, 1253 &disp_clk_shift, 1254 &disp_clk_mask); 1255 if (pool->base.dccg == NULL) { 1256 dm_error("DC: failed to create display clock!\n"); 1257 BREAK_TO_DEBUGGER(); 1258 goto res_create_fail; 1259 } 1260 1261 pool->base.dmcu = dce_dmcu_create(ctx, 1262 &dmcu_regs, 1263 &dmcu_shift, 1264 &dmcu_mask); 1265 if (pool->base.dmcu == NULL) { 1266 dm_error("DC: failed to create dmcu!\n"); 1267 BREAK_TO_DEBUGGER(); 1268 goto res_create_fail; 1269 } 1270 1271 pool->base.abm = dce_abm_create(ctx, 1272 &abm_regs, 1273 &abm_shift, 1274 &abm_mask); 1275 if (pool->base.abm == NULL) { 1276 dm_error("DC: failed to create abm!\n"); 1277 BREAK_TO_DEBUGGER(); 1278 goto res_create_fail; 1279 } 1280 1281 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 1282 pool->base.dccg->max_clks_state = 1283 static_clk_info.max_clocks_state; 1284 1285 { 1286 struct irq_service_init_data init_data; 1287 init_data.ctx = dc->ctx; 1288 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1289 if (!pool->base.irqs) 1290 goto res_create_fail; 1291 } 1292 1293 for (i = 0; i < pool->base.pipe_count; i++) { 1294 pool->base.timing_generators[i] = dce80_timing_generator_create( 1295 ctx, i, &dce80_tg_offsets[i]); 1296 if (pool->base.timing_generators[i] == NULL) { 1297 BREAK_TO_DEBUGGER(); 1298 dm_error("DC: failed to create tg!\n"); 1299 goto res_create_fail; 1300 } 1301 1302 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1303 if (pool->base.mis[i] == NULL) { 1304 BREAK_TO_DEBUGGER(); 1305 dm_error("DC: failed to create memory input!\n"); 1306 goto res_create_fail; 1307 } 1308 1309 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1310 if (pool->base.ipps[i] == NULL) { 1311 BREAK_TO_DEBUGGER(); 1312 dm_error("DC: failed to create input pixel processor!\n"); 1313 goto res_create_fail; 1314 } 1315 1316 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1317 if (pool->base.transforms[i] == NULL) { 1318 BREAK_TO_DEBUGGER(); 1319 dm_error("DC: failed to create transform!\n"); 1320 goto res_create_fail; 1321 } 1322 1323 pool->base.opps[i] = dce80_opp_create(ctx, i); 1324 if (pool->base.opps[i] == NULL) { 1325 BREAK_TO_DEBUGGER(); 1326 dm_error("DC: failed to create output pixel processor!\n"); 1327 goto res_create_fail; 1328 } 1329 } 1330 1331 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1332 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1333 if (pool->base.engines[i] == NULL) { 1334 BREAK_TO_DEBUGGER(); 1335 dm_error( 1336 "DC:failed to create aux engine!!\n"); 1337 goto res_create_fail; 1338 } 1339 } 1340 1341 dc->caps.max_planes = pool->base.pipe_count; 1342 dc->caps.disable_dp_clk_share = true; 1343 1344 if (!resource_construct(num_virtual_links, dc, &pool->base, 1345 &res_create_funcs)) 1346 goto res_create_fail; 1347 1348 /* Create hardware sequencer */ 1349 dce80_hw_sequencer_construct(dc); 1350 1351 return true; 1352 1353 res_create_fail: 1354 destruct(pool); 1355 return false; 1356 } 1357 1358 struct resource_pool *dce83_create_resource_pool( 1359 uint8_t num_virtual_links, 1360 struct dc *dc) 1361 { 1362 struct dce110_resource_pool *pool = 1363 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1364 1365 if (!pool) 1366 return NULL; 1367 1368 if (dce83_construct(num_virtual_links, dc, pool)) 1369 return &pool->base; 1370 1371 BREAK_TO_DEBUGGER(); 1372 return NULL; 1373 } 1374