1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "link_encoder.h" 29 #include "stream_encoder.h" 30 31 #include "resource.h" 32 #include "include/irq_service_interface.h" 33 #include "dce110/dce110_resource.h" 34 #include "dce110/dce110_timing_generator.h" 35 36 #include "irq/dce110/irq_service_dce110.h" 37 38 #include "dce/dce_mem_input.h" 39 #include "dce/dce_transform.h" 40 #include "dce/dce_link_encoder.h" 41 #include "dce/dce_stream_encoder.h" 42 #include "dce/dce_audio.h" 43 #include "dce/dce_opp.h" 44 #include "dce/dce_ipp.h" 45 #include "dce/dce_clocks.h" 46 #include "dce/dce_clock_source.h" 47 48 #include "dce/dce_hwseq.h" 49 #include "dce112/dce112_hw_sequencer.h" 50 #include "dce/dce_abm.h" 51 #include "dce/dce_dmcu.h" 52 #include "dce/dce_aux.h" 53 54 #include "reg_helper.h" 55 56 #include "dce/dce_11_2_d.h" 57 #include "dce/dce_11_2_sh_mask.h" 58 59 #include "dce100/dce100_resource.h" 60 #define DC_LOGGER \ 61 dc->ctx->logger 62 63 #ifndef mmDP_DPHY_INTERNAL_CTRL 64 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 65 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 66 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 67 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 68 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 69 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 70 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 71 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 72 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 73 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 74 #endif 75 76 #ifndef mmBIOS_SCRATCH_2 77 #define mmBIOS_SCRATCH_2 0x05CB 78 #define mmBIOS_SCRATCH_6 0x05CF 79 #endif 80 81 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 82 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 83 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 84 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 85 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 86 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 87 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 88 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 89 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 90 #endif 91 92 #ifndef mmDP_DPHY_FAST_TRAINING 93 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 94 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 95 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 96 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 97 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 98 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 99 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 100 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 101 #endif 102 103 enum dce112_clk_src_array_id { 104 DCE112_CLK_SRC_PLL0, 105 DCE112_CLK_SRC_PLL1, 106 DCE112_CLK_SRC_PLL2, 107 DCE112_CLK_SRC_PLL3, 108 DCE112_CLK_SRC_PLL4, 109 DCE112_CLK_SRC_PLL5, 110 111 DCE112_CLK_SRC_TOTAL 112 }; 113 114 static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = { 115 { 116 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 117 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 118 }, 119 { 120 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 121 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 122 }, 123 { 124 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 125 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 126 }, 127 { 128 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 129 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 130 }, 131 { 132 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 133 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 134 }, 135 { 136 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 137 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 138 } 139 }; 140 141 /* set register offset */ 142 #define SR(reg_name)\ 143 .reg_name = mm ## reg_name 144 145 /* set register offset with instance */ 146 #define SRI(reg_name, block, id)\ 147 .reg_name = mm ## block ## id ## _ ## reg_name 148 149 150 static const struct dccg_registers disp_clk_regs = { 151 CLK_COMMON_REG_LIST_DCE_BASE() 152 }; 153 154 static const struct dccg_shift disp_clk_shift = { 155 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 156 }; 157 158 static const struct dccg_mask disp_clk_mask = { 159 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 160 }; 161 162 static const struct dce_dmcu_registers dmcu_regs = { 163 DMCU_DCE110_COMMON_REG_LIST() 164 }; 165 166 static const struct dce_dmcu_shift dmcu_shift = { 167 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 168 }; 169 170 static const struct dce_dmcu_mask dmcu_mask = { 171 DMCU_MASK_SH_LIST_DCE110(_MASK) 172 }; 173 174 static const struct dce_abm_registers abm_regs = { 175 ABM_DCE110_COMMON_REG_LIST() 176 }; 177 178 static const struct dce_abm_shift abm_shift = { 179 ABM_MASK_SH_LIST_DCE110(__SHIFT) 180 }; 181 182 static const struct dce_abm_mask abm_mask = { 183 ABM_MASK_SH_LIST_DCE110(_MASK) 184 }; 185 186 #define ipp_regs(id)\ 187 [id] = {\ 188 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 189 } 190 191 static const struct dce_ipp_registers ipp_regs[] = { 192 ipp_regs(0), 193 ipp_regs(1), 194 ipp_regs(2), 195 ipp_regs(3), 196 ipp_regs(4), 197 ipp_regs(5) 198 }; 199 200 static const struct dce_ipp_shift ipp_shift = { 201 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 202 }; 203 204 static const struct dce_ipp_mask ipp_mask = { 205 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 206 }; 207 208 #define transform_regs(id)\ 209 [id] = {\ 210 XFM_COMMON_REG_LIST_DCE110(id)\ 211 } 212 213 static const struct dce_transform_registers xfm_regs[] = { 214 transform_regs(0), 215 transform_regs(1), 216 transform_regs(2), 217 transform_regs(3), 218 transform_regs(4), 219 transform_regs(5) 220 }; 221 222 static const struct dce_transform_shift xfm_shift = { 223 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 224 }; 225 226 static const struct dce_transform_mask xfm_mask = { 227 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 228 }; 229 230 #define aux_regs(id)\ 231 [id] = {\ 232 AUX_REG_LIST(id)\ 233 } 234 235 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 236 aux_regs(0), 237 aux_regs(1), 238 aux_regs(2), 239 aux_regs(3), 240 aux_regs(4), 241 aux_regs(5) 242 }; 243 244 #define hpd_regs(id)\ 245 [id] = {\ 246 HPD_REG_LIST(id)\ 247 } 248 249 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 250 hpd_regs(0), 251 hpd_regs(1), 252 hpd_regs(2), 253 hpd_regs(3), 254 hpd_regs(4), 255 hpd_regs(5) 256 }; 257 258 #define link_regs(id)\ 259 [id] = {\ 260 LE_DCE110_REG_LIST(id)\ 261 } 262 263 static const struct dce110_link_enc_registers link_enc_regs[] = { 264 link_regs(0), 265 link_regs(1), 266 link_regs(2), 267 link_regs(3), 268 link_regs(4), 269 link_regs(5), 270 link_regs(6), 271 }; 272 273 #define stream_enc_regs(id)\ 274 [id] = {\ 275 SE_COMMON_REG_LIST(id),\ 276 .TMDS_CNTL = 0,\ 277 } 278 279 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 280 stream_enc_regs(0), 281 stream_enc_regs(1), 282 stream_enc_regs(2), 283 stream_enc_regs(3), 284 stream_enc_regs(4), 285 stream_enc_regs(5) 286 }; 287 288 static const struct dce_stream_encoder_shift se_shift = { 289 SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT) 290 }; 291 292 static const struct dce_stream_encoder_mask se_mask = { 293 SE_COMMON_MASK_SH_LIST_DCE112(_MASK) 294 }; 295 296 #define opp_regs(id)\ 297 [id] = {\ 298 OPP_DCE_112_REG_LIST(id),\ 299 } 300 301 static const struct dce_opp_registers opp_regs[] = { 302 opp_regs(0), 303 opp_regs(1), 304 opp_regs(2), 305 opp_regs(3), 306 opp_regs(4), 307 opp_regs(5) 308 }; 309 310 static const struct dce_opp_shift opp_shift = { 311 OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 312 }; 313 314 static const struct dce_opp_mask opp_mask = { 315 OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK) 316 }; 317 318 #define aux_engine_regs(id)\ 319 [id] = {\ 320 AUX_COMMON_REG_LIST(id), \ 321 .AUX_RESET_MASK = 0 \ 322 } 323 324 static const struct dce110_aux_registers aux_engine_regs[] = { 325 aux_engine_regs(0), 326 aux_engine_regs(1), 327 aux_engine_regs(2), 328 aux_engine_regs(3), 329 aux_engine_regs(4), 330 aux_engine_regs(5) 331 }; 332 333 #define audio_regs(id)\ 334 [id] = {\ 335 AUD_COMMON_REG_LIST(id)\ 336 } 337 338 static const struct dce_audio_registers audio_regs[] = { 339 audio_regs(0), 340 audio_regs(1), 341 audio_regs(2), 342 audio_regs(3), 343 audio_regs(4), 344 audio_regs(5) 345 }; 346 347 static const struct dce_audio_shift audio_shift = { 348 AUD_COMMON_MASK_SH_LIST(__SHIFT) 349 }; 350 351 static const struct dce_aduio_mask audio_mask = { 352 AUD_COMMON_MASK_SH_LIST(_MASK) 353 }; 354 355 #define clk_src_regs(index, id)\ 356 [index] = {\ 357 CS_COMMON_REG_LIST_DCE_112(id),\ 358 } 359 360 static const struct dce110_clk_src_regs clk_src_regs[] = { 361 clk_src_regs(0, A), 362 clk_src_regs(1, B), 363 clk_src_regs(2, C), 364 clk_src_regs(3, D), 365 clk_src_regs(4, E), 366 clk_src_regs(5, F) 367 }; 368 369 static const struct dce110_clk_src_shift cs_shift = { 370 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 371 }; 372 373 static const struct dce110_clk_src_mask cs_mask = { 374 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) 375 }; 376 377 static const struct bios_registers bios_regs = { 378 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 379 }; 380 381 static const struct resource_caps polaris_10_resource_cap = { 382 .num_timing_generator = 6, 383 .num_audio = 6, 384 .num_stream_encoder = 6, 385 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */ 386 .num_ddc = 6, 387 }; 388 389 static const struct resource_caps polaris_11_resource_cap = { 390 .num_timing_generator = 5, 391 .num_audio = 5, 392 .num_stream_encoder = 5, 393 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */ 394 .num_ddc = 5, 395 }; 396 397 #define CTX ctx 398 #define REG(reg) mm ## reg 399 400 #ifndef mmCC_DC_HDMI_STRAPS 401 #define mmCC_DC_HDMI_STRAPS 0x4819 402 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 403 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 404 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 405 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 406 #endif 407 408 static void read_dce_straps( 409 struct dc_context *ctx, 410 struct resource_straps *straps) 411 { 412 REG_GET_2(CC_DC_HDMI_STRAPS, 413 HDMI_DISABLE, &straps->hdmi_disable, 414 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 415 416 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 417 } 418 419 static struct audio *create_audio( 420 struct dc_context *ctx, unsigned int inst) 421 { 422 return dce_audio_create(ctx, inst, 423 &audio_regs[inst], &audio_shift, &audio_mask); 424 } 425 426 427 static struct timing_generator *dce112_timing_generator_create( 428 struct dc_context *ctx, 429 uint32_t instance, 430 const struct dce110_timing_generator_offsets *offsets) 431 { 432 struct dce110_timing_generator *tg110 = 433 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 434 435 if (!tg110) 436 return NULL; 437 438 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 439 return &tg110->base; 440 } 441 442 static struct stream_encoder *dce112_stream_encoder_create( 443 enum engine_id eng_id, 444 struct dc_context *ctx) 445 { 446 struct dce110_stream_encoder *enc110 = 447 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 448 449 if (!enc110) 450 return NULL; 451 452 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 453 &stream_enc_regs[eng_id], 454 &se_shift, &se_mask); 455 return &enc110->base; 456 } 457 458 #define SRII(reg_name, block, id)\ 459 .reg_name[id] = mm ## block ## id ## _ ## reg_name 460 461 static const struct dce_hwseq_registers hwseq_reg = { 462 HWSEQ_DCE112_REG_LIST() 463 }; 464 465 static const struct dce_hwseq_shift hwseq_shift = { 466 HWSEQ_DCE112_MASK_SH_LIST(__SHIFT) 467 }; 468 469 static const struct dce_hwseq_mask hwseq_mask = { 470 HWSEQ_DCE112_MASK_SH_LIST(_MASK) 471 }; 472 473 static struct dce_hwseq *dce112_hwseq_create( 474 struct dc_context *ctx) 475 { 476 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 477 478 if (hws) { 479 hws->ctx = ctx; 480 hws->regs = &hwseq_reg; 481 hws->shifts = &hwseq_shift; 482 hws->masks = &hwseq_mask; 483 } 484 return hws; 485 } 486 487 static const struct resource_create_funcs res_create_funcs = { 488 .read_dce_straps = read_dce_straps, 489 .create_audio = create_audio, 490 .create_stream_encoder = dce112_stream_encoder_create, 491 .create_hwseq = dce112_hwseq_create, 492 }; 493 494 #define mi_inst_regs(id) { MI_DCE11_2_REG_LIST(id) } 495 static const struct dce_mem_input_registers mi_regs[] = { 496 mi_inst_regs(0), 497 mi_inst_regs(1), 498 mi_inst_regs(2), 499 mi_inst_regs(3), 500 mi_inst_regs(4), 501 mi_inst_regs(5), 502 }; 503 504 static const struct dce_mem_input_shift mi_shifts = { 505 MI_DCE11_2_MASK_SH_LIST(__SHIFT) 506 }; 507 508 static const struct dce_mem_input_mask mi_masks = { 509 MI_DCE11_2_MASK_SH_LIST(_MASK) 510 }; 511 512 static struct mem_input *dce112_mem_input_create( 513 struct dc_context *ctx, 514 uint32_t inst) 515 { 516 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 517 GFP_KERNEL); 518 519 if (!dce_mi) { 520 BREAK_TO_DEBUGGER(); 521 return NULL; 522 } 523 524 dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 525 return &dce_mi->base; 526 } 527 528 static void dce112_transform_destroy(struct transform **xfm) 529 { 530 kfree(TO_DCE_TRANSFORM(*xfm)); 531 *xfm = NULL; 532 } 533 534 static struct transform *dce112_transform_create( 535 struct dc_context *ctx, 536 uint32_t inst) 537 { 538 struct dce_transform *transform = 539 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 540 541 if (!transform) 542 return NULL; 543 544 dce_transform_construct(transform, ctx, inst, 545 &xfm_regs[inst], &xfm_shift, &xfm_mask); 546 transform->lb_memory_size = 0x1404; /*5124*/ 547 return &transform->base; 548 } 549 550 static const struct encoder_feature_support link_enc_feature = { 551 .max_hdmi_deep_color = COLOR_DEPTH_121212, 552 .max_hdmi_pixel_clock = 600000, 553 .ycbcr420_supported = true, 554 .flags.bits.IS_HBR2_CAPABLE = true, 555 .flags.bits.IS_HBR3_CAPABLE = true, 556 .flags.bits.IS_TPS3_CAPABLE = true, 557 .flags.bits.IS_TPS4_CAPABLE = true, 558 .flags.bits.IS_YCBCR_CAPABLE = true 559 }; 560 561 struct link_encoder *dce112_link_encoder_create( 562 const struct encoder_init_data *enc_init_data) 563 { 564 struct dce110_link_encoder *enc110 = 565 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 566 567 if (!enc110) 568 return NULL; 569 570 dce110_link_encoder_construct(enc110, 571 enc_init_data, 572 &link_enc_feature, 573 &link_enc_regs[enc_init_data->transmitter], 574 &link_enc_aux_regs[enc_init_data->channel - 1], 575 &link_enc_hpd_regs[enc_init_data->hpd_source]); 576 return &enc110->base; 577 } 578 579 static struct input_pixel_processor *dce112_ipp_create( 580 struct dc_context *ctx, uint32_t inst) 581 { 582 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 583 584 if (!ipp) { 585 BREAK_TO_DEBUGGER(); 586 return NULL; 587 } 588 589 dce_ipp_construct(ipp, ctx, inst, 590 &ipp_regs[inst], &ipp_shift, &ipp_mask); 591 return &ipp->base; 592 } 593 594 struct output_pixel_processor *dce112_opp_create( 595 struct dc_context *ctx, 596 uint32_t inst) 597 { 598 struct dce110_opp *opp = 599 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 600 601 if (!opp) 602 return NULL; 603 604 dce110_opp_construct(opp, 605 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 606 return &opp->base; 607 } 608 609 struct aux_engine *dce112_aux_engine_create( 610 struct dc_context *ctx, 611 uint32_t inst) 612 { 613 struct aux_engine_dce110 *aux_engine = 614 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 615 616 if (!aux_engine) 617 return NULL; 618 619 dce110_aux_engine_construct(aux_engine, ctx, inst, 620 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 621 &aux_engine_regs[inst]); 622 623 return &aux_engine->base; 624 } 625 626 struct clock_source *dce112_clock_source_create( 627 struct dc_context *ctx, 628 struct dc_bios *bios, 629 enum clock_source_id id, 630 const struct dce110_clk_src_regs *regs, 631 bool dp_clk_src) 632 { 633 struct dce110_clk_src *clk_src = 634 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 635 636 if (!clk_src) 637 return NULL; 638 639 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 640 regs, &cs_shift, &cs_mask)) { 641 clk_src->base.dp_clk_src = dp_clk_src; 642 return &clk_src->base; 643 } 644 645 BREAK_TO_DEBUGGER(); 646 return NULL; 647 } 648 649 void dce112_clock_source_destroy(struct clock_source **clk_src) 650 { 651 kfree(TO_DCE110_CLK_SRC(*clk_src)); 652 *clk_src = NULL; 653 } 654 655 static void destruct(struct dce110_resource_pool *pool) 656 { 657 unsigned int i; 658 659 for (i = 0; i < pool->base.pipe_count; i++) { 660 if (pool->base.opps[i] != NULL) 661 dce110_opp_destroy(&pool->base.opps[i]); 662 663 if (pool->base.engines[i] != NULL) 664 dce110_engine_destroy(&pool->base.engines[i]); 665 666 if (pool->base.transforms[i] != NULL) 667 dce112_transform_destroy(&pool->base.transforms[i]); 668 669 if (pool->base.ipps[i] != NULL) 670 dce_ipp_destroy(&pool->base.ipps[i]); 671 672 if (pool->base.mis[i] != NULL) { 673 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 674 pool->base.mis[i] = NULL; 675 } 676 677 if (pool->base.timing_generators[i] != NULL) { 678 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 679 pool->base.timing_generators[i] = NULL; 680 } 681 682 } 683 684 for (i = 0; i < pool->base.stream_enc_count; i++) { 685 if (pool->base.stream_enc[i] != NULL) 686 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 687 } 688 689 for (i = 0; i < pool->base.clk_src_count; i++) { 690 if (pool->base.clock_sources[i] != NULL) { 691 dce112_clock_source_destroy(&pool->base.clock_sources[i]); 692 } 693 } 694 695 if (pool->base.dp_clock_source != NULL) 696 dce112_clock_source_destroy(&pool->base.dp_clock_source); 697 698 for (i = 0; i < pool->base.audio_count; i++) { 699 if (pool->base.audios[i] != NULL) { 700 dce_aud_destroy(&pool->base.audios[i]); 701 } 702 } 703 704 if (pool->base.abm != NULL) 705 dce_abm_destroy(&pool->base.abm); 706 707 if (pool->base.dmcu != NULL) 708 dce_dmcu_destroy(&pool->base.dmcu); 709 710 if (pool->base.dccg != NULL) 711 dce_dccg_destroy(&pool->base.dccg); 712 713 if (pool->base.irqs != NULL) { 714 dal_irq_service_destroy(&pool->base.irqs); 715 } 716 } 717 718 static struct clock_source *find_matching_pll( 719 struct resource_context *res_ctx, 720 const struct resource_pool *pool, 721 const struct dc_stream_state *const stream) 722 { 723 switch (stream->sink->link->link_enc->transmitter) { 724 case TRANSMITTER_UNIPHY_A: 725 return pool->clock_sources[DCE112_CLK_SRC_PLL0]; 726 case TRANSMITTER_UNIPHY_B: 727 return pool->clock_sources[DCE112_CLK_SRC_PLL1]; 728 case TRANSMITTER_UNIPHY_C: 729 return pool->clock_sources[DCE112_CLK_SRC_PLL2]; 730 case TRANSMITTER_UNIPHY_D: 731 return pool->clock_sources[DCE112_CLK_SRC_PLL3]; 732 case TRANSMITTER_UNIPHY_E: 733 return pool->clock_sources[DCE112_CLK_SRC_PLL4]; 734 case TRANSMITTER_UNIPHY_F: 735 return pool->clock_sources[DCE112_CLK_SRC_PLL5]; 736 default: 737 return NULL; 738 }; 739 740 return 0; 741 } 742 743 static enum dc_status build_mapped_resource( 744 const struct dc *dc, 745 struct dc_state *context, 746 struct dc_stream_state *stream) 747 { 748 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 749 750 if (!pipe_ctx) 751 return DC_ERROR_UNEXPECTED; 752 753 dce110_resource_build_pipe_hw_param(pipe_ctx); 754 755 resource_build_info_frame(pipe_ctx); 756 757 return DC_OK; 758 } 759 760 bool dce112_validate_bandwidth( 761 struct dc *dc, 762 struct dc_state *context) 763 { 764 bool result = false; 765 766 DC_LOG_BANDWIDTH_CALCS( 767 "%s: start", 768 __func__); 769 770 if (bw_calcs( 771 dc->ctx, 772 dc->bw_dceip, 773 dc->bw_vbios, 774 context->res_ctx.pipe_ctx, 775 dc->res_pool->pipe_count, 776 &context->bw.dce)) 777 result = true; 778 779 if (!result) 780 DC_LOG_BANDWIDTH_VALIDATION( 781 "%s: Bandwidth validation failed!", 782 __func__); 783 784 if (memcmp(&dc->current_state->bw.dce, 785 &context->bw.dce, sizeof(context->bw.dce))) { 786 787 DC_LOG_BANDWIDTH_CALCS( 788 "%s: finish,\n" 789 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 790 "stutMark_b: %d stutMark_a: %d\n" 791 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 792 "stutMark_b: %d stutMark_a: %d\n" 793 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 794 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n" 795 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n" 796 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n" 797 , 798 __func__, 799 context->bw.dce.nbp_state_change_wm_ns[0].b_mark, 800 context->bw.dce.nbp_state_change_wm_ns[0].a_mark, 801 context->bw.dce.urgent_wm_ns[0].b_mark, 802 context->bw.dce.urgent_wm_ns[0].a_mark, 803 context->bw.dce.stutter_exit_wm_ns[0].b_mark, 804 context->bw.dce.stutter_exit_wm_ns[0].a_mark, 805 context->bw.dce.nbp_state_change_wm_ns[1].b_mark, 806 context->bw.dce.nbp_state_change_wm_ns[1].a_mark, 807 context->bw.dce.urgent_wm_ns[1].b_mark, 808 context->bw.dce.urgent_wm_ns[1].a_mark, 809 context->bw.dce.stutter_exit_wm_ns[1].b_mark, 810 context->bw.dce.stutter_exit_wm_ns[1].a_mark, 811 context->bw.dce.nbp_state_change_wm_ns[2].b_mark, 812 context->bw.dce.nbp_state_change_wm_ns[2].a_mark, 813 context->bw.dce.urgent_wm_ns[2].b_mark, 814 context->bw.dce.urgent_wm_ns[2].a_mark, 815 context->bw.dce.stutter_exit_wm_ns[2].b_mark, 816 context->bw.dce.stutter_exit_wm_ns[2].a_mark, 817 context->bw.dce.stutter_mode_enable, 818 context->bw.dce.cpuc_state_change_enable, 819 context->bw.dce.cpup_state_change_enable, 820 context->bw.dce.nbp_state_change_enable, 821 context->bw.dce.all_displays_in_sync, 822 context->bw.dce.dispclk_khz, 823 context->bw.dce.sclk_khz, 824 context->bw.dce.sclk_deep_sleep_khz, 825 context->bw.dce.yclk_khz, 826 context->bw.dce.blackout_recovery_time_us); 827 } 828 return result; 829 } 830 831 enum dc_status resource_map_phy_clock_resources( 832 const struct dc *dc, 833 struct dc_state *context, 834 struct dc_stream_state *stream) 835 { 836 837 /* acquire new resources */ 838 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream( 839 &context->res_ctx, stream); 840 841 if (!pipe_ctx) 842 return DC_ERROR_UNEXPECTED; 843 844 if (dc_is_dp_signal(pipe_ctx->stream->signal) 845 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) 846 pipe_ctx->clock_source = 847 dc->res_pool->dp_clock_source; 848 else 849 pipe_ctx->clock_source = find_matching_pll( 850 &context->res_ctx, dc->res_pool, 851 stream); 852 853 if (pipe_ctx->clock_source == NULL) 854 return DC_NO_CLOCK_SOURCE_RESOURCE; 855 856 resource_reference_clock_source( 857 &context->res_ctx, 858 dc->res_pool, 859 pipe_ctx->clock_source); 860 861 return DC_OK; 862 } 863 864 static bool dce112_validate_surface_sets( 865 struct dc_state *context) 866 { 867 int i; 868 869 for (i = 0; i < context->stream_count; i++) { 870 if (context->stream_status[i].plane_count == 0) 871 continue; 872 873 if (context->stream_status[i].plane_count > 1) 874 return false; 875 876 if (context->stream_status[i].plane_states[0]->format 877 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 878 return false; 879 } 880 881 return true; 882 } 883 884 enum dc_status dce112_add_stream_to_ctx( 885 struct dc *dc, 886 struct dc_state *new_ctx, 887 struct dc_stream_state *dc_stream) 888 { 889 enum dc_status result = DC_ERROR_UNEXPECTED; 890 891 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 892 893 if (result == DC_OK) 894 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 895 896 897 if (result == DC_OK) 898 result = build_mapped_resource(dc, new_ctx, dc_stream); 899 900 return result; 901 } 902 903 enum dc_status dce112_validate_global( 904 struct dc *dc, 905 struct dc_state *context) 906 { 907 if (!dce112_validate_surface_sets(context)) 908 return DC_FAIL_SURFACE_VALIDATE; 909 910 return DC_OK; 911 } 912 913 static void dce112_destroy_resource_pool(struct resource_pool **pool) 914 { 915 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 916 917 destruct(dce110_pool); 918 kfree(dce110_pool); 919 *pool = NULL; 920 } 921 922 static const struct resource_funcs dce112_res_pool_funcs = { 923 .destroy = dce112_destroy_resource_pool, 924 .link_enc_create = dce112_link_encoder_create, 925 .validate_bandwidth = dce112_validate_bandwidth, 926 .validate_plane = dce100_validate_plane, 927 .add_stream_to_ctx = dce112_add_stream_to_ctx, 928 .validate_global = dce112_validate_global 929 }; 930 931 static void bw_calcs_data_update_from_pplib(struct dc *dc) 932 { 933 struct dm_pp_clock_levels_with_latency eng_clks = {0}; 934 struct dm_pp_clock_levels_with_latency mem_clks = {0}; 935 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; 936 struct dm_pp_clock_levels clks = {0}; 937 938 /*do system clock TODO PPLIB: after PPLIB implement, 939 * then remove old way 940 */ 941 if (!dm_pp_get_clock_levels_by_type_with_latency( 942 dc->ctx, 943 DM_PP_CLOCK_TYPE_ENGINE_CLK, 944 &eng_clks)) { 945 946 /* This is only for temporary */ 947 dm_pp_get_clock_levels_by_type( 948 dc->ctx, 949 DM_PP_CLOCK_TYPE_ENGINE_CLK, 950 &clks); 951 /* convert all the clock fro kHz to fix point mHz */ 952 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 953 clks.clocks_in_khz[clks.num_levels-1], 1000); 954 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 955 clks.clocks_in_khz[clks.num_levels/8], 1000); 956 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 957 clks.clocks_in_khz[clks.num_levels*2/8], 1000); 958 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 959 clks.clocks_in_khz[clks.num_levels*3/8], 1000); 960 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 961 clks.clocks_in_khz[clks.num_levels*4/8], 1000); 962 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 963 clks.clocks_in_khz[clks.num_levels*5/8], 1000); 964 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 965 clks.clocks_in_khz[clks.num_levels*6/8], 1000); 966 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 967 clks.clocks_in_khz[0], 1000); 968 969 /*do memory clock*/ 970 dm_pp_get_clock_levels_by_type( 971 dc->ctx, 972 DM_PP_CLOCK_TYPE_MEMORY_CLK, 973 &clks); 974 975 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 976 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000); 977 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 978 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER, 979 1000); 980 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 981 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER, 982 1000); 983 984 return; 985 } 986 987 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ 988 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 989 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); 990 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 991 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); 992 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 993 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); 994 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 995 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); 996 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 997 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); 998 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 999 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); 1000 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 1001 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); 1002 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1003 eng_clks.data[0].clocks_in_khz, 1000); 1004 1005 /*do memory clock*/ 1006 dm_pp_get_clock_levels_by_type_with_latency( 1007 dc->ctx, 1008 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1009 &mem_clks); 1010 1011 /* we don't need to call PPLIB for validation clock since they 1012 * also give us the highest sclk and highest mclk (UMA clock). 1013 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): 1014 * YCLK = UMACLK*m_memoryTypeMultiplier 1015 */ 1016 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1017 mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000); 1018 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1019 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1020 1000); 1021 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1022 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1023 1000); 1024 1025 /* Now notify PPLib/SMU about which Watermarks sets they should select 1026 * depending on DPM state they are in. And update BW MGR GFX Engine and 1027 * Memory clock member variables for Watermarks calculations for each 1028 * Watermark Set 1029 */ 1030 clk_ranges.num_wm_sets = 4; 1031 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; 1032 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = 1033 eng_clks.data[0].clocks_in_khz; 1034 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = 1035 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 1036 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz = 1037 mem_clks.data[0].clocks_in_khz; 1038 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = 1039 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 1040 1041 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; 1042 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = 1043 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 1044 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 1045 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; 1046 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz = 1047 mem_clks.data[0].clocks_in_khz; 1048 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = 1049 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 1050 1051 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C; 1052 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz = 1053 eng_clks.data[0].clocks_in_khz; 1054 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz = 1055 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 1056 clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz = 1057 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 1058 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 1059 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000; 1060 1061 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D; 1062 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz = 1063 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 1064 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 1065 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000; 1066 clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz = 1067 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 1068 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 1069 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000; 1070 1071 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 1072 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges); 1073 } 1074 1075 const struct resource_caps *dce112_resource_cap( 1076 struct hw_asic_id *asic_id) 1077 { 1078 if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) || 1079 ASIC_REV_IS_POLARIS12_V(asic_id->hw_internal_rev)) 1080 return &polaris_11_resource_cap; 1081 else 1082 return &polaris_10_resource_cap; 1083 } 1084 1085 static bool construct( 1086 uint8_t num_virtual_links, 1087 struct dc *dc, 1088 struct dce110_resource_pool *pool) 1089 { 1090 unsigned int i; 1091 struct dc_context *ctx = dc->ctx; 1092 struct dm_pp_static_clock_info static_clk_info = {0}; 1093 1094 ctx->dc_bios->regs = &bios_regs; 1095 1096 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id); 1097 pool->base.funcs = &dce112_res_pool_funcs; 1098 1099 /************************************************* 1100 * Resource + asic cap harcoding * 1101 *************************************************/ 1102 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1103 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1104 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 1105 dc->caps.max_downscale_ratio = 200; 1106 dc->caps.i2c_speed_in_khz = 100; 1107 dc->caps.max_cursor_size = 128; 1108 dc->caps.dual_link_dvi = true; 1109 1110 1111 /************************************************* 1112 * Create resources * 1113 *************************************************/ 1114 1115 pool->base.clock_sources[DCE112_CLK_SRC_PLL0] = 1116 dce112_clock_source_create( 1117 ctx, ctx->dc_bios, 1118 CLOCK_SOURCE_COMBO_PHY_PLL0, 1119 &clk_src_regs[0], false); 1120 pool->base.clock_sources[DCE112_CLK_SRC_PLL1] = 1121 dce112_clock_source_create( 1122 ctx, ctx->dc_bios, 1123 CLOCK_SOURCE_COMBO_PHY_PLL1, 1124 &clk_src_regs[1], false); 1125 pool->base.clock_sources[DCE112_CLK_SRC_PLL2] = 1126 dce112_clock_source_create( 1127 ctx, ctx->dc_bios, 1128 CLOCK_SOURCE_COMBO_PHY_PLL2, 1129 &clk_src_regs[2], false); 1130 pool->base.clock_sources[DCE112_CLK_SRC_PLL3] = 1131 dce112_clock_source_create( 1132 ctx, ctx->dc_bios, 1133 CLOCK_SOURCE_COMBO_PHY_PLL3, 1134 &clk_src_regs[3], false); 1135 pool->base.clock_sources[DCE112_CLK_SRC_PLL4] = 1136 dce112_clock_source_create( 1137 ctx, ctx->dc_bios, 1138 CLOCK_SOURCE_COMBO_PHY_PLL4, 1139 &clk_src_regs[4], false); 1140 pool->base.clock_sources[DCE112_CLK_SRC_PLL5] = 1141 dce112_clock_source_create( 1142 ctx, ctx->dc_bios, 1143 CLOCK_SOURCE_COMBO_PHY_PLL5, 1144 &clk_src_regs[5], false); 1145 pool->base.clk_src_count = DCE112_CLK_SRC_TOTAL; 1146 1147 pool->base.dp_clock_source = dce112_clock_source_create( 1148 ctx, ctx->dc_bios, 1149 CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); 1150 1151 1152 for (i = 0; i < pool->base.clk_src_count; i++) { 1153 if (pool->base.clock_sources[i] == NULL) { 1154 dm_error("DC: failed to create clock sources!\n"); 1155 BREAK_TO_DEBUGGER(); 1156 goto res_create_fail; 1157 } 1158 } 1159 1160 pool->base.dccg = dce112_dccg_create(ctx, 1161 &disp_clk_regs, 1162 &disp_clk_shift, 1163 &disp_clk_mask); 1164 if (pool->base.dccg == NULL) { 1165 dm_error("DC: failed to create display clock!\n"); 1166 BREAK_TO_DEBUGGER(); 1167 goto res_create_fail; 1168 } 1169 1170 pool->base.dmcu = dce_dmcu_create(ctx, 1171 &dmcu_regs, 1172 &dmcu_shift, 1173 &dmcu_mask); 1174 if (pool->base.dmcu == NULL) { 1175 dm_error("DC: failed to create dmcu!\n"); 1176 BREAK_TO_DEBUGGER(); 1177 goto res_create_fail; 1178 } 1179 1180 pool->base.abm = dce_abm_create(ctx, 1181 &abm_regs, 1182 &abm_shift, 1183 &abm_mask); 1184 if (pool->base.abm == NULL) { 1185 dm_error("DC: failed to create abm!\n"); 1186 BREAK_TO_DEBUGGER(); 1187 goto res_create_fail; 1188 } 1189 1190 /* get static clock information for PPLIB or firmware, save 1191 * max_clock_state 1192 */ 1193 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 1194 pool->base.dccg->max_clks_state = 1195 static_clk_info.max_clocks_state; 1196 1197 { 1198 struct irq_service_init_data init_data; 1199 init_data.ctx = dc->ctx; 1200 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 1201 if (!pool->base.irqs) 1202 goto res_create_fail; 1203 } 1204 1205 for (i = 0; i < pool->base.pipe_count; i++) { 1206 pool->base.timing_generators[i] = 1207 dce112_timing_generator_create( 1208 ctx, 1209 i, 1210 &dce112_tg_offsets[i]); 1211 if (pool->base.timing_generators[i] == NULL) { 1212 BREAK_TO_DEBUGGER(); 1213 dm_error("DC: failed to create tg!\n"); 1214 goto res_create_fail; 1215 } 1216 1217 pool->base.mis[i] = dce112_mem_input_create(ctx, i); 1218 if (pool->base.mis[i] == NULL) { 1219 BREAK_TO_DEBUGGER(); 1220 dm_error( 1221 "DC: failed to create memory input!\n"); 1222 goto res_create_fail; 1223 } 1224 1225 pool->base.ipps[i] = dce112_ipp_create(ctx, i); 1226 if (pool->base.ipps[i] == NULL) { 1227 BREAK_TO_DEBUGGER(); 1228 dm_error( 1229 "DC:failed to create input pixel processor!\n"); 1230 goto res_create_fail; 1231 } 1232 1233 pool->base.transforms[i] = dce112_transform_create(ctx, i); 1234 if (pool->base.transforms[i] == NULL) { 1235 BREAK_TO_DEBUGGER(); 1236 dm_error( 1237 "DC: failed to create transform!\n"); 1238 goto res_create_fail; 1239 } 1240 1241 pool->base.opps[i] = dce112_opp_create( 1242 ctx, 1243 i); 1244 if (pool->base.opps[i] == NULL) { 1245 BREAK_TO_DEBUGGER(); 1246 dm_error( 1247 "DC:failed to create output pixel processor!\n"); 1248 goto res_create_fail; 1249 } 1250 } 1251 1252 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1253 pool->base.engines[i] = dce112_aux_engine_create(ctx, i); 1254 if (pool->base.engines[i] == NULL) { 1255 BREAK_TO_DEBUGGER(); 1256 dm_error( 1257 "DC:failed to create aux engine!!\n"); 1258 goto res_create_fail; 1259 } 1260 } 1261 1262 if (!resource_construct(num_virtual_links, dc, &pool->base, 1263 &res_create_funcs)) 1264 goto res_create_fail; 1265 1266 dc->caps.max_planes = pool->base.pipe_count; 1267 1268 /* Create hardware sequencer */ 1269 dce112_hw_sequencer_construct(dc); 1270 1271 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1272 1273 bw_calcs_data_update_from_pplib(dc); 1274 1275 return true; 1276 1277 res_create_fail: 1278 destruct(pool); 1279 return false; 1280 } 1281 1282 struct resource_pool *dce112_create_resource_pool( 1283 uint8_t num_virtual_links, 1284 struct dc *dc) 1285 { 1286 struct dce110_resource_pool *pool = 1287 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1288 1289 if (!pool) 1290 return NULL; 1291 1292 if (construct(num_virtual_links, dc, pool)) 1293 return &pool->base; 1294 1295 BREAK_TO_DEBUGGER(); 1296 return NULL; 1297 } 1298