1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "link_encoder.h" 29 #include "stream_encoder.h" 30 31 #include "resource.h" 32 #include "dce110/dce110_resource.h" 33 34 #include "include/irq_service_interface.h" 35 #include "dce/dce_audio.h" 36 #include "dce110/dce110_timing_generator.h" 37 #include "irq/dce110/irq_service_dce110.h" 38 #include "dce110/dce110_timing_generator_v.h" 39 #include "dce/dce_link_encoder.h" 40 #include "dce/dce_stream_encoder.h" 41 #include "dce/dce_mem_input.h" 42 #include "dce110/dce110_mem_input_v.h" 43 #include "dce/dce_ipp.h" 44 #include "dce/dce_transform.h" 45 #include "dce110/dce110_transform_v.h" 46 #include "dce/dce_opp.h" 47 #include "dce110/dce110_opp_v.h" 48 #include "dce/dce_clocks.h" 49 #include "dce/dce_clock_source.h" 50 #include "dce/dce_hwseq.h" 51 #include "dce110/dce110_hw_sequencer.h" 52 #include "dce/dce_aux.h" 53 #include "dce/dce_abm.h" 54 #include "dce/dce_dmcu.h" 55 56 #define DC_LOGGER \ 57 dc->ctx->logger 58 59 #include "dce110/dce110_compressor.h" 60 61 #include "reg_helper.h" 62 63 #include "dce/dce_11_0_d.h" 64 #include "dce/dce_11_0_sh_mask.h" 65 66 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 67 #include "gmc/gmc_8_2_d.h" 68 #include "gmc/gmc_8_2_sh_mask.h" 69 #endif 70 71 #ifndef mmDP_DPHY_INTERNAL_CTRL 72 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 73 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 74 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 75 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 76 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 77 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 78 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 79 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 80 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 81 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 82 #endif 83 84 #ifndef mmBIOS_SCRATCH_2 85 #define mmBIOS_SCRATCH_2 0x05CB 86 #define mmBIOS_SCRATCH_6 0x05CF 87 #endif 88 89 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 90 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 91 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 92 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 93 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 94 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 95 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 96 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 97 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 98 #endif 99 100 #ifndef mmDP_DPHY_FAST_TRAINING 101 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 102 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 103 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 104 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 105 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 106 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 107 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 108 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 109 #endif 110 111 #ifndef DPHY_RX_FAST_TRAINING_CAPABLE 112 #define DPHY_RX_FAST_TRAINING_CAPABLE 0x1 113 #endif 114 115 static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = { 116 { 117 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 118 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 119 }, 120 { 121 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 122 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 123 }, 124 { 125 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 126 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 127 }, 128 { 129 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 130 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 131 }, 132 { 133 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 134 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 135 }, 136 { 137 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 138 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 139 } 140 }; 141 142 /* set register offset */ 143 #define SR(reg_name)\ 144 .reg_name = mm ## reg_name 145 146 /* set register offset with instance */ 147 #define SRI(reg_name, block, id)\ 148 .reg_name = mm ## block ## id ## _ ## reg_name 149 150 static const struct dccg_registers disp_clk_regs = { 151 CLK_COMMON_REG_LIST_DCE_BASE() 152 }; 153 154 static const struct dccg_shift disp_clk_shift = { 155 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 156 }; 157 158 static const struct dccg_mask disp_clk_mask = { 159 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 160 }; 161 162 static const struct dce_dmcu_registers dmcu_regs = { 163 DMCU_DCE110_COMMON_REG_LIST() 164 }; 165 166 static const struct dce_dmcu_shift dmcu_shift = { 167 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 168 }; 169 170 static const struct dce_dmcu_mask dmcu_mask = { 171 DMCU_MASK_SH_LIST_DCE110(_MASK) 172 }; 173 174 static const struct dce_abm_registers abm_regs = { 175 ABM_DCE110_COMMON_REG_LIST() 176 }; 177 178 static const struct dce_abm_shift abm_shift = { 179 ABM_MASK_SH_LIST_DCE110(__SHIFT) 180 }; 181 182 static const struct dce_abm_mask abm_mask = { 183 ABM_MASK_SH_LIST_DCE110(_MASK) 184 }; 185 186 #define ipp_regs(id)\ 187 [id] = {\ 188 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 189 } 190 191 static const struct dce_ipp_registers ipp_regs[] = { 192 ipp_regs(0), 193 ipp_regs(1), 194 ipp_regs(2) 195 }; 196 197 static const struct dce_ipp_shift ipp_shift = { 198 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 199 }; 200 201 static const struct dce_ipp_mask ipp_mask = { 202 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 203 }; 204 205 #define transform_regs(id)\ 206 [id] = {\ 207 XFM_COMMON_REG_LIST_DCE110(id)\ 208 } 209 210 static const struct dce_transform_registers xfm_regs[] = { 211 transform_regs(0), 212 transform_regs(1), 213 transform_regs(2) 214 }; 215 216 static const struct dce_transform_shift xfm_shift = { 217 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 218 }; 219 220 static const struct dce_transform_mask xfm_mask = { 221 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 222 }; 223 224 #define aux_regs(id)\ 225 [id] = {\ 226 AUX_REG_LIST(id)\ 227 } 228 229 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 230 aux_regs(0), 231 aux_regs(1), 232 aux_regs(2), 233 aux_regs(3), 234 aux_regs(4), 235 aux_regs(5) 236 }; 237 238 #define hpd_regs(id)\ 239 [id] = {\ 240 HPD_REG_LIST(id)\ 241 } 242 243 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 244 hpd_regs(0), 245 hpd_regs(1), 246 hpd_regs(2), 247 hpd_regs(3), 248 hpd_regs(4), 249 hpd_regs(5) 250 }; 251 252 253 #define link_regs(id)\ 254 [id] = {\ 255 LE_DCE110_REG_LIST(id)\ 256 } 257 258 static const struct dce110_link_enc_registers link_enc_regs[] = { 259 link_regs(0), 260 link_regs(1), 261 link_regs(2), 262 link_regs(3), 263 link_regs(4), 264 link_regs(5), 265 link_regs(6), 266 }; 267 268 #define stream_enc_regs(id)\ 269 [id] = {\ 270 SE_COMMON_REG_LIST(id),\ 271 .TMDS_CNTL = 0,\ 272 } 273 274 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 275 stream_enc_regs(0), 276 stream_enc_regs(1), 277 stream_enc_regs(2) 278 }; 279 280 static const struct dce_stream_encoder_shift se_shift = { 281 SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 282 }; 283 284 static const struct dce_stream_encoder_mask se_mask = { 285 SE_COMMON_MASK_SH_LIST_DCE110(_MASK) 286 }; 287 288 #define opp_regs(id)\ 289 [id] = {\ 290 OPP_DCE_110_REG_LIST(id),\ 291 } 292 293 static const struct dce_opp_registers opp_regs[] = { 294 opp_regs(0), 295 opp_regs(1), 296 opp_regs(2), 297 opp_regs(3), 298 opp_regs(4), 299 opp_regs(5) 300 }; 301 302 static const struct dce_opp_shift opp_shift = { 303 OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT) 304 }; 305 306 static const struct dce_opp_mask opp_mask = { 307 OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK) 308 }; 309 310 #define aux_engine_regs(id)\ 311 [id] = {\ 312 AUX_COMMON_REG_LIST(id), \ 313 .AUX_RESET_MASK = 0 \ 314 } 315 316 static const struct dce110_aux_registers aux_engine_regs[] = { 317 aux_engine_regs(0), 318 aux_engine_regs(1), 319 aux_engine_regs(2), 320 aux_engine_regs(3), 321 aux_engine_regs(4), 322 aux_engine_regs(5) 323 }; 324 325 #define audio_regs(id)\ 326 [id] = {\ 327 AUD_COMMON_REG_LIST(id)\ 328 } 329 330 static const struct dce_audio_registers audio_regs[] = { 331 audio_regs(0), 332 audio_regs(1), 333 audio_regs(2), 334 audio_regs(3), 335 audio_regs(4), 336 audio_regs(5), 337 audio_regs(6), 338 }; 339 340 static const struct dce_audio_shift audio_shift = { 341 AUD_COMMON_MASK_SH_LIST(__SHIFT) 342 }; 343 344 static const struct dce_aduio_mask audio_mask = { 345 AUD_COMMON_MASK_SH_LIST(_MASK) 346 }; 347 348 /* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */ 349 350 351 #define clk_src_regs(id)\ 352 [id] = {\ 353 CS_COMMON_REG_LIST_DCE_100_110(id),\ 354 } 355 356 static const struct dce110_clk_src_regs clk_src_regs[] = { 357 clk_src_regs(0), 358 clk_src_regs(1), 359 clk_src_regs(2) 360 }; 361 362 static const struct dce110_clk_src_shift cs_shift = { 363 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 364 }; 365 366 static const struct dce110_clk_src_mask cs_mask = { 367 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 368 }; 369 370 static const struct bios_registers bios_regs = { 371 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 372 }; 373 374 static const struct resource_caps carrizo_resource_cap = { 375 .num_timing_generator = 3, 376 .num_video_plane = 1, 377 .num_audio = 3, 378 .num_stream_encoder = 3, 379 .num_pll = 2, 380 .num_ddc = 3, 381 }; 382 383 static const struct resource_caps stoney_resource_cap = { 384 .num_timing_generator = 2, 385 .num_video_plane = 1, 386 .num_audio = 3, 387 .num_stream_encoder = 3, 388 .num_pll = 2, 389 .num_ddc = 3, 390 }; 391 392 #define CTX ctx 393 #define REG(reg) mm ## reg 394 395 #ifndef mmCC_DC_HDMI_STRAPS 396 #define mmCC_DC_HDMI_STRAPS 0x4819 397 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 398 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 399 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 400 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 401 #endif 402 403 static void read_dce_straps( 404 struct dc_context *ctx, 405 struct resource_straps *straps) 406 { 407 REG_GET_2(CC_DC_HDMI_STRAPS, 408 HDMI_DISABLE, &straps->hdmi_disable, 409 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 410 411 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 412 } 413 414 static struct audio *create_audio( 415 struct dc_context *ctx, unsigned int inst) 416 { 417 return dce_audio_create(ctx, inst, 418 &audio_regs[inst], &audio_shift, &audio_mask); 419 } 420 421 static struct timing_generator *dce110_timing_generator_create( 422 struct dc_context *ctx, 423 uint32_t instance, 424 const struct dce110_timing_generator_offsets *offsets) 425 { 426 struct dce110_timing_generator *tg110 = 427 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 428 429 if (!tg110) 430 return NULL; 431 432 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 433 return &tg110->base; 434 } 435 436 static struct stream_encoder *dce110_stream_encoder_create( 437 enum engine_id eng_id, 438 struct dc_context *ctx) 439 { 440 struct dce110_stream_encoder *enc110 = 441 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 442 443 if (!enc110) 444 return NULL; 445 446 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 447 &stream_enc_regs[eng_id], 448 &se_shift, &se_mask); 449 return &enc110->base; 450 } 451 452 #define SRII(reg_name, block, id)\ 453 .reg_name[id] = mm ## block ## id ## _ ## reg_name 454 455 static const struct dce_hwseq_registers hwseq_stoney_reg = { 456 HWSEQ_ST_REG_LIST() 457 }; 458 459 static const struct dce_hwseq_registers hwseq_cz_reg = { 460 HWSEQ_CZ_REG_LIST() 461 }; 462 463 static const struct dce_hwseq_shift hwseq_shift = { 464 HWSEQ_DCE11_MASK_SH_LIST(__SHIFT), 465 }; 466 467 static const struct dce_hwseq_mask hwseq_mask = { 468 HWSEQ_DCE11_MASK_SH_LIST(_MASK), 469 }; 470 471 static struct dce_hwseq *dce110_hwseq_create( 472 struct dc_context *ctx) 473 { 474 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 475 476 if (hws) { 477 hws->ctx = ctx; 478 hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ? 479 &hwseq_stoney_reg : &hwseq_cz_reg; 480 hws->shifts = &hwseq_shift; 481 hws->masks = &hwseq_mask; 482 hws->wa.blnd_crtc_trigger = true; 483 } 484 return hws; 485 } 486 487 static const struct resource_create_funcs res_create_funcs = { 488 .read_dce_straps = read_dce_straps, 489 .create_audio = create_audio, 490 .create_stream_encoder = dce110_stream_encoder_create, 491 .create_hwseq = dce110_hwseq_create, 492 }; 493 494 #define mi_inst_regs(id) { \ 495 MI_DCE11_REG_LIST(id), \ 496 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 497 } 498 static const struct dce_mem_input_registers mi_regs[] = { 499 mi_inst_regs(0), 500 mi_inst_regs(1), 501 mi_inst_regs(2), 502 }; 503 504 static const struct dce_mem_input_shift mi_shifts = { 505 MI_DCE11_MASK_SH_LIST(__SHIFT), 506 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 507 }; 508 509 static const struct dce_mem_input_mask mi_masks = { 510 MI_DCE11_MASK_SH_LIST(_MASK), 511 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 512 }; 513 514 515 static struct mem_input *dce110_mem_input_create( 516 struct dc_context *ctx, 517 uint32_t inst) 518 { 519 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 520 GFP_KERNEL); 521 522 if (!dce_mi) { 523 BREAK_TO_DEBUGGER(); 524 return NULL; 525 } 526 527 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 528 dce_mi->wa.single_head_rdreq_dmif_limit = 3; 529 return &dce_mi->base; 530 } 531 532 static void dce110_transform_destroy(struct transform **xfm) 533 { 534 kfree(TO_DCE_TRANSFORM(*xfm)); 535 *xfm = NULL; 536 } 537 538 static struct transform *dce110_transform_create( 539 struct dc_context *ctx, 540 uint32_t inst) 541 { 542 struct dce_transform *transform = 543 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 544 545 if (!transform) 546 return NULL; 547 548 dce_transform_construct(transform, ctx, inst, 549 &xfm_regs[inst], &xfm_shift, &xfm_mask); 550 return &transform->base; 551 } 552 553 static struct input_pixel_processor *dce110_ipp_create( 554 struct dc_context *ctx, uint32_t inst) 555 { 556 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 557 558 if (!ipp) { 559 BREAK_TO_DEBUGGER(); 560 return NULL; 561 } 562 563 dce_ipp_construct(ipp, ctx, inst, 564 &ipp_regs[inst], &ipp_shift, &ipp_mask); 565 return &ipp->base; 566 } 567 568 static const struct encoder_feature_support link_enc_feature = { 569 .max_hdmi_deep_color = COLOR_DEPTH_121212, 570 .max_hdmi_pixel_clock = 594000, 571 .flags.bits.IS_HBR2_CAPABLE = true, 572 .flags.bits.IS_TPS3_CAPABLE = true, 573 .flags.bits.IS_YCBCR_CAPABLE = true 574 }; 575 576 static struct link_encoder *dce110_link_encoder_create( 577 const struct encoder_init_data *enc_init_data) 578 { 579 struct dce110_link_encoder *enc110 = 580 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 581 582 if (!enc110) 583 return NULL; 584 585 dce110_link_encoder_construct(enc110, 586 enc_init_data, 587 &link_enc_feature, 588 &link_enc_regs[enc_init_data->transmitter], 589 &link_enc_aux_regs[enc_init_data->channel - 1], 590 &link_enc_hpd_regs[enc_init_data->hpd_source]); 591 return &enc110->base; 592 } 593 594 static struct output_pixel_processor *dce110_opp_create( 595 struct dc_context *ctx, 596 uint32_t inst) 597 { 598 struct dce110_opp *opp = 599 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 600 601 if (!opp) 602 return NULL; 603 604 dce110_opp_construct(opp, 605 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 606 return &opp->base; 607 } 608 609 struct aux_engine *dce110_aux_engine_create( 610 struct dc_context *ctx, 611 uint32_t inst) 612 { 613 struct aux_engine_dce110 *aux_engine = 614 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 615 616 if (!aux_engine) 617 return NULL; 618 619 dce110_aux_engine_construct(aux_engine, ctx, inst, 620 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 621 &aux_engine_regs[inst]); 622 623 return &aux_engine->base; 624 } 625 626 struct clock_source *dce110_clock_source_create( 627 struct dc_context *ctx, 628 struct dc_bios *bios, 629 enum clock_source_id id, 630 const struct dce110_clk_src_regs *regs, 631 bool dp_clk_src) 632 { 633 struct dce110_clk_src *clk_src = 634 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 635 636 if (!clk_src) 637 return NULL; 638 639 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 640 regs, &cs_shift, &cs_mask)) { 641 clk_src->base.dp_clk_src = dp_clk_src; 642 return &clk_src->base; 643 } 644 645 BREAK_TO_DEBUGGER(); 646 return NULL; 647 } 648 649 void dce110_clock_source_destroy(struct clock_source **clk_src) 650 { 651 struct dce110_clk_src *dce110_clk_src; 652 653 if (!clk_src) 654 return; 655 656 dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src); 657 658 kfree(dce110_clk_src->dp_ss_params); 659 kfree(dce110_clk_src->hdmi_ss_params); 660 kfree(dce110_clk_src->dvi_ss_params); 661 662 kfree(dce110_clk_src); 663 *clk_src = NULL; 664 } 665 666 static void destruct(struct dce110_resource_pool *pool) 667 { 668 unsigned int i; 669 670 for (i = 0; i < pool->base.pipe_count; i++) { 671 if (pool->base.opps[i] != NULL) 672 dce110_opp_destroy(&pool->base.opps[i]); 673 674 if (pool->base.transforms[i] != NULL) 675 dce110_transform_destroy(&pool->base.transforms[i]); 676 677 if (pool->base.ipps[i] != NULL) 678 dce_ipp_destroy(&pool->base.ipps[i]); 679 680 if (pool->base.mis[i] != NULL) { 681 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 682 pool->base.mis[i] = NULL; 683 } 684 685 if (pool->base.timing_generators[i] != NULL) { 686 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 687 pool->base.timing_generators[i] = NULL; 688 } 689 690 if (pool->base.engines[i] != NULL) 691 dce110_engine_destroy(&pool->base.engines[i]); 692 693 } 694 695 for (i = 0; i < pool->base.stream_enc_count; i++) { 696 if (pool->base.stream_enc[i] != NULL) 697 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 698 } 699 700 for (i = 0; i < pool->base.clk_src_count; i++) { 701 if (pool->base.clock_sources[i] != NULL) { 702 dce110_clock_source_destroy(&pool->base.clock_sources[i]); 703 } 704 } 705 706 if (pool->base.dp_clock_source != NULL) 707 dce110_clock_source_destroy(&pool->base.dp_clock_source); 708 709 for (i = 0; i < pool->base.audio_count; i++) { 710 if (pool->base.audios[i] != NULL) { 711 dce_aud_destroy(&pool->base.audios[i]); 712 } 713 } 714 715 if (pool->base.abm != NULL) 716 dce_abm_destroy(&pool->base.abm); 717 718 if (pool->base.dmcu != NULL) 719 dce_dmcu_destroy(&pool->base.dmcu); 720 721 if (pool->base.dccg != NULL) 722 dce_dccg_destroy(&pool->base.dccg); 723 724 if (pool->base.irqs != NULL) { 725 dal_irq_service_destroy(&pool->base.irqs); 726 } 727 } 728 729 730 static void get_pixel_clock_parameters( 731 const struct pipe_ctx *pipe_ctx, 732 struct pixel_clk_params *pixel_clk_params) 733 { 734 const struct dc_stream_state *stream = pipe_ctx->stream; 735 736 /*TODO: is this halved for YCbCr 420? in that case we might want to move 737 * the pixel clock normalization for hdmi up to here instead of doing it 738 * in pll_adjust_pix_clk 739 */ 740 pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz; 741 pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id; 742 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 743 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 744 /* TODO: un-hardcode*/ 745 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 746 LINK_RATE_REF_FREQ_IN_KHZ; 747 pixel_clk_params->flags.ENABLE_SS = 0; 748 pixel_clk_params->color_depth = 749 stream->timing.display_color_depth; 750 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 751 pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding == 752 PIXEL_ENCODING_YCBCR420); 753 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 754 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) { 755 pixel_clk_params->color_depth = COLOR_DEPTH_888; 756 } 757 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 758 pixel_clk_params->requested_pix_clk = pixel_clk_params->requested_pix_clk / 2; 759 } 760 } 761 762 void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 763 { 764 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 765 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 766 pipe_ctx->clock_source, 767 &pipe_ctx->stream_res.pix_clk_params, 768 &pipe_ctx->pll_settings); 769 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 770 &pipe_ctx->stream->bit_depth_params); 771 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 772 } 773 774 static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx) 775 { 776 if (pipe_ctx->pipe_idx != underlay_idx) 777 return true; 778 if (!pipe_ctx->plane_state) 779 return false; 780 if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 781 return false; 782 return true; 783 } 784 785 static enum dc_status build_mapped_resource( 786 const struct dc *dc, 787 struct dc_state *context, 788 struct dc_stream_state *stream) 789 { 790 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 791 792 if (!pipe_ctx) 793 return DC_ERROR_UNEXPECTED; 794 795 if (!is_surface_pixel_format_supported(pipe_ctx, 796 dc->res_pool->underlay_pipe_index)) 797 return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED; 798 799 dce110_resource_build_pipe_hw_param(pipe_ctx); 800 801 /* TODO: validate audio ASIC caps, encoder */ 802 803 resource_build_info_frame(pipe_ctx); 804 805 return DC_OK; 806 } 807 808 static bool dce110_validate_bandwidth( 809 struct dc *dc, 810 struct dc_state *context) 811 { 812 bool result = false; 813 814 DC_LOG_BANDWIDTH_CALCS( 815 "%s: start", 816 __func__); 817 818 if (bw_calcs( 819 dc->ctx, 820 dc->bw_dceip, 821 dc->bw_vbios, 822 context->res_ctx.pipe_ctx, 823 dc->res_pool->pipe_count, 824 &context->bw.dce)) 825 result = true; 826 827 if (!result) 828 DC_LOG_BANDWIDTH_VALIDATION("%s: %dx%d@%d Bandwidth validation failed!\n", 829 __func__, 830 context->streams[0]->timing.h_addressable, 831 context->streams[0]->timing.v_addressable, 832 context->streams[0]->timing.pix_clk_khz); 833 834 if (memcmp(&dc->current_state->bw.dce, 835 &context->bw.dce, sizeof(context->bw.dce))) { 836 837 DC_LOG_BANDWIDTH_CALCS( 838 "%s: finish,\n" 839 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 840 "stutMark_b: %d stutMark_a: %d\n" 841 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 842 "stutMark_b: %d stutMark_a: %d\n" 843 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 844 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n" 845 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n" 846 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n" 847 , 848 __func__, 849 context->bw.dce.nbp_state_change_wm_ns[0].b_mark, 850 context->bw.dce.nbp_state_change_wm_ns[0].a_mark, 851 context->bw.dce.urgent_wm_ns[0].b_mark, 852 context->bw.dce.urgent_wm_ns[0].a_mark, 853 context->bw.dce.stutter_exit_wm_ns[0].b_mark, 854 context->bw.dce.stutter_exit_wm_ns[0].a_mark, 855 context->bw.dce.nbp_state_change_wm_ns[1].b_mark, 856 context->bw.dce.nbp_state_change_wm_ns[1].a_mark, 857 context->bw.dce.urgent_wm_ns[1].b_mark, 858 context->bw.dce.urgent_wm_ns[1].a_mark, 859 context->bw.dce.stutter_exit_wm_ns[1].b_mark, 860 context->bw.dce.stutter_exit_wm_ns[1].a_mark, 861 context->bw.dce.nbp_state_change_wm_ns[2].b_mark, 862 context->bw.dce.nbp_state_change_wm_ns[2].a_mark, 863 context->bw.dce.urgent_wm_ns[2].b_mark, 864 context->bw.dce.urgent_wm_ns[2].a_mark, 865 context->bw.dce.stutter_exit_wm_ns[2].b_mark, 866 context->bw.dce.stutter_exit_wm_ns[2].a_mark, 867 context->bw.dce.stutter_mode_enable, 868 context->bw.dce.cpuc_state_change_enable, 869 context->bw.dce.cpup_state_change_enable, 870 context->bw.dce.nbp_state_change_enable, 871 context->bw.dce.all_displays_in_sync, 872 context->bw.dce.dispclk_khz, 873 context->bw.dce.sclk_khz, 874 context->bw.dce.sclk_deep_sleep_khz, 875 context->bw.dce.yclk_khz, 876 context->bw.dce.blackout_recovery_time_us); 877 } 878 return result; 879 } 880 881 enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state, 882 struct dc_caps *caps) 883 { 884 if (((plane_state->dst_rect.width * 2) < plane_state->src_rect.width) || 885 ((plane_state->dst_rect.height * 2) < plane_state->src_rect.height)) 886 return DC_FAIL_SURFACE_VALIDATE; 887 888 return DC_OK; 889 } 890 891 static bool dce110_validate_surface_sets( 892 struct dc_state *context) 893 { 894 int i, j; 895 896 for (i = 0; i < context->stream_count; i++) { 897 if (context->stream_status[i].plane_count == 0) 898 continue; 899 900 if (context->stream_status[i].plane_count > 2) 901 return false; 902 903 for (j = 0; j < context->stream_status[i].plane_count; j++) { 904 struct dc_plane_state *plane = 905 context->stream_status[i].plane_states[j]; 906 907 /* underlay validation */ 908 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 909 910 if ((plane->src_rect.width > 1920 || 911 plane->src_rect.height > 1080)) 912 return false; 913 914 /* we don't have the logic to support underlay 915 * only yet so block the use case where we get 916 * NV12 plane as top layer 917 */ 918 if (j == 0) 919 return false; 920 921 /* irrespective of plane format, 922 * stream should be RGB encoded 923 */ 924 if (context->streams[i]->timing.pixel_encoding 925 != PIXEL_ENCODING_RGB) 926 return false; 927 928 } 929 930 } 931 } 932 933 return true; 934 } 935 936 enum dc_status dce110_validate_global( 937 struct dc *dc, 938 struct dc_state *context) 939 { 940 if (!dce110_validate_surface_sets(context)) 941 return DC_FAIL_SURFACE_VALIDATE; 942 943 return DC_OK; 944 } 945 946 static enum dc_status dce110_add_stream_to_ctx( 947 struct dc *dc, 948 struct dc_state *new_ctx, 949 struct dc_stream_state *dc_stream) 950 { 951 enum dc_status result = DC_ERROR_UNEXPECTED; 952 953 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 954 955 if (result == DC_OK) 956 result = resource_map_clock_resources(dc, new_ctx, dc_stream); 957 958 959 if (result == DC_OK) 960 result = build_mapped_resource(dc, new_ctx, dc_stream); 961 962 return result; 963 } 964 965 static struct pipe_ctx *dce110_acquire_underlay( 966 struct dc_state *context, 967 const struct resource_pool *pool, 968 struct dc_stream_state *stream) 969 { 970 struct dc *dc = stream->ctx->dc; 971 struct resource_context *res_ctx = &context->res_ctx; 972 unsigned int underlay_idx = pool->underlay_pipe_index; 973 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; 974 975 if (res_ctx->pipe_ctx[underlay_idx].stream) 976 return NULL; 977 978 pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx]; 979 pipe_ctx->plane_res.mi = pool->mis[underlay_idx]; 980 /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/ 981 pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx]; 982 pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; 983 pipe_ctx->pipe_idx = underlay_idx; 984 985 pipe_ctx->stream = stream; 986 987 if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) { 988 struct tg_color black_color = {0}; 989 struct dc_bios *dcb = dc->ctx->dc_bios; 990 991 dc->hwss.enable_display_power_gating( 992 dc, 993 pipe_ctx->stream_res.tg->inst, 994 dcb, PIPE_GATING_CONTROL_DISABLE); 995 996 /* 997 * This is for powering on underlay, so crtc does not 998 * need to be enabled 999 */ 1000 1001 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg, 1002 &stream->timing, 1003 false); 1004 1005 pipe_ctx->stream_res.tg->funcs->enable_advanced_request( 1006 pipe_ctx->stream_res.tg, 1007 true, 1008 &stream->timing); 1009 1010 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi, 1011 stream->timing.h_total, 1012 stream->timing.v_total, 1013 stream->timing.pix_clk_khz, 1014 context->stream_count); 1015 1016 color_space_to_black_color(dc, 1017 COLOR_SPACE_YCBCR601, &black_color); 1018 pipe_ctx->stream_res.tg->funcs->set_blank_color( 1019 pipe_ctx->stream_res.tg, 1020 &black_color); 1021 } 1022 1023 return pipe_ctx; 1024 } 1025 1026 static void dce110_destroy_resource_pool(struct resource_pool **pool) 1027 { 1028 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 1029 1030 destruct(dce110_pool); 1031 kfree(dce110_pool); 1032 *pool = NULL; 1033 } 1034 1035 1036 static const struct resource_funcs dce110_res_pool_funcs = { 1037 .destroy = dce110_destroy_resource_pool, 1038 .link_enc_create = dce110_link_encoder_create, 1039 .validate_bandwidth = dce110_validate_bandwidth, 1040 .validate_plane = dce110_validate_plane, 1041 .acquire_idle_pipe_for_layer = dce110_acquire_underlay, 1042 .add_stream_to_ctx = dce110_add_stream_to_ctx, 1043 .validate_global = dce110_validate_global 1044 }; 1045 1046 static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) 1047 { 1048 struct dce110_timing_generator *dce110_tgv = kzalloc(sizeof(*dce110_tgv), 1049 GFP_KERNEL); 1050 struct dce_transform *dce110_xfmv = kzalloc(sizeof(*dce110_xfmv), 1051 GFP_KERNEL); 1052 struct dce_mem_input *dce110_miv = kzalloc(sizeof(*dce110_miv), 1053 GFP_KERNEL); 1054 struct dce110_opp *dce110_oppv = kzalloc(sizeof(*dce110_oppv), 1055 GFP_KERNEL); 1056 1057 if (!dce110_tgv || !dce110_xfmv || !dce110_miv || !dce110_oppv) { 1058 kfree(dce110_tgv); 1059 kfree(dce110_xfmv); 1060 kfree(dce110_miv); 1061 kfree(dce110_oppv); 1062 return false; 1063 } 1064 1065 dce110_opp_v_construct(dce110_oppv, ctx); 1066 1067 dce110_timing_generator_v_construct(dce110_tgv, ctx); 1068 dce110_mem_input_v_construct(dce110_miv, ctx); 1069 dce110_transform_v_construct(dce110_xfmv, ctx); 1070 1071 pool->opps[pool->pipe_count] = &dce110_oppv->base; 1072 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; 1073 pool->mis[pool->pipe_count] = &dce110_miv->base; 1074 pool->transforms[pool->pipe_count] = &dce110_xfmv->base; 1075 pool->pipe_count++; 1076 1077 /* update the public caps to indicate an underlay is available */ 1078 ctx->dc->caps.max_slave_planes = 1; 1079 ctx->dc->caps.max_slave_planes = 1; 1080 1081 return true; 1082 } 1083 1084 static void bw_calcs_data_update_from_pplib(struct dc *dc) 1085 { 1086 struct dm_pp_clock_levels clks = {0}; 1087 1088 /*do system clock*/ 1089 dm_pp_get_clock_levels_by_type( 1090 dc->ctx, 1091 DM_PP_CLOCK_TYPE_ENGINE_CLK, 1092 &clks); 1093 /* convert all the clock fro kHz to fix point mHz */ 1094 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 1095 clks.clocks_in_khz[clks.num_levels-1], 1000); 1096 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 1097 clks.clocks_in_khz[clks.num_levels/8], 1000); 1098 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 1099 clks.clocks_in_khz[clks.num_levels*2/8], 1000); 1100 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 1101 clks.clocks_in_khz[clks.num_levels*3/8], 1000); 1102 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 1103 clks.clocks_in_khz[clks.num_levels*4/8], 1000); 1104 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 1105 clks.clocks_in_khz[clks.num_levels*5/8], 1000); 1106 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 1107 clks.clocks_in_khz[clks.num_levels*6/8], 1000); 1108 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1109 clks.clocks_in_khz[0], 1000); 1110 dc->sclk_lvls = clks; 1111 1112 /*do display clock*/ 1113 dm_pp_get_clock_levels_by_type( 1114 dc->ctx, 1115 DM_PP_CLOCK_TYPE_DISPLAY_CLK, 1116 &clks); 1117 dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed( 1118 clks.clocks_in_khz[clks.num_levels-1], 1000); 1119 dc->bw_vbios->mid_voltage_max_dispclk = bw_frc_to_fixed( 1120 clks.clocks_in_khz[clks.num_levels>>1], 1000); 1121 dc->bw_vbios->low_voltage_max_dispclk = bw_frc_to_fixed( 1122 clks.clocks_in_khz[0], 1000); 1123 1124 /*do memory clock*/ 1125 dm_pp_get_clock_levels_by_type( 1126 dc->ctx, 1127 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1128 &clks); 1129 1130 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1131 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000); 1132 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1133 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER, 1134 1000); 1135 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1136 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER, 1137 1000); 1138 } 1139 1140 const struct resource_caps *dce110_resource_cap( 1141 struct hw_asic_id *asic_id) 1142 { 1143 if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev)) 1144 return &stoney_resource_cap; 1145 else 1146 return &carrizo_resource_cap; 1147 } 1148 1149 static bool construct( 1150 uint8_t num_virtual_links, 1151 struct dc *dc, 1152 struct dce110_resource_pool *pool, 1153 struct hw_asic_id asic_id) 1154 { 1155 unsigned int i; 1156 struct dc_context *ctx = dc->ctx; 1157 struct dc_firmware_info info; 1158 struct dc_bios *bp; 1159 struct dm_pp_static_clock_info static_clk_info = {0}; 1160 1161 ctx->dc_bios->regs = &bios_regs; 1162 1163 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id); 1164 pool->base.funcs = &dce110_res_pool_funcs; 1165 1166 /************************************************* 1167 * Resource + asic cap harcoding * 1168 *************************************************/ 1169 1170 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1171 pool->base.underlay_pipe_index = pool->base.pipe_count; 1172 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 1173 dc->caps.max_downscale_ratio = 150; 1174 dc->caps.i2c_speed_in_khz = 100; 1175 dc->caps.max_cursor_size = 128; 1176 dc->caps.is_apu = true; 1177 1178 /************************************************* 1179 * Create resources * 1180 *************************************************/ 1181 1182 bp = ctx->dc_bios; 1183 1184 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 1185 info.external_clock_source_frequency_for_dp != 0) { 1186 pool->base.dp_clock_source = 1187 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1188 1189 pool->base.clock_sources[0] = 1190 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, 1191 &clk_src_regs[0], false); 1192 pool->base.clock_sources[1] = 1193 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, 1194 &clk_src_regs[1], false); 1195 1196 pool->base.clk_src_count = 2; 1197 1198 /* TODO: find out if CZ support 3 PLLs */ 1199 } 1200 1201 if (pool->base.dp_clock_source == NULL) { 1202 dm_error("DC: failed to create dp clock source!\n"); 1203 BREAK_TO_DEBUGGER(); 1204 goto res_create_fail; 1205 } 1206 1207 for (i = 0; i < pool->base.clk_src_count; i++) { 1208 if (pool->base.clock_sources[i] == NULL) { 1209 dm_error("DC: failed to create clock sources!\n"); 1210 BREAK_TO_DEBUGGER(); 1211 goto res_create_fail; 1212 } 1213 } 1214 1215 pool->base.dccg = dce110_dccg_create(ctx, 1216 &disp_clk_regs, 1217 &disp_clk_shift, 1218 &disp_clk_mask); 1219 if (pool->base.dccg == NULL) { 1220 dm_error("DC: failed to create display clock!\n"); 1221 BREAK_TO_DEBUGGER(); 1222 goto res_create_fail; 1223 } 1224 1225 pool->base.dmcu = dce_dmcu_create(ctx, 1226 &dmcu_regs, 1227 &dmcu_shift, 1228 &dmcu_mask); 1229 if (pool->base.dmcu == NULL) { 1230 dm_error("DC: failed to create dmcu!\n"); 1231 BREAK_TO_DEBUGGER(); 1232 goto res_create_fail; 1233 } 1234 1235 pool->base.abm = dce_abm_create(ctx, 1236 &abm_regs, 1237 &abm_shift, 1238 &abm_mask); 1239 if (pool->base.abm == NULL) { 1240 dm_error("DC: failed to create abm!\n"); 1241 BREAK_TO_DEBUGGER(); 1242 goto res_create_fail; 1243 } 1244 1245 /* get static clock information for PPLIB or firmware, save 1246 * max_clock_state 1247 */ 1248 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 1249 pool->base.dccg->max_clks_state = 1250 static_clk_info.max_clocks_state; 1251 1252 { 1253 struct irq_service_init_data init_data; 1254 init_data.ctx = dc->ctx; 1255 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 1256 if (!pool->base.irqs) 1257 goto res_create_fail; 1258 } 1259 1260 for (i = 0; i < pool->base.pipe_count; i++) { 1261 pool->base.timing_generators[i] = dce110_timing_generator_create( 1262 ctx, i, &dce110_tg_offsets[i]); 1263 if (pool->base.timing_generators[i] == NULL) { 1264 BREAK_TO_DEBUGGER(); 1265 dm_error("DC: failed to create tg!\n"); 1266 goto res_create_fail; 1267 } 1268 1269 pool->base.mis[i] = dce110_mem_input_create(ctx, i); 1270 if (pool->base.mis[i] == NULL) { 1271 BREAK_TO_DEBUGGER(); 1272 dm_error( 1273 "DC: failed to create memory input!\n"); 1274 goto res_create_fail; 1275 } 1276 1277 pool->base.ipps[i] = dce110_ipp_create(ctx, i); 1278 if (pool->base.ipps[i] == NULL) { 1279 BREAK_TO_DEBUGGER(); 1280 dm_error( 1281 "DC: failed to create input pixel processor!\n"); 1282 goto res_create_fail; 1283 } 1284 1285 pool->base.transforms[i] = dce110_transform_create(ctx, i); 1286 if (pool->base.transforms[i] == NULL) { 1287 BREAK_TO_DEBUGGER(); 1288 dm_error( 1289 "DC: failed to create transform!\n"); 1290 goto res_create_fail; 1291 } 1292 1293 pool->base.opps[i] = dce110_opp_create(ctx, i); 1294 if (pool->base.opps[i] == NULL) { 1295 BREAK_TO_DEBUGGER(); 1296 dm_error( 1297 "DC: failed to create output pixel processor!\n"); 1298 goto res_create_fail; 1299 } 1300 } 1301 1302 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1303 pool->base.engines[i] = dce110_aux_engine_create(ctx, i); 1304 if (pool->base.engines[i] == NULL) { 1305 BREAK_TO_DEBUGGER(); 1306 dm_error( 1307 "DC:failed to create aux engine!!\n"); 1308 goto res_create_fail; 1309 } 1310 } 1311 1312 dc->fbc_compressor = dce110_compressor_create(ctx); 1313 1314 if (!underlay_create(ctx, &pool->base)) 1315 goto res_create_fail; 1316 1317 if (!resource_construct(num_virtual_links, dc, &pool->base, 1318 &res_create_funcs)) 1319 goto res_create_fail; 1320 1321 /* Create hardware sequencer */ 1322 dce110_hw_sequencer_construct(dc); 1323 1324 dc->caps.max_planes = pool->base.pipe_count; 1325 1326 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1327 1328 bw_calcs_data_update_from_pplib(dc); 1329 1330 return true; 1331 1332 res_create_fail: 1333 destruct(pool); 1334 return false; 1335 } 1336 1337 struct resource_pool *dce110_create_resource_pool( 1338 uint8_t num_virtual_links, 1339 struct dc *dc, 1340 struct hw_asic_id asic_id) 1341 { 1342 struct dce110_resource_pool *pool = 1343 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1344 1345 if (!pool) 1346 return NULL; 1347 1348 if (construct(num_virtual_links, dc, pool, asic_id)) 1349 return &pool->base; 1350 1351 BREAK_TO_DEBUGGER(); 1352 return NULL; 1353 } 1354