1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include "dm_services.h" 26 27 #include "link_encoder.h" 28 #include "stream_encoder.h" 29 30 #include "resource.h" 31 #include "include/irq_service_interface.h" 32 #include "../virtual/virtual_stream_encoder.h" 33 #include "dce110/dce110_resource.h" 34 #include "dce110/dce110_timing_generator.h" 35 #include "irq/dce110/irq_service_dce110.h" 36 #include "dce/dce_link_encoder.h" 37 #include "dce/dce_stream_encoder.h" 38 39 #include "dce/dce_mem_input.h" 40 #include "dce/dce_ipp.h" 41 #include "dce/dce_transform.h" 42 #include "dce/dce_opp.h" 43 #include "dce/dce_clocks.h" 44 #include "dce/dce_clock_source.h" 45 #include "dce/dce_audio.h" 46 #include "dce/dce_hwseq.h" 47 #include "dce100/dce100_hw_sequencer.h" 48 49 #include "reg_helper.h" 50 51 #include "dce/dce_10_0_d.h" 52 #include "dce/dce_10_0_sh_mask.h" 53 54 #include "dce/dce_dmcu.h" 55 #include "dce/dce_aux.h" 56 #include "dce/dce_abm.h" 57 58 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 59 #include "gmc/gmc_8_2_d.h" 60 #include "gmc/gmc_8_2_sh_mask.h" 61 #endif 62 63 #ifndef mmDP_DPHY_INTERNAL_CTRL 64 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 65 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 66 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 67 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 68 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 69 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 70 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 71 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 72 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 73 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 74 #endif 75 76 #ifndef mmBIOS_SCRATCH_2 77 #define mmBIOS_SCRATCH_2 0x05CB 78 #define mmBIOS_SCRATCH_6 0x05CF 79 #endif 80 81 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 82 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 83 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 84 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 85 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 86 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 87 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 88 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 89 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 90 #endif 91 92 #ifndef mmDP_DPHY_FAST_TRAINING 93 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 94 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 95 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 96 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 97 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 98 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 99 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 100 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 101 #endif 102 103 static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = { 104 { 105 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 106 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 107 }, 108 { 109 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 110 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 111 }, 112 { 113 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 114 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 115 }, 116 { 117 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 118 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 119 }, 120 { 121 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 122 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 123 }, 124 { 125 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 126 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 127 } 128 }; 129 130 /* set register offset */ 131 #define SR(reg_name)\ 132 .reg_name = mm ## reg_name 133 134 /* set register offset with instance */ 135 #define SRI(reg_name, block, id)\ 136 .reg_name = mm ## block ## id ## _ ## reg_name 137 138 139 static const struct dccg_registers disp_clk_regs = { 140 CLK_COMMON_REG_LIST_DCE_BASE() 141 }; 142 143 static const struct dccg_shift disp_clk_shift = { 144 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 145 }; 146 147 static const struct dccg_mask disp_clk_mask = { 148 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 149 }; 150 151 #define ipp_regs(id)\ 152 [id] = {\ 153 IPP_DCE100_REG_LIST_DCE_BASE(id)\ 154 } 155 156 static const struct dce_ipp_registers ipp_regs[] = { 157 ipp_regs(0), 158 ipp_regs(1), 159 ipp_regs(2), 160 ipp_regs(3), 161 ipp_regs(4), 162 ipp_regs(5) 163 }; 164 165 static const struct dce_ipp_shift ipp_shift = { 166 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 167 }; 168 169 static const struct dce_ipp_mask ipp_mask = { 170 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 171 }; 172 173 #define transform_regs(id)\ 174 [id] = {\ 175 XFM_COMMON_REG_LIST_DCE100(id)\ 176 } 177 178 static const struct dce_transform_registers xfm_regs[] = { 179 transform_regs(0), 180 transform_regs(1), 181 transform_regs(2), 182 transform_regs(3), 183 transform_regs(4), 184 transform_regs(5) 185 }; 186 187 static const struct dce_transform_shift xfm_shift = { 188 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 189 }; 190 191 static const struct dce_transform_mask xfm_mask = { 192 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 193 }; 194 195 #define aux_regs(id)\ 196 [id] = {\ 197 AUX_REG_LIST(id)\ 198 } 199 200 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 201 aux_regs(0), 202 aux_regs(1), 203 aux_regs(2), 204 aux_regs(3), 205 aux_regs(4), 206 aux_regs(5) 207 }; 208 209 #define hpd_regs(id)\ 210 [id] = {\ 211 HPD_REG_LIST(id)\ 212 } 213 214 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 215 hpd_regs(0), 216 hpd_regs(1), 217 hpd_regs(2), 218 hpd_regs(3), 219 hpd_regs(4), 220 hpd_regs(5) 221 }; 222 223 #define link_regs(id)\ 224 [id] = {\ 225 LE_DCE100_REG_LIST(id)\ 226 } 227 228 static const struct dce110_link_enc_registers link_enc_regs[] = { 229 link_regs(0), 230 link_regs(1), 231 link_regs(2), 232 link_regs(3), 233 link_regs(4), 234 link_regs(5), 235 link_regs(6), 236 }; 237 238 #define stream_enc_regs(id)\ 239 [id] = {\ 240 SE_COMMON_REG_LIST_DCE_BASE(id),\ 241 .AFMT_CNTL = 0,\ 242 } 243 244 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 245 stream_enc_regs(0), 246 stream_enc_regs(1), 247 stream_enc_regs(2), 248 stream_enc_regs(3), 249 stream_enc_regs(4), 250 stream_enc_regs(5), 251 stream_enc_regs(6) 252 }; 253 254 static const struct dce_stream_encoder_shift se_shift = { 255 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) 256 }; 257 258 static const struct dce_stream_encoder_mask se_mask = { 259 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) 260 }; 261 262 #define opp_regs(id)\ 263 [id] = {\ 264 OPP_DCE_100_REG_LIST(id),\ 265 } 266 267 static const struct dce_opp_registers opp_regs[] = { 268 opp_regs(0), 269 opp_regs(1), 270 opp_regs(2), 271 opp_regs(3), 272 opp_regs(4), 273 opp_regs(5) 274 }; 275 276 static const struct dce_opp_shift opp_shift = { 277 OPP_COMMON_MASK_SH_LIST_DCE_100(__SHIFT) 278 }; 279 280 static const struct dce_opp_mask opp_mask = { 281 OPP_COMMON_MASK_SH_LIST_DCE_100(_MASK) 282 }; 283 #define aux_engine_regs(id)\ 284 [id] = {\ 285 AUX_COMMON_REG_LIST(id), \ 286 .AUX_RESET_MASK = 0 \ 287 } 288 289 static const struct dce110_aux_registers aux_engine_regs[] = { 290 aux_engine_regs(0), 291 aux_engine_regs(1), 292 aux_engine_regs(2), 293 aux_engine_regs(3), 294 aux_engine_regs(4), 295 aux_engine_regs(5) 296 }; 297 298 #define audio_regs(id)\ 299 [id] = {\ 300 AUD_COMMON_REG_LIST(id)\ 301 } 302 303 static const struct dce_audio_registers audio_regs[] = { 304 audio_regs(0), 305 audio_regs(1), 306 audio_regs(2), 307 audio_regs(3), 308 audio_regs(4), 309 audio_regs(5), 310 audio_regs(6), 311 }; 312 313 static const struct dce_audio_shift audio_shift = { 314 AUD_COMMON_MASK_SH_LIST(__SHIFT) 315 }; 316 317 static const struct dce_aduio_mask audio_mask = { 318 AUD_COMMON_MASK_SH_LIST(_MASK) 319 }; 320 321 #define clk_src_regs(id)\ 322 [id] = {\ 323 CS_COMMON_REG_LIST_DCE_100_110(id),\ 324 } 325 326 static const struct dce110_clk_src_regs clk_src_regs[] = { 327 clk_src_regs(0), 328 clk_src_regs(1), 329 clk_src_regs(2) 330 }; 331 332 static const struct dce110_clk_src_shift cs_shift = { 333 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 334 }; 335 336 static const struct dce110_clk_src_mask cs_mask = { 337 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 338 }; 339 340 static const struct dce_dmcu_registers dmcu_regs = { 341 DMCU_DCE110_COMMON_REG_LIST() 342 }; 343 344 static const struct dce_dmcu_shift dmcu_shift = { 345 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 346 }; 347 348 static const struct dce_dmcu_mask dmcu_mask = { 349 DMCU_MASK_SH_LIST_DCE110(_MASK) 350 }; 351 352 static const struct dce_abm_registers abm_regs = { 353 ABM_DCE110_COMMON_REG_LIST() 354 }; 355 356 static const struct dce_abm_shift abm_shift = { 357 ABM_MASK_SH_LIST_DCE110(__SHIFT) 358 }; 359 360 static const struct dce_abm_mask abm_mask = { 361 ABM_MASK_SH_LIST_DCE110(_MASK) 362 }; 363 364 #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03 365 366 static const struct bios_registers bios_regs = { 367 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 368 }; 369 370 static const struct resource_caps res_cap = { 371 .num_timing_generator = 6, 372 .num_audio = 6, 373 .num_stream_encoder = 6, 374 .num_pll = 3, 375 .num_ddc = 6, 376 }; 377 378 #define CTX ctx 379 #define REG(reg) mm ## reg 380 381 #ifndef mmCC_DC_HDMI_STRAPS 382 #define mmCC_DC_HDMI_STRAPS 0x1918 383 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 384 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 385 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 386 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 387 #endif 388 389 static void read_dce_straps( 390 struct dc_context *ctx, 391 struct resource_straps *straps) 392 { 393 REG_GET_2(CC_DC_HDMI_STRAPS, 394 HDMI_DISABLE, &straps->hdmi_disable, 395 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 396 397 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 398 } 399 400 static struct audio *create_audio( 401 struct dc_context *ctx, unsigned int inst) 402 { 403 return dce_audio_create(ctx, inst, 404 &audio_regs[inst], &audio_shift, &audio_mask); 405 } 406 407 static struct timing_generator *dce100_timing_generator_create( 408 struct dc_context *ctx, 409 uint32_t instance, 410 const struct dce110_timing_generator_offsets *offsets) 411 { 412 struct dce110_timing_generator *tg110 = 413 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 414 415 if (!tg110) 416 return NULL; 417 418 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 419 return &tg110->base; 420 } 421 422 static struct stream_encoder *dce100_stream_encoder_create( 423 enum engine_id eng_id, 424 struct dc_context *ctx) 425 { 426 struct dce110_stream_encoder *enc110 = 427 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 428 429 if (!enc110) 430 return NULL; 431 432 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 433 &stream_enc_regs[eng_id], &se_shift, &se_mask); 434 return &enc110->base; 435 } 436 437 #define SRII(reg_name, block, id)\ 438 .reg_name[id] = mm ## block ## id ## _ ## reg_name 439 440 static const struct dce_hwseq_registers hwseq_reg = { 441 HWSEQ_DCE10_REG_LIST() 442 }; 443 444 static const struct dce_hwseq_shift hwseq_shift = { 445 HWSEQ_DCE10_MASK_SH_LIST(__SHIFT) 446 }; 447 448 static const struct dce_hwseq_mask hwseq_mask = { 449 HWSEQ_DCE10_MASK_SH_LIST(_MASK) 450 }; 451 452 static struct dce_hwseq *dce100_hwseq_create( 453 struct dc_context *ctx) 454 { 455 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 456 457 if (hws) { 458 hws->ctx = ctx; 459 hws->regs = &hwseq_reg; 460 hws->shifts = &hwseq_shift; 461 hws->masks = &hwseq_mask; 462 } 463 return hws; 464 } 465 466 static const struct resource_create_funcs res_create_funcs = { 467 .read_dce_straps = read_dce_straps, 468 .create_audio = create_audio, 469 .create_stream_encoder = dce100_stream_encoder_create, 470 .create_hwseq = dce100_hwseq_create, 471 }; 472 473 #define mi_inst_regs(id) { \ 474 MI_DCE8_REG_LIST(id), \ 475 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 476 } 477 static const struct dce_mem_input_registers mi_regs[] = { 478 mi_inst_regs(0), 479 mi_inst_regs(1), 480 mi_inst_regs(2), 481 mi_inst_regs(3), 482 mi_inst_regs(4), 483 mi_inst_regs(5), 484 }; 485 486 static const struct dce_mem_input_shift mi_shifts = { 487 MI_DCE8_MASK_SH_LIST(__SHIFT), 488 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 489 }; 490 491 static const struct dce_mem_input_mask mi_masks = { 492 MI_DCE8_MASK_SH_LIST(_MASK), 493 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 494 }; 495 496 static struct mem_input *dce100_mem_input_create( 497 struct dc_context *ctx, 498 uint32_t inst) 499 { 500 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 501 GFP_KERNEL); 502 503 if (!dce_mi) { 504 BREAK_TO_DEBUGGER(); 505 return NULL; 506 } 507 508 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 509 dce_mi->wa.single_head_rdreq_dmif_limit = 2; 510 return &dce_mi->base; 511 } 512 513 static void dce100_transform_destroy(struct transform **xfm) 514 { 515 kfree(TO_DCE_TRANSFORM(*xfm)); 516 *xfm = NULL; 517 } 518 519 static struct transform *dce100_transform_create( 520 struct dc_context *ctx, 521 uint32_t inst) 522 { 523 struct dce_transform *transform = 524 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 525 526 if (!transform) 527 return NULL; 528 529 dce_transform_construct(transform, ctx, inst, 530 &xfm_regs[inst], &xfm_shift, &xfm_mask); 531 return &transform->base; 532 } 533 534 static struct input_pixel_processor *dce100_ipp_create( 535 struct dc_context *ctx, uint32_t inst) 536 { 537 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 538 539 if (!ipp) { 540 BREAK_TO_DEBUGGER(); 541 return NULL; 542 } 543 544 dce_ipp_construct(ipp, ctx, inst, 545 &ipp_regs[inst], &ipp_shift, &ipp_mask); 546 return &ipp->base; 547 } 548 549 static const struct encoder_feature_support link_enc_feature = { 550 .max_hdmi_deep_color = COLOR_DEPTH_121212, 551 .max_hdmi_pixel_clock = 300000, 552 .flags.bits.IS_HBR2_CAPABLE = true, 553 .flags.bits.IS_TPS3_CAPABLE = true, 554 .flags.bits.IS_YCBCR_CAPABLE = true 555 }; 556 557 struct link_encoder *dce100_link_encoder_create( 558 const struct encoder_init_data *enc_init_data) 559 { 560 struct dce110_link_encoder *enc110 = 561 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 562 563 if (!enc110) 564 return NULL; 565 566 dce110_link_encoder_construct(enc110, 567 enc_init_data, 568 &link_enc_feature, 569 &link_enc_regs[enc_init_data->transmitter], 570 &link_enc_aux_regs[enc_init_data->channel - 1], 571 &link_enc_hpd_regs[enc_init_data->hpd_source]); 572 return &enc110->base; 573 } 574 575 struct output_pixel_processor *dce100_opp_create( 576 struct dc_context *ctx, 577 uint32_t inst) 578 { 579 struct dce110_opp *opp = 580 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 581 582 if (!opp) 583 return NULL; 584 585 dce110_opp_construct(opp, 586 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 587 return &opp->base; 588 } 589 590 struct aux_engine *dce100_aux_engine_create( 591 struct dc_context *ctx, 592 uint32_t inst) 593 { 594 struct aux_engine_dce110 *aux_engine = 595 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 596 597 if (!aux_engine) 598 return NULL; 599 600 dce110_aux_engine_construct(aux_engine, ctx, inst, 601 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 602 &aux_engine_regs[inst]); 603 604 return &aux_engine->base; 605 } 606 607 struct clock_source *dce100_clock_source_create( 608 struct dc_context *ctx, 609 struct dc_bios *bios, 610 enum clock_source_id id, 611 const struct dce110_clk_src_regs *regs, 612 bool dp_clk_src) 613 { 614 struct dce110_clk_src *clk_src = 615 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 616 617 if (!clk_src) 618 return NULL; 619 620 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 621 regs, &cs_shift, &cs_mask)) { 622 clk_src->base.dp_clk_src = dp_clk_src; 623 return &clk_src->base; 624 } 625 626 BREAK_TO_DEBUGGER(); 627 return NULL; 628 } 629 630 void dce100_clock_source_destroy(struct clock_source **clk_src) 631 { 632 kfree(TO_DCE110_CLK_SRC(*clk_src)); 633 *clk_src = NULL; 634 } 635 636 static void destruct(struct dce110_resource_pool *pool) 637 { 638 unsigned int i; 639 640 for (i = 0; i < pool->base.pipe_count; i++) { 641 if (pool->base.opps[i] != NULL) 642 dce110_opp_destroy(&pool->base.opps[i]); 643 644 if (pool->base.transforms[i] != NULL) 645 dce100_transform_destroy(&pool->base.transforms[i]); 646 647 if (pool->base.ipps[i] != NULL) 648 dce_ipp_destroy(&pool->base.ipps[i]); 649 650 if (pool->base.mis[i] != NULL) { 651 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 652 pool->base.mis[i] = NULL; 653 } 654 655 if (pool->base.timing_generators[i] != NULL) { 656 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 657 pool->base.timing_generators[i] = NULL; 658 } 659 660 if (pool->base.engines[i] != NULL) 661 dce110_engine_destroy(&pool->base.engines[i]); 662 663 } 664 665 for (i = 0; i < pool->base.stream_enc_count; i++) { 666 if (pool->base.stream_enc[i] != NULL) 667 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 668 } 669 670 for (i = 0; i < pool->base.clk_src_count; i++) { 671 if (pool->base.clock_sources[i] != NULL) 672 dce100_clock_source_destroy(&pool->base.clock_sources[i]); 673 } 674 675 if (pool->base.dp_clock_source != NULL) 676 dce100_clock_source_destroy(&pool->base.dp_clock_source); 677 678 for (i = 0; i < pool->base.audio_count; i++) { 679 if (pool->base.audios[i] != NULL) 680 dce_aud_destroy(&pool->base.audios[i]); 681 } 682 683 if (pool->base.dccg != NULL) 684 dce_dccg_destroy(&pool->base.dccg); 685 686 if (pool->base.abm != NULL) 687 dce_abm_destroy(&pool->base.abm); 688 689 if (pool->base.dmcu != NULL) 690 dce_dmcu_destroy(&pool->base.dmcu); 691 692 if (pool->base.irqs != NULL) 693 dal_irq_service_destroy(&pool->base.irqs); 694 } 695 696 static enum dc_status build_mapped_resource( 697 const struct dc *dc, 698 struct dc_state *context, 699 struct dc_stream_state *stream) 700 { 701 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 702 703 if (!pipe_ctx) 704 return DC_ERROR_UNEXPECTED; 705 706 dce110_resource_build_pipe_hw_param(pipe_ctx); 707 708 resource_build_info_frame(pipe_ctx); 709 710 return DC_OK; 711 } 712 713 bool dce100_validate_bandwidth( 714 struct dc *dc, 715 struct dc_state *context) 716 { 717 int i; 718 bool at_least_one_pipe = false; 719 720 for (i = 0; i < dc->res_pool->pipe_count; i++) { 721 if (context->res_ctx.pipe_ctx[i].stream) 722 at_least_one_pipe = true; 723 } 724 725 if (at_least_one_pipe) { 726 /* TODO implement when needed but for now hardcode max value*/ 727 context->bw.dce.dispclk_khz = 681000; 728 context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER; 729 } else { 730 context->bw.dce.dispclk_khz = 0; 731 context->bw.dce.yclk_khz = 0; 732 } 733 734 return true; 735 } 736 737 static bool dce100_validate_surface_sets( 738 struct dc_state *context) 739 { 740 int i; 741 742 for (i = 0; i < context->stream_count; i++) { 743 if (context->stream_status[i].plane_count == 0) 744 continue; 745 746 if (context->stream_status[i].plane_count > 1) 747 return false; 748 749 if (context->stream_status[i].plane_states[0]->format 750 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 751 return false; 752 } 753 754 return true; 755 } 756 757 enum dc_status dce100_validate_global( 758 struct dc *dc, 759 struct dc_state *context) 760 { 761 if (!dce100_validate_surface_sets(context)) 762 return DC_FAIL_SURFACE_VALIDATE; 763 764 return DC_OK; 765 } 766 767 enum dc_status dce100_add_stream_to_ctx( 768 struct dc *dc, 769 struct dc_state *new_ctx, 770 struct dc_stream_state *dc_stream) 771 { 772 enum dc_status result = DC_ERROR_UNEXPECTED; 773 774 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 775 776 if (result == DC_OK) 777 result = resource_map_clock_resources(dc, new_ctx, dc_stream); 778 779 if (result == DC_OK) 780 result = build_mapped_resource(dc, new_ctx, dc_stream); 781 782 return result; 783 } 784 785 static void dce100_destroy_resource_pool(struct resource_pool **pool) 786 { 787 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 788 789 destruct(dce110_pool); 790 kfree(dce110_pool); 791 *pool = NULL; 792 } 793 794 enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) 795 { 796 797 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 798 return DC_OK; 799 800 return DC_FAIL_SURFACE_VALIDATE; 801 } 802 803 static const struct resource_funcs dce100_res_pool_funcs = { 804 .destroy = dce100_destroy_resource_pool, 805 .link_enc_create = dce100_link_encoder_create, 806 .validate_bandwidth = dce100_validate_bandwidth, 807 .validate_plane = dce100_validate_plane, 808 .add_stream_to_ctx = dce100_add_stream_to_ctx, 809 .validate_global = dce100_validate_global 810 }; 811 812 static bool construct( 813 uint8_t num_virtual_links, 814 struct dc *dc, 815 struct dce110_resource_pool *pool) 816 { 817 unsigned int i; 818 struct dc_context *ctx = dc->ctx; 819 struct dc_firmware_info info; 820 struct dc_bios *bp; 821 struct dm_pp_static_clock_info static_clk_info = {0}; 822 823 ctx->dc_bios->regs = &bios_regs; 824 825 pool->base.res_cap = &res_cap; 826 pool->base.funcs = &dce100_res_pool_funcs; 827 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 828 829 bp = ctx->dc_bios; 830 831 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 832 info.external_clock_source_frequency_for_dp != 0) { 833 pool->base.dp_clock_source = 834 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 835 836 pool->base.clock_sources[0] = 837 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 838 pool->base.clock_sources[1] = 839 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 840 pool->base.clock_sources[2] = 841 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 842 pool->base.clk_src_count = 3; 843 844 } else { 845 pool->base.dp_clock_source = 846 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 847 848 pool->base.clock_sources[0] = 849 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 850 pool->base.clock_sources[1] = 851 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 852 pool->base.clk_src_count = 2; 853 } 854 855 if (pool->base.dp_clock_source == NULL) { 856 dm_error("DC: failed to create dp clock source!\n"); 857 BREAK_TO_DEBUGGER(); 858 goto res_create_fail; 859 } 860 861 for (i = 0; i < pool->base.clk_src_count; i++) { 862 if (pool->base.clock_sources[i] == NULL) { 863 dm_error("DC: failed to create clock sources!\n"); 864 BREAK_TO_DEBUGGER(); 865 goto res_create_fail; 866 } 867 } 868 869 pool->base.dccg = dce_dccg_create(ctx, 870 &disp_clk_regs, 871 &disp_clk_shift, 872 &disp_clk_mask); 873 if (pool->base.dccg == NULL) { 874 dm_error("DC: failed to create display clock!\n"); 875 BREAK_TO_DEBUGGER(); 876 goto res_create_fail; 877 } 878 879 pool->base.dmcu = dce_dmcu_create(ctx, 880 &dmcu_regs, 881 &dmcu_shift, 882 &dmcu_mask); 883 if (pool->base.dmcu == NULL) { 884 dm_error("DC: failed to create dmcu!\n"); 885 BREAK_TO_DEBUGGER(); 886 goto res_create_fail; 887 } 888 889 pool->base.abm = dce_abm_create(ctx, 890 &abm_regs, 891 &abm_shift, 892 &abm_mask); 893 if (pool->base.abm == NULL) { 894 dm_error("DC: failed to create abm!\n"); 895 BREAK_TO_DEBUGGER(); 896 goto res_create_fail; 897 } 898 899 /* get static clock information for PPLIB or firmware, save 900 * max_clock_state 901 */ 902 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 903 pool->base.dccg->max_clks_state = 904 static_clk_info.max_clocks_state; 905 { 906 struct irq_service_init_data init_data; 907 init_data.ctx = dc->ctx; 908 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 909 if (!pool->base.irqs) 910 goto res_create_fail; 911 } 912 913 /************************************************* 914 * Resource + asic cap harcoding * 915 *************************************************/ 916 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 917 pool->base.pipe_count = res_cap.num_timing_generator; 918 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 919 dc->caps.max_downscale_ratio = 200; 920 dc->caps.i2c_speed_in_khz = 40; 921 dc->caps.max_cursor_size = 128; 922 dc->caps.dual_link_dvi = true; 923 dc->caps.disable_dp_clk_share = true; 924 for (i = 0; i < pool->base.pipe_count; i++) { 925 pool->base.timing_generators[i] = 926 dce100_timing_generator_create( 927 ctx, 928 i, 929 &dce100_tg_offsets[i]); 930 if (pool->base.timing_generators[i] == NULL) { 931 BREAK_TO_DEBUGGER(); 932 dm_error("DC: failed to create tg!\n"); 933 goto res_create_fail; 934 } 935 936 pool->base.mis[i] = dce100_mem_input_create(ctx, i); 937 if (pool->base.mis[i] == NULL) { 938 BREAK_TO_DEBUGGER(); 939 dm_error( 940 "DC: failed to create memory input!\n"); 941 goto res_create_fail; 942 } 943 944 pool->base.ipps[i] = dce100_ipp_create(ctx, i); 945 if (pool->base.ipps[i] == NULL) { 946 BREAK_TO_DEBUGGER(); 947 dm_error( 948 "DC: failed to create input pixel processor!\n"); 949 goto res_create_fail; 950 } 951 952 pool->base.transforms[i] = dce100_transform_create(ctx, i); 953 if (pool->base.transforms[i] == NULL) { 954 BREAK_TO_DEBUGGER(); 955 dm_error( 956 "DC: failed to create transform!\n"); 957 goto res_create_fail; 958 } 959 960 pool->base.opps[i] = dce100_opp_create(ctx, i); 961 if (pool->base.opps[i] == NULL) { 962 BREAK_TO_DEBUGGER(); 963 dm_error( 964 "DC: failed to create output pixel processor!\n"); 965 goto res_create_fail; 966 } 967 } 968 969 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 970 pool->base.engines[i] = dce100_aux_engine_create(ctx, i); 971 if (pool->base.engines[i] == NULL) { 972 BREAK_TO_DEBUGGER(); 973 dm_error( 974 "DC:failed to create aux engine!!\n"); 975 goto res_create_fail; 976 } 977 } 978 979 dc->caps.max_planes = pool->base.pipe_count; 980 981 if (!resource_construct(num_virtual_links, dc, &pool->base, 982 &res_create_funcs)) 983 goto res_create_fail; 984 985 /* Create hardware sequencer */ 986 dce100_hw_sequencer_construct(dc); 987 return true; 988 989 res_create_fail: 990 destruct(pool); 991 992 return false; 993 } 994 995 struct resource_pool *dce100_create_resource_pool( 996 uint8_t num_virtual_links, 997 struct dc *dc) 998 { 999 struct dce110_resource_pool *pool = 1000 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1001 1002 if (!pool) 1003 return NULL; 1004 1005 if (construct(num_virtual_links, dc, pool)) 1006 return &pool->base; 1007 1008 BREAK_TO_DEBUGGER(); 1009 return NULL; 1010 } 1011 1012