1*5ca02815Sjsg /*
2*5ca02815Sjsg * Copyright 2021 Advanced Micro Devices, Inc.
3*5ca02815Sjsg *
4*5ca02815Sjsg * Permission is hereby granted, free of charge, to any person obtaining a
5*5ca02815Sjsg * copy of this software and associated documentation files (the "Software"),
6*5ca02815Sjsg * to deal in the Software without restriction, including without limitation
7*5ca02815Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*5ca02815Sjsg * and/or sell copies of the Software, and to permit persons to whom the
9*5ca02815Sjsg * Software is furnished to do so, subject to the following conditions:
10*5ca02815Sjsg *
11*5ca02815Sjsg * The above copyright notice and this permission notice shall be included in
12*5ca02815Sjsg * all copies or substantial portions of the Software.
13*5ca02815Sjsg *
14*5ca02815Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*5ca02815Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*5ca02815Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*5ca02815Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*5ca02815Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*5ca02815Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*5ca02815Sjsg * OTHER DEALINGS IN THE SOFTWARE.
21*5ca02815Sjsg *
22*5ca02815Sjsg * Authors: AMD
23*5ca02815Sjsg *
24*5ca02815Sjsg */
25*5ca02815Sjsg
26*5ca02815Sjsg #include "dce/dce_dmcu.h"
27*5ca02815Sjsg #include "dc_edid_parser.h"
28*5ca02815Sjsg
dc_edid_parser_send_cea(struct dc * dc,int offset,int total_length,uint8_t * data,int length)29*5ca02815Sjsg bool dc_edid_parser_send_cea(struct dc *dc,
30*5ca02815Sjsg int offset,
31*5ca02815Sjsg int total_length,
32*5ca02815Sjsg uint8_t *data,
33*5ca02815Sjsg int length)
34*5ca02815Sjsg {
35*5ca02815Sjsg struct dmcu *dmcu = dc->res_pool->dmcu;
36*5ca02815Sjsg
37*5ca02815Sjsg if (dmcu &&
38*5ca02815Sjsg dmcu->funcs->is_dmcu_initialized(dmcu) &&
39*5ca02815Sjsg dmcu->funcs->send_edid_cea) {
40*5ca02815Sjsg return dmcu->funcs->send_edid_cea(dmcu,
41*5ca02815Sjsg offset,
42*5ca02815Sjsg total_length,
43*5ca02815Sjsg data,
44*5ca02815Sjsg length);
45*5ca02815Sjsg }
46*5ca02815Sjsg
47*5ca02815Sjsg return false;
48*5ca02815Sjsg }
49*5ca02815Sjsg
dc_edid_parser_recv_cea_ack(struct dc * dc,int * offset)50*5ca02815Sjsg bool dc_edid_parser_recv_cea_ack(struct dc *dc, int *offset)
51*5ca02815Sjsg {
52*5ca02815Sjsg struct dmcu *dmcu = dc->res_pool->dmcu;
53*5ca02815Sjsg
54*5ca02815Sjsg if (dmcu &&
55*5ca02815Sjsg dmcu->funcs->is_dmcu_initialized(dmcu) &&
56*5ca02815Sjsg dmcu->funcs->recv_edid_cea_ack) {
57*5ca02815Sjsg return dmcu->funcs->recv_edid_cea_ack(dmcu, offset);
58*5ca02815Sjsg }
59*5ca02815Sjsg
60*5ca02815Sjsg return false;
61*5ca02815Sjsg }
62*5ca02815Sjsg
dc_edid_parser_recv_amd_vsdb(struct dc * dc,int * version,int * min_frame_rate,int * max_frame_rate)63*5ca02815Sjsg bool dc_edid_parser_recv_amd_vsdb(struct dc *dc,
64*5ca02815Sjsg int *version,
65*5ca02815Sjsg int *min_frame_rate,
66*5ca02815Sjsg int *max_frame_rate)
67*5ca02815Sjsg {
68*5ca02815Sjsg struct dmcu *dmcu = dc->res_pool->dmcu;
69*5ca02815Sjsg
70*5ca02815Sjsg if (dmcu &&
71*5ca02815Sjsg dmcu->funcs->is_dmcu_initialized(dmcu) &&
72*5ca02815Sjsg dmcu->funcs->recv_amd_vsdb) {
73*5ca02815Sjsg return dmcu->funcs->recv_amd_vsdb(dmcu,
74*5ca02815Sjsg version,
75*5ca02815Sjsg min_frame_rate,
76*5ca02815Sjsg max_frame_rate);
77*5ca02815Sjsg }
78*5ca02815Sjsg
79*5ca02815Sjsg return false;
80*5ca02815Sjsg }
81