1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services_types.h" 27 #include "dc.h" 28 #include "dc/inc/core_types.h" 29 30 #include "vid.h" 31 #include "amdgpu.h" 32 #include "amdgpu_display.h" 33 #include "atom.h" 34 #include "amdgpu_dm.h" 35 #include "amdgpu_pm.h" 36 37 #include "amd_shared.h" 38 #include "amdgpu_dm_irq.h" 39 #include "dm_helpers.h" 40 #include "dm_services_types.h" 41 #include "amdgpu_dm_mst_types.h" 42 #if defined(CONFIG_DEBUG_FS) 43 #include "amdgpu_dm_debugfs.h" 44 #endif 45 46 #include "ivsrcid/ivsrcid_vislands30.h" 47 48 #include <linux/module.h> 49 #include <linux/moduleparam.h> 50 #include <linux/version.h> 51 #include <linux/types.h> 52 #include <linux/pm_runtime.h> 53 54 #include <drm/drmP.h> 55 #include <drm/drm_atomic.h> 56 #include <drm/drm_atomic_helper.h> 57 #include <drm/drm_dp_mst_helper.h> 58 #include <drm/drm_fb_helper.h> 59 #include <drm/drm_edid.h> 60 61 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 62 #include "ivsrcid/irqsrcs_dcn_1_0.h" 63 64 #include "dcn/dcn_1_0_offset.h" 65 #include "dcn/dcn_1_0_sh_mask.h" 66 #include "soc15_hw_ip.h" 67 #include "vega10_ip_offset.h" 68 69 #include "soc15_common.h" 70 #endif 71 72 #include "modules/inc/mod_freesync.h" 73 74 #include "i2caux_interface.h" 75 76 /* basic init/fini API */ 77 static int amdgpu_dm_init(struct amdgpu_device *adev); 78 static void amdgpu_dm_fini(struct amdgpu_device *adev); 79 80 /* initializes drm_device display related structures, based on the information 81 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 82 * drm_encoder, drm_mode_config 83 * 84 * Returns 0 on success 85 */ 86 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 87 /* removes and deallocates the drm structures, created by the above function */ 88 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 89 90 static void 91 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector); 92 93 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 94 struct amdgpu_plane *aplane, 95 unsigned long possible_crtcs); 96 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 97 struct drm_plane *plane, 98 uint32_t link_index); 99 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 100 struct amdgpu_dm_connector *amdgpu_dm_connector, 101 uint32_t link_index, 102 struct amdgpu_encoder *amdgpu_encoder); 103 static int amdgpu_dm_encoder_init(struct drm_device *dev, 104 struct amdgpu_encoder *aencoder, 105 uint32_t link_index); 106 107 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); 108 109 static int amdgpu_dm_atomic_commit(struct drm_device *dev, 110 struct drm_atomic_state *state, 111 bool nonblock); 112 113 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); 114 115 static int amdgpu_dm_atomic_check(struct drm_device *dev, 116 struct drm_atomic_state *state); 117 118 119 120 121 static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = { 122 DRM_PLANE_TYPE_PRIMARY, 123 DRM_PLANE_TYPE_PRIMARY, 124 DRM_PLANE_TYPE_PRIMARY, 125 DRM_PLANE_TYPE_PRIMARY, 126 DRM_PLANE_TYPE_PRIMARY, 127 DRM_PLANE_TYPE_PRIMARY, 128 }; 129 130 static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = { 131 DRM_PLANE_TYPE_PRIMARY, 132 DRM_PLANE_TYPE_PRIMARY, 133 DRM_PLANE_TYPE_PRIMARY, 134 DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */ 135 }; 136 137 static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = { 138 DRM_PLANE_TYPE_PRIMARY, 139 DRM_PLANE_TYPE_PRIMARY, 140 DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */ 141 }; 142 143 /* 144 * dm_vblank_get_counter 145 * 146 * @brief 147 * Get counter for number of vertical blanks 148 * 149 * @param 150 * struct amdgpu_device *adev - [in] desired amdgpu device 151 * int disp_idx - [in] which CRTC to get the counter from 152 * 153 * @return 154 * Counter for vertical blanks 155 */ 156 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 157 { 158 if (crtc >= adev->mode_info.num_crtc) 159 return 0; 160 else { 161 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 162 struct dm_crtc_state *acrtc_state = to_dm_crtc_state( 163 acrtc->base.state); 164 165 166 if (acrtc_state->stream == NULL) { 167 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 168 crtc); 169 return 0; 170 } 171 172 return dc_stream_get_vblank_counter(acrtc_state->stream); 173 } 174 } 175 176 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 177 u32 *vbl, u32 *position) 178 { 179 uint32_t v_blank_start, v_blank_end, h_position, v_position; 180 181 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 182 return -EINVAL; 183 else { 184 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 185 struct dm_crtc_state *acrtc_state = to_dm_crtc_state( 186 acrtc->base.state); 187 188 if (acrtc_state->stream == NULL) { 189 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 190 crtc); 191 return 0; 192 } 193 194 /* 195 * TODO rework base driver to use values directly. 196 * for now parse it back into reg-format 197 */ 198 dc_stream_get_scanoutpos(acrtc_state->stream, 199 &v_blank_start, 200 &v_blank_end, 201 &h_position, 202 &v_position); 203 204 *position = v_position | (h_position << 16); 205 *vbl = v_blank_start | (v_blank_end << 16); 206 } 207 208 return 0; 209 } 210 211 static bool dm_is_idle(void *handle) 212 { 213 /* XXX todo */ 214 return true; 215 } 216 217 static int dm_wait_for_idle(void *handle) 218 { 219 /* XXX todo */ 220 return 0; 221 } 222 223 static bool dm_check_soft_reset(void *handle) 224 { 225 return false; 226 } 227 228 static int dm_soft_reset(void *handle) 229 { 230 /* XXX todo */ 231 return 0; 232 } 233 234 static struct amdgpu_crtc * 235 get_crtc_by_otg_inst(struct amdgpu_device *adev, 236 int otg_inst) 237 { 238 struct drm_device *dev = adev->ddev; 239 struct drm_crtc *crtc; 240 struct amdgpu_crtc *amdgpu_crtc; 241 242 /* 243 * following if is check inherited from both functions where this one is 244 * used now. Need to be checked why it could happen. 245 */ 246 if (otg_inst == -1) { 247 WARN_ON(1); 248 return adev->mode_info.crtcs[0]; 249 } 250 251 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 252 amdgpu_crtc = to_amdgpu_crtc(crtc); 253 254 if (amdgpu_crtc->otg_inst == otg_inst) 255 return amdgpu_crtc; 256 } 257 258 return NULL; 259 } 260 261 static void dm_pflip_high_irq(void *interrupt_params) 262 { 263 struct amdgpu_crtc *amdgpu_crtc; 264 struct common_irq_params *irq_params = interrupt_params; 265 struct amdgpu_device *adev = irq_params->adev; 266 unsigned long flags; 267 268 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); 269 270 /* IRQ could occur when in initial stage */ 271 /*TODO work and BO cleanup */ 272 if (amdgpu_crtc == NULL) { 273 DRM_DEBUG_DRIVER("CRTC is null, returning.\n"); 274 return; 275 } 276 277 spin_lock_irqsave(&adev->ddev->event_lock, flags); 278 279 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 280 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n", 281 amdgpu_crtc->pflip_status, 282 AMDGPU_FLIP_SUBMITTED, 283 amdgpu_crtc->crtc_id, 284 amdgpu_crtc); 285 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 286 return; 287 } 288 289 290 /* wakeup usersapce */ 291 if (amdgpu_crtc->event) { 292 /* Update to correct count/ts if racing with vblank irq */ 293 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); 294 295 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event); 296 297 /* page flip completed. clean up */ 298 amdgpu_crtc->event = NULL; 299 300 } else 301 WARN_ON(1); 302 303 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 304 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 305 306 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n", 307 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc); 308 309 drm_crtc_vblank_put(&amdgpu_crtc->base); 310 } 311 312 static void dm_crtc_high_irq(void *interrupt_params) 313 { 314 struct common_irq_params *irq_params = interrupt_params; 315 struct amdgpu_device *adev = irq_params->adev; 316 uint8_t crtc_index = 0; 317 struct amdgpu_crtc *acrtc; 318 319 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); 320 321 if (acrtc) 322 crtc_index = acrtc->crtc_id; 323 324 drm_handle_vblank(adev->ddev, crtc_index); 325 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); 326 } 327 328 static int dm_set_clockgating_state(void *handle, 329 enum amd_clockgating_state state) 330 { 331 return 0; 332 } 333 334 static int dm_set_powergating_state(void *handle, 335 enum amd_powergating_state state) 336 { 337 return 0; 338 } 339 340 /* Prototypes of private functions */ 341 static int dm_early_init(void* handle); 342 343 static void hotplug_notify_work_func(struct work_struct *work) 344 { 345 struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work); 346 struct drm_device *dev = dm->ddev; 347 348 drm_kms_helper_hotplug_event(dev); 349 } 350 351 /* Allocate memory for FBC compressed data */ 352 static void amdgpu_dm_fbc_init(struct drm_connector *connector) 353 { 354 struct drm_device *dev = connector->dev; 355 struct amdgpu_device *adev = dev->dev_private; 356 struct dm_comressor_info *compressor = &adev->dm.compressor; 357 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); 358 struct drm_display_mode *mode; 359 unsigned long max_size = 0; 360 361 if (adev->dm.dc->fbc_compressor == NULL) 362 return; 363 364 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) 365 return; 366 367 if (compressor->bo_ptr) 368 return; 369 370 371 list_for_each_entry(mode, &connector->modes, head) { 372 if (max_size < mode->htotal * mode->vtotal) 373 max_size = mode->htotal * mode->vtotal; 374 } 375 376 if (max_size) { 377 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, 378 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, 379 &compressor->gpu_addr, &compressor->cpu_addr); 380 381 if (r) 382 DRM_ERROR("DM: Failed to initialize FBC\n"); 383 else { 384 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; 385 DRM_INFO("DM: FBC alloc %lu\n", max_size*4); 386 } 387 388 } 389 390 } 391 392 393 /* Init display KMS 394 * 395 * Returns 0 on success 396 */ 397 static int amdgpu_dm_init(struct amdgpu_device *adev) 398 { 399 struct dc_init_data init_data; 400 adev->dm.ddev = adev->ddev; 401 adev->dm.adev = adev; 402 403 /* Zero all the fields */ 404 memset(&init_data, 0, sizeof(init_data)); 405 406 if(amdgpu_dm_irq_init(adev)) { 407 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); 408 goto error; 409 } 410 411 init_data.asic_id.chip_family = adev->family; 412 413 init_data.asic_id.pci_revision_id = adev->rev_id; 414 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 415 416 init_data.asic_id.vram_width = adev->gmc.vram_width; 417 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 418 init_data.asic_id.atombios_base_address = 419 adev->mode_info.atom_context->bios; 420 421 init_data.driver = adev; 422 423 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 424 425 if (!adev->dm.cgs_device) { 426 DRM_ERROR("amdgpu: failed to create cgs device.\n"); 427 goto error; 428 } 429 430 init_data.cgs_device = adev->dm.cgs_device; 431 432 adev->dm.dal = NULL; 433 434 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 435 436 /* 437 * TODO debug why this doesn't work on Raven 438 */ 439 if (adev->flags & AMD_IS_APU && 440 adev->asic_type >= CHIP_CARRIZO && 441 adev->asic_type < CHIP_RAVEN) 442 init_data.flags.gpu_vm_support = true; 443 444 /* Display Core create. */ 445 adev->dm.dc = dc_create(&init_data); 446 447 if (adev->dm.dc) { 448 DRM_INFO("Display Core initialized with v%s!\n", DC_VER); 449 } else { 450 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER); 451 goto error; 452 } 453 454 INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func); 455 456 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 457 if (!adev->dm.freesync_module) { 458 DRM_ERROR( 459 "amdgpu: failed to initialize freesync_module.\n"); 460 } else 461 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", 462 adev->dm.freesync_module); 463 464 amdgpu_dm_init_color_mod(); 465 466 if (amdgpu_dm_initialize_drm_device(adev)) { 467 DRM_ERROR( 468 "amdgpu: failed to initialize sw for display support.\n"); 469 goto error; 470 } 471 472 /* Update the actual used number of crtc */ 473 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 474 475 /* TODO: Add_display_info? */ 476 477 /* TODO use dynamic cursor width */ 478 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 479 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 480 481 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) { 482 DRM_ERROR( 483 "amdgpu: failed to initialize sw for display support.\n"); 484 goto error; 485 } 486 487 DRM_DEBUG_DRIVER("KMS initialized.\n"); 488 489 return 0; 490 error: 491 amdgpu_dm_fini(adev); 492 493 return -1; 494 } 495 496 static void amdgpu_dm_fini(struct amdgpu_device *adev) 497 { 498 amdgpu_dm_destroy_drm_device(&adev->dm); 499 /* 500 * TODO: pageflip, vlank interrupt 501 * 502 * amdgpu_dm_irq_fini(adev); 503 */ 504 505 if (adev->dm.cgs_device) { 506 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 507 adev->dm.cgs_device = NULL; 508 } 509 if (adev->dm.freesync_module) { 510 mod_freesync_destroy(adev->dm.freesync_module); 511 adev->dm.freesync_module = NULL; 512 } 513 /* DC Destroy TODO: Replace destroy DAL */ 514 if (adev->dm.dc) 515 dc_destroy(&adev->dm.dc); 516 return; 517 } 518 519 static int dm_sw_init(void *handle) 520 { 521 return 0; 522 } 523 524 static int dm_sw_fini(void *handle) 525 { 526 return 0; 527 } 528 529 static int detect_mst_link_for_all_connectors(struct drm_device *dev) 530 { 531 struct amdgpu_dm_connector *aconnector; 532 struct drm_connector *connector; 533 int ret = 0; 534 535 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 536 537 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 538 aconnector = to_amdgpu_dm_connector(connector); 539 if (aconnector->dc_link->type == dc_connection_mst_branch && 540 aconnector->mst_mgr.aux) { 541 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n", 542 aconnector, aconnector->base.base.id); 543 544 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 545 if (ret < 0) { 546 DRM_ERROR("DM_MST: Failed to start MST\n"); 547 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single; 548 return ret; 549 } 550 } 551 } 552 553 drm_modeset_unlock(&dev->mode_config.connection_mutex); 554 return ret; 555 } 556 557 static int dm_late_init(void *handle) 558 { 559 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 560 561 return detect_mst_link_for_all_connectors(adev->ddev); 562 } 563 564 static void s3_handle_mst(struct drm_device *dev, bool suspend) 565 { 566 struct amdgpu_dm_connector *aconnector; 567 struct drm_connector *connector; 568 struct drm_dp_mst_topology_mgr *mgr; 569 int ret; 570 bool need_hotplug = false; 571 572 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 573 574 list_for_each_entry(connector, &dev->mode_config.connector_list, 575 head) { 576 aconnector = to_amdgpu_dm_connector(connector); 577 if (aconnector->dc_link->type != dc_connection_mst_branch || 578 aconnector->mst_port) 579 continue; 580 581 mgr = &aconnector->mst_mgr; 582 583 if (suspend) { 584 drm_dp_mst_topology_mgr_suspend(mgr); 585 } else { 586 ret = drm_dp_mst_topology_mgr_resume(mgr); 587 if (ret < 0) { 588 drm_dp_mst_topology_mgr_set_mst(mgr, false); 589 need_hotplug = true; 590 } 591 } 592 } 593 594 drm_modeset_unlock(&dev->mode_config.connection_mutex); 595 596 if (need_hotplug) 597 drm_kms_helper_hotplug_event(dev); 598 } 599 600 static int dm_hw_init(void *handle) 601 { 602 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 603 /* Create DAL display manager */ 604 amdgpu_dm_init(adev); 605 amdgpu_dm_hpd_init(adev); 606 607 return 0; 608 } 609 610 static int dm_hw_fini(void *handle) 611 { 612 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 613 614 amdgpu_dm_hpd_fini(adev); 615 616 amdgpu_dm_irq_fini(adev); 617 amdgpu_dm_fini(adev); 618 return 0; 619 } 620 621 static int dm_suspend(void *handle) 622 { 623 struct amdgpu_device *adev = handle; 624 struct amdgpu_display_manager *dm = &adev->dm; 625 int ret = 0; 626 627 WARN_ON(adev->dm.cached_state); 628 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev); 629 630 s3_handle_mst(adev->ddev, true); 631 632 amdgpu_dm_irq_suspend(adev); 633 634 635 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 636 637 return ret; 638 } 639 640 static struct amdgpu_dm_connector * 641 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 642 struct drm_crtc *crtc) 643 { 644 uint32_t i; 645 struct drm_connector_state *new_con_state; 646 struct drm_connector *connector; 647 struct drm_crtc *crtc_from_state; 648 649 for_each_new_connector_in_state(state, connector, new_con_state, i) { 650 crtc_from_state = new_con_state->crtc; 651 652 if (crtc_from_state == crtc) 653 return to_amdgpu_dm_connector(connector); 654 } 655 656 return NULL; 657 } 658 659 static void emulated_link_detect(struct dc_link *link) 660 { 661 struct dc_sink_init_data sink_init_data = { 0 }; 662 struct display_sink_capability sink_caps = { 0 }; 663 enum dc_edid_status edid_status; 664 struct dc_context *dc_ctx = link->ctx; 665 struct dc_sink *sink = NULL; 666 struct dc_sink *prev_sink = NULL; 667 668 link->type = dc_connection_none; 669 prev_sink = link->local_sink; 670 671 if (prev_sink != NULL) 672 dc_sink_retain(prev_sink); 673 674 switch (link->connector_signal) { 675 case SIGNAL_TYPE_HDMI_TYPE_A: { 676 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 677 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 678 break; 679 } 680 681 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 682 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 683 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 684 break; 685 } 686 687 case SIGNAL_TYPE_DVI_DUAL_LINK: { 688 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 689 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 690 break; 691 } 692 693 case SIGNAL_TYPE_LVDS: { 694 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 695 sink_caps.signal = SIGNAL_TYPE_LVDS; 696 break; 697 } 698 699 case SIGNAL_TYPE_EDP: { 700 sink_caps.transaction_type = 701 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 702 sink_caps.signal = SIGNAL_TYPE_EDP; 703 break; 704 } 705 706 case SIGNAL_TYPE_DISPLAY_PORT: { 707 sink_caps.transaction_type = 708 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 709 sink_caps.signal = SIGNAL_TYPE_VIRTUAL; 710 break; 711 } 712 713 default: 714 DC_ERROR("Invalid connector type! signal:%d\n", 715 link->connector_signal); 716 return; 717 } 718 719 sink_init_data.link = link; 720 sink_init_data.sink_signal = sink_caps.signal; 721 722 sink = dc_sink_create(&sink_init_data); 723 if (!sink) { 724 DC_ERROR("Failed to create sink!\n"); 725 return; 726 } 727 728 link->local_sink = sink; 729 730 edid_status = dm_helpers_read_local_edid( 731 link->ctx, 732 link, 733 sink); 734 735 if (edid_status != EDID_OK) 736 DC_ERROR("Failed to read EDID"); 737 738 } 739 740 static int dm_resume(void *handle) 741 { 742 struct amdgpu_device *adev = handle; 743 struct drm_device *ddev = adev->ddev; 744 struct amdgpu_display_manager *dm = &adev->dm; 745 struct amdgpu_dm_connector *aconnector; 746 struct drm_connector *connector; 747 struct drm_crtc *crtc; 748 struct drm_crtc_state *new_crtc_state; 749 struct dm_crtc_state *dm_new_crtc_state; 750 struct drm_plane *plane; 751 struct drm_plane_state *new_plane_state; 752 struct dm_plane_state *dm_new_plane_state; 753 enum dc_connection_type new_connection_type = dc_connection_none; 754 int i; 755 756 /* power on hardware */ 757 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 758 759 /* program HPD filter */ 760 dc_resume(dm->dc); 761 762 /* On resume we need to rewrite the MSTM control bits to enamble MST*/ 763 s3_handle_mst(ddev, false); 764 765 /* 766 * early enable HPD Rx IRQ, should be done before set mode as short 767 * pulse interrupts are used for MST 768 */ 769 amdgpu_dm_irq_resume_early(adev); 770 771 /* Do detection*/ 772 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) { 773 aconnector = to_amdgpu_dm_connector(connector); 774 775 /* 776 * this is the case when traversing through already created 777 * MST connectors, should be skipped 778 */ 779 if (aconnector->mst_port) 780 continue; 781 782 mutex_lock(&aconnector->hpd_lock); 783 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) 784 DRM_ERROR("KMS: Failed to detect connector\n"); 785 786 if (aconnector->base.force && new_connection_type == dc_connection_none) 787 emulated_link_detect(aconnector->dc_link); 788 else 789 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 790 791 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 792 aconnector->fake_enable = false; 793 794 aconnector->dc_sink = NULL; 795 amdgpu_dm_update_connector_after_detect(aconnector); 796 mutex_unlock(&aconnector->hpd_lock); 797 } 798 799 /* Force mode set in atomic comit */ 800 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) 801 new_crtc_state->active_changed = true; 802 803 /* 804 * atomic_check is expected to create the dc states. We need to release 805 * them here, since they were duplicated as part of the suspend 806 * procedure. 807 */ 808 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 809 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 810 if (dm_new_crtc_state->stream) { 811 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 812 dc_stream_release(dm_new_crtc_state->stream); 813 dm_new_crtc_state->stream = NULL; 814 } 815 } 816 817 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 818 dm_new_plane_state = to_dm_plane_state(new_plane_state); 819 if (dm_new_plane_state->dc_state) { 820 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 821 dc_plane_state_release(dm_new_plane_state->dc_state); 822 dm_new_plane_state->dc_state = NULL; 823 } 824 } 825 826 drm_atomic_helper_resume(ddev, dm->cached_state); 827 828 dm->cached_state = NULL; 829 830 amdgpu_dm_irq_resume_late(adev); 831 832 return 0; 833 } 834 835 static const struct amd_ip_funcs amdgpu_dm_funcs = { 836 .name = "dm", 837 .early_init = dm_early_init, 838 .late_init = dm_late_init, 839 .sw_init = dm_sw_init, 840 .sw_fini = dm_sw_fini, 841 .hw_init = dm_hw_init, 842 .hw_fini = dm_hw_fini, 843 .suspend = dm_suspend, 844 .resume = dm_resume, 845 .is_idle = dm_is_idle, 846 .wait_for_idle = dm_wait_for_idle, 847 .check_soft_reset = dm_check_soft_reset, 848 .soft_reset = dm_soft_reset, 849 .set_clockgating_state = dm_set_clockgating_state, 850 .set_powergating_state = dm_set_powergating_state, 851 }; 852 853 const struct amdgpu_ip_block_version dm_ip_block = 854 { 855 .type = AMD_IP_BLOCK_TYPE_DCE, 856 .major = 1, 857 .minor = 0, 858 .rev = 0, 859 .funcs = &amdgpu_dm_funcs, 860 }; 861 862 863 static struct drm_atomic_state * 864 dm_atomic_state_alloc(struct drm_device *dev) 865 { 866 struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL); 867 868 if (!state) 869 return NULL; 870 871 if (drm_atomic_state_init(dev, &state->base) < 0) 872 goto fail; 873 874 return &state->base; 875 876 fail: 877 kfree(state); 878 return NULL; 879 } 880 881 static void 882 dm_atomic_state_clear(struct drm_atomic_state *state) 883 { 884 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 885 886 if (dm_state->context) { 887 dc_release_state(dm_state->context); 888 dm_state->context = NULL; 889 } 890 891 drm_atomic_state_default_clear(state); 892 } 893 894 static void 895 dm_atomic_state_alloc_free(struct drm_atomic_state *state) 896 { 897 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 898 drm_atomic_state_default_release(state); 899 kfree(dm_state); 900 } 901 902 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 903 .fb_create = amdgpu_display_user_framebuffer_create, 904 .output_poll_changed = drm_fb_helper_output_poll_changed, 905 .atomic_check = amdgpu_dm_atomic_check, 906 .atomic_commit = amdgpu_dm_atomic_commit, 907 .atomic_state_alloc = dm_atomic_state_alloc, 908 .atomic_state_clear = dm_atomic_state_clear, 909 .atomic_state_free = dm_atomic_state_alloc_free 910 }; 911 912 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 913 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail 914 }; 915 916 static void 917 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector) 918 { 919 struct drm_connector *connector = &aconnector->base; 920 struct drm_device *dev = connector->dev; 921 struct dc_sink *sink; 922 923 /* MST handled by drm_mst framework */ 924 if (aconnector->mst_mgr.mst_state == true) 925 return; 926 927 928 sink = aconnector->dc_link->local_sink; 929 930 /* Edid mgmt connector gets first update only in mode_valid hook and then 931 * the connector sink is set to either fake or physical sink depends on link status. 932 * don't do it here if u are during boot 933 */ 934 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED 935 && aconnector->dc_em_sink) { 936 937 /* For S3 resume with headless use eml_sink to fake stream 938 * because on resume connecotr->sink is set ti NULL 939 */ 940 mutex_lock(&dev->mode_config.mutex); 941 942 if (sink) { 943 if (aconnector->dc_sink) { 944 amdgpu_dm_remove_sink_from_freesync_module( 945 connector); 946 /* retain and release bellow are used for 947 * bump up refcount for sink because the link don't point 948 * to it anymore after disconnect so on next crtc to connector 949 * reshuffle by UMD we will get into unwanted dc_sink release 950 */ 951 if (aconnector->dc_sink != aconnector->dc_em_sink) 952 dc_sink_release(aconnector->dc_sink); 953 } 954 aconnector->dc_sink = sink; 955 amdgpu_dm_add_sink_to_freesync_module( 956 connector, aconnector->edid); 957 } else { 958 amdgpu_dm_remove_sink_from_freesync_module(connector); 959 if (!aconnector->dc_sink) 960 aconnector->dc_sink = aconnector->dc_em_sink; 961 else if (aconnector->dc_sink != aconnector->dc_em_sink) 962 dc_sink_retain(aconnector->dc_sink); 963 } 964 965 mutex_unlock(&dev->mode_config.mutex); 966 return; 967 } 968 969 /* 970 * TODO: temporary guard to look for proper fix 971 * if this sink is MST sink, we should not do anything 972 */ 973 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 974 return; 975 976 if (aconnector->dc_sink == sink) { 977 /* We got a DP short pulse (Link Loss, DP CTS, etc...). 978 * Do nothing!! */ 979 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n", 980 aconnector->connector_id); 981 return; 982 } 983 984 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", 985 aconnector->connector_id, aconnector->dc_sink, sink); 986 987 mutex_lock(&dev->mode_config.mutex); 988 989 /* 1. Update status of the drm connector 990 * 2. Send an event and let userspace tell us what to do */ 991 if (sink) { 992 /* TODO: check if we still need the S3 mode update workaround. 993 * If yes, put it here. */ 994 if (aconnector->dc_sink) 995 amdgpu_dm_remove_sink_from_freesync_module( 996 connector); 997 998 aconnector->dc_sink = sink; 999 if (sink->dc_edid.length == 0) { 1000 aconnector->edid = NULL; 1001 } else { 1002 aconnector->edid = 1003 (struct edid *) sink->dc_edid.raw_edid; 1004 1005 1006 drm_connector_update_edid_property(connector, 1007 aconnector->edid); 1008 } 1009 amdgpu_dm_add_sink_to_freesync_module(connector, aconnector->edid); 1010 1011 } else { 1012 amdgpu_dm_remove_sink_from_freesync_module(connector); 1013 drm_connector_update_edid_property(connector, NULL); 1014 aconnector->num_modes = 0; 1015 aconnector->dc_sink = NULL; 1016 aconnector->edid = NULL; 1017 } 1018 1019 mutex_unlock(&dev->mode_config.mutex); 1020 } 1021 1022 static void handle_hpd_irq(void *param) 1023 { 1024 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 1025 struct drm_connector *connector = &aconnector->base; 1026 struct drm_device *dev = connector->dev; 1027 enum dc_connection_type new_connection_type = dc_connection_none; 1028 1029 /* In case of failure or MST no need to update connector status or notify the OS 1030 * since (for MST case) MST does this in it's own context. 1031 */ 1032 mutex_lock(&aconnector->hpd_lock); 1033 1034 if (aconnector->fake_enable) 1035 aconnector->fake_enable = false; 1036 1037 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) 1038 DRM_ERROR("KMS: Failed to detect connector\n"); 1039 1040 if (aconnector->base.force && new_connection_type == dc_connection_none) { 1041 emulated_link_detect(aconnector->dc_link); 1042 1043 1044 drm_modeset_lock_all(dev); 1045 dm_restore_drm_connector_state(dev, connector); 1046 drm_modeset_unlock_all(dev); 1047 1048 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 1049 drm_kms_helper_hotplug_event(dev); 1050 1051 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) { 1052 amdgpu_dm_update_connector_after_detect(aconnector); 1053 1054 1055 drm_modeset_lock_all(dev); 1056 dm_restore_drm_connector_state(dev, connector); 1057 drm_modeset_unlock_all(dev); 1058 1059 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 1060 drm_kms_helper_hotplug_event(dev); 1061 } 1062 mutex_unlock(&aconnector->hpd_lock); 1063 1064 } 1065 1066 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector) 1067 { 1068 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 }; 1069 uint8_t dret; 1070 bool new_irq_handled = false; 1071 int dpcd_addr; 1072 int dpcd_bytes_to_read; 1073 1074 const int max_process_count = 30; 1075 int process_count = 0; 1076 1077 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link); 1078 1079 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) { 1080 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT; 1081 /* DPCD 0x200 - 0x201 for downstream IRQ */ 1082 dpcd_addr = DP_SINK_COUNT; 1083 } else { 1084 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI; 1085 /* DPCD 0x2002 - 0x2005 for downstream IRQ */ 1086 dpcd_addr = DP_SINK_COUNT_ESI; 1087 } 1088 1089 dret = drm_dp_dpcd_read( 1090 &aconnector->dm_dp_aux.aux, 1091 dpcd_addr, 1092 esi, 1093 dpcd_bytes_to_read); 1094 1095 while (dret == dpcd_bytes_to_read && 1096 process_count < max_process_count) { 1097 uint8_t retry; 1098 dret = 0; 1099 1100 process_count++; 1101 1102 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); 1103 /* handle HPD short pulse irq */ 1104 if (aconnector->mst_mgr.mst_state) 1105 drm_dp_mst_hpd_irq( 1106 &aconnector->mst_mgr, 1107 esi, 1108 &new_irq_handled); 1109 1110 if (new_irq_handled) { 1111 /* ACK at DPCD to notify down stream */ 1112 const int ack_dpcd_bytes_to_write = 1113 dpcd_bytes_to_read - 1; 1114 1115 for (retry = 0; retry < 3; retry++) { 1116 uint8_t wret; 1117 1118 wret = drm_dp_dpcd_write( 1119 &aconnector->dm_dp_aux.aux, 1120 dpcd_addr + 1, 1121 &esi[1], 1122 ack_dpcd_bytes_to_write); 1123 if (wret == ack_dpcd_bytes_to_write) 1124 break; 1125 } 1126 1127 /* check if there is new irq to be handle */ 1128 dret = drm_dp_dpcd_read( 1129 &aconnector->dm_dp_aux.aux, 1130 dpcd_addr, 1131 esi, 1132 dpcd_bytes_to_read); 1133 1134 new_irq_handled = false; 1135 } else { 1136 break; 1137 } 1138 } 1139 1140 if (process_count == max_process_count) 1141 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); 1142 } 1143 1144 static void handle_hpd_rx_irq(void *param) 1145 { 1146 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 1147 struct drm_connector *connector = &aconnector->base; 1148 struct drm_device *dev = connector->dev; 1149 struct dc_link *dc_link = aconnector->dc_link; 1150 bool is_mst_root_connector = aconnector->mst_mgr.mst_state; 1151 enum dc_connection_type new_connection_type = dc_connection_none; 1152 1153 /* TODO:Temporary add mutex to protect hpd interrupt not have a gpio 1154 * conflict, after implement i2c helper, this mutex should be 1155 * retired. 1156 */ 1157 if (dc_link->type != dc_connection_mst_branch) 1158 mutex_lock(&aconnector->hpd_lock); 1159 1160 if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) && 1161 !is_mst_root_connector) { 1162 /* Downstream Port status changed. */ 1163 if (!dc_link_detect_sink(dc_link, &new_connection_type)) 1164 DRM_ERROR("KMS: Failed to detect connector\n"); 1165 1166 if (aconnector->base.force && new_connection_type == dc_connection_none) { 1167 emulated_link_detect(dc_link); 1168 1169 if (aconnector->fake_enable) 1170 aconnector->fake_enable = false; 1171 1172 amdgpu_dm_update_connector_after_detect(aconnector); 1173 1174 1175 drm_modeset_lock_all(dev); 1176 dm_restore_drm_connector_state(dev, connector); 1177 drm_modeset_unlock_all(dev); 1178 1179 drm_kms_helper_hotplug_event(dev); 1180 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) { 1181 1182 if (aconnector->fake_enable) 1183 aconnector->fake_enable = false; 1184 1185 amdgpu_dm_update_connector_after_detect(aconnector); 1186 1187 1188 drm_modeset_lock_all(dev); 1189 dm_restore_drm_connector_state(dev, connector); 1190 drm_modeset_unlock_all(dev); 1191 1192 drm_kms_helper_hotplug_event(dev); 1193 } 1194 } 1195 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || 1196 (dc_link->type == dc_connection_mst_branch)) 1197 dm_handle_hpd_rx_irq(aconnector); 1198 1199 if (dc_link->type != dc_connection_mst_branch) 1200 mutex_unlock(&aconnector->hpd_lock); 1201 } 1202 1203 static void register_hpd_handlers(struct amdgpu_device *adev) 1204 { 1205 struct drm_device *dev = adev->ddev; 1206 struct drm_connector *connector; 1207 struct amdgpu_dm_connector *aconnector; 1208 const struct dc_link *dc_link; 1209 struct dc_interrupt_params int_params = {0}; 1210 1211 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 1212 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 1213 1214 list_for_each_entry(connector, 1215 &dev->mode_config.connector_list, head) { 1216 1217 aconnector = to_amdgpu_dm_connector(connector); 1218 dc_link = aconnector->dc_link; 1219 1220 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) { 1221 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 1222 int_params.irq_source = dc_link->irq_source_hpd; 1223 1224 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1225 handle_hpd_irq, 1226 (void *) aconnector); 1227 } 1228 1229 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) { 1230 1231 /* Also register for DP short pulse (hpd_rx). */ 1232 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 1233 int_params.irq_source = dc_link->irq_source_hpd_rx; 1234 1235 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1236 handle_hpd_rx_irq, 1237 (void *) aconnector); 1238 } 1239 } 1240 } 1241 1242 /* Register IRQ sources and initialize IRQ callbacks */ 1243 static int dce110_register_irq_handlers(struct amdgpu_device *adev) 1244 { 1245 struct dc *dc = adev->dm.dc; 1246 struct common_irq_params *c_irq_params; 1247 struct dc_interrupt_params int_params = {0}; 1248 int r; 1249 int i; 1250 unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY; 1251 1252 if (adev->asic_type == CHIP_VEGA10 || 1253 adev->asic_type == CHIP_VEGA12 || 1254 adev->asic_type == CHIP_VEGA20 || 1255 adev->asic_type == CHIP_RAVEN) 1256 client_id = SOC15_IH_CLIENTID_DCE; 1257 1258 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 1259 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 1260 1261 /* Actions of amdgpu_irq_add_id(): 1262 * 1. Register a set() function with base driver. 1263 * Base driver will call set() function to enable/disable an 1264 * interrupt in DC hardware. 1265 * 2. Register amdgpu_dm_irq_handler(). 1266 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 1267 * coming from DC hardware. 1268 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 1269 * for acknowledging and handling. */ 1270 1271 /* Use VBLANK interrupt */ 1272 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { 1273 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); 1274 if (r) { 1275 DRM_ERROR("Failed to add crtc irq id!\n"); 1276 return r; 1277 } 1278 1279 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1280 int_params.irq_source = 1281 dc_interrupt_to_irq_source(dc, i, 0); 1282 1283 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 1284 1285 c_irq_params->adev = adev; 1286 c_irq_params->irq_src = int_params.irq_source; 1287 1288 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1289 dm_crtc_high_irq, c_irq_params); 1290 } 1291 1292 /* Use GRPH_PFLIP interrupt */ 1293 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 1294 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 1295 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 1296 if (r) { 1297 DRM_ERROR("Failed to add page flip irq id!\n"); 1298 return r; 1299 } 1300 1301 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1302 int_params.irq_source = 1303 dc_interrupt_to_irq_source(dc, i, 0); 1304 1305 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 1306 1307 c_irq_params->adev = adev; 1308 c_irq_params->irq_src = int_params.irq_source; 1309 1310 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1311 dm_pflip_high_irq, c_irq_params); 1312 1313 } 1314 1315 /* HPD */ 1316 r = amdgpu_irq_add_id(adev, client_id, 1317 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 1318 if (r) { 1319 DRM_ERROR("Failed to add hpd irq id!\n"); 1320 return r; 1321 } 1322 1323 register_hpd_handlers(adev); 1324 1325 return 0; 1326 } 1327 1328 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 1329 /* Register IRQ sources and initialize IRQ callbacks */ 1330 static int dcn10_register_irq_handlers(struct amdgpu_device *adev) 1331 { 1332 struct dc *dc = adev->dm.dc; 1333 struct common_irq_params *c_irq_params; 1334 struct dc_interrupt_params int_params = {0}; 1335 int r; 1336 int i; 1337 1338 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 1339 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 1340 1341 /* Actions of amdgpu_irq_add_id(): 1342 * 1. Register a set() function with base driver. 1343 * Base driver will call set() function to enable/disable an 1344 * interrupt in DC hardware. 1345 * 2. Register amdgpu_dm_irq_handler(). 1346 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 1347 * coming from DC hardware. 1348 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 1349 * for acknowledging and handling. 1350 * */ 1351 1352 /* Use VSTARTUP interrupt */ 1353 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; 1354 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; 1355 i++) { 1356 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); 1357 1358 if (r) { 1359 DRM_ERROR("Failed to add crtc irq id!\n"); 1360 return r; 1361 } 1362 1363 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1364 int_params.irq_source = 1365 dc_interrupt_to_irq_source(dc, i, 0); 1366 1367 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 1368 1369 c_irq_params->adev = adev; 1370 c_irq_params->irq_src = int_params.irq_source; 1371 1372 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1373 dm_crtc_high_irq, c_irq_params); 1374 } 1375 1376 /* Use GRPH_PFLIP interrupt */ 1377 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; 1378 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1; 1379 i++) { 1380 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); 1381 if (r) { 1382 DRM_ERROR("Failed to add page flip irq id!\n"); 1383 return r; 1384 } 1385 1386 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1387 int_params.irq_source = 1388 dc_interrupt_to_irq_source(dc, i, 0); 1389 1390 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 1391 1392 c_irq_params->adev = adev; 1393 c_irq_params->irq_src = int_params.irq_source; 1394 1395 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1396 dm_pflip_high_irq, c_irq_params); 1397 1398 } 1399 1400 /* HPD */ 1401 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, 1402 &adev->hpd_irq); 1403 if (r) { 1404 DRM_ERROR("Failed to add hpd irq id!\n"); 1405 return r; 1406 } 1407 1408 register_hpd_handlers(adev); 1409 1410 return 0; 1411 } 1412 #endif 1413 1414 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 1415 { 1416 int r; 1417 1418 adev->mode_info.mode_config_initialized = true; 1419 1420 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; 1421 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 1422 1423 adev->ddev->mode_config.max_width = 16384; 1424 adev->ddev->mode_config.max_height = 16384; 1425 1426 adev->ddev->mode_config.preferred_depth = 24; 1427 adev->ddev->mode_config.prefer_shadow = 1; 1428 /* indicate support of immediate flip */ 1429 adev->ddev->mode_config.async_page_flip = true; 1430 1431 adev->ddev->mode_config.fb_base = adev->gmc.aper_base; 1432 1433 r = amdgpu_display_modeset_create_props(adev); 1434 if (r) 1435 return r; 1436 1437 return 0; 1438 } 1439 1440 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 1441 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 1442 1443 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) 1444 { 1445 struct amdgpu_display_manager *dm = bl_get_data(bd); 1446 1447 if (dc_link_set_backlight_level(dm->backlight_link, 1448 bd->props.brightness, 0, 0)) 1449 return 0; 1450 else 1451 return 1; 1452 } 1453 1454 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) 1455 { 1456 struct amdgpu_display_manager *dm = bl_get_data(bd); 1457 int ret = dc_link_get_backlight_level(dm->backlight_link); 1458 1459 if (ret == DC_ERROR_UNEXPECTED) 1460 return bd->props.brightness; 1461 return ret; 1462 } 1463 1464 static const struct backlight_ops amdgpu_dm_backlight_ops = { 1465 .get_brightness = amdgpu_dm_backlight_get_brightness, 1466 .update_status = amdgpu_dm_backlight_update_status, 1467 }; 1468 1469 static void 1470 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm) 1471 { 1472 char bl_name[16]; 1473 struct backlight_properties props = { 0 }; 1474 1475 props.max_brightness = AMDGPU_MAX_BL_LEVEL; 1476 props.brightness = AMDGPU_MAX_BL_LEVEL; 1477 props.type = BACKLIGHT_RAW; 1478 1479 #ifdef notyet 1480 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", 1481 dm->adev->ddev->primary->index); 1482 #else 1483 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", 0); 1484 #endif 1485 1486 dm->backlight_dev = backlight_device_register(bl_name, 1487 dm->adev->ddev->dev, 1488 dm, 1489 &amdgpu_dm_backlight_ops, 1490 &props); 1491 1492 if (IS_ERR(dm->backlight_dev)) 1493 DRM_ERROR("DM: Backlight registration failed!\n"); 1494 else 1495 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); 1496 } 1497 1498 #endif 1499 1500 static int initialize_plane(struct amdgpu_display_manager *dm, 1501 struct amdgpu_mode_info *mode_info, 1502 int plane_id) 1503 { 1504 struct amdgpu_plane *plane; 1505 unsigned long possible_crtcs; 1506 int ret = 0; 1507 1508 plane = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL); 1509 mode_info->planes[plane_id] = plane; 1510 1511 if (!plane) { 1512 DRM_ERROR("KMS: Failed to allocate plane\n"); 1513 return -ENOMEM; 1514 } 1515 plane->base.type = mode_info->plane_type[plane_id]; 1516 1517 /* 1518 * HACK: IGT tests expect that each plane can only have one 1519 * one possible CRTC. For now, set one CRTC for each 1520 * plane that is not an underlay, but still allow multiple 1521 * CRTCs for underlay planes. 1522 */ 1523 possible_crtcs = 1 << plane_id; 1524 if (plane_id >= dm->dc->caps.max_streams) 1525 possible_crtcs = 0xff; 1526 1527 ret = amdgpu_dm_plane_init(dm, mode_info->planes[plane_id], possible_crtcs); 1528 1529 if (ret) { 1530 DRM_ERROR("KMS: Failed to initialize plane\n"); 1531 return ret; 1532 } 1533 1534 return ret; 1535 } 1536 1537 1538 static void register_backlight_device(struct amdgpu_display_manager *dm, 1539 struct dc_link *link) 1540 { 1541 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 1542 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 1543 1544 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && 1545 link->type != dc_connection_none) { 1546 /* Event if registration failed, we should continue with 1547 * DM initialization because not having a backlight control 1548 * is better then a black screen. 1549 */ 1550 amdgpu_dm_register_backlight_device(dm); 1551 1552 if (dm->backlight_dev) 1553 dm->backlight_link = link; 1554 } 1555 #endif 1556 } 1557 1558 1559 /* In this architecture, the association 1560 * connector -> encoder -> crtc 1561 * id not really requried. The crtc and connector will hold the 1562 * display_index as an abstraction to use with DAL component 1563 * 1564 * Returns 0 on success 1565 */ 1566 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 1567 { 1568 struct amdgpu_display_manager *dm = &adev->dm; 1569 int32_t i; 1570 struct amdgpu_dm_connector *aconnector = NULL; 1571 struct amdgpu_encoder *aencoder = NULL; 1572 struct amdgpu_mode_info *mode_info = &adev->mode_info; 1573 uint32_t link_cnt; 1574 int32_t total_overlay_planes, total_primary_planes; 1575 enum dc_connection_type new_connection_type = dc_connection_none; 1576 1577 link_cnt = dm->dc->caps.max_links; 1578 if (amdgpu_dm_mode_config_init(dm->adev)) { 1579 DRM_ERROR("DM: Failed to initialize mode config\n"); 1580 return -1; 1581 } 1582 1583 /* Identify the number of planes to be initialized */ 1584 total_overlay_planes = dm->dc->caps.max_slave_planes; 1585 total_primary_planes = dm->dc->caps.max_planes - dm->dc->caps.max_slave_planes; 1586 1587 /* First initialize overlay planes, index starting after primary planes */ 1588 for (i = (total_overlay_planes - 1); i >= 0; i--) { 1589 if (initialize_plane(dm, mode_info, (total_primary_planes + i))) { 1590 DRM_ERROR("KMS: Failed to initialize overlay plane\n"); 1591 goto fail; 1592 } 1593 } 1594 1595 /* Initialize primary planes */ 1596 for (i = (total_primary_planes - 1); i >= 0; i--) { 1597 if (initialize_plane(dm, mode_info, i)) { 1598 DRM_ERROR("KMS: Failed to initialize primary plane\n"); 1599 goto fail; 1600 } 1601 } 1602 1603 for (i = 0; i < dm->dc->caps.max_streams; i++) 1604 if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) { 1605 DRM_ERROR("KMS: Failed to initialize crtc\n"); 1606 goto fail; 1607 } 1608 1609 dm->display_indexes_num = dm->dc->caps.max_streams; 1610 1611 /* loops over all connectors on the board */ 1612 for (i = 0; i < link_cnt; i++) { 1613 struct dc_link *link = NULL; 1614 1615 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) { 1616 DRM_ERROR( 1617 "KMS: Cannot support more than %d display indexes\n", 1618 AMDGPU_DM_MAX_DISPLAY_INDEX); 1619 continue; 1620 } 1621 1622 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 1623 if (!aconnector) 1624 goto fail; 1625 1626 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); 1627 if (!aencoder) 1628 goto fail; 1629 1630 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 1631 DRM_ERROR("KMS: Failed to initialize encoder\n"); 1632 goto fail; 1633 } 1634 1635 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 1636 DRM_ERROR("KMS: Failed to initialize connector\n"); 1637 goto fail; 1638 } 1639 1640 link = dc_get_link_at_index(dm->dc, i); 1641 1642 if (!dc_link_detect_sink(link, &new_connection_type)) 1643 DRM_ERROR("KMS: Failed to detect connector\n"); 1644 1645 if (aconnector->base.force && new_connection_type == dc_connection_none) { 1646 emulated_link_detect(link); 1647 amdgpu_dm_update_connector_after_detect(aconnector); 1648 1649 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) { 1650 amdgpu_dm_update_connector_after_detect(aconnector); 1651 register_backlight_device(dm, link); 1652 } 1653 1654 1655 } 1656 1657 /* Software is initialized. Now we can register interrupt handlers. */ 1658 switch (adev->asic_type) { 1659 case CHIP_BONAIRE: 1660 case CHIP_HAWAII: 1661 case CHIP_KAVERI: 1662 case CHIP_KABINI: 1663 case CHIP_MULLINS: 1664 case CHIP_TONGA: 1665 case CHIP_FIJI: 1666 case CHIP_CARRIZO: 1667 case CHIP_STONEY: 1668 case CHIP_POLARIS11: 1669 case CHIP_POLARIS10: 1670 case CHIP_POLARIS12: 1671 case CHIP_VEGAM: 1672 case CHIP_VEGA10: 1673 case CHIP_VEGA12: 1674 case CHIP_VEGA20: 1675 if (dce110_register_irq_handlers(dm->adev)) { 1676 DRM_ERROR("DM: Failed to initialize IRQ\n"); 1677 goto fail; 1678 } 1679 break; 1680 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 1681 case CHIP_RAVEN: 1682 if (dcn10_register_irq_handlers(dm->adev)) { 1683 DRM_ERROR("DM: Failed to initialize IRQ\n"); 1684 goto fail; 1685 } 1686 break; 1687 #endif 1688 default: 1689 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 1690 goto fail; 1691 } 1692 1693 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 1694 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 1695 1696 return 0; 1697 fail: 1698 kfree(aencoder); 1699 kfree(aconnector); 1700 for (i = 0; i < dm->dc->caps.max_planes; i++) 1701 kfree(mode_info->planes[i]); 1702 return -1; 1703 } 1704 1705 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 1706 { 1707 drm_mode_config_cleanup(dm->ddev); 1708 return; 1709 } 1710 1711 /****************************************************************************** 1712 * amdgpu_display_funcs functions 1713 *****************************************************************************/ 1714 1715 /** 1716 * dm_bandwidth_update - program display watermarks 1717 * 1718 * @adev: amdgpu_device pointer 1719 * 1720 * Calculate and program the display watermarks and line buffer allocation. 1721 */ 1722 static void dm_bandwidth_update(struct amdgpu_device *adev) 1723 { 1724 /* TODO: implement later */ 1725 } 1726 1727 static int amdgpu_notify_freesync(struct drm_device *dev, void *data, 1728 struct drm_file *filp) 1729 { 1730 struct mod_freesync_params freesync_params; 1731 uint8_t num_streams; 1732 uint8_t i; 1733 1734 struct amdgpu_device *adev = dev->dev_private; 1735 int r = 0; 1736 1737 /* Get freesync enable flag from DRM */ 1738 1739 num_streams = dc_get_current_stream_count(adev->dm.dc); 1740 1741 for (i = 0; i < num_streams; i++) { 1742 struct dc_stream_state *stream; 1743 stream = dc_get_stream_at_index(adev->dm.dc, i); 1744 1745 mod_freesync_update_state(adev->dm.freesync_module, 1746 &stream, 1, &freesync_params); 1747 } 1748 1749 return r; 1750 } 1751 1752 static const struct amdgpu_display_funcs dm_display_funcs = { 1753 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 1754 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 1755 .backlight_set_level = NULL, /* never called for DC */ 1756 .backlight_get_level = NULL, /* never called for DC */ 1757 .hpd_sense = NULL,/* called unconditionally */ 1758 .hpd_set_polarity = NULL, /* called unconditionally */ 1759 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 1760 .page_flip_get_scanoutpos = 1761 dm_crtc_get_scanoutpos,/* called unconditionally */ 1762 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 1763 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 1764 .notify_freesync = amdgpu_notify_freesync, 1765 1766 }; 1767 1768 #if defined(CONFIG_DEBUG_KERNEL_DC) 1769 1770 static ssize_t s3_debug_store(struct device *device, 1771 struct device_attribute *attr, 1772 const char *buf, 1773 size_t count) 1774 { 1775 int ret; 1776 int s3_state; 1777 struct pci_dev *pdev = to_pci_dev(device); 1778 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1779 struct amdgpu_device *adev = drm_dev->dev_private; 1780 1781 ret = kstrtoint(buf, 0, &s3_state); 1782 1783 if (ret == 0) { 1784 if (s3_state) { 1785 dm_resume(adev); 1786 drm_kms_helper_hotplug_event(adev->ddev); 1787 } else 1788 dm_suspend(adev); 1789 } 1790 1791 return ret == 0 ? count : 0; 1792 } 1793 1794 DEVICE_ATTR_WO(s3_debug); 1795 1796 #endif 1797 1798 static int dm_early_init(void *handle) 1799 { 1800 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1801 1802 switch (adev->asic_type) { 1803 case CHIP_BONAIRE: 1804 case CHIP_HAWAII: 1805 adev->mode_info.num_crtc = 6; 1806 adev->mode_info.num_hpd = 6; 1807 adev->mode_info.num_dig = 6; 1808 adev->mode_info.plane_type = dm_plane_type_default; 1809 break; 1810 case CHIP_KAVERI: 1811 adev->mode_info.num_crtc = 4; 1812 adev->mode_info.num_hpd = 6; 1813 adev->mode_info.num_dig = 7; 1814 adev->mode_info.plane_type = dm_plane_type_default; 1815 break; 1816 case CHIP_KABINI: 1817 case CHIP_MULLINS: 1818 adev->mode_info.num_crtc = 2; 1819 adev->mode_info.num_hpd = 6; 1820 adev->mode_info.num_dig = 6; 1821 adev->mode_info.plane_type = dm_plane_type_default; 1822 break; 1823 case CHIP_FIJI: 1824 case CHIP_TONGA: 1825 adev->mode_info.num_crtc = 6; 1826 adev->mode_info.num_hpd = 6; 1827 adev->mode_info.num_dig = 7; 1828 adev->mode_info.plane_type = dm_plane_type_default; 1829 break; 1830 case CHIP_CARRIZO: 1831 adev->mode_info.num_crtc = 3; 1832 adev->mode_info.num_hpd = 6; 1833 adev->mode_info.num_dig = 9; 1834 adev->mode_info.plane_type = dm_plane_type_carizzo; 1835 break; 1836 case CHIP_STONEY: 1837 adev->mode_info.num_crtc = 2; 1838 adev->mode_info.num_hpd = 6; 1839 adev->mode_info.num_dig = 9; 1840 adev->mode_info.plane_type = dm_plane_type_stoney; 1841 break; 1842 case CHIP_POLARIS11: 1843 case CHIP_POLARIS12: 1844 adev->mode_info.num_crtc = 5; 1845 adev->mode_info.num_hpd = 5; 1846 adev->mode_info.num_dig = 5; 1847 adev->mode_info.plane_type = dm_plane_type_default; 1848 break; 1849 case CHIP_POLARIS10: 1850 case CHIP_VEGAM: 1851 adev->mode_info.num_crtc = 6; 1852 adev->mode_info.num_hpd = 6; 1853 adev->mode_info.num_dig = 6; 1854 adev->mode_info.plane_type = dm_plane_type_default; 1855 break; 1856 case CHIP_VEGA10: 1857 case CHIP_VEGA12: 1858 case CHIP_VEGA20: 1859 adev->mode_info.num_crtc = 6; 1860 adev->mode_info.num_hpd = 6; 1861 adev->mode_info.num_dig = 6; 1862 adev->mode_info.plane_type = dm_plane_type_default; 1863 break; 1864 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 1865 case CHIP_RAVEN: 1866 adev->mode_info.num_crtc = 4; 1867 adev->mode_info.num_hpd = 4; 1868 adev->mode_info.num_dig = 4; 1869 adev->mode_info.plane_type = dm_plane_type_default; 1870 break; 1871 #endif 1872 default: 1873 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 1874 return -EINVAL; 1875 } 1876 1877 amdgpu_dm_set_irq_funcs(adev); 1878 1879 if (adev->mode_info.funcs == NULL) 1880 adev->mode_info.funcs = &dm_display_funcs; 1881 1882 /* Note: Do NOT change adev->audio_endpt_rreg and 1883 * adev->audio_endpt_wreg because they are initialised in 1884 * amdgpu_device_init() */ 1885 #if defined(CONFIG_DEBUG_KERNEL_DC) 1886 device_create_file( 1887 adev->ddev->dev, 1888 &dev_attr_s3_debug); 1889 #endif 1890 1891 return 0; 1892 } 1893 1894 static bool modeset_required(struct drm_crtc_state *crtc_state, 1895 struct dc_stream_state *new_stream, 1896 struct dc_stream_state *old_stream) 1897 { 1898 if (!drm_atomic_crtc_needs_modeset(crtc_state)) 1899 return false; 1900 1901 if (!crtc_state->enable) 1902 return false; 1903 1904 return crtc_state->active; 1905 } 1906 1907 static bool modereset_required(struct drm_crtc_state *crtc_state) 1908 { 1909 if (!drm_atomic_crtc_needs_modeset(crtc_state)) 1910 return false; 1911 1912 return !crtc_state->enable || !crtc_state->active; 1913 } 1914 1915 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 1916 { 1917 drm_encoder_cleanup(encoder); 1918 kfree(encoder); 1919 } 1920 1921 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 1922 .destroy = amdgpu_dm_encoder_destroy, 1923 }; 1924 1925 static bool fill_rects_from_plane_state(const struct drm_plane_state *state, 1926 struct dc_plane_state *plane_state) 1927 { 1928 plane_state->src_rect.x = state->src_x >> 16; 1929 plane_state->src_rect.y = state->src_y >> 16; 1930 /*we ignore for now mantissa and do not to deal with floating pixels :(*/ 1931 plane_state->src_rect.width = state->src_w >> 16; 1932 1933 if (plane_state->src_rect.width == 0) 1934 return false; 1935 1936 plane_state->src_rect.height = state->src_h >> 16; 1937 if (plane_state->src_rect.height == 0) 1938 return false; 1939 1940 plane_state->dst_rect.x = state->crtc_x; 1941 plane_state->dst_rect.y = state->crtc_y; 1942 1943 if (state->crtc_w == 0) 1944 return false; 1945 1946 plane_state->dst_rect.width = state->crtc_w; 1947 1948 if (state->crtc_h == 0) 1949 return false; 1950 1951 plane_state->dst_rect.height = state->crtc_h; 1952 1953 plane_state->clip_rect = plane_state->dst_rect; 1954 1955 switch (state->rotation & DRM_MODE_ROTATE_MASK) { 1956 case DRM_MODE_ROTATE_0: 1957 plane_state->rotation = ROTATION_ANGLE_0; 1958 break; 1959 case DRM_MODE_ROTATE_90: 1960 plane_state->rotation = ROTATION_ANGLE_90; 1961 break; 1962 case DRM_MODE_ROTATE_180: 1963 plane_state->rotation = ROTATION_ANGLE_180; 1964 break; 1965 case DRM_MODE_ROTATE_270: 1966 plane_state->rotation = ROTATION_ANGLE_270; 1967 break; 1968 default: 1969 plane_state->rotation = ROTATION_ANGLE_0; 1970 break; 1971 } 1972 1973 return true; 1974 } 1975 static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, 1976 uint64_t *tiling_flags) 1977 { 1978 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]); 1979 int r = amdgpu_bo_reserve(rbo, false); 1980 1981 if (unlikely(r)) { 1982 // Don't show error msg. when return -ERESTARTSYS 1983 if (r != -ERESTARTSYS) 1984 DRM_ERROR("Unable to reserve buffer: %d\n", r); 1985 return r; 1986 } 1987 1988 if (tiling_flags) 1989 amdgpu_bo_get_tiling_flags(rbo, tiling_flags); 1990 1991 amdgpu_bo_unreserve(rbo); 1992 1993 return r; 1994 } 1995 1996 static int fill_plane_attributes_from_fb(struct amdgpu_device *adev, 1997 struct dc_plane_state *plane_state, 1998 const struct amdgpu_framebuffer *amdgpu_fb) 1999 { 2000 uint64_t tiling_flags; 2001 unsigned int awidth; 2002 const struct drm_framebuffer *fb = &amdgpu_fb->base; 2003 int ret = 0; 2004 struct drm_format_name_buf format_name; 2005 2006 ret = get_fb_info( 2007 amdgpu_fb, 2008 &tiling_flags); 2009 2010 if (ret) 2011 return ret; 2012 2013 switch (fb->format->format) { 2014 case DRM_FORMAT_C8: 2015 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 2016 break; 2017 case DRM_FORMAT_RGB565: 2018 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 2019 break; 2020 case DRM_FORMAT_XRGB8888: 2021 case DRM_FORMAT_ARGB8888: 2022 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 2023 break; 2024 case DRM_FORMAT_XRGB2101010: 2025 case DRM_FORMAT_ARGB2101010: 2026 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 2027 break; 2028 case DRM_FORMAT_XBGR2101010: 2029 case DRM_FORMAT_ABGR2101010: 2030 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 2031 break; 2032 case DRM_FORMAT_NV21: 2033 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 2034 break; 2035 case DRM_FORMAT_NV12: 2036 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 2037 break; 2038 default: 2039 DRM_ERROR("Unsupported screen format %s\n", 2040 drm_get_format_name(fb->format->format, &format_name)); 2041 return -EINVAL; 2042 } 2043 2044 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 2045 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS; 2046 plane_state->plane_size.grph.surface_size.x = 0; 2047 plane_state->plane_size.grph.surface_size.y = 0; 2048 plane_state->plane_size.grph.surface_size.width = fb->width; 2049 plane_state->plane_size.grph.surface_size.height = fb->height; 2050 plane_state->plane_size.grph.surface_pitch = 2051 fb->pitches[0] / fb->format->cpp[0]; 2052 /* TODO: unhardcode */ 2053 plane_state->color_space = COLOR_SPACE_SRGB; 2054 2055 } else { 2056 awidth = roundup2(fb->width, 64); 2057 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; 2058 plane_state->plane_size.video.luma_size.x = 0; 2059 plane_state->plane_size.video.luma_size.y = 0; 2060 plane_state->plane_size.video.luma_size.width = awidth; 2061 plane_state->plane_size.video.luma_size.height = fb->height; 2062 /* TODO: unhardcode */ 2063 plane_state->plane_size.video.luma_pitch = awidth; 2064 2065 plane_state->plane_size.video.chroma_size.x = 0; 2066 plane_state->plane_size.video.chroma_size.y = 0; 2067 plane_state->plane_size.video.chroma_size.width = awidth; 2068 plane_state->plane_size.video.chroma_size.height = fb->height; 2069 plane_state->plane_size.video.chroma_pitch = awidth / 2; 2070 2071 /* TODO: unhardcode */ 2072 plane_state->color_space = COLOR_SPACE_YCBCR709; 2073 } 2074 2075 memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info)); 2076 2077 /* Fill GFX8 params */ 2078 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { 2079 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; 2080 2081 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2082 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2083 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2084 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2085 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2086 2087 /* XXX fix me for VI */ 2088 plane_state->tiling_info.gfx8.num_banks = num_banks; 2089 plane_state->tiling_info.gfx8.array_mode = 2090 DC_ARRAY_2D_TILED_THIN1; 2091 plane_state->tiling_info.gfx8.tile_split = tile_split; 2092 plane_state->tiling_info.gfx8.bank_width = bankw; 2093 plane_state->tiling_info.gfx8.bank_height = bankh; 2094 plane_state->tiling_info.gfx8.tile_aspect = mtaspect; 2095 plane_state->tiling_info.gfx8.tile_mode = 2096 DC_ADDR_SURF_MICRO_TILING_DISPLAY; 2097 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) 2098 == DC_ARRAY_1D_TILED_THIN1) { 2099 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; 2100 } 2101 2102 plane_state->tiling_info.gfx8.pipe_config = 2103 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2104 2105 if (adev->asic_type == CHIP_VEGA10 || 2106 adev->asic_type == CHIP_VEGA12 || 2107 adev->asic_type == CHIP_VEGA20 || 2108 adev->asic_type == CHIP_RAVEN) { 2109 /* Fill GFX9 params */ 2110 plane_state->tiling_info.gfx9.num_pipes = 2111 adev->gfx.config.gb_addr_config_fields.num_pipes; 2112 plane_state->tiling_info.gfx9.num_banks = 2113 adev->gfx.config.gb_addr_config_fields.num_banks; 2114 plane_state->tiling_info.gfx9.pipe_interleave = 2115 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; 2116 plane_state->tiling_info.gfx9.num_shader_engines = 2117 adev->gfx.config.gb_addr_config_fields.num_se; 2118 plane_state->tiling_info.gfx9.max_compressed_frags = 2119 adev->gfx.config.gb_addr_config_fields.max_compress_frags; 2120 plane_state->tiling_info.gfx9.num_rb_per_se = 2121 adev->gfx.config.gb_addr_config_fields.num_rb_per_se; 2122 plane_state->tiling_info.gfx9.swizzle = 2123 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); 2124 plane_state->tiling_info.gfx9.shaderEnable = 1; 2125 } 2126 2127 plane_state->visible = true; 2128 plane_state->scaling_quality.h_taps_c = 0; 2129 plane_state->scaling_quality.v_taps_c = 0; 2130 2131 /* is this needed? is plane_state zeroed at allocation? */ 2132 plane_state->scaling_quality.h_taps = 0; 2133 plane_state->scaling_quality.v_taps = 0; 2134 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE; 2135 2136 return ret; 2137 2138 } 2139 2140 static int fill_plane_attributes(struct amdgpu_device *adev, 2141 struct dc_plane_state *dc_plane_state, 2142 struct drm_plane_state *plane_state, 2143 struct drm_crtc_state *crtc_state) 2144 { 2145 const struct amdgpu_framebuffer *amdgpu_fb = 2146 to_amdgpu_framebuffer(plane_state->fb); 2147 const struct drm_crtc *crtc = plane_state->crtc; 2148 int ret = 0; 2149 2150 if (!fill_rects_from_plane_state(plane_state, dc_plane_state)) 2151 return -EINVAL; 2152 2153 ret = fill_plane_attributes_from_fb( 2154 crtc->dev->dev_private, 2155 dc_plane_state, 2156 amdgpu_fb); 2157 2158 if (ret) 2159 return ret; 2160 2161 /* 2162 * Always set input transfer function, since plane state is refreshed 2163 * every time. 2164 */ 2165 ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state); 2166 if (ret) { 2167 dc_transfer_func_release(dc_plane_state->in_transfer_func); 2168 dc_plane_state->in_transfer_func = NULL; 2169 } 2170 2171 return ret; 2172 } 2173 2174 /*****************************************************************************/ 2175 2176 static void update_stream_scaling_settings(const struct drm_display_mode *mode, 2177 const struct dm_connector_state *dm_state, 2178 struct dc_stream_state *stream) 2179 { 2180 enum amdgpu_rmx_type rmx_type; 2181 2182 struct rect src = { 0 }; /* viewport in composition space*/ 2183 struct rect dst = { 0 }; /* stream addressable area */ 2184 2185 /* no mode. nothing to be done */ 2186 if (!mode) 2187 return; 2188 2189 /* Full screen scaling by default */ 2190 src.width = mode->hdisplay; 2191 src.height = mode->vdisplay; 2192 dst.width = stream->timing.h_addressable; 2193 dst.height = stream->timing.v_addressable; 2194 2195 if (dm_state) { 2196 rmx_type = dm_state->scaling; 2197 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 2198 if (src.width * dst.height < 2199 src.height * dst.width) { 2200 /* height needs less upscaling/more downscaling */ 2201 dst.width = src.width * 2202 dst.height / src.height; 2203 } else { 2204 /* width needs less upscaling/more downscaling */ 2205 dst.height = src.height * 2206 dst.width / src.width; 2207 } 2208 } else if (rmx_type == RMX_CENTER) { 2209 dst = src; 2210 } 2211 2212 dst.x = (stream->timing.h_addressable - dst.width) / 2; 2213 dst.y = (stream->timing.v_addressable - dst.height) / 2; 2214 2215 if (dm_state->underscan_enable) { 2216 dst.x += dm_state->underscan_hborder / 2; 2217 dst.y += dm_state->underscan_vborder / 2; 2218 dst.width -= dm_state->underscan_hborder; 2219 dst.height -= dm_state->underscan_vborder; 2220 } 2221 } 2222 2223 stream->src = src; 2224 stream->dst = dst; 2225 2226 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n", 2227 dst.x, dst.y, dst.width, dst.height); 2228 2229 } 2230 2231 static enum dc_color_depth 2232 convert_color_depth_from_display_info(const struct drm_connector *connector) 2233 { 2234 struct dm_connector_state *dm_conn_state = 2235 to_dm_connector_state(connector->state); 2236 uint32_t bpc = connector->display_info.bpc; 2237 2238 /* TODO: Remove this when there's support for max_bpc in drm */ 2239 if (dm_conn_state && bpc > dm_conn_state->max_bpc) 2240 /* Round down to nearest even number. */ 2241 bpc = dm_conn_state->max_bpc - (dm_conn_state->max_bpc & 1); 2242 2243 switch (bpc) { 2244 case 0: 2245 /* Temporary Work around, DRM don't parse color depth for 2246 * EDID revision before 1.4 2247 * TODO: Fix edid parsing 2248 */ 2249 return COLOR_DEPTH_888; 2250 case 6: 2251 return COLOR_DEPTH_666; 2252 case 8: 2253 return COLOR_DEPTH_888; 2254 case 10: 2255 return COLOR_DEPTH_101010; 2256 case 12: 2257 return COLOR_DEPTH_121212; 2258 case 14: 2259 return COLOR_DEPTH_141414; 2260 case 16: 2261 return COLOR_DEPTH_161616; 2262 default: 2263 return COLOR_DEPTH_UNDEFINED; 2264 } 2265 } 2266 2267 static enum dc_aspect_ratio 2268 get_aspect_ratio(const struct drm_display_mode *mode_in) 2269 { 2270 /* 1-1 mapping, since both enums follow the HDMI spec. */ 2271 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; 2272 } 2273 2274 static enum dc_color_space 2275 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing) 2276 { 2277 enum dc_color_space color_space = COLOR_SPACE_SRGB; 2278 2279 switch (dc_crtc_timing->pixel_encoding) { 2280 case PIXEL_ENCODING_YCBCR422: 2281 case PIXEL_ENCODING_YCBCR444: 2282 case PIXEL_ENCODING_YCBCR420: 2283 { 2284 /* 2285 * 27030khz is the separation point between HDTV and SDTV 2286 * according to HDMI spec, we use YCbCr709 and YCbCr601 2287 * respectively 2288 */ 2289 if (dc_crtc_timing->pix_clk_khz > 27030) { 2290 if (dc_crtc_timing->flags.Y_ONLY) 2291 color_space = 2292 COLOR_SPACE_YCBCR709_LIMITED; 2293 else 2294 color_space = COLOR_SPACE_YCBCR709; 2295 } else { 2296 if (dc_crtc_timing->flags.Y_ONLY) 2297 color_space = 2298 COLOR_SPACE_YCBCR601_LIMITED; 2299 else 2300 color_space = COLOR_SPACE_YCBCR601; 2301 } 2302 2303 } 2304 break; 2305 case PIXEL_ENCODING_RGB: 2306 color_space = COLOR_SPACE_SRGB; 2307 break; 2308 2309 default: 2310 WARN_ON(1); 2311 break; 2312 } 2313 2314 return color_space; 2315 } 2316 2317 static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out) 2318 { 2319 if (timing_out->display_color_depth <= COLOR_DEPTH_888) 2320 return; 2321 2322 timing_out->display_color_depth--; 2323 } 2324 2325 static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out, 2326 const struct drm_display_info *info) 2327 { 2328 int normalized_clk; 2329 if (timing_out->display_color_depth <= COLOR_DEPTH_888) 2330 return; 2331 do { 2332 normalized_clk = timing_out->pix_clk_khz; 2333 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ 2334 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) 2335 normalized_clk /= 2; 2336 /* Adjusting pix clock following on HDMI spec based on colour depth */ 2337 switch (timing_out->display_color_depth) { 2338 case COLOR_DEPTH_101010: 2339 normalized_clk = (normalized_clk * 30) / 24; 2340 break; 2341 case COLOR_DEPTH_121212: 2342 normalized_clk = (normalized_clk * 36) / 24; 2343 break; 2344 case COLOR_DEPTH_161616: 2345 normalized_clk = (normalized_clk * 48) / 24; 2346 break; 2347 default: 2348 return; 2349 } 2350 if (normalized_clk <= info->max_tmds_clock) 2351 return; 2352 reduce_mode_colour_depth(timing_out); 2353 2354 } while (timing_out->display_color_depth > COLOR_DEPTH_888); 2355 2356 } 2357 /*****************************************************************************/ 2358 2359 static void 2360 fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream, 2361 const struct drm_display_mode *mode_in, 2362 const struct drm_connector *connector) 2363 { 2364 struct dc_crtc_timing *timing_out = &stream->timing; 2365 const struct drm_display_info *info = &connector->display_info; 2366 2367 memset(timing_out, 0, sizeof(struct dc_crtc_timing)); 2368 2369 timing_out->h_border_left = 0; 2370 timing_out->h_border_right = 0; 2371 timing_out->v_border_top = 0; 2372 timing_out->v_border_bottom = 0; 2373 /* TODO: un-hardcode */ 2374 if (drm_mode_is_420_only(info, mode_in) 2375 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) 2376 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 2377 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444) 2378 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) 2379 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; 2380 else 2381 timing_out->pixel_encoding = PIXEL_ENCODING_RGB; 2382 2383 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; 2384 timing_out->display_color_depth = convert_color_depth_from_display_info( 2385 connector); 2386 timing_out->scan_type = SCANNING_TYPE_NODATA; 2387 timing_out->hdmi_vic = 0; 2388 timing_out->vic = drm_match_cea_mode(mode_in); 2389 2390 timing_out->h_addressable = mode_in->crtc_hdisplay; 2391 timing_out->h_total = mode_in->crtc_htotal; 2392 timing_out->h_sync_width = 2393 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; 2394 timing_out->h_front_porch = 2395 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; 2396 timing_out->v_total = mode_in->crtc_vtotal; 2397 timing_out->v_addressable = mode_in->crtc_vdisplay; 2398 timing_out->v_front_porch = 2399 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; 2400 timing_out->v_sync_width = 2401 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; 2402 timing_out->pix_clk_khz = mode_in->crtc_clock; 2403 timing_out->aspect_ratio = get_aspect_ratio(mode_in); 2404 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) 2405 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; 2406 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) 2407 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; 2408 2409 stream->output_color_space = get_output_color_space(timing_out); 2410 2411 stream->out_transfer_func->type = TF_TYPE_PREDEFINED; 2412 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; 2413 if (stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) 2414 adjust_colour_depth_from_display_info(timing_out, info); 2415 } 2416 2417 static void fill_audio_info(struct audio_info *audio_info, 2418 const struct drm_connector *drm_connector, 2419 const struct dc_sink *dc_sink) 2420 { 2421 int i = 0; 2422 int cea_revision = 0; 2423 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; 2424 2425 audio_info->manufacture_id = edid_caps->manufacturer_id; 2426 audio_info->product_id = edid_caps->product_id; 2427 2428 cea_revision = drm_connector->display_info.cea_rev; 2429 2430 strncpy(audio_info->display_name, 2431 edid_caps->display_name, 2432 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1); 2433 2434 if (cea_revision >= 3) { 2435 audio_info->mode_count = edid_caps->audio_mode_count; 2436 2437 for (i = 0; i < audio_info->mode_count; ++i) { 2438 audio_info->modes[i].format_code = 2439 (enum audio_format_code) 2440 (edid_caps->audio_modes[i].format_code); 2441 audio_info->modes[i].channel_count = 2442 edid_caps->audio_modes[i].channel_count; 2443 audio_info->modes[i].sample_rates.all = 2444 edid_caps->audio_modes[i].sample_rate; 2445 audio_info->modes[i].sample_size = 2446 edid_caps->audio_modes[i].sample_size; 2447 } 2448 } 2449 2450 audio_info->flags.all = edid_caps->speaker_flags; 2451 2452 /* TODO: We only check for the progressive mode, check for interlace mode too */ 2453 if (drm_connector->latency_present[0]) { 2454 audio_info->video_latency = drm_connector->video_latency[0]; 2455 audio_info->audio_latency = drm_connector->audio_latency[0]; 2456 } 2457 2458 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ 2459 2460 } 2461 2462 static void 2463 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, 2464 struct drm_display_mode *dst_mode) 2465 { 2466 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; 2467 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; 2468 dst_mode->crtc_clock = src_mode->crtc_clock; 2469 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; 2470 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; 2471 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; 2472 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; 2473 dst_mode->crtc_htotal = src_mode->crtc_htotal; 2474 dst_mode->crtc_hskew = src_mode->crtc_hskew; 2475 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; 2476 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; 2477 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; 2478 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; 2479 dst_mode->crtc_vtotal = src_mode->crtc_vtotal; 2480 } 2481 2482 static void 2483 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, 2484 const struct drm_display_mode *native_mode, 2485 bool scale_enabled) 2486 { 2487 if (scale_enabled) { 2488 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 2489 } else if (native_mode->clock == drm_mode->clock && 2490 native_mode->htotal == drm_mode->htotal && 2491 native_mode->vtotal == drm_mode->vtotal) { 2492 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 2493 } else { 2494 /* no scaling nor amdgpu inserted, no need to patch */ 2495 } 2496 } 2497 2498 static struct dc_sink * 2499 create_fake_sink(struct amdgpu_dm_connector *aconnector) 2500 { 2501 struct dc_sink_init_data sink_init_data = { 0 }; 2502 struct dc_sink *sink = NULL; 2503 sink_init_data.link = aconnector->dc_link; 2504 sink_init_data.sink_signal = aconnector->dc_link->connector_signal; 2505 2506 sink = dc_sink_create(&sink_init_data); 2507 if (!sink) { 2508 DRM_ERROR("Failed to create sink!\n"); 2509 return NULL; 2510 } 2511 sink->sink_signal = SIGNAL_TYPE_VIRTUAL; 2512 2513 return sink; 2514 } 2515 2516 static void set_multisync_trigger_params( 2517 struct dc_stream_state *stream) 2518 { 2519 if (stream->triggered_crtc_reset.enabled) { 2520 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING; 2521 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE; 2522 } 2523 } 2524 2525 static void set_master_stream(struct dc_stream_state *stream_set[], 2526 int stream_count) 2527 { 2528 int j, highest_rfr = 0, master_stream = 0; 2529 2530 for (j = 0; j < stream_count; j++) { 2531 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 2532 int refresh_rate = 0; 2533 2534 refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/ 2535 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 2536 if (refresh_rate > highest_rfr) { 2537 highest_rfr = refresh_rate; 2538 master_stream = j; 2539 } 2540 } 2541 } 2542 for (j = 0; j < stream_count; j++) { 2543 if (stream_set[j]) 2544 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 2545 } 2546 } 2547 2548 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 2549 { 2550 int i = 0; 2551 2552 if (context->stream_count < 2) 2553 return; 2554 for (i = 0; i < context->stream_count ; i++) { 2555 if (!context->streams[i]) 2556 continue; 2557 /* TODO: add a function to read AMD VSDB bits and will set 2558 * crtc_sync_master.multi_sync_enabled flag 2559 * For now its set to false 2560 */ 2561 set_multisync_trigger_params(context->streams[i]); 2562 } 2563 set_master_stream(context->streams, context->stream_count); 2564 } 2565 2566 static struct dc_stream_state * 2567 create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 2568 const struct drm_display_mode *drm_mode, 2569 const struct dm_connector_state *dm_state) 2570 { 2571 struct drm_display_mode *preferred_mode = NULL; 2572 struct drm_connector *drm_connector; 2573 struct dc_stream_state *stream = NULL; 2574 struct drm_display_mode mode = *drm_mode; 2575 bool native_mode_found = false; 2576 struct dc_sink *sink = NULL; 2577 if (aconnector == NULL) { 2578 DRM_ERROR("aconnector is NULL!\n"); 2579 return stream; 2580 } 2581 2582 drm_connector = &aconnector->base; 2583 2584 if (!aconnector->dc_sink) { 2585 /* 2586 * Create dc_sink when necessary to MST 2587 * Don't apply fake_sink to MST 2588 */ 2589 if (aconnector->mst_port) { 2590 dm_dp_mst_dc_sink_create(drm_connector); 2591 return stream; 2592 } 2593 2594 sink = create_fake_sink(aconnector); 2595 if (!sink) 2596 return stream; 2597 } else { 2598 sink = aconnector->dc_sink; 2599 } 2600 2601 stream = dc_create_stream_for_sink(sink); 2602 2603 if (stream == NULL) { 2604 DRM_ERROR("Failed to create stream for sink!\n"); 2605 goto finish; 2606 } 2607 2608 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) { 2609 /* Search for preferred mode */ 2610 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { 2611 native_mode_found = true; 2612 break; 2613 } 2614 } 2615 if (!native_mode_found) 2616 preferred_mode = list_first_entry_or_null( 2617 &aconnector->base.modes, 2618 struct drm_display_mode, 2619 head); 2620 2621 if (preferred_mode == NULL) { 2622 /* This may not be an error, the use case is when we we have no 2623 * usermode calls to reset and set mode upon hotplug. In this 2624 * case, we call set mode ourselves to restore the previous mode 2625 * and the modelist may not be filled in in time. 2626 */ 2627 DRM_DEBUG_DRIVER("No preferred mode found\n"); 2628 } else { 2629 decide_crtc_timing_for_drm_display_mode( 2630 &mode, preferred_mode, 2631 dm_state ? (dm_state->scaling != RMX_OFF) : false); 2632 } 2633 2634 if (!dm_state) 2635 drm_mode_set_crtcinfo(&mode, 0); 2636 2637 fill_stream_properties_from_drm_display_mode(stream, 2638 &mode, &aconnector->base); 2639 update_stream_scaling_settings(&mode, dm_state, stream); 2640 2641 fill_audio_info( 2642 &stream->audio_info, 2643 drm_connector, 2644 sink); 2645 2646 update_stream_signal(stream); 2647 2648 if (dm_state && dm_state->freesync_capable) 2649 stream->ignore_msa_timing_param = true; 2650 finish: 2651 if (sink && sink->sink_signal == SIGNAL_TYPE_VIRTUAL && aconnector->base.force != DRM_FORCE_ON) 2652 dc_sink_release(sink); 2653 2654 return stream; 2655 } 2656 2657 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) 2658 { 2659 drm_crtc_cleanup(crtc); 2660 kfree(crtc); 2661 } 2662 2663 static void dm_crtc_destroy_state(struct drm_crtc *crtc, 2664 struct drm_crtc_state *state) 2665 { 2666 struct dm_crtc_state *cur = to_dm_crtc_state(state); 2667 2668 /* TODO Destroy dc_stream objects are stream object is flattened */ 2669 if (cur->stream) 2670 dc_stream_release(cur->stream); 2671 2672 2673 __drm_atomic_helper_crtc_destroy_state(state); 2674 2675 2676 kfree(state); 2677 } 2678 2679 static void dm_crtc_reset_state(struct drm_crtc *crtc) 2680 { 2681 struct dm_crtc_state *state; 2682 2683 if (crtc->state) 2684 dm_crtc_destroy_state(crtc, crtc->state); 2685 2686 state = kzalloc(sizeof(*state), GFP_KERNEL); 2687 if (WARN_ON(!state)) 2688 return; 2689 2690 crtc->state = &state->base; 2691 crtc->state->crtc = crtc; 2692 2693 } 2694 2695 static struct drm_crtc_state * 2696 dm_crtc_duplicate_state(struct drm_crtc *crtc) 2697 { 2698 struct dm_crtc_state *state, *cur; 2699 2700 cur = to_dm_crtc_state(crtc->state); 2701 2702 if (WARN_ON(!crtc->state)) 2703 return NULL; 2704 2705 state = kzalloc(sizeof(*state), GFP_KERNEL); 2706 if (!state) 2707 return NULL; 2708 2709 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 2710 2711 if (cur->stream) { 2712 state->stream = cur->stream; 2713 dc_stream_retain(state->stream); 2714 } 2715 2716 /* TODO Duplicate dc_stream after objects are stream object is flattened */ 2717 2718 return &state->base; 2719 } 2720 2721 2722 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable) 2723 { 2724 enum dc_irq_source irq_source; 2725 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2726 struct amdgpu_device *adev = crtc->dev->dev_private; 2727 2728 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 2729 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 2730 } 2731 2732 static int dm_enable_vblank(struct drm_crtc *crtc) 2733 { 2734 return dm_set_vblank(crtc, true); 2735 } 2736 2737 static void dm_disable_vblank(struct drm_crtc *crtc) 2738 { 2739 dm_set_vblank(crtc, false); 2740 } 2741 2742 /* Implemented only the options currently availible for the driver */ 2743 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { 2744 .reset = dm_crtc_reset_state, 2745 .destroy = amdgpu_dm_crtc_destroy, 2746 .gamma_set = drm_atomic_helper_legacy_gamma_set, 2747 .set_config = drm_atomic_helper_set_config, 2748 .page_flip = drm_atomic_helper_page_flip, 2749 .atomic_duplicate_state = dm_crtc_duplicate_state, 2750 .atomic_destroy_state = dm_crtc_destroy_state, 2751 .set_crc_source = amdgpu_dm_crtc_set_crc_source, 2752 .enable_vblank = dm_enable_vblank, 2753 .disable_vblank = dm_disable_vblank, 2754 }; 2755 2756 static enum drm_connector_status 2757 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) 2758 { 2759 bool connected; 2760 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2761 2762 /* Notes: 2763 * 1. This interface is NOT called in context of HPD irq. 2764 * 2. This interface *is called* in context of user-mode ioctl. Which 2765 * makes it a bad place for *any* MST-related activit. */ 2766 2767 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && 2768 !aconnector->fake_enable) 2769 connected = (aconnector->dc_sink != NULL); 2770 else 2771 connected = (aconnector->base.force == DRM_FORCE_ON); 2772 2773 return (connected ? connector_status_connected : 2774 connector_status_disconnected); 2775 } 2776 2777 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 2778 struct drm_connector_state *connector_state, 2779 struct drm_property *property, 2780 uint64_t val) 2781 { 2782 struct drm_device *dev = connector->dev; 2783 struct amdgpu_device *adev = dev->dev_private; 2784 struct dm_connector_state *dm_old_state = 2785 to_dm_connector_state(connector->state); 2786 struct dm_connector_state *dm_new_state = 2787 to_dm_connector_state(connector_state); 2788 2789 int ret = -EINVAL; 2790 2791 if (property == dev->mode_config.scaling_mode_property) { 2792 enum amdgpu_rmx_type rmx_type; 2793 2794 switch (val) { 2795 case DRM_MODE_SCALE_CENTER: 2796 rmx_type = RMX_CENTER; 2797 break; 2798 case DRM_MODE_SCALE_ASPECT: 2799 rmx_type = RMX_ASPECT; 2800 break; 2801 case DRM_MODE_SCALE_FULLSCREEN: 2802 rmx_type = RMX_FULL; 2803 break; 2804 case DRM_MODE_SCALE_NONE: 2805 default: 2806 rmx_type = RMX_OFF; 2807 break; 2808 } 2809 2810 if (dm_old_state->scaling == rmx_type) 2811 return 0; 2812 2813 dm_new_state->scaling = rmx_type; 2814 ret = 0; 2815 } else if (property == adev->mode_info.underscan_hborder_property) { 2816 dm_new_state->underscan_hborder = val; 2817 ret = 0; 2818 } else if (property == adev->mode_info.underscan_vborder_property) { 2819 dm_new_state->underscan_vborder = val; 2820 ret = 0; 2821 } else if (property == adev->mode_info.underscan_property) { 2822 dm_new_state->underscan_enable = val; 2823 ret = 0; 2824 } else if (property == adev->mode_info.max_bpc_property) { 2825 dm_new_state->max_bpc = val; 2826 ret = 0; 2827 } 2828 2829 return ret; 2830 } 2831 2832 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 2833 const struct drm_connector_state *state, 2834 struct drm_property *property, 2835 uint64_t *val) 2836 { 2837 struct drm_device *dev = connector->dev; 2838 struct amdgpu_device *adev = dev->dev_private; 2839 struct dm_connector_state *dm_state = 2840 to_dm_connector_state(state); 2841 int ret = -EINVAL; 2842 2843 if (property == dev->mode_config.scaling_mode_property) { 2844 switch (dm_state->scaling) { 2845 case RMX_CENTER: 2846 *val = DRM_MODE_SCALE_CENTER; 2847 break; 2848 case RMX_ASPECT: 2849 *val = DRM_MODE_SCALE_ASPECT; 2850 break; 2851 case RMX_FULL: 2852 *val = DRM_MODE_SCALE_FULLSCREEN; 2853 break; 2854 case RMX_OFF: 2855 default: 2856 *val = DRM_MODE_SCALE_NONE; 2857 break; 2858 } 2859 ret = 0; 2860 } else if (property == adev->mode_info.underscan_hborder_property) { 2861 *val = dm_state->underscan_hborder; 2862 ret = 0; 2863 } else if (property == adev->mode_info.underscan_vborder_property) { 2864 *val = dm_state->underscan_vborder; 2865 ret = 0; 2866 } else if (property == adev->mode_info.underscan_property) { 2867 *val = dm_state->underscan_enable; 2868 ret = 0; 2869 } else if (property == adev->mode_info.max_bpc_property) { 2870 *val = dm_state->max_bpc; 2871 ret = 0; 2872 } 2873 return ret; 2874 } 2875 2876 static void amdgpu_dm_connector_destroy(struct drm_connector *connector) 2877 { 2878 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2879 const struct dc_link *link = aconnector->dc_link; 2880 struct amdgpu_device *adev = connector->dev->dev_private; 2881 struct amdgpu_display_manager *dm = &adev->dm; 2882 2883 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 2884 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 2885 2886 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && 2887 link->type != dc_connection_none && 2888 dm->backlight_dev) { 2889 backlight_device_unregister(dm->backlight_dev); 2890 dm->backlight_dev = NULL; 2891 } 2892 #endif 2893 drm_connector_unregister(connector); 2894 drm_connector_cleanup(connector); 2895 kfree(connector); 2896 } 2897 2898 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) 2899 { 2900 struct dm_connector_state *state = 2901 to_dm_connector_state(connector->state); 2902 2903 if (connector->state) 2904 __drm_atomic_helper_connector_destroy_state(connector->state); 2905 2906 kfree(state); 2907 2908 state = kzalloc(sizeof(*state), GFP_KERNEL); 2909 2910 if (state) { 2911 state->scaling = RMX_OFF; 2912 state->underscan_enable = false; 2913 state->underscan_hborder = 0; 2914 state->underscan_vborder = 0; 2915 state->max_bpc = 8; 2916 2917 __drm_atomic_helper_connector_reset(connector, &state->base); 2918 } 2919 } 2920 2921 struct drm_connector_state * 2922 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) 2923 { 2924 struct dm_connector_state *state = 2925 to_dm_connector_state(connector->state); 2926 2927 struct dm_connector_state *new_state = 2928 kmemdup(state, sizeof(*state), GFP_KERNEL); 2929 2930 if (new_state) { 2931 __drm_atomic_helper_connector_duplicate_state(connector, 2932 &new_state->base); 2933 new_state->max_bpc = state->max_bpc; 2934 return &new_state->base; 2935 } 2936 2937 return NULL; 2938 } 2939 2940 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { 2941 .reset = amdgpu_dm_connector_funcs_reset, 2942 .detect = amdgpu_dm_connector_detect, 2943 .fill_modes = drm_helper_probe_single_connector_modes, 2944 .destroy = amdgpu_dm_connector_destroy, 2945 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 2946 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2947 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 2948 .atomic_get_property = amdgpu_dm_connector_atomic_get_property 2949 }; 2950 2951 static struct drm_encoder *best_encoder(struct drm_connector *connector) 2952 { 2953 int enc_id = connector->encoder_ids[0]; 2954 struct drm_mode_object *obj; 2955 struct drm_encoder *encoder; 2956 2957 DRM_DEBUG_DRIVER("Finding the best encoder\n"); 2958 2959 /* pick the encoder ids */ 2960 if (enc_id) { 2961 obj = drm_mode_object_find(connector->dev, NULL, enc_id, DRM_MODE_OBJECT_ENCODER); 2962 if (!obj) { 2963 DRM_ERROR("Couldn't find a matching encoder for our connector\n"); 2964 return NULL; 2965 } 2966 encoder = obj_to_encoder(obj); 2967 return encoder; 2968 } 2969 DRM_ERROR("No encoder id\n"); 2970 return NULL; 2971 } 2972 2973 static int get_modes(struct drm_connector *connector) 2974 { 2975 return amdgpu_dm_connector_get_modes(connector); 2976 } 2977 2978 static void create_eml_sink(struct amdgpu_dm_connector *aconnector) 2979 { 2980 struct dc_sink_init_data init_params = { 2981 .link = aconnector->dc_link, 2982 .sink_signal = SIGNAL_TYPE_VIRTUAL 2983 }; 2984 struct edid *edid; 2985 2986 if (!aconnector->base.edid_blob_ptr) { 2987 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n", 2988 aconnector->base.name); 2989 2990 aconnector->base.force = DRM_FORCE_OFF; 2991 aconnector->base.override_edid = false; 2992 return; 2993 } 2994 2995 edid = (struct edid *) aconnector->base.edid_blob_ptr->data; 2996 2997 aconnector->edid = edid; 2998 2999 aconnector->dc_em_sink = dc_link_add_remote_sink( 3000 aconnector->dc_link, 3001 (uint8_t *)edid, 3002 (edid->extensions + 1) * EDID_LENGTH, 3003 &init_params); 3004 3005 if (aconnector->base.force == DRM_FORCE_ON) 3006 aconnector->dc_sink = aconnector->dc_link->local_sink ? 3007 aconnector->dc_link->local_sink : 3008 aconnector->dc_em_sink; 3009 } 3010 3011 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) 3012 { 3013 struct dc_link *link = (struct dc_link *)aconnector->dc_link; 3014 3015 /* In case of headless boot with force on for DP managed connector 3016 * Those settings have to be != 0 to get initial modeset 3017 */ 3018 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { 3019 link->verified_link_cap.lane_count = LANE_COUNT_FOUR; 3020 link->verified_link_cap.link_rate = LINK_RATE_HIGH2; 3021 } 3022 3023 3024 aconnector->base.override_edid = true; 3025 create_eml_sink(aconnector); 3026 } 3027 3028 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 3029 struct drm_display_mode *mode) 3030 { 3031 int result = MODE_ERROR; 3032 struct dc_sink *dc_sink; 3033 struct amdgpu_device *adev = connector->dev->dev_private; 3034 /* TODO: Unhardcode stream count */ 3035 struct dc_stream_state *stream; 3036 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 3037 enum dc_status dc_result = DC_OK; 3038 3039 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || 3040 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) 3041 return result; 3042 3043 /* Only run this the first time mode_valid is called to initilialize 3044 * EDID mgmt 3045 */ 3046 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && 3047 !aconnector->dc_em_sink) 3048 handle_edid_mgmt(aconnector); 3049 3050 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; 3051 3052 if (dc_sink == NULL) { 3053 DRM_ERROR("dc_sink is NULL!\n"); 3054 goto fail; 3055 } 3056 3057 stream = create_stream_for_sink(aconnector, mode, NULL); 3058 if (stream == NULL) { 3059 DRM_ERROR("Failed to create stream for sink!\n"); 3060 goto fail; 3061 } 3062 3063 dc_result = dc_validate_stream(adev->dm.dc, stream); 3064 3065 if (dc_result == DC_OK) 3066 result = MODE_OK; 3067 else 3068 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n", 3069 mode->vdisplay, 3070 mode->hdisplay, 3071 mode->clock, 3072 dc_result); 3073 3074 dc_stream_release(stream); 3075 3076 fail: 3077 /* TODO: error handling*/ 3078 return result; 3079 } 3080 3081 static const struct drm_connector_helper_funcs 3082 amdgpu_dm_connector_helper_funcs = { 3083 /* 3084 * If hotplug a second bigger display in FB Con mode, bigger resolution 3085 * modes will be filtered by drm_mode_validate_size(), and those modes 3086 * is missing after user start lightdm. So we need to renew modes list. 3087 * in get_modes call back, not just return the modes count 3088 */ 3089 .get_modes = get_modes, 3090 .mode_valid = amdgpu_dm_connector_mode_valid, 3091 .best_encoder = best_encoder 3092 }; 3093 3094 static void dm_crtc_helper_disable(struct drm_crtc *crtc) 3095 { 3096 } 3097 3098 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc, 3099 struct drm_crtc_state *state) 3100 { 3101 struct amdgpu_device *adev = crtc->dev->dev_private; 3102 struct dc *dc = adev->dm.dc; 3103 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state); 3104 int ret = -EINVAL; 3105 3106 if (unlikely(!dm_crtc_state->stream && 3107 modeset_required(state, NULL, dm_crtc_state->stream))) { 3108 WARN_ON(1); 3109 return ret; 3110 } 3111 3112 /* In some use cases, like reset, no stream is attached */ 3113 if (!dm_crtc_state->stream) 3114 return 0; 3115 3116 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK) 3117 return 0; 3118 3119 return ret; 3120 } 3121 3122 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, 3123 const struct drm_display_mode *mode, 3124 struct drm_display_mode *adjusted_mode) 3125 { 3126 return true; 3127 } 3128 3129 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { 3130 .disable = dm_crtc_helper_disable, 3131 .atomic_check = dm_crtc_helper_atomic_check, 3132 .mode_fixup = dm_crtc_helper_mode_fixup 3133 }; 3134 3135 static void dm_encoder_helper_disable(struct drm_encoder *encoder) 3136 { 3137 3138 } 3139 3140 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 3141 struct drm_crtc_state *crtc_state, 3142 struct drm_connector_state *conn_state) 3143 { 3144 return 0; 3145 } 3146 3147 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { 3148 .disable = dm_encoder_helper_disable, 3149 .atomic_check = dm_encoder_helper_atomic_check 3150 }; 3151 3152 static void dm_drm_plane_reset(struct drm_plane *plane) 3153 { 3154 struct dm_plane_state *amdgpu_state = NULL; 3155 3156 if (plane->state) 3157 plane->funcs->atomic_destroy_state(plane, plane->state); 3158 3159 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL); 3160 WARN_ON(amdgpu_state == NULL); 3161 3162 if (amdgpu_state) { 3163 plane->state = &amdgpu_state->base; 3164 plane->state->plane = plane; 3165 plane->state->rotation = DRM_MODE_ROTATE_0; 3166 } 3167 } 3168 3169 static struct drm_plane_state * 3170 dm_drm_plane_duplicate_state(struct drm_plane *plane) 3171 { 3172 struct dm_plane_state *dm_plane_state, *old_dm_plane_state; 3173 3174 old_dm_plane_state = to_dm_plane_state(plane->state); 3175 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL); 3176 if (!dm_plane_state) 3177 return NULL; 3178 3179 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base); 3180 3181 if (old_dm_plane_state->dc_state) { 3182 dm_plane_state->dc_state = old_dm_plane_state->dc_state; 3183 dc_plane_state_retain(dm_plane_state->dc_state); 3184 } 3185 3186 return &dm_plane_state->base; 3187 } 3188 3189 void dm_drm_plane_destroy_state(struct drm_plane *plane, 3190 struct drm_plane_state *state) 3191 { 3192 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 3193 3194 if (dm_plane_state->dc_state) 3195 dc_plane_state_release(dm_plane_state->dc_state); 3196 3197 drm_atomic_helper_plane_destroy_state(plane, state); 3198 } 3199 3200 static const struct drm_plane_funcs dm_plane_funcs = { 3201 .update_plane = drm_atomic_helper_update_plane, 3202 .disable_plane = drm_atomic_helper_disable_plane, 3203 .destroy = drm_primary_helper_destroy, 3204 .reset = dm_drm_plane_reset, 3205 .atomic_duplicate_state = dm_drm_plane_duplicate_state, 3206 .atomic_destroy_state = dm_drm_plane_destroy_state, 3207 }; 3208 3209 static int dm_plane_helper_prepare_fb(struct drm_plane *plane, 3210 struct drm_plane_state *new_state) 3211 { 3212 struct amdgpu_framebuffer *afb; 3213 struct drm_gem_object *obj; 3214 struct amdgpu_device *adev; 3215 struct amdgpu_bo *rbo; 3216 uint64_t chroma_addr = 0; 3217 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old; 3218 unsigned int awidth; 3219 uint32_t domain; 3220 int r; 3221 3222 dm_plane_state_old = to_dm_plane_state(plane->state); 3223 dm_plane_state_new = to_dm_plane_state(new_state); 3224 3225 if (!new_state->fb) { 3226 DRM_DEBUG_DRIVER("No FB bound\n"); 3227 return 0; 3228 } 3229 3230 afb = to_amdgpu_framebuffer(new_state->fb); 3231 obj = new_state->fb->obj[0]; 3232 rbo = gem_to_amdgpu_bo(obj); 3233 adev = amdgpu_ttm_adev(rbo->tbo.bdev); 3234 r = amdgpu_bo_reserve(rbo, false); 3235 if (unlikely(r != 0)) 3236 return r; 3237 3238 if (plane->type != DRM_PLANE_TYPE_CURSOR) 3239 domain = amdgpu_display_supported_domains(adev); 3240 else 3241 domain = AMDGPU_GEM_DOMAIN_VRAM; 3242 3243 r = amdgpu_bo_pin(rbo, domain); 3244 if (unlikely(r != 0)) { 3245 if (r != -ERESTARTSYS) 3246 DRM_ERROR("Failed to pin framebuffer with error %d\n", r); 3247 amdgpu_bo_unreserve(rbo); 3248 return r; 3249 } 3250 3251 r = amdgpu_ttm_alloc_gart(&rbo->tbo); 3252 if (unlikely(r != 0)) { 3253 amdgpu_bo_unpin(rbo); 3254 amdgpu_bo_unreserve(rbo); 3255 DRM_ERROR("%p bind failed\n", rbo); 3256 return r; 3257 } 3258 amdgpu_bo_unreserve(rbo); 3259 3260 afb->address = amdgpu_bo_gpu_offset(rbo); 3261 3262 amdgpu_bo_ref(rbo); 3263 3264 if (dm_plane_state_new->dc_state && 3265 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) { 3266 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state; 3267 3268 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 3269 plane_state->address.grph.addr.low_part = lower_32_bits(afb->address); 3270 plane_state->address.grph.addr.high_part = upper_32_bits(afb->address); 3271 } else { 3272 awidth = roundup2(new_state->fb->width, 64); 3273 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; 3274 plane_state->address.video_progressive.luma_addr.low_part 3275 = lower_32_bits(afb->address); 3276 plane_state->address.video_progressive.luma_addr.high_part 3277 = upper_32_bits(afb->address); 3278 chroma_addr = afb->address + (u64)awidth * new_state->fb->height; 3279 plane_state->address.video_progressive.chroma_addr.low_part 3280 = lower_32_bits(chroma_addr); 3281 plane_state->address.video_progressive.chroma_addr.high_part 3282 = upper_32_bits(chroma_addr); 3283 } 3284 } 3285 3286 return 0; 3287 } 3288 3289 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane, 3290 struct drm_plane_state *old_state) 3291 { 3292 struct amdgpu_bo *rbo; 3293 int r; 3294 3295 if (!old_state->fb) 3296 return; 3297 3298 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]); 3299 r = amdgpu_bo_reserve(rbo, false); 3300 if (unlikely(r)) { 3301 DRM_ERROR("failed to reserve rbo before unpin\n"); 3302 return; 3303 } 3304 3305 amdgpu_bo_unpin(rbo); 3306 amdgpu_bo_unreserve(rbo); 3307 amdgpu_bo_unref(&rbo); 3308 } 3309 3310 static int dm_plane_atomic_check(struct drm_plane *plane, 3311 struct drm_plane_state *state) 3312 { 3313 struct amdgpu_device *adev = plane->dev->dev_private; 3314 struct dc *dc = adev->dm.dc; 3315 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 3316 3317 if (!dm_plane_state->dc_state) 3318 return 0; 3319 3320 if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state)) 3321 return -EINVAL; 3322 3323 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK) 3324 return 0; 3325 3326 return -EINVAL; 3327 } 3328 3329 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { 3330 .prepare_fb = dm_plane_helper_prepare_fb, 3331 .cleanup_fb = dm_plane_helper_cleanup_fb, 3332 .atomic_check = dm_plane_atomic_check, 3333 }; 3334 3335 /* 3336 * TODO: these are currently initialized to rgb formats only. 3337 * For future use cases we should either initialize them dynamically based on 3338 * plane capabilities, or initialize this array to all formats, so internal drm 3339 * check will succeed, and let DC to implement proper check 3340 */ 3341 static const uint32_t rgb_formats[] = { 3342 DRM_FORMAT_RGB888, 3343 DRM_FORMAT_XRGB8888, 3344 DRM_FORMAT_ARGB8888, 3345 DRM_FORMAT_RGBA8888, 3346 DRM_FORMAT_XRGB2101010, 3347 DRM_FORMAT_XBGR2101010, 3348 DRM_FORMAT_ARGB2101010, 3349 DRM_FORMAT_ABGR2101010, 3350 }; 3351 3352 static const uint32_t yuv_formats[] = { 3353 DRM_FORMAT_NV12, 3354 DRM_FORMAT_NV21, 3355 }; 3356 3357 static const u32 cursor_formats[] = { 3358 DRM_FORMAT_ARGB8888 3359 }; 3360 3361 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 3362 struct amdgpu_plane *aplane, 3363 unsigned long possible_crtcs) 3364 { 3365 int res = -EPERM; 3366 3367 switch (aplane->base.type) { 3368 case DRM_PLANE_TYPE_PRIMARY: 3369 res = drm_universal_plane_init( 3370 dm->adev->ddev, 3371 &aplane->base, 3372 possible_crtcs, 3373 &dm_plane_funcs, 3374 rgb_formats, 3375 ARRAY_SIZE(rgb_formats), 3376 NULL, aplane->base.type, NULL); 3377 break; 3378 case DRM_PLANE_TYPE_OVERLAY: 3379 res = drm_universal_plane_init( 3380 dm->adev->ddev, 3381 &aplane->base, 3382 possible_crtcs, 3383 &dm_plane_funcs, 3384 yuv_formats, 3385 ARRAY_SIZE(yuv_formats), 3386 NULL, aplane->base.type, NULL); 3387 break; 3388 case DRM_PLANE_TYPE_CURSOR: 3389 res = drm_universal_plane_init( 3390 dm->adev->ddev, 3391 &aplane->base, 3392 possible_crtcs, 3393 &dm_plane_funcs, 3394 cursor_formats, 3395 ARRAY_SIZE(cursor_formats), 3396 NULL, aplane->base.type, NULL); 3397 break; 3398 } 3399 3400 drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs); 3401 3402 /* Create (reset) the plane state */ 3403 if (aplane->base.funcs->reset) 3404 aplane->base.funcs->reset(&aplane->base); 3405 3406 3407 return res; 3408 } 3409 3410 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 3411 struct drm_plane *plane, 3412 uint32_t crtc_index) 3413 { 3414 struct amdgpu_crtc *acrtc = NULL; 3415 struct amdgpu_plane *cursor_plane; 3416 3417 int res = -ENOMEM; 3418 3419 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL); 3420 if (!cursor_plane) 3421 goto fail; 3422 3423 cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR; 3424 res = amdgpu_dm_plane_init(dm, cursor_plane, 0); 3425 3426 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); 3427 if (!acrtc) 3428 goto fail; 3429 3430 res = drm_crtc_init_with_planes( 3431 dm->ddev, 3432 &acrtc->base, 3433 plane, 3434 &cursor_plane->base, 3435 &amdgpu_dm_crtc_funcs, NULL); 3436 3437 if (res) 3438 goto fail; 3439 3440 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs); 3441 3442 /* Create (reset) the plane state */ 3443 if (acrtc->base.funcs->reset) 3444 acrtc->base.funcs->reset(&acrtc->base); 3445 3446 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size; 3447 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size; 3448 3449 acrtc->crtc_id = crtc_index; 3450 acrtc->base.enabled = false; 3451 3452 dm->adev->mode_info.crtcs[crtc_index] = acrtc; 3453 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES, 3454 true, MAX_COLOR_LUT_ENTRIES); 3455 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); 3456 3457 return 0; 3458 3459 fail: 3460 kfree(acrtc); 3461 kfree(cursor_plane); 3462 return res; 3463 } 3464 3465 3466 static int to_drm_connector_type(enum amd_signal_type st) 3467 { 3468 switch (st) { 3469 case SIGNAL_TYPE_HDMI_TYPE_A: 3470 return DRM_MODE_CONNECTOR_HDMIA; 3471 case SIGNAL_TYPE_EDP: 3472 return DRM_MODE_CONNECTOR_eDP; 3473 case SIGNAL_TYPE_RGB: 3474 return DRM_MODE_CONNECTOR_VGA; 3475 case SIGNAL_TYPE_DISPLAY_PORT: 3476 case SIGNAL_TYPE_DISPLAY_PORT_MST: 3477 return DRM_MODE_CONNECTOR_DisplayPort; 3478 case SIGNAL_TYPE_DVI_DUAL_LINK: 3479 case SIGNAL_TYPE_DVI_SINGLE_LINK: 3480 return DRM_MODE_CONNECTOR_DVID; 3481 case SIGNAL_TYPE_VIRTUAL: 3482 return DRM_MODE_CONNECTOR_VIRTUAL; 3483 3484 default: 3485 return DRM_MODE_CONNECTOR_Unknown; 3486 } 3487 } 3488 3489 static void amdgpu_dm_get_native_mode(struct drm_connector *connector) 3490 { 3491 const struct drm_connector_helper_funcs *helper = 3492 connector->helper_private; 3493 struct drm_encoder *encoder; 3494 struct amdgpu_encoder *amdgpu_encoder; 3495 3496 encoder = helper->best_encoder(connector); 3497 3498 if (encoder == NULL) 3499 return; 3500 3501 amdgpu_encoder = to_amdgpu_encoder(encoder); 3502 3503 amdgpu_encoder->native_mode.clock = 0; 3504 3505 if (!list_empty(&connector->probed_modes)) { 3506 struct drm_display_mode *preferred_mode = NULL; 3507 3508 list_for_each_entry(preferred_mode, 3509 &connector->probed_modes, 3510 head) { 3511 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) 3512 amdgpu_encoder->native_mode = *preferred_mode; 3513 3514 break; 3515 } 3516 3517 } 3518 } 3519 3520 static struct drm_display_mode * 3521 amdgpu_dm_create_common_mode(struct drm_encoder *encoder, 3522 char *name, 3523 int hdisplay, int vdisplay) 3524 { 3525 struct drm_device *dev = encoder->dev; 3526 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3527 struct drm_display_mode *mode = NULL; 3528 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 3529 3530 mode = drm_mode_duplicate(dev, native_mode); 3531 3532 if (mode == NULL) 3533 return NULL; 3534 3535 mode->hdisplay = hdisplay; 3536 mode->vdisplay = vdisplay; 3537 mode->type &= ~DRM_MODE_TYPE_PREFERRED; 3538 strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN); 3539 3540 return mode; 3541 3542 } 3543 3544 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, 3545 struct drm_connector *connector) 3546 { 3547 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3548 struct drm_display_mode *mode = NULL; 3549 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 3550 struct amdgpu_dm_connector *amdgpu_dm_connector = 3551 to_amdgpu_dm_connector(connector); 3552 int i; 3553 int n; 3554 struct mode_size { 3555 char name[DRM_DISPLAY_MODE_LEN]; 3556 int w; 3557 int h; 3558 } common_modes[] = { 3559 { "640x480", 640, 480}, 3560 { "800x600", 800, 600}, 3561 { "1024x768", 1024, 768}, 3562 { "1280x720", 1280, 720}, 3563 { "1280x800", 1280, 800}, 3564 {"1280x1024", 1280, 1024}, 3565 { "1440x900", 1440, 900}, 3566 {"1680x1050", 1680, 1050}, 3567 {"1600x1200", 1600, 1200}, 3568 {"1920x1080", 1920, 1080}, 3569 {"1920x1200", 1920, 1200} 3570 }; 3571 3572 n = ARRAY_SIZE(common_modes); 3573 3574 for (i = 0; i < n; i++) { 3575 struct drm_display_mode *curmode = NULL; 3576 bool mode_existed = false; 3577 3578 if (common_modes[i].w > native_mode->hdisplay || 3579 common_modes[i].h > native_mode->vdisplay || 3580 (common_modes[i].w == native_mode->hdisplay && 3581 common_modes[i].h == native_mode->vdisplay)) 3582 continue; 3583 3584 list_for_each_entry(curmode, &connector->probed_modes, head) { 3585 if (common_modes[i].w == curmode->hdisplay && 3586 common_modes[i].h == curmode->vdisplay) { 3587 mode_existed = true; 3588 break; 3589 } 3590 } 3591 3592 if (mode_existed) 3593 continue; 3594 3595 mode = amdgpu_dm_create_common_mode(encoder, 3596 common_modes[i].name, common_modes[i].w, 3597 common_modes[i].h); 3598 drm_mode_probed_add(connector, mode); 3599 amdgpu_dm_connector->num_modes++; 3600 } 3601 } 3602 3603 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, 3604 struct edid *edid) 3605 { 3606 struct amdgpu_dm_connector *amdgpu_dm_connector = 3607 to_amdgpu_dm_connector(connector); 3608 3609 if (edid) { 3610 /* empty probed_modes */ 3611 INIT_LIST_HEAD(&connector->probed_modes); 3612 amdgpu_dm_connector->num_modes = 3613 drm_add_edid_modes(connector, edid); 3614 3615 amdgpu_dm_get_native_mode(connector); 3616 } else { 3617 amdgpu_dm_connector->num_modes = 0; 3618 } 3619 } 3620 3621 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) 3622 { 3623 const struct drm_connector_helper_funcs *helper = 3624 connector->helper_private; 3625 struct amdgpu_dm_connector *amdgpu_dm_connector = 3626 to_amdgpu_dm_connector(connector); 3627 struct drm_encoder *encoder; 3628 struct edid *edid = amdgpu_dm_connector->edid; 3629 3630 encoder = helper->best_encoder(connector); 3631 3632 if (!edid || !drm_edid_is_valid(edid)) { 3633 drm_add_modes_noedid(connector, 640, 480); 3634 } else { 3635 amdgpu_dm_connector_ddc_get_modes(connector, edid); 3636 amdgpu_dm_connector_add_common_modes(encoder, connector); 3637 } 3638 amdgpu_dm_fbc_init(connector); 3639 3640 return amdgpu_dm_connector->num_modes; 3641 } 3642 3643 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 3644 struct amdgpu_dm_connector *aconnector, 3645 int connector_type, 3646 struct dc_link *link, 3647 int link_index) 3648 { 3649 struct amdgpu_device *adev = dm->ddev->dev_private; 3650 3651 aconnector->connector_id = link_index; 3652 aconnector->dc_link = link; 3653 aconnector->base.interlace_allowed = false; 3654 aconnector->base.doublescan_allowed = false; 3655 aconnector->base.stereo_allowed = false; 3656 aconnector->base.dpms = DRM_MODE_DPMS_OFF; 3657 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ 3658 rw_init(&aconnector->hpd_lock, "dmhpd"); 3659 3660 /* configure support HPD hot plug connector_>polled default value is 0 3661 * which means HPD hot plug not supported 3662 */ 3663 switch (connector_type) { 3664 case DRM_MODE_CONNECTOR_HDMIA: 3665 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 3666 aconnector->base.ycbcr_420_allowed = 3667 link->link_enc->features.ycbcr420_supported ? true : false; 3668 break; 3669 case DRM_MODE_CONNECTOR_DisplayPort: 3670 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 3671 aconnector->base.ycbcr_420_allowed = 3672 link->link_enc->features.ycbcr420_supported ? true : false; 3673 break; 3674 case DRM_MODE_CONNECTOR_DVID: 3675 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 3676 break; 3677 default: 3678 break; 3679 } 3680 3681 drm_object_attach_property(&aconnector->base.base, 3682 dm->ddev->mode_config.scaling_mode_property, 3683 DRM_MODE_SCALE_NONE); 3684 3685 drm_object_attach_property(&aconnector->base.base, 3686 adev->mode_info.underscan_property, 3687 UNDERSCAN_OFF); 3688 drm_object_attach_property(&aconnector->base.base, 3689 adev->mode_info.underscan_hborder_property, 3690 0); 3691 drm_object_attach_property(&aconnector->base.base, 3692 adev->mode_info.underscan_vborder_property, 3693 0); 3694 drm_object_attach_property(&aconnector->base.base, 3695 adev->mode_info.max_bpc_property, 3696 0); 3697 3698 } 3699 3700 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, 3701 struct i2c_msg *msgs, int num) 3702 { 3703 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); 3704 struct ddc_service *ddc_service = i2c->ddc_service; 3705 struct i2c_command cmd; 3706 int i; 3707 int result = -EIO; 3708 3709 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); 3710 3711 if (!cmd.payloads) 3712 return result; 3713 3714 cmd.number_of_payloads = num; 3715 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 3716 cmd.speed = 100; 3717 3718 for (i = 0; i < num; i++) { 3719 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); 3720 cmd.payloads[i].address = msgs[i].addr; 3721 cmd.payloads[i].length = msgs[i].len; 3722 cmd.payloads[i].data = msgs[i].buf; 3723 } 3724 3725 if (dal_i2caux_submit_i2c_command( 3726 ddc_service->ctx->i2caux, 3727 ddc_service->ddc_pin, 3728 &cmd)) 3729 result = num; 3730 3731 kfree(cmd.payloads); 3732 return result; 3733 } 3734 3735 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) 3736 { 3737 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 3738 } 3739 3740 static const struct i2c_algorithm amdgpu_dm_i2c_algo = { 3741 .master_xfer = amdgpu_dm_i2c_xfer, 3742 .functionality = amdgpu_dm_i2c_func, 3743 }; 3744 3745 static struct amdgpu_i2c_adapter * 3746 create_i2c(struct ddc_service *ddc_service, 3747 int link_index, 3748 int *res) 3749 { 3750 struct amdgpu_device *adev = ddc_service->ctx->driver_context; 3751 struct amdgpu_i2c_adapter *i2c; 3752 3753 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); 3754 if (!i2c) 3755 return NULL; 3756 #ifdef __linux__ 3757 i2c->base.owner = THIS_MODULE; 3758 i2c->base.class = I2C_CLASS_DDC; 3759 i2c->base.dev.parent = &adev->pdev->dev; 3760 #endif 3761 i2c->base.algo = &amdgpu_dm_i2c_algo; 3762 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); 3763 i2c_set_adapdata(&i2c->base, i2c); 3764 i2c->ddc_service = ddc_service; 3765 3766 return i2c; 3767 } 3768 3769 3770 /* Note: this function assumes that dc_link_detect() was called for the 3771 * dc_link which will be represented by this aconnector. 3772 */ 3773 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 3774 struct amdgpu_dm_connector *aconnector, 3775 uint32_t link_index, 3776 struct amdgpu_encoder *aencoder) 3777 { 3778 int res = 0; 3779 int connector_type; 3780 struct dc *dc = dm->dc; 3781 struct dc_link *link = dc_get_link_at_index(dc, link_index); 3782 struct amdgpu_i2c_adapter *i2c; 3783 3784 link->priv = aconnector; 3785 3786 DRM_DEBUG_DRIVER("%s()\n", __func__); 3787 3788 i2c = create_i2c(link->ddc, link->link_index, &res); 3789 if (!i2c) { 3790 DRM_ERROR("Failed to create i2c adapter data\n"); 3791 return -ENOMEM; 3792 } 3793 3794 aconnector->i2c = i2c; 3795 res = i2c_add_adapter(&i2c->base); 3796 3797 if (res) { 3798 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); 3799 goto out_free; 3800 } 3801 3802 connector_type = to_drm_connector_type(link->connector_signal); 3803 3804 res = drm_connector_init( 3805 dm->ddev, 3806 &aconnector->base, 3807 &amdgpu_dm_connector_funcs, 3808 connector_type); 3809 3810 if (res) { 3811 DRM_ERROR("connector_init failed\n"); 3812 aconnector->connector_id = -1; 3813 goto out_free; 3814 } 3815 3816 drm_connector_helper_add( 3817 &aconnector->base, 3818 &amdgpu_dm_connector_helper_funcs); 3819 3820 if (aconnector->base.funcs->reset) 3821 aconnector->base.funcs->reset(&aconnector->base); 3822 3823 amdgpu_dm_connector_init_helper( 3824 dm, 3825 aconnector, 3826 connector_type, 3827 link, 3828 link_index); 3829 3830 drm_connector_attach_encoder( 3831 &aconnector->base, &aencoder->base); 3832 3833 drm_connector_register(&aconnector->base); 3834 #if defined(CONFIG_DEBUG_FS) 3835 res = connector_debugfs_init(aconnector); 3836 if (res) { 3837 DRM_ERROR("Failed to create debugfs for connector"); 3838 goto out_free; 3839 } 3840 #endif 3841 3842 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort 3843 || connector_type == DRM_MODE_CONNECTOR_eDP) 3844 amdgpu_dm_initialize_dp_connector(dm, aconnector); 3845 3846 out_free: 3847 if (res) { 3848 kfree(i2c); 3849 aconnector->i2c = NULL; 3850 } 3851 return res; 3852 } 3853 3854 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) 3855 { 3856 switch (adev->mode_info.num_crtc) { 3857 case 1: 3858 return 0x1; 3859 case 2: 3860 return 0x3; 3861 case 3: 3862 return 0x7; 3863 case 4: 3864 return 0xf; 3865 case 5: 3866 return 0x1f; 3867 case 6: 3868 default: 3869 return 0x3f; 3870 } 3871 } 3872 3873 static int amdgpu_dm_encoder_init(struct drm_device *dev, 3874 struct amdgpu_encoder *aencoder, 3875 uint32_t link_index) 3876 { 3877 struct amdgpu_device *adev = dev->dev_private; 3878 3879 int res = drm_encoder_init(dev, 3880 &aencoder->base, 3881 &amdgpu_dm_encoder_funcs, 3882 DRM_MODE_ENCODER_TMDS, 3883 NULL); 3884 3885 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 3886 3887 if (!res) 3888 aencoder->encoder_id = link_index; 3889 else 3890 aencoder->encoder_id = -1; 3891 3892 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); 3893 3894 return res; 3895 } 3896 3897 static void manage_dm_interrupts(struct amdgpu_device *adev, 3898 struct amdgpu_crtc *acrtc, 3899 bool enable) 3900 { 3901 /* 3902 * this is not correct translation but will work as soon as VBLANK 3903 * constant is the same as PFLIP 3904 */ 3905 int irq_type = 3906 amdgpu_display_crtc_idx_to_irq_type( 3907 adev, 3908 acrtc->crtc_id); 3909 3910 if (enable) { 3911 drm_crtc_vblank_on(&acrtc->base); 3912 amdgpu_irq_get( 3913 adev, 3914 &adev->pageflip_irq, 3915 irq_type); 3916 } else { 3917 3918 amdgpu_irq_put( 3919 adev, 3920 &adev->pageflip_irq, 3921 irq_type); 3922 drm_crtc_vblank_off(&acrtc->base); 3923 } 3924 } 3925 3926 static bool 3927 is_scaling_state_different(const struct dm_connector_state *dm_state, 3928 const struct dm_connector_state *old_dm_state) 3929 { 3930 if (dm_state->scaling != old_dm_state->scaling) 3931 return true; 3932 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 3933 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 3934 return true; 3935 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 3936 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 3937 return true; 3938 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 3939 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 3940 return true; 3941 return false; 3942 } 3943 3944 static void remove_stream(struct amdgpu_device *adev, 3945 struct amdgpu_crtc *acrtc, 3946 struct dc_stream_state *stream) 3947 { 3948 /* this is the update mode case */ 3949 if (adev->dm.freesync_module) 3950 mod_freesync_remove_stream(adev->dm.freesync_module, stream); 3951 3952 acrtc->otg_inst = -1; 3953 acrtc->enabled = false; 3954 } 3955 3956 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, 3957 struct dc_cursor_position *position) 3958 { 3959 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 3960 int x, y; 3961 int xorigin = 0, yorigin = 0; 3962 3963 if (!crtc || !plane->state->fb) { 3964 position->enable = false; 3965 position->x = 0; 3966 position->y = 0; 3967 return 0; 3968 } 3969 3970 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) || 3971 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) { 3972 DRM_ERROR("%s: bad cursor width or height %d x %d\n", 3973 __func__, 3974 plane->state->crtc_w, 3975 plane->state->crtc_h); 3976 return -EINVAL; 3977 } 3978 3979 x = plane->state->crtc_x; 3980 y = plane->state->crtc_y; 3981 /* avivo cursor are offset into the total surface */ 3982 x += crtc->primary->state->src_x >> 16; 3983 y += crtc->primary->state->src_y >> 16; 3984 if (x < 0) { 3985 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 3986 x = 0; 3987 } 3988 if (y < 0) { 3989 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 3990 y = 0; 3991 } 3992 position->enable = true; 3993 position->x = x; 3994 position->y = y; 3995 position->x_hotspot = xorigin; 3996 position->y_hotspot = yorigin; 3997 3998 return 0; 3999 } 4000 4001 static void handle_cursor_update(struct drm_plane *plane, 4002 struct drm_plane_state *old_plane_state) 4003 { 4004 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 4005 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 4006 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 4007 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 4008 uint64_t address = afb ? afb->address : 0; 4009 struct dc_cursor_position position; 4010 struct dc_cursor_attributes attributes; 4011 int ret; 4012 4013 if (!plane->state->fb && !old_plane_state->fb) 4014 return; 4015 4016 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n", 4017 __func__, 4018 amdgpu_crtc->crtc_id, 4019 plane->state->crtc_w, 4020 plane->state->crtc_h); 4021 4022 ret = get_cursor_position(plane, crtc, &position); 4023 if (ret) 4024 return; 4025 4026 if (!position.enable) { 4027 /* turn off cursor */ 4028 if (crtc_state && crtc_state->stream) 4029 dc_stream_set_cursor_position(crtc_state->stream, 4030 &position); 4031 return; 4032 } 4033 4034 amdgpu_crtc->cursor_width = plane->state->crtc_w; 4035 amdgpu_crtc->cursor_height = plane->state->crtc_h; 4036 4037 memset(&attributes, 0, sizeof(attributes)); 4038 attributes.address.high_part = upper_32_bits(address); 4039 attributes.address.low_part = lower_32_bits(address); 4040 attributes.width = plane->state->crtc_w; 4041 attributes.height = plane->state->crtc_h; 4042 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 4043 attributes.rotation_angle = 0; 4044 attributes.attribute_flags.value = 0; 4045 4046 attributes.pitch = attributes.width; 4047 4048 if (crtc_state->stream) { 4049 if (!dc_stream_set_cursor_attributes(crtc_state->stream, 4050 &attributes)) 4051 DRM_ERROR("DC failed to set cursor attributes\n"); 4052 4053 if (!dc_stream_set_cursor_position(crtc_state->stream, 4054 &position)) 4055 DRM_ERROR("DC failed to set cursor position\n"); 4056 } 4057 } 4058 4059 static void prepare_flip_isr(struct amdgpu_crtc *acrtc) 4060 { 4061 4062 assert_spin_locked(&acrtc->base.dev->event_lock); 4063 WARN_ON(acrtc->event); 4064 4065 acrtc->event = acrtc->base.state->event; 4066 4067 /* Set the flip status */ 4068 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 4069 4070 /* Mark this event as consumed */ 4071 acrtc->base.state->event = NULL; 4072 4073 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 4074 acrtc->crtc_id); 4075 } 4076 4077 /* 4078 * Executes flip 4079 * 4080 * Waits on all BO's fences and for proper vblank count 4081 */ 4082 static void amdgpu_dm_do_flip(struct drm_crtc *crtc, 4083 struct drm_framebuffer *fb, 4084 uint32_t target, 4085 struct dc_state *state) 4086 { 4087 unsigned long flags; 4088 uint32_t target_vblank; 4089 int r, vpos, hpos; 4090 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4091 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); 4092 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); 4093 struct amdgpu_device *adev = crtc->dev->dev_private; 4094 bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 4095 struct dc_flip_addrs addr = { {0} }; 4096 /* TODO eliminate or rename surface_update */ 4097 struct dc_surface_update surface_updates[1] = { {0} }; 4098 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); 4099 4100 4101 /* Prepare wait for target vblank early - before the fence-waits */ 4102 target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) + 4103 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id); 4104 4105 /* TODO This might fail and hence better not used, wait 4106 * explicitly on fences instead 4107 * and in general should be called for 4108 * blocking commit to as per framework helpers 4109 */ 4110 r = amdgpu_bo_reserve(abo, true); 4111 if (unlikely(r != 0)) { 4112 DRM_ERROR("failed to reserve buffer before flip\n"); 4113 WARN_ON(1); 4114 } 4115 4116 /* Wait for all fences on this FB */ 4117 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false, 4118 MAX_SCHEDULE_TIMEOUT) < 0); 4119 4120 amdgpu_bo_unreserve(abo); 4121 4122 /* Wait until we're out of the vertical blank period before the one 4123 * targeted by the flip 4124 */ 4125 while ((acrtc->enabled && 4126 (amdgpu_display_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id, 4127 0, &vpos, &hpos, NULL, 4128 NULL, &crtc->hwmode) 4129 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 4130 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 4131 (int)(target_vblank - 4132 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) { 4133 usleep_range(1000, 1100); 4134 } 4135 4136 /* Flip */ 4137 spin_lock_irqsave(&crtc->dev->event_lock, flags); 4138 4139 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE); 4140 WARN_ON(!acrtc_state->stream); 4141 4142 addr.address.grph.addr.low_part = lower_32_bits(afb->address); 4143 addr.address.grph.addr.high_part = upper_32_bits(afb->address); 4144 addr.flip_immediate = async_flip; 4145 4146 4147 if (acrtc->base.state->event) 4148 prepare_flip_isr(acrtc); 4149 4150 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 4151 4152 surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0]; 4153 surface_updates->flip_addr = &addr; 4154 4155 dc_commit_updates_for_stream(adev->dm.dc, 4156 surface_updates, 4157 1, 4158 acrtc_state->stream, 4159 NULL, 4160 &surface_updates->surface, 4161 state); 4162 4163 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n", 4164 __func__, 4165 addr.address.grph.addr.high_part, 4166 addr.address.grph.addr.low_part); 4167 } 4168 4169 /* 4170 * TODO this whole function needs to go 4171 * 4172 * dc_surface_update is needlessly complex. See if we can just replace this 4173 * with a dc_plane_state and follow the atomic model a bit more closely here. 4174 */ 4175 static bool commit_planes_to_stream( 4176 struct dc *dc, 4177 struct dc_plane_state **plane_states, 4178 uint8_t new_plane_count, 4179 struct dm_crtc_state *dm_new_crtc_state, 4180 struct dm_crtc_state *dm_old_crtc_state, 4181 struct dc_state *state) 4182 { 4183 /* no need to dynamically allocate this. it's pretty small */ 4184 struct dc_surface_update updates[MAX_SURFACES]; 4185 struct dc_flip_addrs *flip_addr; 4186 struct dc_plane_info *plane_info; 4187 struct dc_scaling_info *scaling_info; 4188 int i; 4189 struct dc_stream_state *dc_stream = dm_new_crtc_state->stream; 4190 struct dc_stream_update *stream_update = 4191 kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL); 4192 4193 if (!stream_update) { 4194 BREAK_TO_DEBUGGER(); 4195 return false; 4196 } 4197 4198 flip_addr = kcalloc(MAX_SURFACES, sizeof(struct dc_flip_addrs), 4199 GFP_KERNEL); 4200 plane_info = kcalloc(MAX_SURFACES, sizeof(struct dc_plane_info), 4201 GFP_KERNEL); 4202 scaling_info = kcalloc(MAX_SURFACES, sizeof(struct dc_scaling_info), 4203 GFP_KERNEL); 4204 4205 if (!flip_addr || !plane_info || !scaling_info) { 4206 kfree(flip_addr); 4207 kfree(plane_info); 4208 kfree(scaling_info); 4209 kfree(stream_update); 4210 return false; 4211 } 4212 4213 memset(updates, 0, sizeof(updates)); 4214 4215 stream_update->src = dc_stream->src; 4216 stream_update->dst = dc_stream->dst; 4217 stream_update->out_transfer_func = dc_stream->out_transfer_func; 4218 4219 for (i = 0; i < new_plane_count; i++) { 4220 updates[i].surface = plane_states[i]; 4221 updates[i].gamma = 4222 (struct dc_gamma *)plane_states[i]->gamma_correction; 4223 updates[i].in_transfer_func = plane_states[i]->in_transfer_func; 4224 flip_addr[i].address = plane_states[i]->address; 4225 flip_addr[i].flip_immediate = plane_states[i]->flip_immediate; 4226 plane_info[i].color_space = plane_states[i]->color_space; 4227 plane_info[i].format = plane_states[i]->format; 4228 plane_info[i].plane_size = plane_states[i]->plane_size; 4229 plane_info[i].rotation = plane_states[i]->rotation; 4230 plane_info[i].horizontal_mirror = plane_states[i]->horizontal_mirror; 4231 plane_info[i].stereo_format = plane_states[i]->stereo_format; 4232 plane_info[i].tiling_info = plane_states[i]->tiling_info; 4233 plane_info[i].visible = plane_states[i]->visible; 4234 plane_info[i].per_pixel_alpha = plane_states[i]->per_pixel_alpha; 4235 plane_info[i].dcc = plane_states[i]->dcc; 4236 scaling_info[i].scaling_quality = plane_states[i]->scaling_quality; 4237 scaling_info[i].src_rect = plane_states[i]->src_rect; 4238 scaling_info[i].dst_rect = plane_states[i]->dst_rect; 4239 scaling_info[i].clip_rect = plane_states[i]->clip_rect; 4240 4241 updates[i].flip_addr = &flip_addr[i]; 4242 updates[i].plane_info = &plane_info[i]; 4243 updates[i].scaling_info = &scaling_info[i]; 4244 } 4245 4246 dc_commit_updates_for_stream( 4247 dc, 4248 updates, 4249 new_plane_count, 4250 dc_stream, stream_update, plane_states, state); 4251 4252 kfree(flip_addr); 4253 kfree(plane_info); 4254 kfree(scaling_info); 4255 kfree(stream_update); 4256 return true; 4257 } 4258 4259 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 4260 struct drm_device *dev, 4261 struct amdgpu_display_manager *dm, 4262 struct drm_crtc *pcrtc, 4263 bool *wait_for_vblank) 4264 { 4265 uint32_t i; 4266 struct drm_plane *plane; 4267 struct drm_plane_state *old_plane_state, *new_plane_state; 4268 struct dc_stream_state *dc_stream_attach; 4269 struct dc_plane_state *plane_states_constructed[MAX_SURFACES]; 4270 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 4271 struct drm_crtc_state *new_pcrtc_state = 4272 drm_atomic_get_new_crtc_state(state, pcrtc); 4273 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 4274 struct dm_crtc_state *dm_old_crtc_state = 4275 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 4276 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 4277 int planes_count = 0; 4278 unsigned long flags; 4279 4280 /* update planes when needed */ 4281 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 4282 struct drm_crtc *crtc = new_plane_state->crtc; 4283 struct drm_crtc_state *new_crtc_state; 4284 struct drm_framebuffer *fb = new_plane_state->fb; 4285 bool pflip_needed; 4286 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 4287 4288 if (plane->type == DRM_PLANE_TYPE_CURSOR) { 4289 handle_cursor_update(plane, old_plane_state); 4290 continue; 4291 } 4292 4293 if (!fb || !crtc || pcrtc != crtc) 4294 continue; 4295 4296 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 4297 if (!new_crtc_state->active) 4298 continue; 4299 4300 pflip_needed = !state->allow_modeset; 4301 4302 spin_lock_irqsave(&crtc->dev->event_lock, flags); 4303 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) { 4304 DRM_ERROR("%s: acrtc %d, already busy\n", 4305 __func__, 4306 acrtc_attach->crtc_id); 4307 /* In commit tail framework this cannot happen */ 4308 WARN_ON(1); 4309 } 4310 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 4311 4312 if (!pflip_needed || plane->type == DRM_PLANE_TYPE_OVERLAY) { 4313 WARN_ON(!dm_new_plane_state->dc_state); 4314 4315 plane_states_constructed[planes_count] = dm_new_plane_state->dc_state; 4316 4317 dc_stream_attach = acrtc_state->stream; 4318 planes_count++; 4319 4320 } else if (new_crtc_state->planes_changed) { 4321 /* Assume even ONE crtc with immediate flip means 4322 * entire can't wait for VBLANK 4323 * TODO Check if it's correct 4324 */ 4325 *wait_for_vblank = 4326 new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ? 4327 false : true; 4328 4329 /* TODO: Needs rework for multiplane flip */ 4330 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 4331 drm_crtc_vblank_get(crtc); 4332 4333 amdgpu_dm_do_flip( 4334 crtc, 4335 fb, 4336 (uint32_t)drm_crtc_vblank_count(crtc) + *wait_for_vblank, 4337 dm_state->context); 4338 } 4339 4340 } 4341 4342 if (planes_count) { 4343 unsigned long flags; 4344 4345 if (new_pcrtc_state->event) { 4346 4347 drm_crtc_vblank_get(pcrtc); 4348 4349 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 4350 prepare_flip_isr(acrtc_attach); 4351 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4352 } 4353 4354 4355 if (false == commit_planes_to_stream(dm->dc, 4356 plane_states_constructed, 4357 planes_count, 4358 acrtc_state, 4359 dm_old_crtc_state, 4360 dm_state->context)) 4361 dm_error("%s: Failed to attach plane!\n", __func__); 4362 } else { 4363 /*TODO BUG Here should go disable planes on CRTC. */ 4364 } 4365 } 4366 4367 /** 4368 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 4369 * @crtc_state: the DRM CRTC state 4370 * @stream_state: the DC stream state. 4371 * 4372 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 4373 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 4374 */ 4375 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 4376 struct dc_stream_state *stream_state) 4377 { 4378 stream_state->mode_changed = 4379 crtc_state->mode_changed || crtc_state->active_changed; 4380 } 4381 4382 static int amdgpu_dm_atomic_commit(struct drm_device *dev, 4383 struct drm_atomic_state *state, 4384 bool nonblock) 4385 { 4386 struct drm_crtc *crtc; 4387 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4388 struct amdgpu_device *adev = dev->dev_private; 4389 int i; 4390 4391 /* 4392 * We evade vblanks and pflips on crtc that 4393 * should be changed. We do it here to flush & disable 4394 * interrupts before drm_swap_state is called in drm_atomic_helper_commit 4395 * it will update crtc->dm_crtc_state->stream pointer which is used in 4396 * the ISRs. 4397 */ 4398 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 4399 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4400 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4401 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4402 4403 if (drm_atomic_crtc_needs_modeset(new_crtc_state) 4404 && dm_old_crtc_state->stream) { 4405 /* 4406 * CRC capture was enabled but not disabled. 4407 * Release the vblank reference. 4408 */ 4409 if (dm_new_crtc_state->crc_enabled) { 4410 drm_crtc_vblank_put(crtc); 4411 dm_new_crtc_state->crc_enabled = false; 4412 } 4413 4414 manage_dm_interrupts(adev, acrtc, false); 4415 } 4416 } 4417 /* Add check here for SoC's that support hardware cursor plane, to 4418 * unset legacy_cursor_update */ 4419 4420 return drm_atomic_helper_commit(dev, state, nonblock); 4421 4422 /*TODO Handle EINTR, reenable IRQ*/ 4423 } 4424 4425 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) 4426 { 4427 struct drm_device *dev = state->dev; 4428 struct amdgpu_device *adev = dev->dev_private; 4429 struct amdgpu_display_manager *dm = &adev->dm; 4430 struct dm_atomic_state *dm_state; 4431 uint32_t i, j; 4432 struct drm_crtc *crtc; 4433 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4434 unsigned long flags; 4435 bool wait_for_vblank = true; 4436 struct drm_connector *connector; 4437 struct drm_connector_state *old_con_state, *new_con_state; 4438 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 4439 int crtc_disable_count = 0; 4440 4441 drm_atomic_helper_update_legacy_modeset_state(dev, state); 4442 4443 dm_state = to_dm_atomic_state(state); 4444 4445 /* update changed items */ 4446 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 4447 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4448 4449 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4450 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4451 4452 DRM_DEBUG_DRIVER( 4453 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 4454 "planes_changed:%d, mode_changed:%d,active_changed:%d," 4455 "connectors_changed:%d\n", 4456 acrtc->crtc_id, 4457 new_crtc_state->enable, 4458 new_crtc_state->active, 4459 new_crtc_state->planes_changed, 4460 new_crtc_state->mode_changed, 4461 new_crtc_state->active_changed, 4462 new_crtc_state->connectors_changed); 4463 4464 /* Copy all transient state flags into dc state */ 4465 if (dm_new_crtc_state->stream) { 4466 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 4467 dm_new_crtc_state->stream); 4468 } 4469 4470 /* handles headless hotplug case, updating new_state and 4471 * aconnector as needed 4472 */ 4473 4474 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 4475 4476 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); 4477 4478 if (!dm_new_crtc_state->stream) { 4479 /* 4480 * this could happen because of issues with 4481 * userspace notifications delivery. 4482 * In this case userspace tries to set mode on 4483 * display which is disconnect in fact. 4484 * dc_sink in NULL in this case on aconnector. 4485 * We expect reset mode will come soon. 4486 * 4487 * This can also happen when unplug is done 4488 * during resume sequence ended 4489 * 4490 * In this case, we want to pretend we still 4491 * have a sink to keep the pipe running so that 4492 * hw state is consistent with the sw state 4493 */ 4494 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 4495 __func__, acrtc->base.base.id); 4496 continue; 4497 } 4498 4499 if (dm_old_crtc_state->stream) 4500 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 4501 4502 pm_runtime_get_noresume(dev->dev); 4503 4504 acrtc->enabled = true; 4505 acrtc->hw_mode = new_crtc_state->mode; 4506 crtc->hwmode = new_crtc_state->mode; 4507 } else if (modereset_required(new_crtc_state)) { 4508 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); 4509 4510 /* i.e. reset mode */ 4511 if (dm_old_crtc_state->stream) 4512 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 4513 } 4514 } /* for_each_crtc_in_state() */ 4515 4516 /* 4517 * Add streams after required streams from new and replaced streams 4518 * are removed from freesync module 4519 */ 4520 if (adev->dm.freesync_module) { 4521 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 4522 new_crtc_state, i) { 4523 struct amdgpu_dm_connector *aconnector = NULL; 4524 struct dm_connector_state *dm_new_con_state = NULL; 4525 struct amdgpu_crtc *acrtc = NULL; 4526 bool modeset_needed; 4527 4528 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4529 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4530 modeset_needed = modeset_required( 4531 new_crtc_state, 4532 dm_new_crtc_state->stream, 4533 dm_old_crtc_state->stream); 4534 /* We add stream to freesync if: 4535 * 1. Said stream is not null, and 4536 * 2. A modeset is requested. This means that the 4537 * stream was removed previously, and needs to be 4538 * replaced. 4539 */ 4540 if (dm_new_crtc_state->stream == NULL || 4541 !modeset_needed) 4542 continue; 4543 4544 acrtc = to_amdgpu_crtc(crtc); 4545 4546 aconnector = 4547 amdgpu_dm_find_first_crtc_matching_connector( 4548 state, crtc); 4549 if (!aconnector) { 4550 DRM_DEBUG_DRIVER("Atomic commit: Failed to " 4551 "find connector for acrtc " 4552 "id:%d skipping freesync " 4553 "init\n", 4554 acrtc->crtc_id); 4555 continue; 4556 } 4557 4558 mod_freesync_add_stream(adev->dm.freesync_module, 4559 dm_new_crtc_state->stream, 4560 &aconnector->caps); 4561 new_con_state = drm_atomic_get_new_connector_state( 4562 state, &aconnector->base); 4563 dm_new_con_state = to_dm_connector_state(new_con_state); 4564 4565 mod_freesync_set_user_enable(adev->dm.freesync_module, 4566 &dm_new_crtc_state->stream, 4567 1, 4568 &dm_new_con_state->user_enable); 4569 } 4570 } 4571 4572 if (dm_state->context) { 4573 dm_enable_per_frame_crtc_master_sync(dm_state->context); 4574 WARN_ON(!dc_commit_state(dm->dc, dm_state->context)); 4575 } 4576 4577 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 4578 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4579 4580 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4581 4582 if (dm_new_crtc_state->stream != NULL) { 4583 const struct dc_stream_status *status = 4584 dc_stream_get_status(dm_new_crtc_state->stream); 4585 4586 if (!status) 4587 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc); 4588 else 4589 acrtc->otg_inst = status->primary_otg_inst; 4590 } 4591 } 4592 4593 /* Handle scaling and underscan changes*/ 4594 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 4595 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 4596 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 4597 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 4598 struct dc_stream_status *status = NULL; 4599 4600 if (acrtc) { 4601 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 4602 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 4603 } 4604 4605 /* Skip any modesets/resets */ 4606 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 4607 continue; 4608 4609 /* Skip any thing not scale or underscan changes */ 4610 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 4611 continue; 4612 4613 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4614 4615 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, 4616 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream); 4617 4618 if (!dm_new_crtc_state->stream) 4619 continue; 4620 4621 status = dc_stream_get_status(dm_new_crtc_state->stream); 4622 WARN_ON(!status); 4623 WARN_ON(!status->plane_count); 4624 4625 /*TODO How it works with MPO ?*/ 4626 if (!commit_planes_to_stream( 4627 dm->dc, 4628 status->plane_states, 4629 status->plane_count, 4630 dm_new_crtc_state, 4631 to_dm_crtc_state(old_crtc_state), 4632 dm_state->context)) 4633 dm_error("%s: Failed to update stream scaling!\n", __func__); 4634 } 4635 4636 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 4637 new_crtc_state, i) { 4638 /* 4639 * loop to enable interrupts on newly arrived crtc 4640 */ 4641 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4642 bool modeset_needed; 4643 4644 if (old_crtc_state->active && !new_crtc_state->active) 4645 crtc_disable_count++; 4646 4647 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4648 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4649 modeset_needed = modeset_required( 4650 new_crtc_state, 4651 dm_new_crtc_state->stream, 4652 dm_old_crtc_state->stream); 4653 4654 if (dm_new_crtc_state->stream == NULL || !modeset_needed) 4655 continue; 4656 4657 if (adev->dm.freesync_module) 4658 mod_freesync_notify_mode_change( 4659 adev->dm.freesync_module, 4660 &dm_new_crtc_state->stream, 1); 4661 4662 manage_dm_interrupts(adev, acrtc, true); 4663 } 4664 4665 /* update planes when needed per crtc*/ 4666 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 4667 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4668 4669 if (dm_new_crtc_state->stream) 4670 amdgpu_dm_commit_planes(state, dev, dm, crtc, &wait_for_vblank); 4671 } 4672 4673 4674 /* 4675 * send vblank event on all events not handled in flip and 4676 * mark consumed event for drm_atomic_helper_commit_hw_done 4677 */ 4678 spin_lock_irqsave(&adev->ddev->event_lock, flags); 4679 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 4680 4681 if (new_crtc_state->event) 4682 drm_send_event_locked(dev, &new_crtc_state->event->base); 4683 4684 new_crtc_state->event = NULL; 4685 } 4686 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 4687 4688 4689 if (wait_for_vblank) 4690 drm_atomic_helper_wait_for_flip_done(dev, state); 4691 4692 /* 4693 * FIXME: 4694 * Delay hw_done() until flip_done() is signaled. This is to block 4695 * another commit from freeing the CRTC state while we're still 4696 * waiting on flip_done. 4697 */ 4698 drm_atomic_helper_commit_hw_done(state); 4699 4700 drm_atomic_helper_cleanup_planes(dev, state); 4701 4702 /* Finally, drop a runtime PM reference for each newly disabled CRTC, 4703 * so we can put the GPU into runtime suspend if we're not driving any 4704 * displays anymore 4705 */ 4706 for (i = 0; i < crtc_disable_count; i++) 4707 pm_runtime_put_autosuspend(dev->dev); 4708 pm_runtime_mark_last_busy(dev->dev); 4709 } 4710 4711 4712 static int dm_force_atomic_commit(struct drm_connector *connector) 4713 { 4714 int ret = 0; 4715 struct drm_device *ddev = connector->dev; 4716 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); 4717 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 4718 struct drm_plane *plane = disconnected_acrtc->base.primary; 4719 struct drm_connector_state *conn_state; 4720 struct drm_crtc_state *crtc_state; 4721 struct drm_plane_state *plane_state; 4722 4723 if (!state) 4724 return -ENOMEM; 4725 4726 state->acquire_ctx = ddev->mode_config.acquire_ctx; 4727 4728 /* Construct an atomic state to restore previous display setting */ 4729 4730 /* 4731 * Attach connectors to drm_atomic_state 4732 */ 4733 conn_state = drm_atomic_get_connector_state(state, connector); 4734 4735 ret = PTR_ERR_OR_ZERO(conn_state); 4736 if (ret) 4737 goto err; 4738 4739 /* Attach crtc to drm_atomic_state*/ 4740 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); 4741 4742 ret = PTR_ERR_OR_ZERO(crtc_state); 4743 if (ret) 4744 goto err; 4745 4746 /* force a restore */ 4747 crtc_state->mode_changed = true; 4748 4749 /* Attach plane to drm_atomic_state */ 4750 plane_state = drm_atomic_get_plane_state(state, plane); 4751 4752 ret = PTR_ERR_OR_ZERO(plane_state); 4753 if (ret) 4754 goto err; 4755 4756 4757 /* Call commit internally with the state we just constructed */ 4758 ret = drm_atomic_commit(state); 4759 if (!ret) 4760 return 0; 4761 4762 err: 4763 DRM_ERROR("Restoring old state failed with %i\n", ret); 4764 drm_atomic_state_put(state); 4765 4766 return ret; 4767 } 4768 4769 /* 4770 * This functions handle all cases when set mode does not come upon hotplug. 4771 * This include when the same display is unplugged then plugged back into the 4772 * same port and when we are running without usermode desktop manager supprot 4773 */ 4774 void dm_restore_drm_connector_state(struct drm_device *dev, 4775 struct drm_connector *connector) 4776 { 4777 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 4778 struct amdgpu_crtc *disconnected_acrtc; 4779 struct dm_crtc_state *acrtc_state; 4780 4781 if (!aconnector->dc_sink || !connector->state || !connector->encoder) 4782 return; 4783 4784 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 4785 if (!disconnected_acrtc) 4786 return; 4787 4788 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); 4789 if (!acrtc_state->stream) 4790 return; 4791 4792 /* 4793 * If the previous sink is not released and different from the current, 4794 * we deduce we are in a state where we can not rely on usermode call 4795 * to turn on the display, so we do it here 4796 */ 4797 if (acrtc_state->stream->sink != aconnector->dc_sink) 4798 dm_force_atomic_commit(&aconnector->base); 4799 } 4800 4801 /*` 4802 * Grabs all modesetting locks to serialize against any blocking commits, 4803 * Waits for completion of all non blocking commits. 4804 */ 4805 static int do_aquire_global_lock(struct drm_device *dev, 4806 struct drm_atomic_state *state) 4807 { 4808 struct drm_crtc *crtc; 4809 struct drm_crtc_commit *commit; 4810 long ret; 4811 4812 /* Adding all modeset locks to aquire_ctx will 4813 * ensure that when the framework release it the 4814 * extra locks we are locking here will get released to 4815 */ 4816 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 4817 if (ret) 4818 return ret; 4819 4820 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 4821 spin_lock(&crtc->commit_lock); 4822 commit = list_first_entry_or_null(&crtc->commit_list, 4823 struct drm_crtc_commit, commit_entry); 4824 if (commit) 4825 drm_crtc_commit_get(commit); 4826 spin_unlock(&crtc->commit_lock); 4827 4828 if (!commit) 4829 continue; 4830 4831 /* Make sure all pending HW programming completed and 4832 * page flips done 4833 */ 4834 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 4835 4836 if (ret > 0) 4837 ret = wait_for_completion_interruptible_timeout( 4838 &commit->flip_done, 10*HZ); 4839 4840 if (ret == 0) 4841 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done " 4842 "timed out\n", crtc->base.id, crtc->name); 4843 4844 drm_crtc_commit_put(commit); 4845 } 4846 4847 return ret < 0 ? ret : 0; 4848 } 4849 4850 static int dm_update_crtcs_state(struct dc *dc, 4851 struct drm_atomic_state *state, 4852 bool enable, 4853 bool *lock_and_validation_needed) 4854 { 4855 struct drm_crtc *crtc; 4856 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4857 int i; 4858 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 4859 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 4860 struct dc_stream_state *new_stream; 4861 int ret = 0; 4862 4863 /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */ 4864 /* update changed items */ 4865 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 4866 struct amdgpu_crtc *acrtc = NULL; 4867 struct amdgpu_dm_connector *aconnector = NULL; 4868 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 4869 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 4870 struct drm_plane_state *new_plane_state = NULL; 4871 4872 new_stream = NULL; 4873 4874 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4875 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4876 acrtc = to_amdgpu_crtc(crtc); 4877 4878 new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary); 4879 4880 if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) { 4881 ret = -EINVAL; 4882 goto fail; 4883 } 4884 4885 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 4886 4887 /* TODO This hack should go away */ 4888 if (aconnector && enable) { 4889 // Make sure fake sink is created in plug-in scenario 4890 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 4891 &aconnector->base); 4892 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 4893 &aconnector->base); 4894 4895 if (IS_ERR(drm_new_conn_state)) { 4896 ret = PTR_ERR_OR_ZERO(drm_new_conn_state); 4897 break; 4898 } 4899 4900 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 4901 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 4902 4903 new_stream = create_stream_for_sink(aconnector, 4904 &new_crtc_state->mode, 4905 dm_new_conn_state); 4906 4907 /* 4908 * we can have no stream on ACTION_SET if a display 4909 * was disconnected during S3, in this case it not and 4910 * error, the OS will be updated after detection, and 4911 * do the right thing on next atomic commit 4912 */ 4913 4914 if (!new_stream) { 4915 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 4916 __func__, acrtc->base.base.id); 4917 break; 4918 } 4919 4920 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 4921 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 4922 new_crtc_state->mode_changed = false; 4923 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", 4924 new_crtc_state->mode_changed); 4925 } 4926 } 4927 4928 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 4929 goto next_crtc; 4930 4931 DRM_DEBUG_DRIVER( 4932 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 4933 "planes_changed:%d, mode_changed:%d,active_changed:%d," 4934 "connectors_changed:%d\n", 4935 acrtc->crtc_id, 4936 new_crtc_state->enable, 4937 new_crtc_state->active, 4938 new_crtc_state->planes_changed, 4939 new_crtc_state->mode_changed, 4940 new_crtc_state->active_changed, 4941 new_crtc_state->connectors_changed); 4942 4943 /* Remove stream for any changed/disabled CRTC */ 4944 if (!enable) { 4945 4946 if (!dm_old_crtc_state->stream) 4947 goto next_crtc; 4948 4949 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", 4950 crtc->base.id); 4951 4952 /* i.e. reset mode */ 4953 if (dc_remove_stream_from_ctx( 4954 dc, 4955 dm_state->context, 4956 dm_old_crtc_state->stream) != DC_OK) { 4957 ret = -EINVAL; 4958 goto fail; 4959 } 4960 4961 dc_stream_release(dm_old_crtc_state->stream); 4962 dm_new_crtc_state->stream = NULL; 4963 4964 *lock_and_validation_needed = true; 4965 4966 } else {/* Add stream for any updated/enabled CRTC */ 4967 /* 4968 * Quick fix to prevent NULL pointer on new_stream when 4969 * added MST connectors not found in existing crtc_state in the chained mode 4970 * TODO: need to dig out the root cause of that 4971 */ 4972 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port)) 4973 goto next_crtc; 4974 4975 if (modereset_required(new_crtc_state)) 4976 goto next_crtc; 4977 4978 if (modeset_required(new_crtc_state, new_stream, 4979 dm_old_crtc_state->stream)) { 4980 4981 WARN_ON(dm_new_crtc_state->stream); 4982 4983 dm_new_crtc_state->stream = new_stream; 4984 4985 dc_stream_retain(new_stream); 4986 4987 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n", 4988 crtc->base.id); 4989 4990 if (dc_add_stream_to_ctx( 4991 dc, 4992 dm_state->context, 4993 dm_new_crtc_state->stream) != DC_OK) { 4994 ret = -EINVAL; 4995 goto fail; 4996 } 4997 4998 *lock_and_validation_needed = true; 4999 } 5000 } 5001 5002 next_crtc: 5003 /* Release extra reference */ 5004 if (new_stream) 5005 dc_stream_release(new_stream); 5006 5007 /* 5008 * We want to do dc stream updates that do not require a 5009 * full modeset below. 5010 */ 5011 if (!(enable && aconnector && new_crtc_state->enable && 5012 new_crtc_state->active)) 5013 continue; 5014 /* 5015 * Given above conditions, the dc state cannot be NULL because: 5016 * 1. We're in the process of enabling CRTCs (just been added 5017 * to the dc context, or already is on the context) 5018 * 2. Has a valid connector attached, and 5019 * 3. Is currently active and enabled. 5020 * => The dc stream state currently exists. 5021 */ 5022 BUG_ON(dm_new_crtc_state->stream == NULL); 5023 5024 /* Scaling or underscan settings */ 5025 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state)) 5026 update_stream_scaling_settings( 5027 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 5028 5029 /* 5030 * Color management settings. We also update color properties 5031 * when a modeset is needed, to ensure it gets reprogrammed. 5032 */ 5033 if (dm_new_crtc_state->base.color_mgmt_changed || 5034 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 5035 ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state); 5036 if (ret) 5037 goto fail; 5038 amdgpu_dm_set_ctm(dm_new_crtc_state); 5039 } 5040 } 5041 5042 return ret; 5043 5044 fail: 5045 if (new_stream) 5046 dc_stream_release(new_stream); 5047 return ret; 5048 } 5049 5050 static int dm_update_planes_state(struct dc *dc, 5051 struct drm_atomic_state *state, 5052 bool enable, 5053 bool *lock_and_validation_needed) 5054 { 5055 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 5056 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5057 struct drm_plane *plane; 5058 struct drm_plane_state *old_plane_state, *new_plane_state; 5059 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 5060 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 5061 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 5062 int i ; 5063 /* TODO return page_flip_needed() function */ 5064 bool pflip_needed = !state->allow_modeset; 5065 int ret = 0; 5066 5067 5068 /* Add new planes, in reverse order as DC expectation */ 5069 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 5070 new_plane_crtc = new_plane_state->crtc; 5071 old_plane_crtc = old_plane_state->crtc; 5072 dm_new_plane_state = to_dm_plane_state(new_plane_state); 5073 dm_old_plane_state = to_dm_plane_state(old_plane_state); 5074 5075 /*TODO Implement atomic check for cursor plane */ 5076 if (plane->type == DRM_PLANE_TYPE_CURSOR) 5077 continue; 5078 5079 /* Remove any changed/removed planes */ 5080 if (!enable) { 5081 if (pflip_needed && 5082 plane->type != DRM_PLANE_TYPE_OVERLAY) 5083 continue; 5084 5085 if (!old_plane_crtc) 5086 continue; 5087 5088 old_crtc_state = drm_atomic_get_old_crtc_state( 5089 state, old_plane_crtc); 5090 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5091 5092 if (!dm_old_crtc_state->stream) 5093 continue; 5094 5095 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", 5096 plane->base.id, old_plane_crtc->base.id); 5097 5098 if (!dc_remove_plane_from_context( 5099 dc, 5100 dm_old_crtc_state->stream, 5101 dm_old_plane_state->dc_state, 5102 dm_state->context)) { 5103 5104 ret = EINVAL; 5105 return ret; 5106 } 5107 5108 5109 dc_plane_state_release(dm_old_plane_state->dc_state); 5110 dm_new_plane_state->dc_state = NULL; 5111 5112 *lock_and_validation_needed = true; 5113 5114 } else { /* Add new planes */ 5115 struct dc_plane_state *dc_new_plane_state; 5116 5117 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 5118 continue; 5119 5120 if (!new_plane_crtc) 5121 continue; 5122 5123 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 5124 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5125 5126 if (!dm_new_crtc_state->stream) 5127 continue; 5128 5129 if (pflip_needed && 5130 plane->type != DRM_PLANE_TYPE_OVERLAY) 5131 continue; 5132 5133 WARN_ON(dm_new_plane_state->dc_state); 5134 5135 dc_new_plane_state = dc_create_plane_state(dc); 5136 if (!dc_new_plane_state) 5137 return -ENOMEM; 5138 5139 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n", 5140 plane->base.id, new_plane_crtc->base.id); 5141 5142 ret = fill_plane_attributes( 5143 new_plane_crtc->dev->dev_private, 5144 dc_new_plane_state, 5145 new_plane_state, 5146 new_crtc_state); 5147 if (ret) { 5148 dc_plane_state_release(dc_new_plane_state); 5149 return ret; 5150 } 5151 5152 /* 5153 * Any atomic check errors that occur after this will 5154 * not need a release. The plane state will be attached 5155 * to the stream, and therefore part of the atomic 5156 * state. It'll be released when the atomic state is 5157 * cleaned. 5158 */ 5159 if (!dc_add_plane_to_context( 5160 dc, 5161 dm_new_crtc_state->stream, 5162 dc_new_plane_state, 5163 dm_state->context)) { 5164 5165 dc_plane_state_release(dc_new_plane_state); 5166 return -EINVAL; 5167 } 5168 5169 dm_new_plane_state->dc_state = dc_new_plane_state; 5170 5171 /* Tell DC to do a full surface update every time there 5172 * is a plane change. Inefficient, but works for now. 5173 */ 5174 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; 5175 5176 *lock_and_validation_needed = true; 5177 } 5178 } 5179 5180 5181 return ret; 5182 } 5183 5184 static int amdgpu_dm_atomic_check(struct drm_device *dev, 5185 struct drm_atomic_state *state) 5186 { 5187 struct amdgpu_device *adev = dev->dev_private; 5188 struct dc *dc = adev->dm.dc; 5189 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 5190 struct drm_connector *connector; 5191 struct drm_connector_state *old_con_state, *new_con_state; 5192 struct drm_crtc *crtc; 5193 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5194 int ret, i; 5195 5196 /* 5197 * This bool will be set for true for any modeset/reset 5198 * or plane update which implies non fast surface update. 5199 */ 5200 bool lock_and_validation_needed = false; 5201 5202 ret = drm_atomic_helper_check_modeset(dev, state); 5203 if (ret) 5204 goto fail; 5205 5206 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 5207 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 5208 !new_crtc_state->color_mgmt_changed) 5209 continue; 5210 5211 if (!new_crtc_state->enable) 5212 continue; 5213 5214 ret = drm_atomic_add_affected_connectors(state, crtc); 5215 if (ret) 5216 return ret; 5217 5218 ret = drm_atomic_add_affected_planes(state, crtc); 5219 if (ret) 5220 goto fail; 5221 } 5222 5223 dm_state->context = dc_create_state(); 5224 ASSERT(dm_state->context); 5225 dc_resource_state_copy_construct_current(dc, dm_state->context); 5226 5227 /* Remove exiting planes if they are modified */ 5228 ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed); 5229 if (ret) { 5230 goto fail; 5231 } 5232 5233 /* Disable all crtcs which require disable */ 5234 ret = dm_update_crtcs_state(dc, state, false, &lock_and_validation_needed); 5235 if (ret) { 5236 goto fail; 5237 } 5238 5239 /* Enable all crtcs which require enable */ 5240 ret = dm_update_crtcs_state(dc, state, true, &lock_and_validation_needed); 5241 if (ret) { 5242 goto fail; 5243 } 5244 5245 /* Add new/modified planes */ 5246 ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed); 5247 if (ret) { 5248 goto fail; 5249 } 5250 5251 /* Run this here since we want to validate the streams we created */ 5252 ret = drm_atomic_helper_check_planes(dev, state); 5253 if (ret) 5254 goto fail; 5255 5256 /* Check scaling and underscan changes*/ 5257 /*TODO Removed scaling changes validation due to inability to commit 5258 * new stream into context w\o causing full reset. Need to 5259 * decide how to handle. 5260 */ 5261 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 5262 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 5263 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 5264 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 5265 5266 /* Skip any modesets/resets */ 5267 if (!acrtc || drm_atomic_crtc_needs_modeset( 5268 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 5269 continue; 5270 5271 /* Skip any thing not scale or underscan changes */ 5272 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 5273 continue; 5274 5275 lock_and_validation_needed = true; 5276 } 5277 5278 /* 5279 * For full updates case when 5280 * removing/adding/updating streams on once CRTC while flipping 5281 * on another CRTC, 5282 * acquiring global lock will guarantee that any such full 5283 * update commit 5284 * will wait for completion of any outstanding flip using DRMs 5285 * synchronization events. 5286 */ 5287 5288 if (lock_and_validation_needed) { 5289 5290 ret = do_aquire_global_lock(dev, state); 5291 if (ret) 5292 goto fail; 5293 5294 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) { 5295 ret = -EINVAL; 5296 goto fail; 5297 } 5298 } 5299 5300 /* Must be success */ 5301 WARN_ON(ret); 5302 return ret; 5303 5304 fail: 5305 if (ret == -EDEADLK) 5306 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n"); 5307 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 5308 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); 5309 else 5310 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret); 5311 5312 return ret; 5313 } 5314 5315 static bool is_dp_capable_without_timing_msa(struct dc *dc, 5316 struct amdgpu_dm_connector *amdgpu_dm_connector) 5317 { 5318 uint8_t dpcd_data; 5319 bool capable = false; 5320 5321 if (amdgpu_dm_connector->dc_link && 5322 dm_helpers_dp_read_dpcd( 5323 NULL, 5324 amdgpu_dm_connector->dc_link, 5325 DP_DOWN_STREAM_PORT_COUNT, 5326 &dpcd_data, 5327 sizeof(dpcd_data))) { 5328 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; 5329 } 5330 5331 return capable; 5332 } 5333 void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector, 5334 struct edid *edid) 5335 { 5336 int i; 5337 bool edid_check_required; 5338 struct detailed_timing *timing; 5339 struct detailed_non_pixel *data; 5340 struct detailed_data_monitor_range *range; 5341 struct amdgpu_dm_connector *amdgpu_dm_connector = 5342 to_amdgpu_dm_connector(connector); 5343 struct dm_connector_state *dm_con_state; 5344 5345 struct drm_device *dev = connector->dev; 5346 struct amdgpu_device *adev = dev->dev_private; 5347 5348 if (!connector->state) { 5349 DRM_ERROR("%s - Connector has no state", __func__); 5350 return; 5351 } 5352 5353 dm_con_state = to_dm_connector_state(connector->state); 5354 5355 edid_check_required = false; 5356 if (!amdgpu_dm_connector->dc_sink) { 5357 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n"); 5358 return; 5359 } 5360 if (!adev->dm.freesync_module) 5361 return; 5362 /* 5363 * if edid non zero restrict freesync only for dp and edp 5364 */ 5365 if (edid) { 5366 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT 5367 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) { 5368 edid_check_required = is_dp_capable_without_timing_msa( 5369 adev->dm.dc, 5370 amdgpu_dm_connector); 5371 } 5372 } 5373 dm_con_state->freesync_capable = false; 5374 if (edid_check_required == true && (edid->version > 1 || 5375 (edid->version == 1 && edid->revision > 1))) { 5376 for (i = 0; i < 4; i++) { 5377 5378 timing = &edid->detailed_timings[i]; 5379 data = &timing->data.other_data; 5380 range = &data->data.range; 5381 /* 5382 * Check if monitor has continuous frequency mode 5383 */ 5384 if (data->type != EDID_DETAIL_MONITOR_RANGE) 5385 continue; 5386 /* 5387 * Check for flag range limits only. If flag == 1 then 5388 * no additional timing information provided. 5389 * Default GTF, GTF Secondary curve and CVT are not 5390 * supported 5391 */ 5392 if (range->flags != 1) 5393 continue; 5394 5395 amdgpu_dm_connector->min_vfreq = range->min_vfreq; 5396 amdgpu_dm_connector->max_vfreq = range->max_vfreq; 5397 amdgpu_dm_connector->pixel_clock_mhz = 5398 range->pixel_clock_mhz * 10; 5399 break; 5400 } 5401 5402 if (amdgpu_dm_connector->max_vfreq - 5403 amdgpu_dm_connector->min_vfreq > 10) { 5404 amdgpu_dm_connector->caps.supported = true; 5405 amdgpu_dm_connector->caps.min_refresh_in_micro_hz = 5406 amdgpu_dm_connector->min_vfreq * 1000000; 5407 amdgpu_dm_connector->caps.max_refresh_in_micro_hz = 5408 amdgpu_dm_connector->max_vfreq * 1000000; 5409 dm_con_state->freesync_capable = true; 5410 } 5411 } 5412 5413 /* 5414 * TODO figure out how to notify user-mode or DRM of freesync caps 5415 * once we figure out how to deal with freesync in an upstreamable 5416 * fashion 5417 */ 5418 5419 } 5420 5421 void amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector) 5422 { 5423 /* 5424 * TODO fill in once we figure out how to deal with freesync in 5425 * an upstreamable fashion 5426 */ 5427 } 5428