1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* The caprices of the preprocessor require that this be declared right here */ 27 #define CREATE_TRACE_POINTS 28 29 #include "dm_services_types.h" 30 #include "dc.h" 31 #include "link_enc_cfg.h" 32 #include "dc/inc/core_types.h" 33 #include "dal_asic_id.h" 34 #include "dmub/dmub_srv.h" 35 #include "dc/inc/hw/dmcu.h" 36 #include "dc/inc/hw/abm.h" 37 #include "dc/dc_dmub_srv.h" 38 #include "dc/dc_edid_parser.h" 39 #include "dc/dc_stat.h" 40 #include "amdgpu_dm_trace.h" 41 #include "dpcd_defs.h" 42 #include "link/protocols/link_dpcd.h" 43 #include "link_service_types.h" 44 #include "link/protocols/link_dp_capability.h" 45 #include "link/protocols/link_ddc.h" 46 47 #include "vid.h" 48 #include "amdgpu.h" 49 #include "amdgpu_display.h" 50 #include "amdgpu_ucode.h" 51 #include "atom.h" 52 #include "amdgpu_dm.h" 53 #include "amdgpu_dm_plane.h" 54 #include "amdgpu_dm_crtc.h" 55 #include "amdgpu_dm_hdcp.h" 56 #include <drm/display/drm_hdcp_helper.h> 57 #include "amdgpu_pm.h" 58 #include "amdgpu_atombios.h" 59 60 #include "amd_shared.h" 61 #include "amdgpu_dm_irq.h" 62 #include "dm_helpers.h" 63 #include "amdgpu_dm_mst_types.h" 64 #if defined(CONFIG_DEBUG_FS) 65 #include "amdgpu_dm_debugfs.h" 66 #endif 67 #include "amdgpu_dm_psr.h" 68 69 #include "ivsrcid/ivsrcid_vislands30.h" 70 71 #include <linux/backlight.h> 72 #include <linux/module.h> 73 #include <linux/moduleparam.h> 74 #include <linux/types.h> 75 #include <linux/pm_runtime.h> 76 #include <linux/pci.h> 77 #include <linux/firmware.h> 78 #include <linux/component.h> 79 #include <linux/dmi.h> 80 81 #include <drm/display/drm_dp_mst_helper.h> 82 #include <drm/display/drm_hdmi_helper.h> 83 #include <drm/drm_atomic.h> 84 #include <drm/drm_atomic_uapi.h> 85 #include <drm/drm_atomic_helper.h> 86 #include <drm/drm_blend.h> 87 #include <drm/drm_fourcc.h> 88 #include <drm/drm_edid.h> 89 #include <drm/drm_vblank.h> 90 #include <drm/drm_audio_component.h> 91 #include <drm/drm_gem_atomic_helper.h> 92 #include <drm/drm_plane_helper.h> 93 94 #include <acpi/video.h> 95 96 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 97 98 #include "dcn/dcn_1_0_offset.h" 99 #include "dcn/dcn_1_0_sh_mask.h" 100 #include "soc15_hw_ip.h" 101 #include "soc15_common.h" 102 #include "vega10_ip_offset.h" 103 104 #include "gc/gc_11_0_0_offset.h" 105 #include "gc/gc_11_0_0_sh_mask.h" 106 107 #include "modules/inc/mod_freesync.h" 108 #include "modules/power/power_helpers.h" 109 110 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin" 111 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB); 112 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin" 113 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB); 114 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin" 115 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB); 116 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin" 117 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB); 118 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin" 119 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB); 120 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin" 121 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB); 122 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin" 123 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB); 124 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin" 125 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB); 126 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin" 127 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB); 128 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin" 129 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB); 130 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin" 131 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB); 132 133 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin" 134 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB); 135 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin" 136 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB); 137 138 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" 139 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); 140 141 #define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin" 142 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU); 143 144 /* Number of bytes in PSP header for firmware. */ 145 #define PSP_HEADER_BYTES 0x100 146 147 /* Number of bytes in PSP footer for firmware. */ 148 #define PSP_FOOTER_BYTES 0x100 149 150 /** 151 * DOC: overview 152 * 153 * The AMDgpu display manager, **amdgpu_dm** (or even simpler, 154 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM 155 * requests into DC requests, and DC responses into DRM responses. 156 * 157 * The root control structure is &struct amdgpu_display_manager. 158 */ 159 160 /* basic init/fini API */ 161 static int amdgpu_dm_init(struct amdgpu_device *adev); 162 static void amdgpu_dm_fini(struct amdgpu_device *adev); 163 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector); 164 165 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link) 166 { 167 switch (link->dpcd_caps.dongle_type) { 168 case DISPLAY_DONGLE_NONE: 169 return DRM_MODE_SUBCONNECTOR_Native; 170 case DISPLAY_DONGLE_DP_VGA_CONVERTER: 171 return DRM_MODE_SUBCONNECTOR_VGA; 172 case DISPLAY_DONGLE_DP_DVI_CONVERTER: 173 case DISPLAY_DONGLE_DP_DVI_DONGLE: 174 return DRM_MODE_SUBCONNECTOR_DVID; 175 case DISPLAY_DONGLE_DP_HDMI_CONVERTER: 176 case DISPLAY_DONGLE_DP_HDMI_DONGLE: 177 return DRM_MODE_SUBCONNECTOR_HDMIA; 178 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE: 179 default: 180 return DRM_MODE_SUBCONNECTOR_Unknown; 181 } 182 } 183 184 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector) 185 { 186 struct dc_link *link = aconnector->dc_link; 187 struct drm_connector *connector = &aconnector->base; 188 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown; 189 190 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 191 return; 192 193 if (aconnector->dc_sink) 194 subconnector = get_subconnector_type(link); 195 196 drm_object_property_set_value(&connector->base, 197 connector->dev->mode_config.dp_subconnector_property, 198 subconnector); 199 } 200 201 /* 202 * initializes drm_device display related structures, based on the information 203 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 204 * drm_encoder, drm_mode_config 205 * 206 * Returns 0 on success 207 */ 208 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 209 /* removes and deallocates the drm structures, created by the above function */ 210 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 211 212 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 213 struct amdgpu_dm_connector *amdgpu_dm_connector, 214 u32 link_index, 215 struct amdgpu_encoder *amdgpu_encoder); 216 static int amdgpu_dm_encoder_init(struct drm_device *dev, 217 struct amdgpu_encoder *aencoder, 218 uint32_t link_index); 219 220 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); 221 222 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); 223 224 static int amdgpu_dm_atomic_check(struct drm_device *dev, 225 struct drm_atomic_state *state); 226 227 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector); 228 static void handle_hpd_rx_irq(void *param); 229 230 static bool 231 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 232 struct drm_crtc_state *new_crtc_state); 233 /* 234 * dm_vblank_get_counter 235 * 236 * @brief 237 * Get counter for number of vertical blanks 238 * 239 * @param 240 * struct amdgpu_device *adev - [in] desired amdgpu device 241 * int disp_idx - [in] which CRTC to get the counter from 242 * 243 * @return 244 * Counter for vertical blanks 245 */ 246 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 247 { 248 struct amdgpu_crtc *acrtc = NULL; 249 250 if (crtc >= adev->mode_info.num_crtc) 251 return 0; 252 253 acrtc = adev->mode_info.crtcs[crtc]; 254 255 if (!acrtc->dm_irq_params.stream) { 256 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 257 crtc); 258 return 0; 259 } 260 261 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream); 262 } 263 264 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 265 u32 *vbl, u32 *position) 266 { 267 u32 v_blank_start, v_blank_end, h_position, v_position; 268 struct amdgpu_crtc *acrtc = NULL; 269 270 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 271 return -EINVAL; 272 273 acrtc = adev->mode_info.crtcs[crtc]; 274 275 if (!acrtc->dm_irq_params.stream) { 276 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 277 crtc); 278 return 0; 279 } 280 281 /* 282 * TODO rework base driver to use values directly. 283 * for now parse it back into reg-format 284 */ 285 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream, 286 &v_blank_start, 287 &v_blank_end, 288 &h_position, 289 &v_position); 290 291 *position = v_position | (h_position << 16); 292 *vbl = v_blank_start | (v_blank_end << 16); 293 294 return 0; 295 } 296 297 static bool dm_is_idle(void *handle) 298 { 299 /* XXX todo */ 300 return true; 301 } 302 303 static int dm_wait_for_idle(void *handle) 304 { 305 /* XXX todo */ 306 return 0; 307 } 308 309 static bool dm_check_soft_reset(void *handle) 310 { 311 return false; 312 } 313 314 static int dm_soft_reset(void *handle) 315 { 316 /* XXX todo */ 317 return 0; 318 } 319 320 static struct amdgpu_crtc * 321 get_crtc_by_otg_inst(struct amdgpu_device *adev, 322 int otg_inst) 323 { 324 struct drm_device *dev = adev_to_drm(adev); 325 struct drm_crtc *crtc; 326 struct amdgpu_crtc *amdgpu_crtc; 327 328 if (WARN_ON(otg_inst == -1)) 329 return adev->mode_info.crtcs[0]; 330 331 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 332 amdgpu_crtc = to_amdgpu_crtc(crtc); 333 334 if (amdgpu_crtc->otg_inst == otg_inst) 335 return amdgpu_crtc; 336 } 337 338 return NULL; 339 } 340 341 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state, 342 struct dm_crtc_state *new_state) 343 { 344 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) 345 return true; 346 else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state)) 347 return true; 348 else 349 return false; 350 } 351 352 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update, 353 int planes_count) 354 { 355 int i, j; 356 357 for (i = 0, j = planes_count - 1; i < j; i++, j--) 358 swap(array_of_surface_update[i], array_of_surface_update[j]); 359 } 360 361 /** 362 * update_planes_and_stream_adapter() - Send planes to be updated in DC 363 * 364 * DC has a generic way to update planes and stream via 365 * dc_update_planes_and_stream function; however, DM might need some 366 * adjustments and preparation before calling it. This function is a wrapper 367 * for the dc_update_planes_and_stream that does any required configuration 368 * before passing control to DC. 369 * 370 * @dc: Display Core control structure 371 * @update_type: specify whether it is FULL/MEDIUM/FAST update 372 * @planes_count: planes count to update 373 * @stream: stream state 374 * @stream_update: stream update 375 * @array_of_surface_update: dc surface update pointer 376 * 377 */ 378 static inline bool update_planes_and_stream_adapter(struct dc *dc, 379 int update_type, 380 int planes_count, 381 struct dc_stream_state *stream, 382 struct dc_stream_update *stream_update, 383 struct dc_surface_update *array_of_surface_update) 384 { 385 reverse_planes_order(array_of_surface_update, planes_count); 386 387 /* 388 * Previous frame finished and HW is ready for optimization. 389 */ 390 if (update_type == UPDATE_TYPE_FAST) 391 dc_post_update_surfaces_to_stream(dc); 392 393 return dc_update_planes_and_stream(dc, 394 array_of_surface_update, 395 planes_count, 396 stream, 397 stream_update); 398 } 399 400 /** 401 * dm_pflip_high_irq() - Handle pageflip interrupt 402 * @interrupt_params: ignored 403 * 404 * Handles the pageflip interrupt by notifying all interested parties 405 * that the pageflip has been completed. 406 */ 407 static void dm_pflip_high_irq(void *interrupt_params) 408 { 409 struct amdgpu_crtc *amdgpu_crtc; 410 struct common_irq_params *irq_params = interrupt_params; 411 struct amdgpu_device *adev = irq_params->adev; 412 unsigned long flags; 413 struct drm_pending_vblank_event *e; 414 u32 vpos, hpos, v_blank_start, v_blank_end; 415 bool vrr_active; 416 417 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); 418 419 /* IRQ could occur when in initial stage */ 420 /* TODO work and BO cleanup */ 421 if (amdgpu_crtc == NULL) { 422 DC_LOG_PFLIP("CRTC is null, returning.\n"); 423 return; 424 } 425 426 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 427 428 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { 429 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n", 430 amdgpu_crtc->pflip_status, 431 AMDGPU_FLIP_SUBMITTED, 432 amdgpu_crtc->crtc_id, 433 amdgpu_crtc); 434 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 435 return; 436 } 437 438 /* page flip completed. */ 439 e = amdgpu_crtc->event; 440 amdgpu_crtc->event = NULL; 441 442 WARN_ON(!e); 443 444 vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc); 445 446 /* Fixed refresh rate, or VRR scanout position outside front-porch? */ 447 if (!vrr_active || 448 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start, 449 &v_blank_end, &hpos, &vpos) || 450 (vpos < v_blank_start)) { 451 /* Update to correct count and vblank timestamp if racing with 452 * vblank irq. This also updates to the correct vblank timestamp 453 * even in VRR mode, as scanout is past the front-porch atm. 454 */ 455 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); 456 457 /* Wake up userspace by sending the pageflip event with proper 458 * count and timestamp of vblank of flip completion. 459 */ 460 if (e) { 461 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e); 462 463 /* Event sent, so done with vblank for this flip */ 464 drm_crtc_vblank_put(&amdgpu_crtc->base); 465 } 466 } else if (e) { 467 /* VRR active and inside front-porch: vblank count and 468 * timestamp for pageflip event will only be up to date after 469 * drm_crtc_handle_vblank() has been executed from late vblank 470 * irq handler after start of back-porch (vline 0). We queue the 471 * pageflip event for send-out by drm_crtc_handle_vblank() with 472 * updated timestamp and count, once it runs after us. 473 * 474 * We need to open-code this instead of using the helper 475 * drm_crtc_arm_vblank_event(), as that helper would 476 * call drm_crtc_accurate_vblank_count(), which we must 477 * not call in VRR mode while we are in front-porch! 478 */ 479 480 /* sequence will be replaced by real count during send-out. */ 481 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base); 482 e->pipe = amdgpu_crtc->crtc_id; 483 484 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list); 485 e = NULL; 486 } 487 488 /* Keep track of vblank of this flip for flip throttling. We use the 489 * cooked hw counter, as that one incremented at start of this vblank 490 * of pageflip completion, so last_flip_vblank is the forbidden count 491 * for queueing new pageflips if vsync + VRR is enabled. 492 */ 493 amdgpu_crtc->dm_irq_params.last_flip_vblank = 494 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base); 495 496 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 497 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 498 499 DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n", 500 amdgpu_crtc->crtc_id, amdgpu_crtc, 501 vrr_active, (int) !e); 502 } 503 504 static void dm_vupdate_high_irq(void *interrupt_params) 505 { 506 struct common_irq_params *irq_params = interrupt_params; 507 struct amdgpu_device *adev = irq_params->adev; 508 struct amdgpu_crtc *acrtc; 509 struct drm_device *drm_dev; 510 struct drm_vblank_crtc *vblank; 511 ktime_t frame_duration_ns, previous_timestamp; 512 unsigned long flags; 513 int vrr_active; 514 515 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); 516 517 if (acrtc) { 518 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); 519 drm_dev = acrtc->base.dev; 520 vblank = &drm_dev->vblank[acrtc->base.index]; 521 previous_timestamp = atomic64_read(&irq_params->previous_timestamp); 522 frame_duration_ns = vblank->time - previous_timestamp; 523 524 if (frame_duration_ns > 0) { 525 trace_amdgpu_refresh_rate_track(acrtc->base.index, 526 frame_duration_ns, 527 ktime_divns(NSEC_PER_SEC, frame_duration_ns)); 528 atomic64_set(&irq_params->previous_timestamp, vblank->time); 529 } 530 531 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n", 532 acrtc->crtc_id, 533 vrr_active); 534 535 /* Core vblank handling is done here after end of front-porch in 536 * vrr mode, as vblank timestamping will give valid results 537 * while now done after front-porch. This will also deliver 538 * page-flip completion events that have been queued to us 539 * if a pageflip happened inside front-porch. 540 */ 541 if (vrr_active) { 542 amdgpu_dm_crtc_handle_vblank(acrtc); 543 544 /* BTR processing for pre-DCE12 ASICs */ 545 if (acrtc->dm_irq_params.stream && 546 adev->family < AMDGPU_FAMILY_AI) { 547 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 548 mod_freesync_handle_v_update( 549 adev->dm.freesync_module, 550 acrtc->dm_irq_params.stream, 551 &acrtc->dm_irq_params.vrr_params); 552 553 dc_stream_adjust_vmin_vmax( 554 adev->dm.dc, 555 acrtc->dm_irq_params.stream, 556 &acrtc->dm_irq_params.vrr_params.adjust); 557 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 558 } 559 } 560 } 561 } 562 563 /** 564 * dm_crtc_high_irq() - Handles CRTC interrupt 565 * @interrupt_params: used for determining the CRTC instance 566 * 567 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK 568 * event handler. 569 */ 570 static void dm_crtc_high_irq(void *interrupt_params) 571 { 572 struct common_irq_params *irq_params = interrupt_params; 573 struct amdgpu_device *adev = irq_params->adev; 574 struct amdgpu_crtc *acrtc; 575 unsigned long flags; 576 int vrr_active; 577 578 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); 579 if (!acrtc) 580 return; 581 582 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); 583 584 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id, 585 vrr_active, acrtc->dm_irq_params.active_planes); 586 587 /** 588 * Core vblank handling at start of front-porch is only possible 589 * in non-vrr mode, as only there vblank timestamping will give 590 * valid results while done in front-porch. Otherwise defer it 591 * to dm_vupdate_high_irq after end of front-porch. 592 */ 593 if (!vrr_active) 594 amdgpu_dm_crtc_handle_vblank(acrtc); 595 596 /** 597 * Following stuff must happen at start of vblank, for crc 598 * computation and below-the-range btr support in vrr mode. 599 */ 600 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); 601 602 /* BTR updates need to happen before VUPDATE on Vega and above. */ 603 if (adev->family < AMDGPU_FAMILY_AI) 604 return; 605 606 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 607 608 if (acrtc->dm_irq_params.stream && 609 acrtc->dm_irq_params.vrr_params.supported && 610 acrtc->dm_irq_params.freesync_config.state == 611 VRR_STATE_ACTIVE_VARIABLE) { 612 mod_freesync_handle_v_update(adev->dm.freesync_module, 613 acrtc->dm_irq_params.stream, 614 &acrtc->dm_irq_params.vrr_params); 615 616 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream, 617 &acrtc->dm_irq_params.vrr_params.adjust); 618 } 619 620 /* 621 * If there aren't any active_planes then DCH HUBP may be clock-gated. 622 * In that case, pageflip completion interrupts won't fire and pageflip 623 * completion events won't get delivered. Prevent this by sending 624 * pending pageflip events from here if a flip is still pending. 625 * 626 * If any planes are enabled, use dm_pflip_high_irq() instead, to 627 * avoid race conditions between flip programming and completion, 628 * which could cause too early flip completion events. 629 */ 630 if (adev->family >= AMDGPU_FAMILY_RV && 631 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED && 632 acrtc->dm_irq_params.active_planes == 0) { 633 if (acrtc->event) { 634 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event); 635 acrtc->event = NULL; 636 drm_crtc_vblank_put(&acrtc->base); 637 } 638 acrtc->pflip_status = AMDGPU_FLIP_NONE; 639 } 640 641 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 642 } 643 644 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 645 /** 646 * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for 647 * DCN generation ASICs 648 * @interrupt_params: interrupt parameters 649 * 650 * Used to set crc window/read out crc value at vertical line 0 position 651 */ 652 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params) 653 { 654 struct common_irq_params *irq_params = interrupt_params; 655 struct amdgpu_device *adev = irq_params->adev; 656 struct amdgpu_crtc *acrtc; 657 658 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0); 659 660 if (!acrtc) 661 return; 662 663 amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base); 664 } 665 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */ 666 667 /** 668 * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command. 669 * @adev: amdgpu_device pointer 670 * @notify: dmub notification structure 671 * 672 * Dmub AUX or SET_CONFIG command completion processing callback 673 * Copies dmub notification to DM which is to be read by AUX command. 674 * issuing thread and also signals the event to wake up the thread. 675 */ 676 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev, 677 struct dmub_notification *notify) 678 { 679 if (adev->dm.dmub_notify) 680 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification)); 681 if (notify->type == DMUB_NOTIFICATION_AUX_REPLY) 682 complete(&adev->dm.dmub_aux_transfer_done); 683 } 684 685 /** 686 * dmub_hpd_callback - DMUB HPD interrupt processing callback. 687 * @adev: amdgpu_device pointer 688 * @notify: dmub notification structure 689 * 690 * Dmub Hpd interrupt processing callback. Gets displayindex through the 691 * ink index and calls helper to do the processing. 692 */ 693 static void dmub_hpd_callback(struct amdgpu_device *adev, 694 struct dmub_notification *notify) 695 { 696 struct amdgpu_dm_connector *aconnector; 697 struct amdgpu_dm_connector *hpd_aconnector = NULL; 698 struct drm_connector *connector; 699 struct drm_connector_list_iter iter; 700 struct dc_link *link; 701 u8 link_index = 0; 702 struct drm_device *dev; 703 704 if (adev == NULL) 705 return; 706 707 if (notify == NULL) { 708 DRM_ERROR("DMUB HPD callback notification was NULL"); 709 return; 710 } 711 712 if (notify->link_index > adev->dm.dc->link_count) { 713 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index); 714 return; 715 } 716 717 link_index = notify->link_index; 718 link = adev->dm.dc->links[link_index]; 719 dev = adev->dm.ddev; 720 721 drm_connector_list_iter_begin(dev, &iter); 722 drm_for_each_connector_iter(connector, &iter) { 723 aconnector = to_amdgpu_dm_connector(connector); 724 if (link && aconnector->dc_link == link) { 725 if (notify->type == DMUB_NOTIFICATION_HPD) 726 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index); 727 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) 728 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index); 729 else 730 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n", 731 notify->type, link_index); 732 733 hpd_aconnector = aconnector; 734 break; 735 } 736 } 737 drm_connector_list_iter_end(&iter); 738 739 if (hpd_aconnector) { 740 if (notify->type == DMUB_NOTIFICATION_HPD) 741 handle_hpd_irq_helper(hpd_aconnector); 742 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) 743 handle_hpd_rx_irq(hpd_aconnector); 744 } 745 } 746 747 /** 748 * register_dmub_notify_callback - Sets callback for DMUB notify 749 * @adev: amdgpu_device pointer 750 * @type: Type of dmub notification 751 * @callback: Dmub interrupt callback function 752 * @dmub_int_thread_offload: offload indicator 753 * 754 * API to register a dmub callback handler for a dmub notification 755 * Also sets indicator whether callback processing to be offloaded. 756 * to dmub interrupt handling thread 757 * Return: true if successfully registered, false if there is existing registration 758 */ 759 static bool register_dmub_notify_callback(struct amdgpu_device *adev, 760 enum dmub_notification_type type, 761 dmub_notify_interrupt_callback_t callback, 762 bool dmub_int_thread_offload) 763 { 764 if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) { 765 adev->dm.dmub_callback[type] = callback; 766 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload; 767 } else 768 return false; 769 770 return true; 771 } 772 773 static void dm_handle_hpd_work(struct work_struct *work) 774 { 775 struct dmub_hpd_work *dmub_hpd_wrk; 776 777 dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work); 778 779 if (!dmub_hpd_wrk->dmub_notify) { 780 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL"); 781 return; 782 } 783 784 if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) { 785 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev, 786 dmub_hpd_wrk->dmub_notify); 787 } 788 789 kfree(dmub_hpd_wrk->dmub_notify); 790 kfree(dmub_hpd_wrk); 791 792 } 793 794 #define DMUB_TRACE_MAX_READ 64 795 /** 796 * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt 797 * @interrupt_params: used for determining the Outbox instance 798 * 799 * Handles the Outbox Interrupt 800 * event handler. 801 */ 802 static void dm_dmub_outbox1_low_irq(void *interrupt_params) 803 { 804 struct dmub_notification notify; 805 struct common_irq_params *irq_params = interrupt_params; 806 struct amdgpu_device *adev = irq_params->adev; 807 struct amdgpu_display_manager *dm = &adev->dm; 808 struct dmcub_trace_buf_entry entry = { 0 }; 809 u32 count = 0; 810 struct dmub_hpd_work *dmub_hpd_wrk; 811 struct dc_link *plink = NULL; 812 813 if (dc_enable_dmub_notifications(adev->dm.dc) && 814 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) { 815 816 do { 817 dc_stat_get_dmub_notification(adev->dm.dc, ¬ify); 818 if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) { 819 DRM_ERROR("DM: notify type %d invalid!", notify.type); 820 continue; 821 } 822 if (!dm->dmub_callback[notify.type]) { 823 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type); 824 continue; 825 } 826 if (dm->dmub_thread_offload[notify.type] == true) { 827 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC); 828 if (!dmub_hpd_wrk) { 829 DRM_ERROR("Failed to allocate dmub_hpd_wrk"); 830 return; 831 } 832 dmub_hpd_wrk->dmub_notify = kmemdup(¬ify, sizeof(struct dmub_notification), 833 GFP_ATOMIC); 834 if (!dmub_hpd_wrk->dmub_notify) { 835 kfree(dmub_hpd_wrk); 836 DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify"); 837 return; 838 } 839 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work); 840 dmub_hpd_wrk->adev = adev; 841 if (notify.type == DMUB_NOTIFICATION_HPD) { 842 plink = adev->dm.dc->links[notify.link_index]; 843 if (plink) { 844 plink->hpd_status = 845 notify.hpd_status == DP_HPD_PLUG; 846 } 847 } 848 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work); 849 } else { 850 dm->dmub_callback[notify.type](adev, ¬ify); 851 } 852 } while (notify.pending_notification); 853 } 854 855 856 do { 857 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) { 858 trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count, 859 entry.param0, entry.param1); 860 861 DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n", 862 entry.trace_code, entry.tick_count, entry.param0, entry.param1); 863 } else 864 break; 865 866 count++; 867 868 } while (count <= DMUB_TRACE_MAX_READ); 869 870 if (count > DMUB_TRACE_MAX_READ) 871 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ"); 872 } 873 874 static int dm_set_clockgating_state(void *handle, 875 enum amd_clockgating_state state) 876 { 877 return 0; 878 } 879 880 static int dm_set_powergating_state(void *handle, 881 enum amd_powergating_state state) 882 { 883 return 0; 884 } 885 886 /* Prototypes of private functions */ 887 static int dm_early_init(void *handle); 888 889 /* Allocate memory for FBC compressed data */ 890 static void amdgpu_dm_fbc_init(struct drm_connector *connector) 891 { 892 struct drm_device *dev = connector->dev; 893 struct amdgpu_device *adev = drm_to_adev(dev); 894 struct dm_compressor_info *compressor = &adev->dm.compressor; 895 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); 896 struct drm_display_mode *mode; 897 unsigned long max_size = 0; 898 899 if (adev->dm.dc->fbc_compressor == NULL) 900 return; 901 902 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) 903 return; 904 905 if (compressor->bo_ptr) 906 return; 907 908 909 list_for_each_entry(mode, &connector->modes, head) { 910 if (max_size < mode->htotal * mode->vtotal) 911 max_size = mode->htotal * mode->vtotal; 912 } 913 914 if (max_size) { 915 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, 916 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, 917 &compressor->gpu_addr, &compressor->cpu_addr); 918 919 if (r) 920 DRM_ERROR("DM: Failed to initialize FBC\n"); 921 else { 922 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; 923 DRM_INFO("DM: FBC alloc %lu\n", max_size*4); 924 } 925 926 } 927 928 } 929 930 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, 931 int pipe, bool *enabled, 932 unsigned char *buf, int max_bytes) 933 { 934 struct drm_device *dev = dev_get_drvdata(kdev); 935 struct amdgpu_device *adev = drm_to_adev(dev); 936 struct drm_connector *connector; 937 struct drm_connector_list_iter conn_iter; 938 struct amdgpu_dm_connector *aconnector; 939 int ret = 0; 940 941 *enabled = false; 942 943 mutex_lock(&adev->dm.audio_lock); 944 945 drm_connector_list_iter_begin(dev, &conn_iter); 946 drm_for_each_connector_iter(connector, &conn_iter) { 947 aconnector = to_amdgpu_dm_connector(connector); 948 if (aconnector->audio_inst != port) 949 continue; 950 951 *enabled = true; 952 ret = drm_eld_size(connector->eld); 953 memcpy(buf, connector->eld, min(max_bytes, ret)); 954 955 break; 956 } 957 drm_connector_list_iter_end(&conn_iter); 958 959 mutex_unlock(&adev->dm.audio_lock); 960 961 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled); 962 963 return ret; 964 } 965 966 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = { 967 .get_eld = amdgpu_dm_audio_component_get_eld, 968 }; 969 970 static int amdgpu_dm_audio_component_bind(struct device *kdev, 971 struct device *hda_kdev, void *data) 972 { 973 struct drm_device *dev = dev_get_drvdata(kdev); 974 struct amdgpu_device *adev = drm_to_adev(dev); 975 struct drm_audio_component *acomp = data; 976 977 acomp->ops = &amdgpu_dm_audio_component_ops; 978 acomp->dev = kdev; 979 adev->dm.audio_component = acomp; 980 981 return 0; 982 } 983 984 static void amdgpu_dm_audio_component_unbind(struct device *kdev, 985 struct device *hda_kdev, void *data) 986 { 987 struct drm_device *dev = dev_get_drvdata(kdev); 988 struct amdgpu_device *adev = drm_to_adev(dev); 989 struct drm_audio_component *acomp = data; 990 991 acomp->ops = NULL; 992 acomp->dev = NULL; 993 adev->dm.audio_component = NULL; 994 } 995 996 static const struct component_ops amdgpu_dm_audio_component_bind_ops = { 997 .bind = amdgpu_dm_audio_component_bind, 998 .unbind = amdgpu_dm_audio_component_unbind, 999 }; 1000 1001 static int amdgpu_dm_audio_init(struct amdgpu_device *adev) 1002 { 1003 int i, ret; 1004 1005 if (!amdgpu_audio) 1006 return 0; 1007 1008 adev->mode_info.audio.enabled = true; 1009 1010 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count; 1011 1012 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1013 adev->mode_info.audio.pin[i].channels = -1; 1014 adev->mode_info.audio.pin[i].rate = -1; 1015 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1016 adev->mode_info.audio.pin[i].status_bits = 0; 1017 adev->mode_info.audio.pin[i].category_code = 0; 1018 adev->mode_info.audio.pin[i].connected = false; 1019 adev->mode_info.audio.pin[i].id = 1020 adev->dm.dc->res_pool->audios[i]->inst; 1021 adev->mode_info.audio.pin[i].offset = 0; 1022 } 1023 1024 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops); 1025 if (ret < 0) 1026 return ret; 1027 1028 adev->dm.audio_registered = true; 1029 1030 return 0; 1031 } 1032 1033 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev) 1034 { 1035 if (!amdgpu_audio) 1036 return; 1037 1038 if (!adev->mode_info.audio.enabled) 1039 return; 1040 1041 if (adev->dm.audio_registered) { 1042 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops); 1043 adev->dm.audio_registered = false; 1044 } 1045 1046 /* TODO: Disable audio? */ 1047 1048 adev->mode_info.audio.enabled = false; 1049 } 1050 1051 static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) 1052 { 1053 struct drm_audio_component *acomp = adev->dm.audio_component; 1054 1055 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { 1056 DRM_DEBUG_KMS("Notify ELD: %d\n", pin); 1057 1058 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, 1059 pin, -1); 1060 } 1061 } 1062 1063 static int dm_dmub_hw_init(struct amdgpu_device *adev) 1064 { 1065 const struct dmcub_firmware_header_v1_0 *hdr; 1066 struct dmub_srv *dmub_srv = adev->dm.dmub_srv; 1067 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 1068 const struct firmware *dmub_fw = adev->dm.dmub_fw; 1069 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; 1070 struct abm *abm = adev->dm.dc->res_pool->abm; 1071 struct dmub_srv_hw_params hw_params; 1072 enum dmub_status status; 1073 const unsigned char *fw_inst_const, *fw_bss_data; 1074 u32 i, fw_inst_const_size, fw_bss_data_size; 1075 bool has_hw_support; 1076 1077 if (!dmub_srv) 1078 /* DMUB isn't supported on the ASIC. */ 1079 return 0; 1080 1081 if (!fb_info) { 1082 DRM_ERROR("No framebuffer info for DMUB service.\n"); 1083 return -EINVAL; 1084 } 1085 1086 if (!dmub_fw) { 1087 /* Firmware required for DMUB support. */ 1088 DRM_ERROR("No firmware provided for DMUB.\n"); 1089 return -EINVAL; 1090 } 1091 1092 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support); 1093 if (status != DMUB_STATUS_OK) { 1094 DRM_ERROR("Error checking HW support for DMUB: %d\n", status); 1095 return -EINVAL; 1096 } 1097 1098 if (!has_hw_support) { 1099 DRM_INFO("DMUB unsupported on ASIC\n"); 1100 return 0; 1101 } 1102 1103 /* Reset DMCUB if it was previously running - before we overwrite its memory. */ 1104 status = dmub_srv_hw_reset(dmub_srv); 1105 if (status != DMUB_STATUS_OK) 1106 DRM_WARN("Error resetting DMUB HW: %d\n", status); 1107 1108 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data; 1109 1110 fw_inst_const = dmub_fw->data + 1111 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 1112 PSP_HEADER_BYTES; 1113 1114 fw_bss_data = dmub_fw->data + 1115 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 1116 le32_to_cpu(hdr->inst_const_bytes); 1117 1118 /* Copy firmware and bios info into FB memory. */ 1119 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - 1120 PSP_HEADER_BYTES - PSP_FOOTER_BYTES; 1121 1122 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes); 1123 1124 /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP, 1125 * amdgpu_ucode_init_single_fw will load dmub firmware 1126 * fw_inst_const part to cw0; otherwise, the firmware back door load 1127 * will be done by dm_dmub_hw_init 1128 */ 1129 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1130 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const, 1131 fw_inst_const_size); 1132 } 1133 1134 if (fw_bss_data_size) 1135 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr, 1136 fw_bss_data, fw_bss_data_size); 1137 1138 /* Copy firmware bios info into FB memory. */ 1139 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios, 1140 adev->bios_size); 1141 1142 /* Reset regions that need to be reset. */ 1143 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0, 1144 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size); 1145 1146 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0, 1147 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size); 1148 1149 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0, 1150 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size); 1151 1152 /* Initialize hardware. */ 1153 memset(&hw_params, 0, sizeof(hw_params)); 1154 hw_params.fb_base = adev->gmc.fb_start; 1155 hw_params.fb_offset = adev->vm_manager.vram_base_offset; 1156 1157 /* backdoor load firmware and trigger dmub running */ 1158 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 1159 hw_params.load_inst_const = true; 1160 1161 if (dmcu) 1162 hw_params.psp_version = dmcu->psp_version; 1163 1164 for (i = 0; i < fb_info->num_fb; ++i) 1165 hw_params.fb[i] = &fb_info->fb[i]; 1166 1167 switch (adev->ip_versions[DCE_HWIP][0]) { 1168 case IP_VERSION(3, 1, 3): 1169 case IP_VERSION(3, 1, 4): 1170 hw_params.dpia_supported = true; 1171 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia; 1172 break; 1173 default: 1174 break; 1175 } 1176 1177 status = dmub_srv_hw_init(dmub_srv, &hw_params); 1178 if (status != DMUB_STATUS_OK) { 1179 DRM_ERROR("Error initializing DMUB HW: %d\n", status); 1180 return -EINVAL; 1181 } 1182 1183 /* Wait for firmware load to finish. */ 1184 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); 1185 if (status != DMUB_STATUS_OK) 1186 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); 1187 1188 /* Init DMCU and ABM if available. */ 1189 if (dmcu && abm) { 1190 dmcu->funcs->dmcu_init(dmcu); 1191 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 1192 } 1193 1194 if (!adev->dm.dc->ctx->dmub_srv) 1195 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv); 1196 if (!adev->dm.dc->ctx->dmub_srv) { 1197 DRM_ERROR("Couldn't allocate DC DMUB server!\n"); 1198 return -ENOMEM; 1199 } 1200 1201 DRM_INFO("DMUB hardware initialized: version=0x%08X\n", 1202 adev->dm.dmcub_fw_version); 1203 1204 return 0; 1205 } 1206 1207 static void dm_dmub_hw_resume(struct amdgpu_device *adev) 1208 { 1209 struct dmub_srv *dmub_srv = adev->dm.dmub_srv; 1210 enum dmub_status status; 1211 bool init; 1212 1213 if (!dmub_srv) { 1214 /* DMUB isn't supported on the ASIC. */ 1215 return; 1216 } 1217 1218 status = dmub_srv_is_hw_init(dmub_srv, &init); 1219 if (status != DMUB_STATUS_OK) 1220 DRM_WARN("DMUB hardware init check failed: %d\n", status); 1221 1222 if (status == DMUB_STATUS_OK && init) { 1223 /* Wait for firmware load to finish. */ 1224 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); 1225 if (status != DMUB_STATUS_OK) 1226 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); 1227 } else { 1228 /* Perform the full hardware initialization. */ 1229 dm_dmub_hw_init(adev); 1230 } 1231 } 1232 1233 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config) 1234 { 1235 u64 pt_base; 1236 u32 logical_addr_low; 1237 u32 logical_addr_high; 1238 u32 agp_base, agp_bot, agp_top; 1239 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base; 1240 1241 memset(pa_config, 0, sizeof(*pa_config)); 1242 1243 agp_base = 0; 1244 agp_bot = adev->gmc.agp_start >> 24; 1245 agp_top = adev->gmc.agp_end >> 24; 1246 1247 /* AGP aperture is disabled */ 1248 if (agp_bot == agp_top) { 1249 logical_addr_low = adev->gmc.fb_start >> 18; 1250 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 1251 AMD_APU_IS_RENOIR | 1252 AMD_APU_IS_GREEN_SARDINE)) 1253 /* 1254 * Raven2 has a HW issue that it is unable to use the vram which 1255 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 1256 * workaround that increase system aperture high address (add 1) 1257 * to get rid of the VM fault and hardware hang. 1258 */ 1259 logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1; 1260 else 1261 logical_addr_high = adev->gmc.fb_end >> 18; 1262 } else { 1263 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18; 1264 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 1265 AMD_APU_IS_RENOIR | 1266 AMD_APU_IS_GREEN_SARDINE)) 1267 /* 1268 * Raven2 has a HW issue that it is unable to use the vram which 1269 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 1270 * workaround that increase system aperture high address (add 1) 1271 * to get rid of the VM fault and hardware hang. 1272 */ 1273 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18); 1274 else 1275 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18; 1276 } 1277 1278 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 1279 1280 page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >> 1281 AMDGPU_GPU_PAGE_SHIFT); 1282 page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >> 1283 AMDGPU_GPU_PAGE_SHIFT); 1284 page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >> 1285 AMDGPU_GPU_PAGE_SHIFT); 1286 page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >> 1287 AMDGPU_GPU_PAGE_SHIFT); 1288 page_table_base.high_part = upper_32_bits(pt_base); 1289 page_table_base.low_part = lower_32_bits(pt_base); 1290 1291 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; 1292 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18; 1293 1294 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24; 1295 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24; 1296 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; 1297 1298 pa_config->system_aperture.fb_base = adev->gmc.fb_start; 1299 pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset; 1300 pa_config->system_aperture.fb_top = adev->gmc.fb_end; 1301 1302 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12; 1303 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12; 1304 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part; 1305 1306 pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support; 1307 1308 } 1309 1310 static void force_connector_state( 1311 struct amdgpu_dm_connector *aconnector, 1312 enum drm_connector_force force_state) 1313 { 1314 struct drm_connector *connector = &aconnector->base; 1315 1316 mutex_lock(&connector->dev->mode_config.mutex); 1317 aconnector->base.force = force_state; 1318 mutex_unlock(&connector->dev->mode_config.mutex); 1319 1320 mutex_lock(&aconnector->hpd_lock); 1321 drm_kms_helper_connector_hotplug_event(connector); 1322 mutex_unlock(&aconnector->hpd_lock); 1323 } 1324 1325 static void dm_handle_hpd_rx_offload_work(struct work_struct *work) 1326 { 1327 struct hpd_rx_irq_offload_work *offload_work; 1328 struct amdgpu_dm_connector *aconnector; 1329 struct dc_link *dc_link; 1330 struct amdgpu_device *adev; 1331 enum dc_connection_type new_connection_type = dc_connection_none; 1332 unsigned long flags; 1333 union test_response test_response; 1334 1335 memset(&test_response, 0, sizeof(test_response)); 1336 1337 offload_work = container_of(work, struct hpd_rx_irq_offload_work, work); 1338 aconnector = offload_work->offload_wq->aconnector; 1339 1340 if (!aconnector) { 1341 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work"); 1342 goto skip; 1343 } 1344 1345 adev = drm_to_adev(aconnector->base.dev); 1346 dc_link = aconnector->dc_link; 1347 1348 mutex_lock(&aconnector->hpd_lock); 1349 if (!dc_link_detect_connection_type(dc_link, &new_connection_type)) 1350 DRM_ERROR("KMS: Failed to detect connector\n"); 1351 mutex_unlock(&aconnector->hpd_lock); 1352 1353 if (new_connection_type == dc_connection_none) 1354 goto skip; 1355 1356 if (amdgpu_in_reset(adev)) 1357 goto skip; 1358 1359 if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || 1360 offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { 1361 dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT); 1362 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags); 1363 offload_work->offload_wq->is_handling_mst_msg_rdy_event = false; 1364 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags); 1365 goto skip; 1366 } 1367 1368 mutex_lock(&adev->dm.dc_lock); 1369 if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) { 1370 dc_link_dp_handle_automated_test(dc_link); 1371 1372 if (aconnector->timing_changed) { 1373 /* force connector disconnect and reconnect */ 1374 force_connector_state(aconnector, DRM_FORCE_OFF); 1375 drm_msleep(100); 1376 force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED); 1377 } 1378 1379 test_response.bits.ACK = 1; 1380 1381 core_link_write_dpcd( 1382 dc_link, 1383 DP_TEST_RESPONSE, 1384 &test_response.raw, 1385 sizeof(test_response)); 1386 } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) && 1387 dc_link_check_link_loss_status(dc_link, &offload_work->data) && 1388 dc_link_dp_allow_hpd_rx_irq(dc_link)) { 1389 /* offload_work->data is from handle_hpd_rx_irq-> 1390 * schedule_hpd_rx_offload_work.this is defer handle 1391 * for hpd short pulse. upon here, link status may be 1392 * changed, need get latest link status from dpcd 1393 * registers. if link status is good, skip run link 1394 * training again. 1395 */ 1396 union hpd_irq_data irq_data; 1397 1398 memset(&irq_data, 0, sizeof(irq_data)); 1399 1400 /* before dc_link_dp_handle_link_loss, allow new link lost handle 1401 * request be added to work queue if link lost at end of dc_link_ 1402 * dp_handle_link_loss 1403 */ 1404 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags); 1405 offload_work->offload_wq->is_handling_link_loss = false; 1406 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags); 1407 1408 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) && 1409 dc_link_check_link_loss_status(dc_link, &irq_data)) 1410 dc_link_dp_handle_link_loss(dc_link); 1411 } 1412 mutex_unlock(&adev->dm.dc_lock); 1413 1414 skip: 1415 kfree(offload_work); 1416 1417 } 1418 1419 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc) 1420 { 1421 int max_caps = dc->caps.max_links; 1422 int i = 0; 1423 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL; 1424 1425 hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL); 1426 1427 if (!hpd_rx_offload_wq) 1428 return NULL; 1429 1430 1431 for (i = 0; i < max_caps; i++) { 1432 hpd_rx_offload_wq[i].wq = 1433 create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq"); 1434 1435 if (hpd_rx_offload_wq[i].wq == NULL) { 1436 DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!"); 1437 goto out_err; 1438 } 1439 1440 mtx_init(&hpd_rx_offload_wq[i].offload_lock, IPL_TTY); 1441 } 1442 1443 return hpd_rx_offload_wq; 1444 1445 out_err: 1446 for (i = 0; i < max_caps; i++) { 1447 if (hpd_rx_offload_wq[i].wq) 1448 destroy_workqueue(hpd_rx_offload_wq[i].wq); 1449 } 1450 kfree(hpd_rx_offload_wq); 1451 return NULL; 1452 } 1453 1454 struct amdgpu_stutter_quirk { 1455 u16 chip_vendor; 1456 u16 chip_device; 1457 u16 subsys_vendor; 1458 u16 subsys_device; 1459 u8 revision; 1460 }; 1461 1462 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = { 1463 /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */ 1464 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, 1465 { 0, 0, 0, 0, 0 }, 1466 }; 1467 1468 static bool dm_should_disable_stutter(struct pci_dev *pdev) 1469 { 1470 const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list; 1471 1472 while (p && p->chip_device != 0) { 1473 if (pdev->vendor == p->chip_vendor && 1474 pdev->device == p->chip_device && 1475 pdev->subsystem_vendor == p->subsys_vendor && 1476 pdev->subsystem_device == p->subsys_device && 1477 pdev->revision == p->revision) { 1478 return true; 1479 } 1480 ++p; 1481 } 1482 return false; 1483 } 1484 1485 static const struct dmi_system_id hpd_disconnect_quirk_table[] = { 1486 { 1487 .matches = { 1488 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1489 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"), 1490 }, 1491 }, 1492 { 1493 .matches = { 1494 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1495 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"), 1496 }, 1497 }, 1498 { 1499 .matches = { 1500 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1501 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"), 1502 }, 1503 }, 1504 { 1505 .matches = { 1506 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1507 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"), 1508 }, 1509 }, 1510 { 1511 .matches = { 1512 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1513 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"), 1514 }, 1515 }, 1516 { 1517 .matches = { 1518 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1519 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"), 1520 }, 1521 }, 1522 { 1523 .matches = { 1524 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1525 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"), 1526 }, 1527 }, 1528 { 1529 .matches = { 1530 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1531 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"), 1532 }, 1533 }, 1534 { 1535 .matches = { 1536 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1537 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"), 1538 }, 1539 }, 1540 {} 1541 /* TODO: refactor this from a fixed table to a dynamic option */ 1542 }; 1543 1544 static void retrieve_dmi_info(struct amdgpu_display_manager *dm) 1545 { 1546 const struct dmi_system_id *dmi_id; 1547 1548 dm->aux_hpd_discon_quirk = false; 1549 1550 dmi_id = dmi_first_match(hpd_disconnect_quirk_table); 1551 if (dmi_id) { 1552 dm->aux_hpd_discon_quirk = true; 1553 DRM_INFO("aux_hpd_discon_quirk attached\n"); 1554 } 1555 } 1556 1557 static int amdgpu_dm_init(struct amdgpu_device *adev) 1558 { 1559 struct dc_init_data init_data; 1560 struct dc_callback_init init_params; 1561 int r; 1562 1563 adev->dm.ddev = adev_to_drm(adev); 1564 adev->dm.adev = adev; 1565 1566 /* Zero all the fields */ 1567 memset(&init_data, 0, sizeof(init_data)); 1568 memset(&init_params, 0, sizeof(init_params)); 1569 1570 rw_init(&adev->dm.dpia_aux_lock, "dmdpia"); 1571 rw_init(&adev->dm.dc_lock, "dmdc"); 1572 rw_init(&adev->dm.audio_lock, "dmaud"); 1573 1574 if (amdgpu_dm_irq_init(adev)) { 1575 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); 1576 goto error; 1577 } 1578 1579 init_data.asic_id.chip_family = adev->family; 1580 1581 init_data.asic_id.pci_revision_id = adev->pdev->revision; 1582 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 1583 init_data.asic_id.chip_id = adev->pdev->device; 1584 1585 init_data.asic_id.vram_width = adev->gmc.vram_width; 1586 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 1587 init_data.asic_id.atombios_base_address = 1588 adev->mode_info.atom_context->bios; 1589 1590 init_data.driver = adev; 1591 1592 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 1593 1594 if (!adev->dm.cgs_device) { 1595 DRM_ERROR("amdgpu: failed to create cgs device.\n"); 1596 goto error; 1597 } 1598 1599 init_data.cgs_device = adev->dm.cgs_device; 1600 1601 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 1602 1603 switch (adev->ip_versions[DCE_HWIP][0]) { 1604 case IP_VERSION(2, 1, 0): 1605 switch (adev->dm.dmcub_fw_version) { 1606 case 0: /* development */ 1607 case 0x1: /* linux-firmware.git hash 6d9f399 */ 1608 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */ 1609 init_data.flags.disable_dmcu = false; 1610 break; 1611 default: 1612 init_data.flags.disable_dmcu = true; 1613 } 1614 break; 1615 case IP_VERSION(2, 0, 3): 1616 init_data.flags.disable_dmcu = true; 1617 break; 1618 default: 1619 break; 1620 } 1621 1622 switch (adev->asic_type) { 1623 case CHIP_CARRIZO: 1624 case CHIP_STONEY: 1625 init_data.flags.gpu_vm_support = true; 1626 break; 1627 default: 1628 switch (adev->ip_versions[DCE_HWIP][0]) { 1629 case IP_VERSION(1, 0, 0): 1630 case IP_VERSION(1, 0, 1): 1631 /* enable S/G on PCO and RV2 */ 1632 if ((adev->apu_flags & AMD_APU_IS_RAVEN2) || 1633 (adev->apu_flags & AMD_APU_IS_PICASSO)) 1634 init_data.flags.gpu_vm_support = true; 1635 break; 1636 case IP_VERSION(2, 1, 0): 1637 case IP_VERSION(3, 0, 1): 1638 case IP_VERSION(3, 1, 2): 1639 case IP_VERSION(3, 1, 3): 1640 case IP_VERSION(3, 1, 4): 1641 case IP_VERSION(3, 1, 5): 1642 case IP_VERSION(3, 1, 6): 1643 init_data.flags.gpu_vm_support = true; 1644 break; 1645 default: 1646 break; 1647 } 1648 break; 1649 } 1650 if (init_data.flags.gpu_vm_support && 1651 (amdgpu_sg_display == 0)) 1652 init_data.flags.gpu_vm_support = false; 1653 1654 if (init_data.flags.gpu_vm_support) 1655 adev->mode_info.gpu_vm_support = true; 1656 1657 if (amdgpu_dc_feature_mask & DC_FBC_MASK) 1658 init_data.flags.fbc_support = true; 1659 1660 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) 1661 init_data.flags.multi_mon_pp_mclk_switch = true; 1662 1663 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK) 1664 init_data.flags.disable_fractional_pwm = true; 1665 1666 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING) 1667 init_data.flags.edp_no_power_sequencing = true; 1668 1669 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A) 1670 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true; 1671 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0) 1672 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true; 1673 1674 init_data.flags.seamless_boot_edp_requested = false; 1675 1676 if (check_seamless_boot_capability(adev)) { 1677 init_data.flags.seamless_boot_edp_requested = true; 1678 init_data.flags.allow_seamless_boot_optimization = true; 1679 DRM_INFO("Seamless boot condition check passed\n"); 1680 } 1681 1682 init_data.flags.enable_mipi_converter_optimization = true; 1683 1684 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0]; 1685 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0]; 1686 1687 INIT_LIST_HEAD(&adev->dm.da_list); 1688 1689 retrieve_dmi_info(&adev->dm); 1690 1691 /* Display Core create. */ 1692 adev->dm.dc = dc_create(&init_data); 1693 1694 if (adev->dm.dc) { 1695 DRM_INFO("Display Core v%s initialized on %s\n", DC_VER, 1696 dce_version_to_string(adev->dm.dc->ctx->dce_version)); 1697 } else { 1698 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER); 1699 goto error; 1700 } 1701 1702 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) { 1703 adev->dm.dc->debug.force_single_disp_pipe_split = false; 1704 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; 1705 } 1706 1707 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 1708 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 1709 if (dm_should_disable_stutter(adev->pdev)) 1710 adev->dm.dc->debug.disable_stutter = true; 1711 1712 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER) 1713 adev->dm.dc->debug.disable_stutter = true; 1714 1715 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) 1716 adev->dm.dc->debug.disable_dsc = true; 1717 1718 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) 1719 adev->dm.dc->debug.disable_clock_gate = true; 1720 1721 if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH) 1722 adev->dm.dc->debug.force_subvp_mclk_switch = true; 1723 1724 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm; 1725 1726 /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */ 1727 adev->dm.dc->debug.ignore_cable_id = true; 1728 1729 /* TODO: There is a new drm mst change where the freedom of 1730 * vc_next_start_slot update is revoked/moved into drm, instead of in 1731 * driver. This forces us to make sure to get vc_next_start_slot updated 1732 * in drm function each time without considering if mst_state is active 1733 * or not. Otherwise, next time hotplug will give wrong start_slot 1734 * number. We are implementing a temporary solution to even notify drm 1735 * mst deallocation when link is no longer of MST type when uncommitting 1736 * the stream so we will have more time to work on a proper solution. 1737 * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we 1738 * should notify drm to do a complete "reset" of its states and stop 1739 * calling further drm mst functions when link is no longer of an MST 1740 * type. This could happen when we unplug an MST hubs/displays. When 1741 * uncommit stream comes later after unplug, we should just reset 1742 * hardware states only. 1743 */ 1744 adev->dm.dc->debug.temp_mst_deallocation_sequence = true; 1745 1746 if (adev->dm.dc->caps.dp_hdmi21_pcon_support) 1747 DRM_INFO("DP-HDMI FRL PCON supported\n"); 1748 1749 r = dm_dmub_hw_init(adev); 1750 if (r) { 1751 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 1752 goto error; 1753 } 1754 1755 dc_hardware_init(adev->dm.dc); 1756 1757 adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc); 1758 if (!adev->dm.hpd_rx_offload_wq) { 1759 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n"); 1760 goto error; 1761 } 1762 1763 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) { 1764 struct dc_phy_addr_space_config pa_config; 1765 1766 mmhub_read_system_context(adev, &pa_config); 1767 1768 // Call the DC init_memory func 1769 dc_setup_system_context(adev->dm.dc, &pa_config); 1770 } 1771 1772 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 1773 if (!adev->dm.freesync_module) { 1774 DRM_ERROR( 1775 "amdgpu: failed to initialize freesync_module.\n"); 1776 } else 1777 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", 1778 adev->dm.freesync_module); 1779 1780 amdgpu_dm_init_color_mod(); 1781 1782 if (adev->dm.dc->caps.max_links > 0) { 1783 adev->dm.vblank_control_workqueue = 1784 create_singlethread_workqueue("dm_vblank_control_workqueue"); 1785 if (!adev->dm.vblank_control_workqueue) 1786 DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n"); 1787 } 1788 1789 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) { 1790 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc); 1791 1792 if (!adev->dm.hdcp_workqueue) 1793 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n"); 1794 else 1795 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue); 1796 1797 dc_init_callbacks(adev->dm.dc, &init_params); 1798 } 1799 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 1800 init_completion(&adev->dm.dmub_aux_transfer_done); 1801 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL); 1802 if (!adev->dm.dmub_notify) { 1803 DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify"); 1804 goto error; 1805 } 1806 1807 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq"); 1808 if (!adev->dm.delayed_hpd_wq) { 1809 DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n"); 1810 goto error; 1811 } 1812 1813 amdgpu_dm_outbox_init(adev); 1814 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY, 1815 dmub_aux_setconfig_callback, false)) { 1816 DRM_ERROR("amdgpu: fail to register dmub aux callback"); 1817 goto error; 1818 } 1819 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive. 1820 * It is expected that DMUB will resend any pending notifications at this point. Note 1821 * that hpd and hpd_irq handler registration are deferred to register_hpd_handlers() to 1822 * align legacy interface initialization sequence. Connection status will be proactivly 1823 * detected once in the amdgpu_dm_initialize_drm_device. 1824 */ 1825 dc_enable_dmub_outbox(adev->dm.dc); 1826 1827 /* DPIA trace goes to dmesg logs only if outbox is enabled */ 1828 if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE) 1829 dc_dmub_srv_enable_dpia_trace(adev->dm.dc); 1830 } 1831 1832 if (amdgpu_dm_initialize_drm_device(adev)) { 1833 DRM_ERROR( 1834 "amdgpu: failed to initialize sw for display support.\n"); 1835 goto error; 1836 } 1837 1838 /* create fake encoders for MST */ 1839 dm_dp_create_fake_mst_encoders(adev); 1840 1841 /* TODO: Add_display_info? */ 1842 1843 /* TODO use dynamic cursor width */ 1844 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 1845 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 1846 1847 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { 1848 DRM_ERROR( 1849 "amdgpu: failed to initialize sw for display support.\n"); 1850 goto error; 1851 } 1852 1853 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 1854 adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev); 1855 if (!adev->dm.secure_display_ctxs) 1856 DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n"); 1857 #endif 1858 1859 DRM_DEBUG_DRIVER("KMS initialized.\n"); 1860 1861 return 0; 1862 error: 1863 amdgpu_dm_fini(adev); 1864 1865 return -EINVAL; 1866 } 1867 1868 static int amdgpu_dm_early_fini(void *handle) 1869 { 1870 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1871 1872 amdgpu_dm_audio_fini(adev); 1873 1874 return 0; 1875 } 1876 1877 static void amdgpu_dm_fini(struct amdgpu_device *adev) 1878 { 1879 int i; 1880 1881 if (adev->dm.vblank_control_workqueue) { 1882 destroy_workqueue(adev->dm.vblank_control_workqueue); 1883 adev->dm.vblank_control_workqueue = NULL; 1884 } 1885 1886 amdgpu_dm_destroy_drm_device(&adev->dm); 1887 1888 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 1889 if (adev->dm.secure_display_ctxs) { 1890 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1891 if (adev->dm.secure_display_ctxs[i].crtc) { 1892 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work); 1893 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work); 1894 } 1895 } 1896 kfree(adev->dm.secure_display_ctxs); 1897 adev->dm.secure_display_ctxs = NULL; 1898 } 1899 #endif 1900 if (adev->dm.hdcp_workqueue) { 1901 #ifdef notyet 1902 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue); 1903 #else 1904 hdcp_destroy(NULL, adev->dm.hdcp_workqueue); 1905 #endif 1906 adev->dm.hdcp_workqueue = NULL; 1907 } 1908 1909 if (adev->dm.dc) 1910 dc_deinit_callbacks(adev->dm.dc); 1911 1912 if (adev->dm.dc) 1913 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); 1914 1915 if (dc_enable_dmub_notifications(adev->dm.dc)) { 1916 kfree(adev->dm.dmub_notify); 1917 adev->dm.dmub_notify = NULL; 1918 destroy_workqueue(adev->dm.delayed_hpd_wq); 1919 adev->dm.delayed_hpd_wq = NULL; 1920 } 1921 1922 if (adev->dm.dmub_bo) 1923 amdgpu_bo_free_kernel(&adev->dm.dmub_bo, 1924 &adev->dm.dmub_bo_gpu_addr, 1925 &adev->dm.dmub_bo_cpu_addr); 1926 1927 if (adev->dm.hpd_rx_offload_wq) { 1928 for (i = 0; i < adev->dm.dc->caps.max_links; i++) { 1929 if (adev->dm.hpd_rx_offload_wq[i].wq) { 1930 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq); 1931 adev->dm.hpd_rx_offload_wq[i].wq = NULL; 1932 } 1933 } 1934 1935 kfree(adev->dm.hpd_rx_offload_wq); 1936 adev->dm.hpd_rx_offload_wq = NULL; 1937 } 1938 1939 /* DC Destroy TODO: Replace destroy DAL */ 1940 if (adev->dm.dc) 1941 dc_destroy(&adev->dm.dc); 1942 /* 1943 * TODO: pageflip, vlank interrupt 1944 * 1945 * amdgpu_dm_irq_fini(adev); 1946 */ 1947 1948 if (adev->dm.cgs_device) { 1949 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 1950 adev->dm.cgs_device = NULL; 1951 } 1952 if (adev->dm.freesync_module) { 1953 mod_freesync_destroy(adev->dm.freesync_module); 1954 adev->dm.freesync_module = NULL; 1955 } 1956 1957 mutex_destroy(&adev->dm.audio_lock); 1958 mutex_destroy(&adev->dm.dc_lock); 1959 mutex_destroy(&adev->dm.dpia_aux_lock); 1960 } 1961 1962 static int load_dmcu_fw(struct amdgpu_device *adev) 1963 { 1964 const char *fw_name_dmcu = NULL; 1965 int r; 1966 const struct dmcu_firmware_header_v1_0 *hdr; 1967 1968 switch (adev->asic_type) { 1969 #if defined(CONFIG_DRM_AMD_DC_SI) 1970 case CHIP_TAHITI: 1971 case CHIP_PITCAIRN: 1972 case CHIP_VERDE: 1973 case CHIP_OLAND: 1974 #endif 1975 case CHIP_BONAIRE: 1976 case CHIP_HAWAII: 1977 case CHIP_KAVERI: 1978 case CHIP_KABINI: 1979 case CHIP_MULLINS: 1980 case CHIP_TONGA: 1981 case CHIP_FIJI: 1982 case CHIP_CARRIZO: 1983 case CHIP_STONEY: 1984 case CHIP_POLARIS11: 1985 case CHIP_POLARIS10: 1986 case CHIP_POLARIS12: 1987 case CHIP_VEGAM: 1988 case CHIP_VEGA10: 1989 case CHIP_VEGA12: 1990 case CHIP_VEGA20: 1991 return 0; 1992 case CHIP_NAVI12: 1993 fw_name_dmcu = FIRMWARE_NAVI12_DMCU; 1994 break; 1995 case CHIP_RAVEN: 1996 if (ASICREV_IS_PICASSO(adev->external_rev_id)) 1997 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 1998 else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) 1999 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 2000 else 2001 return 0; 2002 break; 2003 default: 2004 switch (adev->ip_versions[DCE_HWIP][0]) { 2005 case IP_VERSION(2, 0, 2): 2006 case IP_VERSION(2, 0, 3): 2007 case IP_VERSION(2, 0, 0): 2008 case IP_VERSION(2, 1, 0): 2009 case IP_VERSION(3, 0, 0): 2010 case IP_VERSION(3, 0, 2): 2011 case IP_VERSION(3, 0, 3): 2012 case IP_VERSION(3, 0, 1): 2013 case IP_VERSION(3, 1, 2): 2014 case IP_VERSION(3, 1, 3): 2015 case IP_VERSION(3, 1, 4): 2016 case IP_VERSION(3, 1, 5): 2017 case IP_VERSION(3, 1, 6): 2018 case IP_VERSION(3, 2, 0): 2019 case IP_VERSION(3, 2, 1): 2020 return 0; 2021 default: 2022 break; 2023 } 2024 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 2025 return -EINVAL; 2026 } 2027 2028 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2029 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); 2030 return 0; 2031 } 2032 2033 r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu); 2034 if (r == -ENODEV) { 2035 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 2036 DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); 2037 adev->dm.fw_dmcu = NULL; 2038 return 0; 2039 } 2040 if (r) { 2041 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", 2042 fw_name_dmcu); 2043 amdgpu_ucode_release(&adev->dm.fw_dmcu); 2044 return r; 2045 } 2046 2047 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; 2048 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; 2049 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; 2050 adev->firmware.fw_size += 2051 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 2052 2053 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; 2054 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; 2055 adev->firmware.fw_size += 2056 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 2057 2058 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 2059 2060 DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); 2061 2062 return 0; 2063 } 2064 2065 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address) 2066 { 2067 struct amdgpu_device *adev = ctx; 2068 2069 return dm_read_reg(adev->dm.dc->ctx, address); 2070 } 2071 2072 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address, 2073 uint32_t value) 2074 { 2075 struct amdgpu_device *adev = ctx; 2076 2077 return dm_write_reg(adev->dm.dc->ctx, address, value); 2078 } 2079 2080 static int dm_dmub_sw_init(struct amdgpu_device *adev) 2081 { 2082 struct dmub_srv_create_params create_params; 2083 struct dmub_srv_region_params region_params; 2084 struct dmub_srv_region_info region_info; 2085 struct dmub_srv_memory_params memory_params; 2086 struct dmub_srv_fb_info *fb_info; 2087 struct dmub_srv *dmub_srv; 2088 const struct dmcub_firmware_header_v1_0 *hdr; 2089 enum dmub_asic dmub_asic; 2090 enum dmub_status status; 2091 int r; 2092 2093 switch (adev->ip_versions[DCE_HWIP][0]) { 2094 case IP_VERSION(2, 1, 0): 2095 dmub_asic = DMUB_ASIC_DCN21; 2096 break; 2097 case IP_VERSION(3, 0, 0): 2098 dmub_asic = DMUB_ASIC_DCN30; 2099 break; 2100 case IP_VERSION(3, 0, 1): 2101 dmub_asic = DMUB_ASIC_DCN301; 2102 break; 2103 case IP_VERSION(3, 0, 2): 2104 dmub_asic = DMUB_ASIC_DCN302; 2105 break; 2106 case IP_VERSION(3, 0, 3): 2107 dmub_asic = DMUB_ASIC_DCN303; 2108 break; 2109 case IP_VERSION(3, 1, 2): 2110 case IP_VERSION(3, 1, 3): 2111 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31; 2112 break; 2113 case IP_VERSION(3, 1, 4): 2114 dmub_asic = DMUB_ASIC_DCN314; 2115 break; 2116 case IP_VERSION(3, 1, 5): 2117 dmub_asic = DMUB_ASIC_DCN315; 2118 break; 2119 case IP_VERSION(3, 1, 6): 2120 dmub_asic = DMUB_ASIC_DCN316; 2121 break; 2122 case IP_VERSION(3, 2, 0): 2123 dmub_asic = DMUB_ASIC_DCN32; 2124 break; 2125 case IP_VERSION(3, 2, 1): 2126 dmub_asic = DMUB_ASIC_DCN321; 2127 break; 2128 default: 2129 /* ASIC doesn't support DMUB. */ 2130 return 0; 2131 } 2132 2133 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data; 2134 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version); 2135 2136 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2137 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id = 2138 AMDGPU_UCODE_ID_DMCUB; 2139 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw = 2140 adev->dm.dmub_fw; 2141 adev->firmware.fw_size += 2142 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE); 2143 2144 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n", 2145 adev->dm.dmcub_fw_version); 2146 } 2147 2148 2149 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL); 2150 dmub_srv = adev->dm.dmub_srv; 2151 2152 if (!dmub_srv) { 2153 DRM_ERROR("Failed to allocate DMUB service!\n"); 2154 return -ENOMEM; 2155 } 2156 2157 memset(&create_params, 0, sizeof(create_params)); 2158 create_params.user_ctx = adev; 2159 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read; 2160 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write; 2161 create_params.asic = dmub_asic; 2162 2163 /* Create the DMUB service. */ 2164 status = dmub_srv_create(dmub_srv, &create_params); 2165 if (status != DMUB_STATUS_OK) { 2166 DRM_ERROR("Error creating DMUB service: %d\n", status); 2167 return -EINVAL; 2168 } 2169 2170 /* Calculate the size of all the regions for the DMUB service. */ 2171 memset(®ion_params, 0, sizeof(region_params)); 2172 2173 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - 2174 PSP_HEADER_BYTES - PSP_FOOTER_BYTES; 2175 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes); 2176 region_params.vbios_size = adev->bios_size; 2177 region_params.fw_bss_data = region_params.bss_data_size ? 2178 adev->dm.dmub_fw->data + 2179 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 2180 le32_to_cpu(hdr->inst_const_bytes) : NULL; 2181 region_params.fw_inst_const = 2182 adev->dm.dmub_fw->data + 2183 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 2184 PSP_HEADER_BYTES; 2185 region_params.is_mailbox_in_inbox = false; 2186 2187 status = dmub_srv_calc_region_info(dmub_srv, ®ion_params, 2188 ®ion_info); 2189 2190 if (status != DMUB_STATUS_OK) { 2191 DRM_ERROR("Error calculating DMUB region info: %d\n", status); 2192 return -EINVAL; 2193 } 2194 2195 /* 2196 * Allocate a framebuffer based on the total size of all the regions. 2197 * TODO: Move this into GART. 2198 */ 2199 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE, 2200 AMDGPU_GEM_DOMAIN_VRAM | 2201 AMDGPU_GEM_DOMAIN_GTT, 2202 &adev->dm.dmub_bo, 2203 &adev->dm.dmub_bo_gpu_addr, 2204 &adev->dm.dmub_bo_cpu_addr); 2205 if (r) 2206 return r; 2207 2208 /* Rebase the regions on the framebuffer address. */ 2209 memset(&memory_params, 0, sizeof(memory_params)); 2210 memory_params.cpu_fb_addr = adev->dm.dmub_bo_cpu_addr; 2211 memory_params.gpu_fb_addr = adev->dm.dmub_bo_gpu_addr; 2212 memory_params.region_info = ®ion_info; 2213 2214 adev->dm.dmub_fb_info = 2215 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL); 2216 fb_info = adev->dm.dmub_fb_info; 2217 2218 if (!fb_info) { 2219 DRM_ERROR( 2220 "Failed to allocate framebuffer info for DMUB service!\n"); 2221 return -ENOMEM; 2222 } 2223 2224 status = dmub_srv_calc_mem_info(dmub_srv, &memory_params, fb_info); 2225 if (status != DMUB_STATUS_OK) { 2226 DRM_ERROR("Error calculating DMUB FB info: %d\n", status); 2227 return -EINVAL; 2228 } 2229 2230 return 0; 2231 } 2232 2233 static int dm_sw_init(void *handle) 2234 { 2235 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2236 int r; 2237 2238 r = dm_dmub_sw_init(adev); 2239 if (r) 2240 return r; 2241 2242 return load_dmcu_fw(adev); 2243 } 2244 2245 static int dm_sw_fini(void *handle) 2246 { 2247 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2248 2249 kfree(adev->dm.dmub_fb_info); 2250 adev->dm.dmub_fb_info = NULL; 2251 2252 if (adev->dm.dmub_srv) { 2253 dmub_srv_destroy(adev->dm.dmub_srv); 2254 kfree(adev->dm.dmub_srv); 2255 adev->dm.dmub_srv = NULL; 2256 } 2257 2258 amdgpu_ucode_release(&adev->dm.dmub_fw); 2259 amdgpu_ucode_release(&adev->dm.fw_dmcu); 2260 2261 return 0; 2262 } 2263 2264 static int detect_mst_link_for_all_connectors(struct drm_device *dev) 2265 { 2266 struct amdgpu_dm_connector *aconnector; 2267 struct drm_connector *connector; 2268 struct drm_connector_list_iter iter; 2269 int ret = 0; 2270 2271 drm_connector_list_iter_begin(dev, &iter); 2272 drm_for_each_connector_iter(connector, &iter) { 2273 aconnector = to_amdgpu_dm_connector(connector); 2274 if (aconnector->dc_link->type == dc_connection_mst_branch && 2275 aconnector->mst_mgr.aux) { 2276 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n", 2277 aconnector, 2278 aconnector->base.base.id); 2279 2280 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 2281 if (ret < 0) { 2282 DRM_ERROR("DM_MST: Failed to start MST\n"); 2283 aconnector->dc_link->type = 2284 dc_connection_single; 2285 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, 2286 aconnector->dc_link); 2287 break; 2288 } 2289 } 2290 } 2291 drm_connector_list_iter_end(&iter); 2292 2293 return ret; 2294 } 2295 2296 static int dm_late_init(void *handle) 2297 { 2298 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2299 2300 struct dmcu_iram_parameters params; 2301 unsigned int linear_lut[16]; 2302 int i; 2303 struct dmcu *dmcu = NULL; 2304 2305 dmcu = adev->dm.dc->res_pool->dmcu; 2306 2307 for (i = 0; i < 16; i++) 2308 linear_lut[i] = 0xFFFF * i / 15; 2309 2310 params.set = 0; 2311 params.backlight_ramping_override = false; 2312 params.backlight_ramping_start = 0xCCCC; 2313 params.backlight_ramping_reduction = 0xCCCCCCCC; 2314 params.backlight_lut_array_size = 16; 2315 params.backlight_lut_array = linear_lut; 2316 2317 /* Min backlight level after ABM reduction, Don't allow below 1% 2318 * 0xFFFF x 0.01 = 0x28F 2319 */ 2320 params.min_abm_backlight = 0x28F; 2321 /* In the case where abm is implemented on dmcub, 2322 * dmcu object will be null. 2323 * ABM 2.4 and up are implemented on dmcub. 2324 */ 2325 if (dmcu) { 2326 if (!dmcu_load_iram(dmcu, params)) 2327 return -EINVAL; 2328 } else if (adev->dm.dc->ctx->dmub_srv) { 2329 struct dc_link *edp_links[MAX_NUM_EDP]; 2330 int edp_num; 2331 2332 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num); 2333 for (i = 0; i < edp_num; i++) { 2334 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i)) 2335 return -EINVAL; 2336 } 2337 } 2338 2339 return detect_mst_link_for_all_connectors(adev_to_drm(adev)); 2340 } 2341 2342 static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr) 2343 { 2344 int ret; 2345 u8 guid[16]; 2346 u64 tmp64; 2347 2348 mutex_lock(&mgr->lock); 2349 if (!mgr->mst_primary) 2350 goto out_fail; 2351 2352 if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) { 2353 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 2354 goto out_fail; 2355 } 2356 2357 ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 2358 DP_MST_EN | 2359 DP_UP_REQ_EN | 2360 DP_UPSTREAM_IS_SRC); 2361 if (ret < 0) { 2362 drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n"); 2363 goto out_fail; 2364 } 2365 2366 /* Some hubs forget their guids after they resume */ 2367 ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16); 2368 if (ret != 16) { 2369 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 2370 goto out_fail; 2371 } 2372 2373 if (memchr_inv(guid, 0, 16) == NULL) { 2374 tmp64 = get_jiffies_64(); 2375 memcpy(&guid[0], &tmp64, sizeof(u64)); 2376 memcpy(&guid[8], &tmp64, sizeof(u64)); 2377 2378 ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, guid, 16); 2379 2380 if (ret != 16) { 2381 drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n"); 2382 goto out_fail; 2383 } 2384 } 2385 2386 memcpy(mgr->mst_primary->guid, guid, 16); 2387 2388 out_fail: 2389 mutex_unlock(&mgr->lock); 2390 } 2391 2392 static void s3_handle_mst(struct drm_device *dev, bool suspend) 2393 { 2394 struct amdgpu_dm_connector *aconnector; 2395 struct drm_connector *connector; 2396 struct drm_connector_list_iter iter; 2397 struct drm_dp_mst_topology_mgr *mgr; 2398 2399 drm_connector_list_iter_begin(dev, &iter); 2400 drm_for_each_connector_iter(connector, &iter) { 2401 aconnector = to_amdgpu_dm_connector(connector); 2402 if (aconnector->dc_link->type != dc_connection_mst_branch || 2403 aconnector->mst_root) 2404 continue; 2405 2406 mgr = &aconnector->mst_mgr; 2407 2408 if (suspend) { 2409 drm_dp_mst_topology_mgr_suspend(mgr); 2410 } else { 2411 /* if extended timeout is supported in hardware, 2412 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer 2413 * CTS 4.2.1.1 regression introduced by CTS specs requirement update. 2414 */ 2415 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD); 2416 if (!dp_is_lttpr_present(aconnector->dc_link)) 2417 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); 2418 2419 /* TODO: move resume_mst_branch_status() into drm mst resume again 2420 * once topology probing work is pulled out from mst resume into mst 2421 * resume 2nd step. mst resume 2nd step should be called after old 2422 * state getting restored (i.e. drm_atomic_helper_resume()). 2423 */ 2424 resume_mst_branch_status(mgr); 2425 } 2426 } 2427 drm_connector_list_iter_end(&iter); 2428 } 2429 2430 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) 2431 { 2432 int ret = 0; 2433 2434 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends 2435 * on window driver dc implementation. 2436 * For Navi1x, clock settings of dcn watermarks are fixed. the settings 2437 * should be passed to smu during boot up and resume from s3. 2438 * boot up: dc calculate dcn watermark clock settings within dc_create, 2439 * dcn20_resource_construct 2440 * then call pplib functions below to pass the settings to smu: 2441 * smu_set_watermarks_for_clock_ranges 2442 * smu_set_watermarks_table 2443 * navi10_set_watermarks_table 2444 * smu_write_watermarks_table 2445 * 2446 * For Renoir, clock settings of dcn watermark are also fixed values. 2447 * dc has implemented different flow for window driver: 2448 * dc_hardware_init / dc_set_power_state 2449 * dcn10_init_hw 2450 * notify_wm_ranges 2451 * set_wm_ranges 2452 * -- Linux 2453 * smu_set_watermarks_for_clock_ranges 2454 * renoir_set_watermarks_table 2455 * smu_write_watermarks_table 2456 * 2457 * For Linux, 2458 * dc_hardware_init -> amdgpu_dm_init 2459 * dc_set_power_state --> dm_resume 2460 * 2461 * therefore, this function apply to navi10/12/14 but not Renoir 2462 * * 2463 */ 2464 switch (adev->ip_versions[DCE_HWIP][0]) { 2465 case IP_VERSION(2, 0, 2): 2466 case IP_VERSION(2, 0, 0): 2467 break; 2468 default: 2469 return 0; 2470 } 2471 2472 ret = amdgpu_dpm_write_watermarks_table(adev); 2473 if (ret) { 2474 DRM_ERROR("Failed to update WMTABLE!\n"); 2475 return ret; 2476 } 2477 2478 return 0; 2479 } 2480 2481 /** 2482 * dm_hw_init() - Initialize DC device 2483 * @handle: The base driver device containing the amdgpu_dm device. 2484 * 2485 * Initialize the &struct amdgpu_display_manager device. This involves calling 2486 * the initializers of each DM component, then populating the struct with them. 2487 * 2488 * Although the function implies hardware initialization, both hardware and 2489 * software are initialized here. Splitting them out to their relevant init 2490 * hooks is a future TODO item. 2491 * 2492 * Some notable things that are initialized here: 2493 * 2494 * - Display Core, both software and hardware 2495 * - DC modules that we need (freesync and color management) 2496 * - DRM software states 2497 * - Interrupt sources and handlers 2498 * - Vblank support 2499 * - Debug FS entries, if enabled 2500 */ 2501 static int dm_hw_init(void *handle) 2502 { 2503 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2504 /* Create DAL display manager */ 2505 amdgpu_dm_init(adev); 2506 amdgpu_dm_hpd_init(adev); 2507 2508 return 0; 2509 } 2510 2511 /** 2512 * dm_hw_fini() - Teardown DC device 2513 * @handle: The base driver device containing the amdgpu_dm device. 2514 * 2515 * Teardown components within &struct amdgpu_display_manager that require 2516 * cleanup. This involves cleaning up the DRM device, DC, and any modules that 2517 * were loaded. Also flush IRQ workqueues and disable them. 2518 */ 2519 static int dm_hw_fini(void *handle) 2520 { 2521 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2522 2523 amdgpu_dm_hpd_fini(adev); 2524 2525 amdgpu_dm_irq_fini(adev); 2526 amdgpu_dm_fini(adev); 2527 return 0; 2528 } 2529 2530 2531 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev, 2532 struct dc_state *state, bool enable) 2533 { 2534 enum dc_irq_source irq_source; 2535 struct amdgpu_crtc *acrtc; 2536 int rc = -EBUSY; 2537 int i = 0; 2538 2539 for (i = 0; i < state->stream_count; i++) { 2540 acrtc = get_crtc_by_otg_inst( 2541 adev, state->stream_status[i].primary_otg_inst); 2542 2543 if (acrtc && state->stream_status[i].plane_count != 0) { 2544 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; 2545 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 2546 if (rc) 2547 DRM_WARN("Failed to %s pflip interrupts\n", 2548 enable ? "enable" : "disable"); 2549 2550 if (enable) { 2551 if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state))) 2552 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true); 2553 } else 2554 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false); 2555 2556 if (rc) 2557 DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis"); 2558 2559 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 2560 /* During gpu-reset we disable and then enable vblank irq, so 2561 * don't use amdgpu_irq_get/put() to avoid refcount change. 2562 */ 2563 if (!dc_interrupt_set(adev->dm.dc, irq_source, enable)) 2564 DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis"); 2565 } 2566 } 2567 2568 } 2569 2570 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc) 2571 { 2572 struct dc_state *context = NULL; 2573 enum dc_status res = DC_ERROR_UNEXPECTED; 2574 int i; 2575 struct dc_stream_state *del_streams[MAX_PIPES]; 2576 int del_streams_count = 0; 2577 2578 memset(del_streams, 0, sizeof(del_streams)); 2579 2580 context = dc_create_state(dc); 2581 if (context == NULL) 2582 goto context_alloc_fail; 2583 2584 dc_resource_state_copy_construct_current(dc, context); 2585 2586 /* First remove from context all streams */ 2587 for (i = 0; i < context->stream_count; i++) { 2588 struct dc_stream_state *stream = context->streams[i]; 2589 2590 del_streams[del_streams_count++] = stream; 2591 } 2592 2593 /* Remove all planes for removed streams and then remove the streams */ 2594 for (i = 0; i < del_streams_count; i++) { 2595 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) { 2596 res = DC_FAIL_DETACH_SURFACES; 2597 goto fail; 2598 } 2599 2600 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]); 2601 if (res != DC_OK) 2602 goto fail; 2603 } 2604 2605 res = dc_commit_streams(dc, context->streams, context->stream_count); 2606 2607 fail: 2608 dc_release_state(context); 2609 2610 context_alloc_fail: 2611 return res; 2612 } 2613 2614 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm) 2615 { 2616 int i; 2617 2618 if (dm->hpd_rx_offload_wq) { 2619 for (i = 0; i < dm->dc->caps.max_links; i++) 2620 flush_workqueue(dm->hpd_rx_offload_wq[i].wq); 2621 } 2622 } 2623 2624 static int dm_suspend(void *handle) 2625 { 2626 struct amdgpu_device *adev = handle; 2627 struct amdgpu_display_manager *dm = &adev->dm; 2628 int ret = 0; 2629 2630 if (amdgpu_in_reset(adev)) { 2631 mutex_lock(&dm->dc_lock); 2632 2633 dc_allow_idle_optimizations(adev->dm.dc, false); 2634 2635 dm->cached_dc_state = dc_copy_state(dm->dc->current_state); 2636 2637 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false); 2638 2639 amdgpu_dm_commit_zero_streams(dm->dc); 2640 2641 amdgpu_dm_irq_suspend(adev); 2642 2643 hpd_rx_irq_work_suspend(dm); 2644 2645 return ret; 2646 } 2647 2648 WARN_ON(adev->dm.cached_state); 2649 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); 2650 2651 s3_handle_mst(adev_to_drm(adev), true); 2652 2653 amdgpu_dm_irq_suspend(adev); 2654 2655 hpd_rx_irq_work_suspend(dm); 2656 2657 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 2658 2659 return 0; 2660 } 2661 2662 struct amdgpu_dm_connector * 2663 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 2664 struct drm_crtc *crtc) 2665 { 2666 u32 i; 2667 struct drm_connector_state *new_con_state; 2668 struct drm_connector *connector; 2669 struct drm_crtc *crtc_from_state; 2670 2671 for_each_new_connector_in_state(state, connector, new_con_state, i) { 2672 crtc_from_state = new_con_state->crtc; 2673 2674 if (crtc_from_state == crtc) 2675 return to_amdgpu_dm_connector(connector); 2676 } 2677 2678 return NULL; 2679 } 2680 2681 static void emulated_link_detect(struct dc_link *link) 2682 { 2683 struct dc_sink_init_data sink_init_data = { 0 }; 2684 struct display_sink_capability sink_caps = { 0 }; 2685 enum dc_edid_status edid_status; 2686 struct dc_context *dc_ctx = link->ctx; 2687 struct dc_sink *sink = NULL; 2688 struct dc_sink *prev_sink = NULL; 2689 2690 link->type = dc_connection_none; 2691 prev_sink = link->local_sink; 2692 2693 if (prev_sink) 2694 dc_sink_release(prev_sink); 2695 2696 switch (link->connector_signal) { 2697 case SIGNAL_TYPE_HDMI_TYPE_A: { 2698 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2699 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 2700 break; 2701 } 2702 2703 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 2704 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2705 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 2706 break; 2707 } 2708 2709 case SIGNAL_TYPE_DVI_DUAL_LINK: { 2710 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2711 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 2712 break; 2713 } 2714 2715 case SIGNAL_TYPE_LVDS: { 2716 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2717 sink_caps.signal = SIGNAL_TYPE_LVDS; 2718 break; 2719 } 2720 2721 case SIGNAL_TYPE_EDP: { 2722 sink_caps.transaction_type = 2723 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 2724 sink_caps.signal = SIGNAL_TYPE_EDP; 2725 break; 2726 } 2727 2728 case SIGNAL_TYPE_DISPLAY_PORT: { 2729 sink_caps.transaction_type = 2730 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 2731 sink_caps.signal = SIGNAL_TYPE_VIRTUAL; 2732 break; 2733 } 2734 2735 default: 2736 DC_ERROR("Invalid connector type! signal:%d\n", 2737 link->connector_signal); 2738 return; 2739 } 2740 2741 sink_init_data.link = link; 2742 sink_init_data.sink_signal = sink_caps.signal; 2743 2744 sink = dc_sink_create(&sink_init_data); 2745 if (!sink) { 2746 DC_ERROR("Failed to create sink!\n"); 2747 return; 2748 } 2749 2750 /* dc_sink_create returns a new reference */ 2751 link->local_sink = sink; 2752 2753 edid_status = dm_helpers_read_local_edid( 2754 link->ctx, 2755 link, 2756 sink); 2757 2758 if (edid_status != EDID_OK) 2759 DC_ERROR("Failed to read EDID"); 2760 2761 } 2762 2763 static void dm_gpureset_commit_state(struct dc_state *dc_state, 2764 struct amdgpu_display_manager *dm) 2765 { 2766 struct { 2767 struct dc_surface_update surface_updates[MAX_SURFACES]; 2768 struct dc_plane_info plane_infos[MAX_SURFACES]; 2769 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 2770 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 2771 struct dc_stream_update stream_update; 2772 } *bundle; 2773 int k, m; 2774 2775 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 2776 2777 if (!bundle) { 2778 dm_error("Failed to allocate update bundle\n"); 2779 goto cleanup; 2780 } 2781 2782 for (k = 0; k < dc_state->stream_count; k++) { 2783 bundle->stream_update.stream = dc_state->streams[k]; 2784 2785 for (m = 0; m < dc_state->stream_status->plane_count; m++) { 2786 bundle->surface_updates[m].surface = 2787 dc_state->stream_status->plane_states[m]; 2788 bundle->surface_updates[m].surface->force_full_update = 2789 true; 2790 } 2791 2792 update_planes_and_stream_adapter(dm->dc, 2793 UPDATE_TYPE_FULL, 2794 dc_state->stream_status->plane_count, 2795 dc_state->streams[k], 2796 &bundle->stream_update, 2797 bundle->surface_updates); 2798 } 2799 2800 cleanup: 2801 kfree(bundle); 2802 } 2803 2804 static int dm_resume(void *handle) 2805 { 2806 struct amdgpu_device *adev = handle; 2807 struct drm_device *ddev = adev_to_drm(adev); 2808 struct amdgpu_display_manager *dm = &adev->dm; 2809 struct amdgpu_dm_connector *aconnector; 2810 struct drm_connector *connector; 2811 struct drm_connector_list_iter iter; 2812 struct drm_crtc *crtc; 2813 struct drm_crtc_state *new_crtc_state; 2814 struct dm_crtc_state *dm_new_crtc_state; 2815 struct drm_plane *plane; 2816 struct drm_plane_state *new_plane_state; 2817 struct dm_plane_state *dm_new_plane_state; 2818 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); 2819 enum dc_connection_type new_connection_type = dc_connection_none; 2820 struct dc_state *dc_state; 2821 int i, r, j, ret; 2822 bool need_hotplug = false; 2823 2824 if (amdgpu_in_reset(adev)) { 2825 dc_state = dm->cached_dc_state; 2826 2827 /* 2828 * The dc->current_state is backed up into dm->cached_dc_state 2829 * before we commit 0 streams. 2830 * 2831 * DC will clear link encoder assignments on the real state 2832 * but the changes won't propagate over to the copy we made 2833 * before the 0 streams commit. 2834 * 2835 * DC expects that link encoder assignments are *not* valid 2836 * when committing a state, so as a workaround we can copy 2837 * off of the current state. 2838 * 2839 * We lose the previous assignments, but we had already 2840 * commit 0 streams anyway. 2841 */ 2842 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state); 2843 2844 r = dm_dmub_hw_init(adev); 2845 if (r) 2846 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 2847 2848 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 2849 dc_resume(dm->dc); 2850 2851 amdgpu_dm_irq_resume_early(adev); 2852 2853 for (i = 0; i < dc_state->stream_count; i++) { 2854 dc_state->streams[i]->mode_changed = true; 2855 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) { 2856 dc_state->stream_status[i].plane_states[j]->update_flags.raw 2857 = 0xffffffff; 2858 } 2859 } 2860 2861 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 2862 amdgpu_dm_outbox_init(adev); 2863 dc_enable_dmub_outbox(adev->dm.dc); 2864 } 2865 2866 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count)); 2867 2868 dm_gpureset_commit_state(dm->cached_dc_state, dm); 2869 2870 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true); 2871 2872 dc_release_state(dm->cached_dc_state); 2873 dm->cached_dc_state = NULL; 2874 2875 amdgpu_dm_irq_resume_late(adev); 2876 2877 mutex_unlock(&dm->dc_lock); 2878 2879 return 0; 2880 } 2881 /* Recreate dc_state - DC invalidates it when setting power state to S3. */ 2882 dc_release_state(dm_state->context); 2883 dm_state->context = dc_create_state(dm->dc); 2884 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ 2885 dc_resource_state_construct(dm->dc, dm_state->context); 2886 2887 /* Before powering on DC we need to re-initialize DMUB. */ 2888 dm_dmub_hw_resume(adev); 2889 2890 /* Re-enable outbox interrupts for DPIA. */ 2891 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 2892 amdgpu_dm_outbox_init(adev); 2893 dc_enable_dmub_outbox(adev->dm.dc); 2894 } 2895 2896 /* power on hardware */ 2897 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 2898 2899 /* program HPD filter */ 2900 dc_resume(dm->dc); 2901 2902 /* 2903 * early enable HPD Rx IRQ, should be done before set mode as short 2904 * pulse interrupts are used for MST 2905 */ 2906 amdgpu_dm_irq_resume_early(adev); 2907 2908 /* On resume we need to rewrite the MSTM control bits to enable MST*/ 2909 s3_handle_mst(ddev, false); 2910 2911 /* Do detection*/ 2912 drm_connector_list_iter_begin(ddev, &iter); 2913 drm_for_each_connector_iter(connector, &iter) { 2914 aconnector = to_amdgpu_dm_connector(connector); 2915 2916 if (!aconnector->dc_link) 2917 continue; 2918 2919 /* 2920 * this is the case when traversing through already created end sink 2921 * MST connectors, should be skipped 2922 */ 2923 if (aconnector && aconnector->mst_root) 2924 continue; 2925 2926 mutex_lock(&aconnector->hpd_lock); 2927 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) 2928 DRM_ERROR("KMS: Failed to detect connector\n"); 2929 2930 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2931 emulated_link_detect(aconnector->dc_link); 2932 } else { 2933 mutex_lock(&dm->dc_lock); 2934 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 2935 mutex_unlock(&dm->dc_lock); 2936 } 2937 2938 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 2939 aconnector->fake_enable = false; 2940 2941 if (aconnector->dc_sink) 2942 dc_sink_release(aconnector->dc_sink); 2943 aconnector->dc_sink = NULL; 2944 amdgpu_dm_update_connector_after_detect(aconnector); 2945 mutex_unlock(&aconnector->hpd_lock); 2946 } 2947 drm_connector_list_iter_end(&iter); 2948 2949 /* Force mode set in atomic commit */ 2950 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) 2951 new_crtc_state->active_changed = true; 2952 2953 /* 2954 * atomic_check is expected to create the dc states. We need to release 2955 * them here, since they were duplicated as part of the suspend 2956 * procedure. 2957 */ 2958 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 2959 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 2960 if (dm_new_crtc_state->stream) { 2961 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 2962 dc_stream_release(dm_new_crtc_state->stream); 2963 dm_new_crtc_state->stream = NULL; 2964 } 2965 } 2966 2967 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 2968 dm_new_plane_state = to_dm_plane_state(new_plane_state); 2969 if (dm_new_plane_state->dc_state) { 2970 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 2971 dc_plane_state_release(dm_new_plane_state->dc_state); 2972 dm_new_plane_state->dc_state = NULL; 2973 } 2974 } 2975 2976 drm_atomic_helper_resume(ddev, dm->cached_state); 2977 2978 dm->cached_state = NULL; 2979 2980 /* Do mst topology probing after resuming cached state*/ 2981 drm_connector_list_iter_begin(ddev, &iter); 2982 drm_for_each_connector_iter(connector, &iter) { 2983 aconnector = to_amdgpu_dm_connector(connector); 2984 if (aconnector->dc_link->type != dc_connection_mst_branch || 2985 aconnector->mst_root) 2986 continue; 2987 2988 ret = drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr, true); 2989 2990 if (ret < 0) { 2991 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, 2992 aconnector->dc_link); 2993 need_hotplug = true; 2994 } 2995 } 2996 drm_connector_list_iter_end(&iter); 2997 2998 if (need_hotplug) 2999 drm_kms_helper_hotplug_event(ddev); 3000 3001 amdgpu_dm_irq_resume_late(adev); 3002 3003 amdgpu_dm_smu_write_watermarks_table(adev); 3004 3005 return 0; 3006 } 3007 3008 /** 3009 * DOC: DM Lifecycle 3010 * 3011 * DM (and consequently DC) is registered in the amdgpu base driver as a IP 3012 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to 3013 * the base driver's device list to be initialized and torn down accordingly. 3014 * 3015 * The functions to do so are provided as hooks in &struct amd_ip_funcs. 3016 */ 3017 3018 static const struct amd_ip_funcs amdgpu_dm_funcs = { 3019 .name = "dm", 3020 .early_init = dm_early_init, 3021 .late_init = dm_late_init, 3022 .sw_init = dm_sw_init, 3023 .sw_fini = dm_sw_fini, 3024 .early_fini = amdgpu_dm_early_fini, 3025 .hw_init = dm_hw_init, 3026 .hw_fini = dm_hw_fini, 3027 .suspend = dm_suspend, 3028 .resume = dm_resume, 3029 .is_idle = dm_is_idle, 3030 .wait_for_idle = dm_wait_for_idle, 3031 .check_soft_reset = dm_check_soft_reset, 3032 .soft_reset = dm_soft_reset, 3033 .set_clockgating_state = dm_set_clockgating_state, 3034 .set_powergating_state = dm_set_powergating_state, 3035 }; 3036 3037 const struct amdgpu_ip_block_version dm_ip_block = { 3038 .type = AMD_IP_BLOCK_TYPE_DCE, 3039 .major = 1, 3040 .minor = 0, 3041 .rev = 0, 3042 .funcs = &amdgpu_dm_funcs, 3043 }; 3044 3045 3046 /** 3047 * DOC: atomic 3048 * 3049 * *WIP* 3050 */ 3051 3052 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 3053 .fb_create = amdgpu_display_user_framebuffer_create, 3054 .get_format_info = amdgpu_dm_plane_get_format_info, 3055 .atomic_check = amdgpu_dm_atomic_check, 3056 .atomic_commit = drm_atomic_helper_commit, 3057 }; 3058 3059 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 3060 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, 3061 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, 3062 }; 3063 3064 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) 3065 { 3066 struct amdgpu_dm_backlight_caps *caps; 3067 struct drm_connector *conn_base; 3068 struct amdgpu_device *adev; 3069 struct drm_luminance_range_info *luminance_range; 3070 3071 if (aconnector->bl_idx == -1 || 3072 aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP) 3073 return; 3074 3075 conn_base = &aconnector->base; 3076 adev = drm_to_adev(conn_base->dev); 3077 3078 caps = &adev->dm.backlight_caps[aconnector->bl_idx]; 3079 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps; 3080 caps->aux_support = false; 3081 3082 if (caps->ext_caps->bits.oled == 1 3083 /* 3084 * || 3085 * caps->ext_caps->bits.sdr_aux_backlight_control == 1 || 3086 * caps->ext_caps->bits.hdr_aux_backlight_control == 1 3087 */) 3088 caps->aux_support = true; 3089 3090 if (amdgpu_backlight == 0) 3091 caps->aux_support = false; 3092 else if (amdgpu_backlight == 1) 3093 caps->aux_support = true; 3094 3095 luminance_range = &conn_base->display_info.luminance_range; 3096 3097 if (luminance_range->max_luminance) { 3098 caps->aux_min_input_signal = luminance_range->min_luminance; 3099 caps->aux_max_input_signal = luminance_range->max_luminance; 3100 } else { 3101 caps->aux_min_input_signal = 0; 3102 caps->aux_max_input_signal = 512; 3103 } 3104 } 3105 3106 void amdgpu_dm_update_connector_after_detect( 3107 struct amdgpu_dm_connector *aconnector) 3108 { 3109 struct drm_connector *connector = &aconnector->base; 3110 struct drm_device *dev = connector->dev; 3111 struct dc_sink *sink; 3112 3113 /* MST handled by drm_mst framework */ 3114 if (aconnector->mst_mgr.mst_state == true) 3115 return; 3116 3117 sink = aconnector->dc_link->local_sink; 3118 if (sink) 3119 dc_sink_retain(sink); 3120 3121 /* 3122 * Edid mgmt connector gets first update only in mode_valid hook and then 3123 * the connector sink is set to either fake or physical sink depends on link status. 3124 * Skip if already done during boot. 3125 */ 3126 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED 3127 && aconnector->dc_em_sink) { 3128 3129 /* 3130 * For S3 resume with headless use eml_sink to fake stream 3131 * because on resume connector->sink is set to NULL 3132 */ 3133 mutex_lock(&dev->mode_config.mutex); 3134 3135 if (sink) { 3136 if (aconnector->dc_sink) { 3137 amdgpu_dm_update_freesync_caps(connector, NULL); 3138 /* 3139 * retain and release below are used to 3140 * bump up refcount for sink because the link doesn't point 3141 * to it anymore after disconnect, so on next crtc to connector 3142 * reshuffle by UMD we will get into unwanted dc_sink release 3143 */ 3144 dc_sink_release(aconnector->dc_sink); 3145 } 3146 aconnector->dc_sink = sink; 3147 dc_sink_retain(aconnector->dc_sink); 3148 amdgpu_dm_update_freesync_caps(connector, 3149 aconnector->edid); 3150 } else { 3151 amdgpu_dm_update_freesync_caps(connector, NULL); 3152 if (!aconnector->dc_sink) { 3153 aconnector->dc_sink = aconnector->dc_em_sink; 3154 dc_sink_retain(aconnector->dc_sink); 3155 } 3156 } 3157 3158 mutex_unlock(&dev->mode_config.mutex); 3159 3160 if (sink) 3161 dc_sink_release(sink); 3162 return; 3163 } 3164 3165 /* 3166 * TODO: temporary guard to look for proper fix 3167 * if this sink is MST sink, we should not do anything 3168 */ 3169 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 3170 dc_sink_release(sink); 3171 return; 3172 } 3173 3174 if (aconnector->dc_sink == sink) { 3175 /* 3176 * We got a DP short pulse (Link Loss, DP CTS, etc...). 3177 * Do nothing!! 3178 */ 3179 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n", 3180 aconnector->connector_id); 3181 if (sink) 3182 dc_sink_release(sink); 3183 return; 3184 } 3185 3186 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", 3187 aconnector->connector_id, aconnector->dc_sink, sink); 3188 3189 mutex_lock(&dev->mode_config.mutex); 3190 3191 /* 3192 * 1. Update status of the drm connector 3193 * 2. Send an event and let userspace tell us what to do 3194 */ 3195 if (sink) { 3196 /* 3197 * TODO: check if we still need the S3 mode update workaround. 3198 * If yes, put it here. 3199 */ 3200 if (aconnector->dc_sink) { 3201 amdgpu_dm_update_freesync_caps(connector, NULL); 3202 dc_sink_release(aconnector->dc_sink); 3203 } 3204 3205 aconnector->dc_sink = sink; 3206 dc_sink_retain(aconnector->dc_sink); 3207 if (sink->dc_edid.length == 0) { 3208 aconnector->edid = NULL; 3209 if (aconnector->dc_link->aux_mode) { 3210 drm_dp_cec_unset_edid( 3211 &aconnector->dm_dp_aux.aux); 3212 } 3213 } else { 3214 aconnector->edid = 3215 (struct edid *)sink->dc_edid.raw_edid; 3216 3217 if (aconnector->dc_link->aux_mode) 3218 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, 3219 aconnector->edid); 3220 } 3221 3222 if (!aconnector->timing_requested) { 3223 aconnector->timing_requested = 3224 kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL); 3225 if (!aconnector->timing_requested) 3226 dm_error("failed to create aconnector->requested_timing\n"); 3227 } 3228 3229 drm_connector_update_edid_property(connector, aconnector->edid); 3230 amdgpu_dm_update_freesync_caps(connector, aconnector->edid); 3231 update_connector_ext_caps(aconnector); 3232 } else { 3233 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 3234 amdgpu_dm_update_freesync_caps(connector, NULL); 3235 drm_connector_update_edid_property(connector, NULL); 3236 aconnector->num_modes = 0; 3237 dc_sink_release(aconnector->dc_sink); 3238 aconnector->dc_sink = NULL; 3239 aconnector->edid = NULL; 3240 kfree(aconnector->timing_requested); 3241 aconnector->timing_requested = NULL; 3242 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */ 3243 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 3244 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3245 } 3246 3247 mutex_unlock(&dev->mode_config.mutex); 3248 3249 update_subconnector_property(aconnector); 3250 3251 if (sink) 3252 dc_sink_release(sink); 3253 } 3254 3255 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) 3256 { 3257 struct drm_connector *connector = &aconnector->base; 3258 struct drm_device *dev = connector->dev; 3259 enum dc_connection_type new_connection_type = dc_connection_none; 3260 struct amdgpu_device *adev = drm_to_adev(dev); 3261 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 3262 bool ret = false; 3263 3264 if (adev->dm.disable_hpd_irq) 3265 return; 3266 3267 /* 3268 * In case of failure or MST no need to update connector status or notify the OS 3269 * since (for MST case) MST does this in its own context. 3270 */ 3271 mutex_lock(&aconnector->hpd_lock); 3272 3273 if (adev->dm.hdcp_workqueue) { 3274 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 3275 dm_con_state->update_hdcp = true; 3276 } 3277 if (aconnector->fake_enable) 3278 aconnector->fake_enable = false; 3279 3280 aconnector->timing_changed = false; 3281 3282 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) 3283 DRM_ERROR("KMS: Failed to detect connector\n"); 3284 3285 if (aconnector->base.force && new_connection_type == dc_connection_none) { 3286 emulated_link_detect(aconnector->dc_link); 3287 3288 drm_modeset_lock_all(dev); 3289 dm_restore_drm_connector_state(dev, connector); 3290 drm_modeset_unlock_all(dev); 3291 3292 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 3293 drm_kms_helper_connector_hotplug_event(connector); 3294 } else { 3295 mutex_lock(&adev->dm.dc_lock); 3296 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 3297 mutex_unlock(&adev->dm.dc_lock); 3298 if (ret) { 3299 amdgpu_dm_update_connector_after_detect(aconnector); 3300 3301 drm_modeset_lock_all(dev); 3302 dm_restore_drm_connector_state(dev, connector); 3303 drm_modeset_unlock_all(dev); 3304 3305 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 3306 drm_kms_helper_connector_hotplug_event(connector); 3307 } 3308 } 3309 mutex_unlock(&aconnector->hpd_lock); 3310 3311 } 3312 3313 static void handle_hpd_irq(void *param) 3314 { 3315 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 3316 3317 handle_hpd_irq_helper(aconnector); 3318 3319 } 3320 3321 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq, 3322 union hpd_irq_data hpd_irq_data) 3323 { 3324 struct hpd_rx_irq_offload_work *offload_work = 3325 kzalloc(sizeof(*offload_work), GFP_KERNEL); 3326 3327 if (!offload_work) { 3328 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n"); 3329 return; 3330 } 3331 3332 INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work); 3333 offload_work->data = hpd_irq_data; 3334 offload_work->offload_wq = offload_wq; 3335 3336 queue_work(offload_wq->wq, &offload_work->work); 3337 DRM_DEBUG_KMS("queue work to handle hpd_rx offload work"); 3338 } 3339 3340 static void handle_hpd_rx_irq(void *param) 3341 { 3342 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 3343 struct drm_connector *connector = &aconnector->base; 3344 struct drm_device *dev = connector->dev; 3345 struct dc_link *dc_link = aconnector->dc_link; 3346 bool is_mst_root_connector = aconnector->mst_mgr.mst_state; 3347 bool result = false; 3348 enum dc_connection_type new_connection_type = dc_connection_none; 3349 struct amdgpu_device *adev = drm_to_adev(dev); 3350 union hpd_irq_data hpd_irq_data; 3351 bool link_loss = false; 3352 bool has_left_work = false; 3353 int idx = dc_link->link_index; 3354 struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx]; 3355 3356 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data)); 3357 3358 if (adev->dm.disable_hpd_irq) 3359 return; 3360 3361 /* 3362 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio 3363 * conflict, after implement i2c helper, this mutex should be 3364 * retired. 3365 */ 3366 mutex_lock(&aconnector->hpd_lock); 3367 3368 result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, 3369 &link_loss, true, &has_left_work); 3370 3371 if (!has_left_work) 3372 goto out; 3373 3374 if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) { 3375 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); 3376 goto out; 3377 } 3378 3379 if (dc_link_dp_allow_hpd_rx_irq(dc_link)) { 3380 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || 3381 hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { 3382 bool skip = false; 3383 3384 /* 3385 * DOWN_REP_MSG_RDY is also handled by polling method 3386 * mgr->cbs->poll_hpd_irq() 3387 */ 3388 spin_lock(&offload_wq->offload_lock); 3389 skip = offload_wq->is_handling_mst_msg_rdy_event; 3390 3391 if (!skip) 3392 offload_wq->is_handling_mst_msg_rdy_event = true; 3393 3394 spin_unlock(&offload_wq->offload_lock); 3395 3396 if (!skip) 3397 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); 3398 3399 goto out; 3400 } 3401 3402 if (link_loss) { 3403 bool skip = false; 3404 3405 spin_lock(&offload_wq->offload_lock); 3406 skip = offload_wq->is_handling_link_loss; 3407 3408 if (!skip) 3409 offload_wq->is_handling_link_loss = true; 3410 3411 spin_unlock(&offload_wq->offload_lock); 3412 3413 if (!skip) 3414 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); 3415 3416 goto out; 3417 } 3418 } 3419 3420 out: 3421 if (result && !is_mst_root_connector) { 3422 /* Downstream Port status changed. */ 3423 if (!dc_link_detect_connection_type(dc_link, &new_connection_type)) 3424 DRM_ERROR("KMS: Failed to detect connector\n"); 3425 3426 if (aconnector->base.force && new_connection_type == dc_connection_none) { 3427 emulated_link_detect(dc_link); 3428 3429 if (aconnector->fake_enable) 3430 aconnector->fake_enable = false; 3431 3432 amdgpu_dm_update_connector_after_detect(aconnector); 3433 3434 3435 drm_modeset_lock_all(dev); 3436 dm_restore_drm_connector_state(dev, connector); 3437 drm_modeset_unlock_all(dev); 3438 3439 drm_kms_helper_connector_hotplug_event(connector); 3440 } else { 3441 bool ret = false; 3442 3443 mutex_lock(&adev->dm.dc_lock); 3444 ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX); 3445 mutex_unlock(&adev->dm.dc_lock); 3446 3447 if (ret) { 3448 if (aconnector->fake_enable) 3449 aconnector->fake_enable = false; 3450 3451 amdgpu_dm_update_connector_after_detect(aconnector); 3452 3453 drm_modeset_lock_all(dev); 3454 dm_restore_drm_connector_state(dev, connector); 3455 drm_modeset_unlock_all(dev); 3456 3457 drm_kms_helper_connector_hotplug_event(connector); 3458 } 3459 } 3460 } 3461 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) { 3462 if (adev->dm.hdcp_workqueue) 3463 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index); 3464 } 3465 3466 if (dc_link->type != dc_connection_mst_branch) 3467 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); 3468 3469 mutex_unlock(&aconnector->hpd_lock); 3470 } 3471 3472 static void register_hpd_handlers(struct amdgpu_device *adev) 3473 { 3474 struct drm_device *dev = adev_to_drm(adev); 3475 struct drm_connector *connector; 3476 struct amdgpu_dm_connector *aconnector; 3477 const struct dc_link *dc_link; 3478 struct dc_interrupt_params int_params = {0}; 3479 3480 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3481 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3482 3483 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 3484 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) 3485 DRM_ERROR("amdgpu: fail to register dmub hpd callback"); 3486 3487 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) 3488 DRM_ERROR("amdgpu: fail to register dmub hpd callback"); 3489 } 3490 3491 list_for_each_entry(connector, 3492 &dev->mode_config.connector_list, head) { 3493 3494 aconnector = to_amdgpu_dm_connector(connector); 3495 dc_link = aconnector->dc_link; 3496 3497 if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) { 3498 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 3499 int_params.irq_source = dc_link->irq_source_hpd; 3500 3501 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3502 handle_hpd_irq, 3503 (void *) aconnector); 3504 } 3505 3506 if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) { 3507 3508 /* Also register for DP short pulse (hpd_rx). */ 3509 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 3510 int_params.irq_source = dc_link->irq_source_hpd_rx; 3511 3512 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3513 handle_hpd_rx_irq, 3514 (void *) aconnector); 3515 } 3516 } 3517 } 3518 3519 #if defined(CONFIG_DRM_AMD_DC_SI) 3520 /* Register IRQ sources and initialize IRQ callbacks */ 3521 static int dce60_register_irq_handlers(struct amdgpu_device *adev) 3522 { 3523 struct dc *dc = adev->dm.dc; 3524 struct common_irq_params *c_irq_params; 3525 struct dc_interrupt_params int_params = {0}; 3526 int r; 3527 int i; 3528 unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3529 3530 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3531 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3532 3533 /* 3534 * Actions of amdgpu_irq_add_id(): 3535 * 1. Register a set() function with base driver. 3536 * Base driver will call set() function to enable/disable an 3537 * interrupt in DC hardware. 3538 * 2. Register amdgpu_dm_irq_handler(). 3539 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3540 * coming from DC hardware. 3541 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3542 * for acknowledging and handling. 3543 */ 3544 3545 /* Use VBLANK interrupt */ 3546 for (i = 0; i < adev->mode_info.num_crtc; i++) { 3547 r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq); 3548 if (r) { 3549 DRM_ERROR("Failed to add crtc irq id!\n"); 3550 return r; 3551 } 3552 3553 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3554 int_params.irq_source = 3555 dc_interrupt_to_irq_source(dc, i + 1, 0); 3556 3557 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3558 3559 c_irq_params->adev = adev; 3560 c_irq_params->irq_src = int_params.irq_source; 3561 3562 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3563 dm_crtc_high_irq, c_irq_params); 3564 } 3565 3566 /* Use GRPH_PFLIP interrupt */ 3567 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 3568 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 3569 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 3570 if (r) { 3571 DRM_ERROR("Failed to add page flip irq id!\n"); 3572 return r; 3573 } 3574 3575 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3576 int_params.irq_source = 3577 dc_interrupt_to_irq_source(dc, i, 0); 3578 3579 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 3580 3581 c_irq_params->adev = adev; 3582 c_irq_params->irq_src = int_params.irq_source; 3583 3584 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3585 dm_pflip_high_irq, c_irq_params); 3586 3587 } 3588 3589 /* HPD */ 3590 r = amdgpu_irq_add_id(adev, client_id, 3591 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 3592 if (r) { 3593 DRM_ERROR("Failed to add hpd irq id!\n"); 3594 return r; 3595 } 3596 3597 register_hpd_handlers(adev); 3598 3599 return 0; 3600 } 3601 #endif 3602 3603 /* Register IRQ sources and initialize IRQ callbacks */ 3604 static int dce110_register_irq_handlers(struct amdgpu_device *adev) 3605 { 3606 struct dc *dc = adev->dm.dc; 3607 struct common_irq_params *c_irq_params; 3608 struct dc_interrupt_params int_params = {0}; 3609 int r; 3610 int i; 3611 unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3612 3613 if (adev->family >= AMDGPU_FAMILY_AI) 3614 client_id = SOC15_IH_CLIENTID_DCE; 3615 3616 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3617 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3618 3619 /* 3620 * Actions of amdgpu_irq_add_id(): 3621 * 1. Register a set() function with base driver. 3622 * Base driver will call set() function to enable/disable an 3623 * interrupt in DC hardware. 3624 * 2. Register amdgpu_dm_irq_handler(). 3625 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3626 * coming from DC hardware. 3627 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3628 * for acknowledging and handling. 3629 */ 3630 3631 /* Use VBLANK interrupt */ 3632 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { 3633 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); 3634 if (r) { 3635 DRM_ERROR("Failed to add crtc irq id!\n"); 3636 return r; 3637 } 3638 3639 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3640 int_params.irq_source = 3641 dc_interrupt_to_irq_source(dc, i, 0); 3642 3643 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3644 3645 c_irq_params->adev = adev; 3646 c_irq_params->irq_src = int_params.irq_source; 3647 3648 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3649 dm_crtc_high_irq, c_irq_params); 3650 } 3651 3652 /* Use VUPDATE interrupt */ 3653 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { 3654 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq); 3655 if (r) { 3656 DRM_ERROR("Failed to add vupdate irq id!\n"); 3657 return r; 3658 } 3659 3660 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3661 int_params.irq_source = 3662 dc_interrupt_to_irq_source(dc, i, 0); 3663 3664 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 3665 3666 c_irq_params->adev = adev; 3667 c_irq_params->irq_src = int_params.irq_source; 3668 3669 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3670 dm_vupdate_high_irq, c_irq_params); 3671 } 3672 3673 /* Use GRPH_PFLIP interrupt */ 3674 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 3675 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 3676 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 3677 if (r) { 3678 DRM_ERROR("Failed to add page flip irq id!\n"); 3679 return r; 3680 } 3681 3682 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3683 int_params.irq_source = 3684 dc_interrupt_to_irq_source(dc, i, 0); 3685 3686 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 3687 3688 c_irq_params->adev = adev; 3689 c_irq_params->irq_src = int_params.irq_source; 3690 3691 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3692 dm_pflip_high_irq, c_irq_params); 3693 3694 } 3695 3696 /* HPD */ 3697 r = amdgpu_irq_add_id(adev, client_id, 3698 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 3699 if (r) { 3700 DRM_ERROR("Failed to add hpd irq id!\n"); 3701 return r; 3702 } 3703 3704 register_hpd_handlers(adev); 3705 3706 return 0; 3707 } 3708 3709 /* Register IRQ sources and initialize IRQ callbacks */ 3710 static int dcn10_register_irq_handlers(struct amdgpu_device *adev) 3711 { 3712 struct dc *dc = adev->dm.dc; 3713 struct common_irq_params *c_irq_params; 3714 struct dc_interrupt_params int_params = {0}; 3715 int r; 3716 int i; 3717 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3718 static const unsigned int vrtl_int_srcid[] = { 3719 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL, 3720 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL, 3721 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL, 3722 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL, 3723 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL, 3724 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL 3725 }; 3726 #endif 3727 3728 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3729 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3730 3731 /* 3732 * Actions of amdgpu_irq_add_id(): 3733 * 1. Register a set() function with base driver. 3734 * Base driver will call set() function to enable/disable an 3735 * interrupt in DC hardware. 3736 * 2. Register amdgpu_dm_irq_handler(). 3737 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3738 * coming from DC hardware. 3739 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3740 * for acknowledging and handling. 3741 */ 3742 3743 /* Use VSTARTUP interrupt */ 3744 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; 3745 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; 3746 i++) { 3747 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); 3748 3749 if (r) { 3750 DRM_ERROR("Failed to add crtc irq id!\n"); 3751 return r; 3752 } 3753 3754 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3755 int_params.irq_source = 3756 dc_interrupt_to_irq_source(dc, i, 0); 3757 3758 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3759 3760 c_irq_params->adev = adev; 3761 c_irq_params->irq_src = int_params.irq_source; 3762 3763 amdgpu_dm_irq_register_interrupt( 3764 adev, &int_params, dm_crtc_high_irq, c_irq_params); 3765 } 3766 3767 /* Use otg vertical line interrupt */ 3768 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3769 for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) { 3770 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, 3771 vrtl_int_srcid[i], &adev->vline0_irq); 3772 3773 if (r) { 3774 DRM_ERROR("Failed to add vline0 irq id!\n"); 3775 return r; 3776 } 3777 3778 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3779 int_params.irq_source = 3780 dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0); 3781 3782 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) { 3783 DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]); 3784 break; 3785 } 3786 3787 c_irq_params = &adev->dm.vline0_params[int_params.irq_source 3788 - DC_IRQ_SOURCE_DC1_VLINE0]; 3789 3790 c_irq_params->adev = adev; 3791 c_irq_params->irq_src = int_params.irq_source; 3792 3793 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3794 dm_dcn_vertical_interrupt0_high_irq, c_irq_params); 3795 } 3796 #endif 3797 3798 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to 3799 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx 3800 * to trigger at end of each vblank, regardless of state of the lock, 3801 * matching DCE behaviour. 3802 */ 3803 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT; 3804 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1; 3805 i++) { 3806 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq); 3807 3808 if (r) { 3809 DRM_ERROR("Failed to add vupdate irq id!\n"); 3810 return r; 3811 } 3812 3813 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3814 int_params.irq_source = 3815 dc_interrupt_to_irq_source(dc, i, 0); 3816 3817 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 3818 3819 c_irq_params->adev = adev; 3820 c_irq_params->irq_src = int_params.irq_source; 3821 3822 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3823 dm_vupdate_high_irq, c_irq_params); 3824 } 3825 3826 /* Use GRPH_PFLIP interrupt */ 3827 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; 3828 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1; 3829 i++) { 3830 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); 3831 if (r) { 3832 DRM_ERROR("Failed to add page flip irq id!\n"); 3833 return r; 3834 } 3835 3836 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3837 int_params.irq_source = 3838 dc_interrupt_to_irq_source(dc, i, 0); 3839 3840 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 3841 3842 c_irq_params->adev = adev; 3843 c_irq_params->irq_src = int_params.irq_source; 3844 3845 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3846 dm_pflip_high_irq, c_irq_params); 3847 3848 } 3849 3850 /* HPD */ 3851 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, 3852 &adev->hpd_irq); 3853 if (r) { 3854 DRM_ERROR("Failed to add hpd irq id!\n"); 3855 return r; 3856 } 3857 3858 register_hpd_handlers(adev); 3859 3860 return 0; 3861 } 3862 /* Register Outbox IRQ sources and initialize IRQ callbacks */ 3863 static int register_outbox_irq_handlers(struct amdgpu_device *adev) 3864 { 3865 struct dc *dc = adev->dm.dc; 3866 struct common_irq_params *c_irq_params; 3867 struct dc_interrupt_params int_params = {0}; 3868 int r, i; 3869 3870 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3871 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3872 3873 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT, 3874 &adev->dmub_outbox_irq); 3875 if (r) { 3876 DRM_ERROR("Failed to add outbox irq id!\n"); 3877 return r; 3878 } 3879 3880 if (dc->ctx->dmub_srv) { 3881 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT; 3882 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 3883 int_params.irq_source = 3884 dc_interrupt_to_irq_source(dc, i, 0); 3885 3886 c_irq_params = &adev->dm.dmub_outbox_params[0]; 3887 3888 c_irq_params->adev = adev; 3889 c_irq_params->irq_src = int_params.irq_source; 3890 3891 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3892 dm_dmub_outbox1_low_irq, c_irq_params); 3893 } 3894 3895 return 0; 3896 } 3897 3898 /* 3899 * Acquires the lock for the atomic state object and returns 3900 * the new atomic state. 3901 * 3902 * This should only be called during atomic check. 3903 */ 3904 int dm_atomic_get_state(struct drm_atomic_state *state, 3905 struct dm_atomic_state **dm_state) 3906 { 3907 struct drm_device *dev = state->dev; 3908 struct amdgpu_device *adev = drm_to_adev(dev); 3909 struct amdgpu_display_manager *dm = &adev->dm; 3910 struct drm_private_state *priv_state; 3911 3912 if (*dm_state) 3913 return 0; 3914 3915 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); 3916 if (IS_ERR(priv_state)) 3917 return PTR_ERR(priv_state); 3918 3919 *dm_state = to_dm_atomic_state(priv_state); 3920 3921 return 0; 3922 } 3923 3924 static struct dm_atomic_state * 3925 dm_atomic_get_new_state(struct drm_atomic_state *state) 3926 { 3927 struct drm_device *dev = state->dev; 3928 struct amdgpu_device *adev = drm_to_adev(dev); 3929 struct amdgpu_display_manager *dm = &adev->dm; 3930 struct drm_private_obj *obj; 3931 struct drm_private_state *new_obj_state; 3932 int i; 3933 3934 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { 3935 if (obj->funcs == dm->atomic_obj.funcs) 3936 return to_dm_atomic_state(new_obj_state); 3937 } 3938 3939 return NULL; 3940 } 3941 3942 static struct drm_private_state * 3943 dm_atomic_duplicate_state(struct drm_private_obj *obj) 3944 { 3945 struct dm_atomic_state *old_state, *new_state; 3946 3947 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 3948 if (!new_state) 3949 return NULL; 3950 3951 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); 3952 3953 old_state = to_dm_atomic_state(obj->state); 3954 3955 if (old_state && old_state->context) 3956 new_state->context = dc_copy_state(old_state->context); 3957 3958 if (!new_state->context) { 3959 kfree(new_state); 3960 return NULL; 3961 } 3962 3963 return &new_state->base; 3964 } 3965 3966 static void dm_atomic_destroy_state(struct drm_private_obj *obj, 3967 struct drm_private_state *state) 3968 { 3969 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 3970 3971 if (dm_state && dm_state->context) 3972 dc_release_state(dm_state->context); 3973 3974 kfree(dm_state); 3975 } 3976 3977 static struct drm_private_state_funcs dm_atomic_state_funcs = { 3978 .atomic_duplicate_state = dm_atomic_duplicate_state, 3979 .atomic_destroy_state = dm_atomic_destroy_state, 3980 }; 3981 3982 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 3983 { 3984 struct dm_atomic_state *state; 3985 int r; 3986 3987 adev->mode_info.mode_config_initialized = true; 3988 3989 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; 3990 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 3991 3992 adev_to_drm(adev)->mode_config.max_width = 16384; 3993 adev_to_drm(adev)->mode_config.max_height = 16384; 3994 3995 adev_to_drm(adev)->mode_config.preferred_depth = 24; 3996 if (adev->asic_type == CHIP_HAWAII) 3997 /* disable prefer shadow for now due to hibernation issues */ 3998 adev_to_drm(adev)->mode_config.prefer_shadow = 0; 3999 else 4000 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 4001 /* indicates support for immediate flip */ 4002 adev_to_drm(adev)->mode_config.async_page_flip = true; 4003 4004 state = kzalloc(sizeof(*state), GFP_KERNEL); 4005 if (!state) 4006 return -ENOMEM; 4007 4008 state->context = dc_create_state(adev->dm.dc); 4009 if (!state->context) { 4010 kfree(state); 4011 return -ENOMEM; 4012 } 4013 4014 dc_resource_state_copy_construct_current(adev->dm.dc, state->context); 4015 4016 drm_atomic_private_obj_init(adev_to_drm(adev), 4017 &adev->dm.atomic_obj, 4018 &state->base, 4019 &dm_atomic_state_funcs); 4020 4021 r = amdgpu_display_modeset_create_props(adev); 4022 if (r) { 4023 dc_release_state(state->context); 4024 kfree(state); 4025 return r; 4026 } 4027 4028 r = amdgpu_dm_audio_init(adev); 4029 if (r) { 4030 dc_release_state(state->context); 4031 kfree(state); 4032 return r; 4033 } 4034 4035 return 0; 4036 } 4037 4038 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 4039 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 4040 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50 4041 4042 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, 4043 int bl_idx) 4044 { 4045 #if defined(CONFIG_ACPI) 4046 struct amdgpu_dm_backlight_caps caps; 4047 4048 memset(&caps, 0, sizeof(caps)); 4049 4050 if (dm->backlight_caps[bl_idx].caps_valid) 4051 return; 4052 4053 amdgpu_acpi_get_backlight_caps(&caps); 4054 if (caps.caps_valid) { 4055 dm->backlight_caps[bl_idx].caps_valid = true; 4056 if (caps.aux_support) 4057 return; 4058 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal; 4059 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal; 4060 } else { 4061 dm->backlight_caps[bl_idx].min_input_signal = 4062 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 4063 dm->backlight_caps[bl_idx].max_input_signal = 4064 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 4065 } 4066 #else 4067 if (dm->backlight_caps[bl_idx].aux_support) 4068 return; 4069 4070 dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 4071 dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 4072 #endif 4073 } 4074 4075 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, 4076 unsigned int *min, unsigned int *max) 4077 { 4078 if (!caps) 4079 return 0; 4080 4081 if (caps->aux_support) { 4082 // Firmware limits are in nits, DC API wants millinits. 4083 *max = 1000 * caps->aux_max_input_signal; 4084 *min = 1000 * caps->aux_min_input_signal; 4085 } else { 4086 // Firmware limits are 8-bit, PWM control is 16-bit. 4087 *max = 0x101 * caps->max_input_signal; 4088 *min = 0x101 * caps->min_input_signal; 4089 } 4090 return 1; 4091 } 4092 4093 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps, 4094 uint32_t brightness) 4095 { 4096 unsigned int min, max; 4097 4098 if (!get_brightness_range(caps, &min, &max)) 4099 return brightness; 4100 4101 // Rescale 0..255 to min..max 4102 return min + DIV_ROUND_CLOSEST((max - min) * brightness, 4103 AMDGPU_MAX_BL_LEVEL); 4104 } 4105 4106 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps, 4107 uint32_t brightness) 4108 { 4109 unsigned int min, max; 4110 4111 if (!get_brightness_range(caps, &min, &max)) 4112 return brightness; 4113 4114 if (brightness < min) 4115 return 0; 4116 // Rescale min..max to 0..255 4117 return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min), 4118 max - min); 4119 } 4120 4121 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, 4122 int bl_idx, 4123 u32 user_brightness) 4124 { 4125 struct amdgpu_dm_backlight_caps caps; 4126 struct dc_link *link; 4127 u32 brightness; 4128 bool rc; 4129 4130 amdgpu_dm_update_backlight_caps(dm, bl_idx); 4131 caps = dm->backlight_caps[bl_idx]; 4132 4133 dm->brightness[bl_idx] = user_brightness; 4134 /* update scratch register */ 4135 if (bl_idx == 0) 4136 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]); 4137 brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]); 4138 link = (struct dc_link *)dm->backlight_link[bl_idx]; 4139 4140 /* Change brightness based on AUX property */ 4141 if (caps.aux_support) { 4142 rc = dc_link_set_backlight_level_nits(link, true, brightness, 4143 AUX_BL_DEFAULT_TRANSITION_TIME_MS); 4144 if (!rc) 4145 DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx); 4146 } else { 4147 rc = dc_link_set_backlight_level(link, brightness, 0); 4148 if (!rc) 4149 DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx); 4150 } 4151 4152 if (rc) 4153 dm->actual_brightness[bl_idx] = user_brightness; 4154 } 4155 4156 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) 4157 { 4158 struct amdgpu_display_manager *dm = bl_get_data(bd); 4159 int i; 4160 4161 for (i = 0; i < dm->num_of_edps; i++) { 4162 if (bd == dm->backlight_dev[i]) 4163 break; 4164 } 4165 if (i >= AMDGPU_DM_MAX_NUM_EDP) 4166 i = 0; 4167 amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness); 4168 4169 return 0; 4170 } 4171 4172 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm, 4173 int bl_idx) 4174 { 4175 int ret; 4176 struct amdgpu_dm_backlight_caps caps; 4177 struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx]; 4178 4179 amdgpu_dm_update_backlight_caps(dm, bl_idx); 4180 caps = dm->backlight_caps[bl_idx]; 4181 4182 if (caps.aux_support) { 4183 u32 avg, peak; 4184 bool rc; 4185 4186 rc = dc_link_get_backlight_level_nits(link, &avg, &peak); 4187 if (!rc) 4188 return dm->brightness[bl_idx]; 4189 return convert_brightness_to_user(&caps, avg); 4190 } 4191 4192 ret = dc_link_get_backlight_level(link); 4193 4194 if (ret == DC_ERROR_UNEXPECTED) 4195 return dm->brightness[bl_idx]; 4196 4197 return convert_brightness_to_user(&caps, ret); 4198 } 4199 4200 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) 4201 { 4202 struct amdgpu_display_manager *dm = bl_get_data(bd); 4203 int i; 4204 4205 for (i = 0; i < dm->num_of_edps; i++) { 4206 if (bd == dm->backlight_dev[i]) 4207 break; 4208 } 4209 if (i >= AMDGPU_DM_MAX_NUM_EDP) 4210 i = 0; 4211 return amdgpu_dm_backlight_get_level(dm, i); 4212 } 4213 4214 static const struct backlight_ops amdgpu_dm_backlight_ops = { 4215 .options = BL_CORE_SUSPENDRESUME, 4216 .get_brightness = amdgpu_dm_backlight_get_brightness, 4217 .update_status = amdgpu_dm_backlight_update_status, 4218 }; 4219 4220 static void 4221 amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector) 4222 { 4223 struct drm_device *drm = aconnector->base.dev; 4224 struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm; 4225 struct backlight_properties props = { 0 }; 4226 char bl_name[16]; 4227 4228 if (aconnector->bl_idx == -1) 4229 return; 4230 4231 if (!acpi_video_backlight_use_native()) { 4232 drm_info(drm, "Skipping amdgpu DM backlight registration\n"); 4233 /* Try registering an ACPI video backlight device instead. */ 4234 acpi_video_register_backlight(); 4235 return; 4236 } 4237 4238 props.max_brightness = AMDGPU_MAX_BL_LEVEL; 4239 props.brightness = AMDGPU_MAX_BL_LEVEL; 4240 props.type = BACKLIGHT_RAW; 4241 4242 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", 4243 drm->primary->index + aconnector->bl_idx); 4244 4245 dm->backlight_dev[aconnector->bl_idx] = 4246 backlight_device_register(bl_name, aconnector->base.kdev, dm, 4247 &amdgpu_dm_backlight_ops, &props); 4248 4249 if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) { 4250 DRM_ERROR("DM: Backlight registration failed!\n"); 4251 dm->backlight_dev[aconnector->bl_idx] = NULL; 4252 } else 4253 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); 4254 } 4255 4256 static int initialize_plane(struct amdgpu_display_manager *dm, 4257 struct amdgpu_mode_info *mode_info, int plane_id, 4258 enum drm_plane_type plane_type, 4259 const struct dc_plane_cap *plane_cap) 4260 { 4261 struct drm_plane *plane; 4262 unsigned long possible_crtcs; 4263 int ret = 0; 4264 4265 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL); 4266 if (!plane) { 4267 DRM_ERROR("KMS: Failed to allocate plane\n"); 4268 return -ENOMEM; 4269 } 4270 plane->type = plane_type; 4271 4272 /* 4273 * HACK: IGT tests expect that the primary plane for a CRTC 4274 * can only have one possible CRTC. Only expose support for 4275 * any CRTC if they're not going to be used as a primary plane 4276 * for a CRTC - like overlay or underlay planes. 4277 */ 4278 possible_crtcs = 1 << plane_id; 4279 if (plane_id >= dm->dc->caps.max_streams) 4280 possible_crtcs = 0xff; 4281 4282 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); 4283 4284 if (ret) { 4285 DRM_ERROR("KMS: Failed to initialize plane\n"); 4286 kfree(plane); 4287 return ret; 4288 } 4289 4290 if (mode_info) 4291 mode_info->planes[plane_id] = plane; 4292 4293 return ret; 4294 } 4295 4296 4297 static void setup_backlight_device(struct amdgpu_display_manager *dm, 4298 struct amdgpu_dm_connector *aconnector) 4299 { 4300 struct dc_link *link = aconnector->dc_link; 4301 int bl_idx = dm->num_of_edps; 4302 4303 if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) || 4304 link->type == dc_connection_none) 4305 return; 4306 4307 if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) { 4308 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n"); 4309 return; 4310 } 4311 4312 aconnector->bl_idx = bl_idx; 4313 4314 amdgpu_dm_update_backlight_caps(dm, bl_idx); 4315 dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL; 4316 dm->backlight_link[bl_idx] = link; 4317 dm->num_of_edps++; 4318 4319 update_connector_ext_caps(aconnector); 4320 } 4321 4322 static void amdgpu_set_panel_orientation(struct drm_connector *connector); 4323 4324 /* 4325 * In this architecture, the association 4326 * connector -> encoder -> crtc 4327 * id not really requried. The crtc and connector will hold the 4328 * display_index as an abstraction to use with DAL component 4329 * 4330 * Returns 0 on success 4331 */ 4332 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 4333 { 4334 struct amdgpu_display_manager *dm = &adev->dm; 4335 s32 i; 4336 struct amdgpu_dm_connector *aconnector = NULL; 4337 struct amdgpu_encoder *aencoder = NULL; 4338 struct amdgpu_mode_info *mode_info = &adev->mode_info; 4339 u32 link_cnt; 4340 s32 primary_planes; 4341 enum dc_connection_type new_connection_type = dc_connection_none; 4342 const struct dc_plane_cap *plane; 4343 bool psr_feature_enabled = false; 4344 int max_overlay = dm->dc->caps.max_slave_planes; 4345 4346 dm->display_indexes_num = dm->dc->caps.max_streams; 4347 /* Update the actual used number of crtc */ 4348 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 4349 4350 amdgpu_dm_set_irq_funcs(adev); 4351 4352 link_cnt = dm->dc->caps.max_links; 4353 if (amdgpu_dm_mode_config_init(dm->adev)) { 4354 DRM_ERROR("DM: Failed to initialize mode config\n"); 4355 return -EINVAL; 4356 } 4357 4358 /* There is one primary plane per CRTC */ 4359 primary_planes = dm->dc->caps.max_streams; 4360 ASSERT(primary_planes <= AMDGPU_MAX_PLANES); 4361 4362 /* 4363 * Initialize primary planes, implicit planes for legacy IOCTLS. 4364 * Order is reversed to match iteration order in atomic check. 4365 */ 4366 for (i = (primary_planes - 1); i >= 0; i--) { 4367 plane = &dm->dc->caps.planes[i]; 4368 4369 if (initialize_plane(dm, mode_info, i, 4370 DRM_PLANE_TYPE_PRIMARY, plane)) { 4371 DRM_ERROR("KMS: Failed to initialize primary plane\n"); 4372 goto fail; 4373 } 4374 } 4375 4376 /* 4377 * Initialize overlay planes, index starting after primary planes. 4378 * These planes have a higher DRM index than the primary planes since 4379 * they should be considered as having a higher z-order. 4380 * Order is reversed to match iteration order in atomic check. 4381 * 4382 * Only support DCN for now, and only expose one so we don't encourage 4383 * userspace to use up all the pipes. 4384 */ 4385 for (i = 0; i < dm->dc->caps.max_planes; ++i) { 4386 struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; 4387 4388 /* Do not create overlay if MPO disabled */ 4389 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO) 4390 break; 4391 4392 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) 4393 continue; 4394 4395 if (!plane->pixel_format_support.argb8888) 4396 continue; 4397 4398 if (max_overlay-- == 0) 4399 break; 4400 4401 if (initialize_plane(dm, NULL, primary_planes + i, 4402 DRM_PLANE_TYPE_OVERLAY, plane)) { 4403 DRM_ERROR("KMS: Failed to initialize overlay plane\n"); 4404 goto fail; 4405 } 4406 } 4407 4408 for (i = 0; i < dm->dc->caps.max_streams; i++) 4409 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { 4410 DRM_ERROR("KMS: Failed to initialize crtc\n"); 4411 goto fail; 4412 } 4413 4414 /* Use Outbox interrupt */ 4415 switch (adev->ip_versions[DCE_HWIP][0]) { 4416 case IP_VERSION(3, 0, 0): 4417 case IP_VERSION(3, 1, 2): 4418 case IP_VERSION(3, 1, 3): 4419 case IP_VERSION(3, 1, 4): 4420 case IP_VERSION(3, 1, 5): 4421 case IP_VERSION(3, 1, 6): 4422 case IP_VERSION(3, 2, 0): 4423 case IP_VERSION(3, 2, 1): 4424 case IP_VERSION(2, 1, 0): 4425 if (register_outbox_irq_handlers(dm->adev)) { 4426 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4427 goto fail; 4428 } 4429 break; 4430 default: 4431 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n", 4432 adev->ip_versions[DCE_HWIP][0]); 4433 } 4434 4435 /* Determine whether to enable PSR support by default. */ 4436 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) { 4437 switch (adev->ip_versions[DCE_HWIP][0]) { 4438 case IP_VERSION(3, 1, 2): 4439 case IP_VERSION(3, 1, 3): 4440 case IP_VERSION(3, 1, 4): 4441 case IP_VERSION(3, 1, 5): 4442 case IP_VERSION(3, 1, 6): 4443 case IP_VERSION(3, 2, 0): 4444 case IP_VERSION(3, 2, 1): 4445 psr_feature_enabled = true; 4446 break; 4447 default: 4448 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK; 4449 break; 4450 } 4451 } 4452 4453 /* loops over all connectors on the board */ 4454 for (i = 0; i < link_cnt; i++) { 4455 struct dc_link *link = NULL; 4456 4457 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) { 4458 DRM_ERROR( 4459 "KMS: Cannot support more than %d display indexes\n", 4460 AMDGPU_DM_MAX_DISPLAY_INDEX); 4461 continue; 4462 } 4463 4464 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 4465 if (!aconnector) 4466 goto fail; 4467 4468 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); 4469 if (!aencoder) 4470 goto fail; 4471 4472 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 4473 DRM_ERROR("KMS: Failed to initialize encoder\n"); 4474 goto fail; 4475 } 4476 4477 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 4478 DRM_ERROR("KMS: Failed to initialize connector\n"); 4479 goto fail; 4480 } 4481 4482 link = dc_get_link_at_index(dm->dc, i); 4483 4484 if (dm->hpd_rx_offload_wq) 4485 dm->hpd_rx_offload_wq[aconnector->base.index].aconnector = 4486 aconnector; 4487 4488 if (!dc_link_detect_connection_type(link, &new_connection_type)) 4489 DRM_ERROR("KMS: Failed to detect connector\n"); 4490 4491 if (aconnector->base.force && new_connection_type == dc_connection_none) { 4492 emulated_link_detect(link); 4493 amdgpu_dm_update_connector_after_detect(aconnector); 4494 } else { 4495 bool ret = false; 4496 4497 mutex_lock(&dm->dc_lock); 4498 ret = dc_link_detect(link, DETECT_REASON_BOOT); 4499 mutex_unlock(&dm->dc_lock); 4500 4501 if (ret) { 4502 amdgpu_dm_update_connector_after_detect(aconnector); 4503 setup_backlight_device(dm, aconnector); 4504 4505 if (psr_feature_enabled) 4506 amdgpu_dm_set_psr_caps(link); 4507 4508 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when 4509 * PSR is also supported. 4510 */ 4511 if (link->psr_settings.psr_feature_enabled) 4512 adev_to_drm(adev)->vblank_disable_immediate = false; 4513 } 4514 } 4515 amdgpu_set_panel_orientation(&aconnector->base); 4516 } 4517 4518 /* Software is initialized. Now we can register interrupt handlers. */ 4519 switch (adev->asic_type) { 4520 #if defined(CONFIG_DRM_AMD_DC_SI) 4521 case CHIP_TAHITI: 4522 case CHIP_PITCAIRN: 4523 case CHIP_VERDE: 4524 case CHIP_OLAND: 4525 if (dce60_register_irq_handlers(dm->adev)) { 4526 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4527 goto fail; 4528 } 4529 break; 4530 #endif 4531 case CHIP_BONAIRE: 4532 case CHIP_HAWAII: 4533 case CHIP_KAVERI: 4534 case CHIP_KABINI: 4535 case CHIP_MULLINS: 4536 case CHIP_TONGA: 4537 case CHIP_FIJI: 4538 case CHIP_CARRIZO: 4539 case CHIP_STONEY: 4540 case CHIP_POLARIS11: 4541 case CHIP_POLARIS10: 4542 case CHIP_POLARIS12: 4543 case CHIP_VEGAM: 4544 case CHIP_VEGA10: 4545 case CHIP_VEGA12: 4546 case CHIP_VEGA20: 4547 if (dce110_register_irq_handlers(dm->adev)) { 4548 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4549 goto fail; 4550 } 4551 break; 4552 default: 4553 switch (adev->ip_versions[DCE_HWIP][0]) { 4554 case IP_VERSION(1, 0, 0): 4555 case IP_VERSION(1, 0, 1): 4556 case IP_VERSION(2, 0, 2): 4557 case IP_VERSION(2, 0, 3): 4558 case IP_VERSION(2, 0, 0): 4559 case IP_VERSION(2, 1, 0): 4560 case IP_VERSION(3, 0, 0): 4561 case IP_VERSION(3, 0, 2): 4562 case IP_VERSION(3, 0, 3): 4563 case IP_VERSION(3, 0, 1): 4564 case IP_VERSION(3, 1, 2): 4565 case IP_VERSION(3, 1, 3): 4566 case IP_VERSION(3, 1, 4): 4567 case IP_VERSION(3, 1, 5): 4568 case IP_VERSION(3, 1, 6): 4569 case IP_VERSION(3, 2, 0): 4570 case IP_VERSION(3, 2, 1): 4571 if (dcn10_register_irq_handlers(dm->adev)) { 4572 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4573 goto fail; 4574 } 4575 break; 4576 default: 4577 DRM_ERROR("Unsupported DCE IP versions: 0x%X\n", 4578 adev->ip_versions[DCE_HWIP][0]); 4579 goto fail; 4580 } 4581 break; 4582 } 4583 4584 return 0; 4585 fail: 4586 kfree(aencoder); 4587 kfree(aconnector); 4588 4589 return -EINVAL; 4590 } 4591 4592 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 4593 { 4594 drm_atomic_private_obj_fini(&dm->atomic_obj); 4595 } 4596 4597 /****************************************************************************** 4598 * amdgpu_display_funcs functions 4599 *****************************************************************************/ 4600 4601 /* 4602 * dm_bandwidth_update - program display watermarks 4603 * 4604 * @adev: amdgpu_device pointer 4605 * 4606 * Calculate and program the display watermarks and line buffer allocation. 4607 */ 4608 static void dm_bandwidth_update(struct amdgpu_device *adev) 4609 { 4610 /* TODO: implement later */ 4611 } 4612 4613 static const struct amdgpu_display_funcs dm_display_funcs = { 4614 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 4615 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 4616 .backlight_set_level = NULL, /* never called for DC */ 4617 .backlight_get_level = NULL, /* never called for DC */ 4618 .hpd_sense = NULL,/* called unconditionally */ 4619 .hpd_set_polarity = NULL, /* called unconditionally */ 4620 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 4621 .page_flip_get_scanoutpos = 4622 dm_crtc_get_scanoutpos,/* called unconditionally */ 4623 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 4624 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 4625 }; 4626 4627 #if defined(CONFIG_DEBUG_KERNEL_DC) 4628 4629 static ssize_t s3_debug_store(struct device *device, 4630 struct device_attribute *attr, 4631 const char *buf, 4632 size_t count) 4633 { 4634 int ret; 4635 int s3_state; 4636 struct drm_device *drm_dev = dev_get_drvdata(device); 4637 struct amdgpu_device *adev = drm_to_adev(drm_dev); 4638 4639 ret = kstrtoint(buf, 0, &s3_state); 4640 4641 if (ret == 0) { 4642 if (s3_state) { 4643 dm_resume(adev); 4644 drm_kms_helper_hotplug_event(adev_to_drm(adev)); 4645 } else 4646 dm_suspend(adev); 4647 } 4648 4649 return ret == 0 ? count : 0; 4650 } 4651 4652 DEVICE_ATTR_WO(s3_debug); 4653 4654 #endif 4655 4656 static int dm_init_microcode(struct amdgpu_device *adev) 4657 { 4658 char *fw_name_dmub; 4659 int r; 4660 4661 switch (adev->ip_versions[DCE_HWIP][0]) { 4662 case IP_VERSION(2, 1, 0): 4663 fw_name_dmub = FIRMWARE_RENOIR_DMUB; 4664 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)) 4665 fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB; 4666 break; 4667 case IP_VERSION(3, 0, 0): 4668 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) 4669 fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB; 4670 else 4671 fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB; 4672 break; 4673 case IP_VERSION(3, 0, 1): 4674 fw_name_dmub = FIRMWARE_VANGOGH_DMUB; 4675 break; 4676 case IP_VERSION(3, 0, 2): 4677 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB; 4678 break; 4679 case IP_VERSION(3, 0, 3): 4680 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB; 4681 break; 4682 case IP_VERSION(3, 1, 2): 4683 case IP_VERSION(3, 1, 3): 4684 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB; 4685 break; 4686 case IP_VERSION(3, 1, 4): 4687 fw_name_dmub = FIRMWARE_DCN_314_DMUB; 4688 break; 4689 case IP_VERSION(3, 1, 5): 4690 fw_name_dmub = FIRMWARE_DCN_315_DMUB; 4691 break; 4692 case IP_VERSION(3, 1, 6): 4693 fw_name_dmub = FIRMWARE_DCN316_DMUB; 4694 break; 4695 case IP_VERSION(3, 2, 0): 4696 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB; 4697 break; 4698 case IP_VERSION(3, 2, 1): 4699 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB; 4700 break; 4701 default: 4702 /* ASIC doesn't support DMUB. */ 4703 return 0; 4704 } 4705 r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub); 4706 if (r) 4707 DRM_ERROR("DMUB firmware loading failed: %d\n", r); 4708 return r; 4709 } 4710 4711 static int dm_early_init(void *handle) 4712 { 4713 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4714 struct amdgpu_mode_info *mode_info = &adev->mode_info; 4715 struct atom_context *ctx = mode_info->atom_context; 4716 int index = GetIndexIntoMasterTable(DATA, Object_Header); 4717 u16 data_offset; 4718 4719 /* if there is no object header, skip DM */ 4720 if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { 4721 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 4722 dev_info(adev->dev, "No object header, skipping DM\n"); 4723 return -ENOENT; 4724 } 4725 4726 switch (adev->asic_type) { 4727 #if defined(CONFIG_DRM_AMD_DC_SI) 4728 case CHIP_TAHITI: 4729 case CHIP_PITCAIRN: 4730 case CHIP_VERDE: 4731 adev->mode_info.num_crtc = 6; 4732 adev->mode_info.num_hpd = 6; 4733 adev->mode_info.num_dig = 6; 4734 break; 4735 case CHIP_OLAND: 4736 adev->mode_info.num_crtc = 2; 4737 adev->mode_info.num_hpd = 2; 4738 adev->mode_info.num_dig = 2; 4739 break; 4740 #endif 4741 case CHIP_BONAIRE: 4742 case CHIP_HAWAII: 4743 adev->mode_info.num_crtc = 6; 4744 adev->mode_info.num_hpd = 6; 4745 adev->mode_info.num_dig = 6; 4746 break; 4747 case CHIP_KAVERI: 4748 adev->mode_info.num_crtc = 4; 4749 adev->mode_info.num_hpd = 6; 4750 adev->mode_info.num_dig = 7; 4751 break; 4752 case CHIP_KABINI: 4753 case CHIP_MULLINS: 4754 adev->mode_info.num_crtc = 2; 4755 adev->mode_info.num_hpd = 6; 4756 adev->mode_info.num_dig = 6; 4757 break; 4758 case CHIP_FIJI: 4759 case CHIP_TONGA: 4760 adev->mode_info.num_crtc = 6; 4761 adev->mode_info.num_hpd = 6; 4762 adev->mode_info.num_dig = 7; 4763 break; 4764 case CHIP_CARRIZO: 4765 adev->mode_info.num_crtc = 3; 4766 adev->mode_info.num_hpd = 6; 4767 adev->mode_info.num_dig = 9; 4768 break; 4769 case CHIP_STONEY: 4770 adev->mode_info.num_crtc = 2; 4771 adev->mode_info.num_hpd = 6; 4772 adev->mode_info.num_dig = 9; 4773 break; 4774 case CHIP_POLARIS11: 4775 case CHIP_POLARIS12: 4776 adev->mode_info.num_crtc = 5; 4777 adev->mode_info.num_hpd = 5; 4778 adev->mode_info.num_dig = 5; 4779 break; 4780 case CHIP_POLARIS10: 4781 case CHIP_VEGAM: 4782 adev->mode_info.num_crtc = 6; 4783 adev->mode_info.num_hpd = 6; 4784 adev->mode_info.num_dig = 6; 4785 break; 4786 case CHIP_VEGA10: 4787 case CHIP_VEGA12: 4788 case CHIP_VEGA20: 4789 adev->mode_info.num_crtc = 6; 4790 adev->mode_info.num_hpd = 6; 4791 adev->mode_info.num_dig = 6; 4792 break; 4793 default: 4794 4795 switch (adev->ip_versions[DCE_HWIP][0]) { 4796 case IP_VERSION(2, 0, 2): 4797 case IP_VERSION(3, 0, 0): 4798 adev->mode_info.num_crtc = 6; 4799 adev->mode_info.num_hpd = 6; 4800 adev->mode_info.num_dig = 6; 4801 break; 4802 case IP_VERSION(2, 0, 0): 4803 case IP_VERSION(3, 0, 2): 4804 adev->mode_info.num_crtc = 5; 4805 adev->mode_info.num_hpd = 5; 4806 adev->mode_info.num_dig = 5; 4807 break; 4808 case IP_VERSION(2, 0, 3): 4809 case IP_VERSION(3, 0, 3): 4810 adev->mode_info.num_crtc = 2; 4811 adev->mode_info.num_hpd = 2; 4812 adev->mode_info.num_dig = 2; 4813 break; 4814 case IP_VERSION(1, 0, 0): 4815 case IP_VERSION(1, 0, 1): 4816 case IP_VERSION(3, 0, 1): 4817 case IP_VERSION(2, 1, 0): 4818 case IP_VERSION(3, 1, 2): 4819 case IP_VERSION(3, 1, 3): 4820 case IP_VERSION(3, 1, 4): 4821 case IP_VERSION(3, 1, 5): 4822 case IP_VERSION(3, 1, 6): 4823 case IP_VERSION(3, 2, 0): 4824 case IP_VERSION(3, 2, 1): 4825 adev->mode_info.num_crtc = 4; 4826 adev->mode_info.num_hpd = 4; 4827 adev->mode_info.num_dig = 4; 4828 break; 4829 default: 4830 DRM_ERROR("Unsupported DCE IP versions: 0x%x\n", 4831 adev->ip_versions[DCE_HWIP][0]); 4832 return -EINVAL; 4833 } 4834 break; 4835 } 4836 4837 if (adev->mode_info.funcs == NULL) 4838 adev->mode_info.funcs = &dm_display_funcs; 4839 4840 /* 4841 * Note: Do NOT change adev->audio_endpt_rreg and 4842 * adev->audio_endpt_wreg because they are initialised in 4843 * amdgpu_device_init() 4844 */ 4845 #if defined(CONFIG_DEBUG_KERNEL_DC) 4846 device_create_file( 4847 adev_to_drm(adev)->dev, 4848 &dev_attr_s3_debug); 4849 #endif 4850 adev->dc_enabled = true; 4851 4852 return dm_init_microcode(adev); 4853 } 4854 4855 static bool modereset_required(struct drm_crtc_state *crtc_state) 4856 { 4857 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 4858 } 4859 4860 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 4861 { 4862 drm_encoder_cleanup(encoder); 4863 kfree(encoder); 4864 } 4865 4866 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 4867 .destroy = amdgpu_dm_encoder_destroy, 4868 }; 4869 4870 static int 4871 fill_plane_color_attributes(const struct drm_plane_state *plane_state, 4872 const enum surface_pixel_format format, 4873 enum dc_color_space *color_space) 4874 { 4875 bool full_range; 4876 4877 *color_space = COLOR_SPACE_SRGB; 4878 4879 /* DRM color properties only affect non-RGB formats. */ 4880 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 4881 return 0; 4882 4883 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); 4884 4885 switch (plane_state->color_encoding) { 4886 case DRM_COLOR_YCBCR_BT601: 4887 if (full_range) 4888 *color_space = COLOR_SPACE_YCBCR601; 4889 else 4890 *color_space = COLOR_SPACE_YCBCR601_LIMITED; 4891 break; 4892 4893 case DRM_COLOR_YCBCR_BT709: 4894 if (full_range) 4895 *color_space = COLOR_SPACE_YCBCR709; 4896 else 4897 *color_space = COLOR_SPACE_YCBCR709_LIMITED; 4898 break; 4899 4900 case DRM_COLOR_YCBCR_BT2020: 4901 if (full_range) 4902 *color_space = COLOR_SPACE_2020_YCBCR; 4903 else 4904 return -EINVAL; 4905 break; 4906 4907 default: 4908 return -EINVAL; 4909 } 4910 4911 return 0; 4912 } 4913 4914 static int 4915 fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 4916 const struct drm_plane_state *plane_state, 4917 const u64 tiling_flags, 4918 struct dc_plane_info *plane_info, 4919 struct dc_plane_address *address, 4920 bool tmz_surface, 4921 bool force_disable_dcc) 4922 { 4923 const struct drm_framebuffer *fb = plane_state->fb; 4924 const struct amdgpu_framebuffer *afb = 4925 to_amdgpu_framebuffer(plane_state->fb); 4926 int ret; 4927 4928 memset(plane_info, 0, sizeof(*plane_info)); 4929 4930 switch (fb->format->format) { 4931 case DRM_FORMAT_C8: 4932 plane_info->format = 4933 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 4934 break; 4935 case DRM_FORMAT_RGB565: 4936 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 4937 break; 4938 case DRM_FORMAT_XRGB8888: 4939 case DRM_FORMAT_ARGB8888: 4940 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 4941 break; 4942 case DRM_FORMAT_XRGB2101010: 4943 case DRM_FORMAT_ARGB2101010: 4944 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 4945 break; 4946 case DRM_FORMAT_XBGR2101010: 4947 case DRM_FORMAT_ABGR2101010: 4948 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 4949 break; 4950 case DRM_FORMAT_XBGR8888: 4951 case DRM_FORMAT_ABGR8888: 4952 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; 4953 break; 4954 case DRM_FORMAT_NV21: 4955 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 4956 break; 4957 case DRM_FORMAT_NV12: 4958 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 4959 break; 4960 case DRM_FORMAT_P010: 4961 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; 4962 break; 4963 case DRM_FORMAT_XRGB16161616F: 4964 case DRM_FORMAT_ARGB16161616F: 4965 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; 4966 break; 4967 case DRM_FORMAT_XBGR16161616F: 4968 case DRM_FORMAT_ABGR16161616F: 4969 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; 4970 break; 4971 case DRM_FORMAT_XRGB16161616: 4972 case DRM_FORMAT_ARGB16161616: 4973 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; 4974 break; 4975 case DRM_FORMAT_XBGR16161616: 4976 case DRM_FORMAT_ABGR16161616: 4977 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; 4978 break; 4979 default: 4980 DRM_ERROR( 4981 "Unsupported screen format %p4cc\n", 4982 &fb->format->format); 4983 return -EINVAL; 4984 } 4985 4986 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 4987 case DRM_MODE_ROTATE_0: 4988 plane_info->rotation = ROTATION_ANGLE_0; 4989 break; 4990 case DRM_MODE_ROTATE_90: 4991 plane_info->rotation = ROTATION_ANGLE_90; 4992 break; 4993 case DRM_MODE_ROTATE_180: 4994 plane_info->rotation = ROTATION_ANGLE_180; 4995 break; 4996 case DRM_MODE_ROTATE_270: 4997 plane_info->rotation = ROTATION_ANGLE_270; 4998 break; 4999 default: 5000 plane_info->rotation = ROTATION_ANGLE_0; 5001 break; 5002 } 5003 5004 5005 plane_info->visible = true; 5006 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; 5007 5008 plane_info->layer_index = plane_state->normalized_zpos; 5009 5010 ret = fill_plane_color_attributes(plane_state, plane_info->format, 5011 &plane_info->color_space); 5012 if (ret) 5013 return ret; 5014 5015 ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format, 5016 plane_info->rotation, tiling_flags, 5017 &plane_info->tiling_info, 5018 &plane_info->plane_size, 5019 &plane_info->dcc, address, 5020 tmz_surface, force_disable_dcc); 5021 if (ret) 5022 return ret; 5023 5024 amdgpu_dm_plane_fill_blending_from_plane_state( 5025 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha, 5026 &plane_info->global_alpha, &plane_info->global_alpha_value); 5027 5028 return 0; 5029 } 5030 5031 static int fill_dc_plane_attributes(struct amdgpu_device *adev, 5032 struct dc_plane_state *dc_plane_state, 5033 struct drm_plane_state *plane_state, 5034 struct drm_crtc_state *crtc_state) 5035 { 5036 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 5037 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb; 5038 struct dc_scaling_info scaling_info; 5039 struct dc_plane_info plane_info; 5040 int ret; 5041 bool force_disable_dcc = false; 5042 5043 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info); 5044 if (ret) 5045 return ret; 5046 5047 dc_plane_state->src_rect = scaling_info.src_rect; 5048 dc_plane_state->dst_rect = scaling_info.dst_rect; 5049 dc_plane_state->clip_rect = scaling_info.clip_rect; 5050 dc_plane_state->scaling_quality = scaling_info.scaling_quality; 5051 5052 force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend; 5053 ret = fill_dc_plane_info_and_addr(adev, plane_state, 5054 afb->tiling_flags, 5055 &plane_info, 5056 &dc_plane_state->address, 5057 afb->tmz_surface, 5058 force_disable_dcc); 5059 if (ret) 5060 return ret; 5061 5062 dc_plane_state->format = plane_info.format; 5063 dc_plane_state->color_space = plane_info.color_space; 5064 dc_plane_state->format = plane_info.format; 5065 dc_plane_state->plane_size = plane_info.plane_size; 5066 dc_plane_state->rotation = plane_info.rotation; 5067 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; 5068 dc_plane_state->stereo_format = plane_info.stereo_format; 5069 dc_plane_state->tiling_info = plane_info.tiling_info; 5070 dc_plane_state->visible = plane_info.visible; 5071 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; 5072 dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha; 5073 dc_plane_state->global_alpha = plane_info.global_alpha; 5074 dc_plane_state->global_alpha_value = plane_info.global_alpha_value; 5075 dc_plane_state->dcc = plane_info.dcc; 5076 dc_plane_state->layer_index = plane_info.layer_index; 5077 dc_plane_state->flip_int_enabled = true; 5078 5079 /* 5080 * Always set input transfer function, since plane state is refreshed 5081 * every time. 5082 */ 5083 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state); 5084 if (ret) 5085 return ret; 5086 5087 return 0; 5088 } 5089 5090 static inline void fill_dc_dirty_rect(struct drm_plane *plane, 5091 struct rect *dirty_rect, int32_t x, 5092 s32 y, s32 width, s32 height, 5093 int *i, bool ffu) 5094 { 5095 WARN_ON(*i >= DC_MAX_DIRTY_RECTS); 5096 5097 dirty_rect->x = x; 5098 dirty_rect->y = y; 5099 dirty_rect->width = width; 5100 dirty_rect->height = height; 5101 5102 if (ffu) 5103 drm_dbg(plane->dev, 5104 "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n", 5105 plane->base.id, width, height); 5106 else 5107 drm_dbg(plane->dev, 5108 "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)", 5109 plane->base.id, x, y, width, height); 5110 5111 (*i)++; 5112 } 5113 5114 /** 5115 * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates 5116 * 5117 * @plane: DRM plane containing dirty regions that need to be flushed to the eDP 5118 * remote fb 5119 * @old_plane_state: Old state of @plane 5120 * @new_plane_state: New state of @plane 5121 * @crtc_state: New state of CRTC connected to the @plane 5122 * @flip_addrs: DC flip tracking struct, which also tracts dirty rects 5123 * @dirty_regions_changed: dirty regions changed 5124 * 5125 * For PSR SU, DC informs the DMUB uController of dirty rectangle regions 5126 * (referred to as "damage clips" in DRM nomenclature) that require updating on 5127 * the eDP remote buffer. The responsibility of specifying the dirty regions is 5128 * amdgpu_dm's. 5129 * 5130 * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the 5131 * plane with regions that require flushing to the eDP remote buffer. In 5132 * addition, certain use cases - such as cursor and multi-plane overlay (MPO) - 5133 * implicitly provide damage clips without any client support via the plane 5134 * bounds. 5135 */ 5136 static void fill_dc_dirty_rects(struct drm_plane *plane, 5137 struct drm_plane_state *old_plane_state, 5138 struct drm_plane_state *new_plane_state, 5139 struct drm_crtc_state *crtc_state, 5140 struct dc_flip_addrs *flip_addrs, 5141 bool *dirty_regions_changed) 5142 { 5143 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 5144 struct rect *dirty_rects = flip_addrs->dirty_rects; 5145 u32 num_clips; 5146 struct drm_mode_rect *clips; 5147 bool bb_changed; 5148 bool fb_changed; 5149 u32 i = 0; 5150 *dirty_regions_changed = false; 5151 5152 /* 5153 * Cursor plane has it's own dirty rect update interface. See 5154 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data 5155 */ 5156 if (plane->type == DRM_PLANE_TYPE_CURSOR) 5157 return; 5158 5159 if (new_plane_state->rotation != DRM_MODE_ROTATE_0) 5160 goto ffu; 5161 5162 num_clips = drm_plane_get_damage_clips_count(new_plane_state); 5163 clips = drm_plane_get_damage_clips(new_plane_state); 5164 5165 if (!dm_crtc_state->mpo_requested) { 5166 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS) 5167 goto ffu; 5168 5169 for (; flip_addrs->dirty_rect_count < num_clips; clips++) 5170 fill_dc_dirty_rect(new_plane_state->plane, 5171 &dirty_rects[flip_addrs->dirty_rect_count], 5172 clips->x1, clips->y1, 5173 clips->x2 - clips->x1, clips->y2 - clips->y1, 5174 &flip_addrs->dirty_rect_count, 5175 false); 5176 return; 5177 } 5178 5179 /* 5180 * MPO is requested. Add entire plane bounding box to dirty rects if 5181 * flipped to or damaged. 5182 * 5183 * If plane is moved or resized, also add old bounding box to dirty 5184 * rects. 5185 */ 5186 fb_changed = old_plane_state->fb->base.id != 5187 new_plane_state->fb->base.id; 5188 bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x || 5189 old_plane_state->crtc_y != new_plane_state->crtc_y || 5190 old_plane_state->crtc_w != new_plane_state->crtc_w || 5191 old_plane_state->crtc_h != new_plane_state->crtc_h); 5192 5193 drm_dbg(plane->dev, 5194 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n", 5195 new_plane_state->plane->base.id, 5196 bb_changed, fb_changed, num_clips); 5197 5198 *dirty_regions_changed = bb_changed; 5199 5200 if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS) 5201 goto ffu; 5202 5203 if (bb_changed) { 5204 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 5205 new_plane_state->crtc_x, 5206 new_plane_state->crtc_y, 5207 new_plane_state->crtc_w, 5208 new_plane_state->crtc_h, &i, false); 5209 5210 /* Add old plane bounding-box if plane is moved or resized */ 5211 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 5212 old_plane_state->crtc_x, 5213 old_plane_state->crtc_y, 5214 old_plane_state->crtc_w, 5215 old_plane_state->crtc_h, &i, false); 5216 } 5217 5218 if (num_clips) { 5219 for (; i < num_clips; clips++) 5220 fill_dc_dirty_rect(new_plane_state->plane, 5221 &dirty_rects[i], clips->x1, 5222 clips->y1, clips->x2 - clips->x1, 5223 clips->y2 - clips->y1, &i, false); 5224 } else if (fb_changed && !bb_changed) { 5225 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 5226 new_plane_state->crtc_x, 5227 new_plane_state->crtc_y, 5228 new_plane_state->crtc_w, 5229 new_plane_state->crtc_h, &i, false); 5230 } 5231 5232 flip_addrs->dirty_rect_count = i; 5233 return; 5234 5235 ffu: 5236 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0, 5237 dm_crtc_state->base.mode.crtc_hdisplay, 5238 dm_crtc_state->base.mode.crtc_vdisplay, 5239 &flip_addrs->dirty_rect_count, true); 5240 } 5241 5242 static void update_stream_scaling_settings(const struct drm_display_mode *mode, 5243 const struct dm_connector_state *dm_state, 5244 struct dc_stream_state *stream) 5245 { 5246 enum amdgpu_rmx_type rmx_type; 5247 5248 struct rect src = { 0 }; /* viewport in composition space*/ 5249 struct rect dst = { 0 }; /* stream addressable area */ 5250 5251 /* no mode. nothing to be done */ 5252 if (!mode) 5253 return; 5254 5255 /* Full screen scaling by default */ 5256 src.width = mode->hdisplay; 5257 src.height = mode->vdisplay; 5258 dst.width = stream->timing.h_addressable; 5259 dst.height = stream->timing.v_addressable; 5260 5261 if (dm_state) { 5262 rmx_type = dm_state->scaling; 5263 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 5264 if (src.width * dst.height < 5265 src.height * dst.width) { 5266 /* height needs less upscaling/more downscaling */ 5267 dst.width = src.width * 5268 dst.height / src.height; 5269 } else { 5270 /* width needs less upscaling/more downscaling */ 5271 dst.height = src.height * 5272 dst.width / src.width; 5273 } 5274 } else if (rmx_type == RMX_CENTER) { 5275 dst = src; 5276 } 5277 5278 dst.x = (stream->timing.h_addressable - dst.width) / 2; 5279 dst.y = (stream->timing.v_addressable - dst.height) / 2; 5280 5281 if (dm_state->underscan_enable) { 5282 dst.x += dm_state->underscan_hborder / 2; 5283 dst.y += dm_state->underscan_vborder / 2; 5284 dst.width -= dm_state->underscan_hborder; 5285 dst.height -= dm_state->underscan_vborder; 5286 } 5287 } 5288 5289 stream->src = src; 5290 stream->dst = dst; 5291 5292 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n", 5293 dst.x, dst.y, dst.width, dst.height); 5294 5295 } 5296 5297 static enum dc_color_depth 5298 convert_color_depth_from_display_info(const struct drm_connector *connector, 5299 bool is_y420, int requested_bpc) 5300 { 5301 u8 bpc; 5302 5303 if (is_y420) { 5304 bpc = 8; 5305 5306 /* Cap display bpc based on HDMI 2.0 HF-VSDB */ 5307 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) 5308 bpc = 16; 5309 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) 5310 bpc = 12; 5311 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) 5312 bpc = 10; 5313 } else { 5314 bpc = (uint8_t)connector->display_info.bpc; 5315 /* Assume 8 bpc by default if no bpc is specified. */ 5316 bpc = bpc ? bpc : 8; 5317 } 5318 5319 if (requested_bpc > 0) { 5320 /* 5321 * Cap display bpc based on the user requested value. 5322 * 5323 * The value for state->max_bpc may not correctly updated 5324 * depending on when the connector gets added to the state 5325 * or if this was called outside of atomic check, so it 5326 * can't be used directly. 5327 */ 5328 bpc = min_t(u8, bpc, requested_bpc); 5329 5330 /* Round down to the nearest even number. */ 5331 bpc = bpc - (bpc & 1); 5332 } 5333 5334 switch (bpc) { 5335 case 0: 5336 /* 5337 * Temporary Work around, DRM doesn't parse color depth for 5338 * EDID revision before 1.4 5339 * TODO: Fix edid parsing 5340 */ 5341 return COLOR_DEPTH_888; 5342 case 6: 5343 return COLOR_DEPTH_666; 5344 case 8: 5345 return COLOR_DEPTH_888; 5346 case 10: 5347 return COLOR_DEPTH_101010; 5348 case 12: 5349 return COLOR_DEPTH_121212; 5350 case 14: 5351 return COLOR_DEPTH_141414; 5352 case 16: 5353 return COLOR_DEPTH_161616; 5354 default: 5355 return COLOR_DEPTH_UNDEFINED; 5356 } 5357 } 5358 5359 static enum dc_aspect_ratio 5360 get_aspect_ratio(const struct drm_display_mode *mode_in) 5361 { 5362 /* 1-1 mapping, since both enums follow the HDMI spec. */ 5363 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; 5364 } 5365 5366 static enum dc_color_space 5367 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, 5368 const struct drm_connector_state *connector_state) 5369 { 5370 enum dc_color_space color_space = COLOR_SPACE_SRGB; 5371 5372 switch (connector_state->colorspace) { 5373 case DRM_MODE_COLORIMETRY_BT601_YCC: 5374 if (dc_crtc_timing->flags.Y_ONLY) 5375 color_space = COLOR_SPACE_YCBCR601_LIMITED; 5376 else 5377 color_space = COLOR_SPACE_YCBCR601; 5378 break; 5379 case DRM_MODE_COLORIMETRY_BT709_YCC: 5380 if (dc_crtc_timing->flags.Y_ONLY) 5381 color_space = COLOR_SPACE_YCBCR709_LIMITED; 5382 else 5383 color_space = COLOR_SPACE_YCBCR709; 5384 break; 5385 case DRM_MODE_COLORIMETRY_OPRGB: 5386 color_space = COLOR_SPACE_ADOBERGB; 5387 break; 5388 case DRM_MODE_COLORIMETRY_BT2020_RGB: 5389 case DRM_MODE_COLORIMETRY_BT2020_YCC: 5390 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) 5391 color_space = COLOR_SPACE_2020_RGB_FULLRANGE; 5392 else 5393 color_space = COLOR_SPACE_2020_YCBCR; 5394 break; 5395 case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601 5396 default: 5397 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) { 5398 color_space = COLOR_SPACE_SRGB; 5399 /* 5400 * 27030khz is the separation point between HDTV and SDTV 5401 * according to HDMI spec, we use YCbCr709 and YCbCr601 5402 * respectively 5403 */ 5404 } else if (dc_crtc_timing->pix_clk_100hz > 270300) { 5405 if (dc_crtc_timing->flags.Y_ONLY) 5406 color_space = 5407 COLOR_SPACE_YCBCR709_LIMITED; 5408 else 5409 color_space = COLOR_SPACE_YCBCR709; 5410 } else { 5411 if (dc_crtc_timing->flags.Y_ONLY) 5412 color_space = 5413 COLOR_SPACE_YCBCR601_LIMITED; 5414 else 5415 color_space = COLOR_SPACE_YCBCR601; 5416 } 5417 break; 5418 } 5419 5420 return color_space; 5421 } 5422 5423 static bool adjust_colour_depth_from_display_info( 5424 struct dc_crtc_timing *timing_out, 5425 const struct drm_display_info *info) 5426 { 5427 enum dc_color_depth depth = timing_out->display_color_depth; 5428 int normalized_clk; 5429 5430 do { 5431 normalized_clk = timing_out->pix_clk_100hz / 10; 5432 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ 5433 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) 5434 normalized_clk /= 2; 5435 /* Adjusting pix clock following on HDMI spec based on colour depth */ 5436 switch (depth) { 5437 case COLOR_DEPTH_888: 5438 break; 5439 case COLOR_DEPTH_101010: 5440 normalized_clk = (normalized_clk * 30) / 24; 5441 break; 5442 case COLOR_DEPTH_121212: 5443 normalized_clk = (normalized_clk * 36) / 24; 5444 break; 5445 case COLOR_DEPTH_161616: 5446 normalized_clk = (normalized_clk * 48) / 24; 5447 break; 5448 default: 5449 /* The above depths are the only ones valid for HDMI. */ 5450 return false; 5451 } 5452 if (normalized_clk <= info->max_tmds_clock) { 5453 timing_out->display_color_depth = depth; 5454 return true; 5455 } 5456 } while (--depth > COLOR_DEPTH_666); 5457 return false; 5458 } 5459 5460 static void fill_stream_properties_from_drm_display_mode( 5461 struct dc_stream_state *stream, 5462 const struct drm_display_mode *mode_in, 5463 const struct drm_connector *connector, 5464 const struct drm_connector_state *connector_state, 5465 const struct dc_stream_state *old_stream, 5466 int requested_bpc) 5467 { 5468 struct dc_crtc_timing *timing_out = &stream->timing; 5469 const struct drm_display_info *info = &connector->display_info; 5470 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 5471 struct hdmi_vendor_infoframe hv_frame; 5472 struct hdmi_avi_infoframe avi_frame; 5473 5474 memset(&hv_frame, 0, sizeof(hv_frame)); 5475 memset(&avi_frame, 0, sizeof(avi_frame)); 5476 5477 timing_out->h_border_left = 0; 5478 timing_out->h_border_right = 0; 5479 timing_out->v_border_top = 0; 5480 timing_out->v_border_bottom = 0; 5481 /* TODO: un-hardcode */ 5482 if (drm_mode_is_420_only(info, mode_in) 5483 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 5484 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 5485 else if (drm_mode_is_420_also(info, mode_in) 5486 && aconnector->force_yuv420_output) 5487 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 5488 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444) 5489 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 5490 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; 5491 else 5492 timing_out->pixel_encoding = PIXEL_ENCODING_RGB; 5493 5494 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; 5495 timing_out->display_color_depth = convert_color_depth_from_display_info( 5496 connector, 5497 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420), 5498 requested_bpc); 5499 timing_out->scan_type = SCANNING_TYPE_NODATA; 5500 timing_out->hdmi_vic = 0; 5501 5502 if (old_stream) { 5503 timing_out->vic = old_stream->timing.vic; 5504 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; 5505 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; 5506 } else { 5507 timing_out->vic = drm_match_cea_mode(mode_in); 5508 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) 5509 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; 5510 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) 5511 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; 5512 } 5513 5514 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { 5515 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in); 5516 timing_out->vic = avi_frame.video_code; 5517 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in); 5518 timing_out->hdmi_vic = hv_frame.vic; 5519 } 5520 5521 if (is_freesync_video_mode(mode_in, aconnector)) { 5522 timing_out->h_addressable = mode_in->hdisplay; 5523 timing_out->h_total = mode_in->htotal; 5524 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start; 5525 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay; 5526 timing_out->v_total = mode_in->vtotal; 5527 timing_out->v_addressable = mode_in->vdisplay; 5528 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay; 5529 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start; 5530 timing_out->pix_clk_100hz = mode_in->clock * 10; 5531 } else { 5532 timing_out->h_addressable = mode_in->crtc_hdisplay; 5533 timing_out->h_total = mode_in->crtc_htotal; 5534 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; 5535 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; 5536 timing_out->v_total = mode_in->crtc_vtotal; 5537 timing_out->v_addressable = mode_in->crtc_vdisplay; 5538 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; 5539 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; 5540 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; 5541 } 5542 5543 timing_out->aspect_ratio = get_aspect_ratio(mode_in); 5544 5545 stream->out_transfer_func->type = TF_TYPE_PREDEFINED; 5546 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; 5547 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { 5548 if (!adjust_colour_depth_from_display_info(timing_out, info) && 5549 drm_mode_is_420_also(info, mode_in) && 5550 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) { 5551 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 5552 adjust_colour_depth_from_display_info(timing_out, info); 5553 } 5554 } 5555 5556 stream->output_color_space = get_output_color_space(timing_out, connector_state); 5557 } 5558 5559 static void fill_audio_info(struct audio_info *audio_info, 5560 const struct drm_connector *drm_connector, 5561 const struct dc_sink *dc_sink) 5562 { 5563 int i = 0; 5564 int cea_revision = 0; 5565 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; 5566 5567 audio_info->manufacture_id = edid_caps->manufacturer_id; 5568 audio_info->product_id = edid_caps->product_id; 5569 5570 cea_revision = drm_connector->display_info.cea_rev; 5571 5572 strscpy(audio_info->display_name, 5573 edid_caps->display_name, 5574 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 5575 5576 if (cea_revision >= 3) { 5577 audio_info->mode_count = edid_caps->audio_mode_count; 5578 5579 for (i = 0; i < audio_info->mode_count; ++i) { 5580 audio_info->modes[i].format_code = 5581 (enum audio_format_code) 5582 (edid_caps->audio_modes[i].format_code); 5583 audio_info->modes[i].channel_count = 5584 edid_caps->audio_modes[i].channel_count; 5585 audio_info->modes[i].sample_rates.all = 5586 edid_caps->audio_modes[i].sample_rate; 5587 audio_info->modes[i].sample_size = 5588 edid_caps->audio_modes[i].sample_size; 5589 } 5590 } 5591 5592 audio_info->flags.all = edid_caps->speaker_flags; 5593 5594 /* TODO: We only check for the progressive mode, check for interlace mode too */ 5595 if (drm_connector->latency_present[0]) { 5596 audio_info->video_latency = drm_connector->video_latency[0]; 5597 audio_info->audio_latency = drm_connector->audio_latency[0]; 5598 } 5599 5600 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ 5601 5602 } 5603 5604 static void 5605 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, 5606 struct drm_display_mode *dst_mode) 5607 { 5608 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; 5609 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; 5610 dst_mode->crtc_clock = src_mode->crtc_clock; 5611 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; 5612 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; 5613 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; 5614 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; 5615 dst_mode->crtc_htotal = src_mode->crtc_htotal; 5616 dst_mode->crtc_hskew = src_mode->crtc_hskew; 5617 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; 5618 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; 5619 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; 5620 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; 5621 dst_mode->crtc_vtotal = src_mode->crtc_vtotal; 5622 } 5623 5624 static void 5625 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, 5626 const struct drm_display_mode *native_mode, 5627 bool scale_enabled) 5628 { 5629 if (scale_enabled) { 5630 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 5631 } else if (native_mode->clock == drm_mode->clock && 5632 native_mode->htotal == drm_mode->htotal && 5633 native_mode->vtotal == drm_mode->vtotal) { 5634 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 5635 } else { 5636 /* no scaling nor amdgpu inserted, no need to patch */ 5637 } 5638 } 5639 5640 static struct dc_sink * 5641 create_fake_sink(struct amdgpu_dm_connector *aconnector) 5642 { 5643 struct dc_sink_init_data sink_init_data = { 0 }; 5644 struct dc_sink *sink = NULL; 5645 5646 sink_init_data.link = aconnector->dc_link; 5647 sink_init_data.sink_signal = aconnector->dc_link->connector_signal; 5648 5649 sink = dc_sink_create(&sink_init_data); 5650 if (!sink) { 5651 DRM_ERROR("Failed to create sink!\n"); 5652 return NULL; 5653 } 5654 sink->sink_signal = SIGNAL_TYPE_VIRTUAL; 5655 5656 return sink; 5657 } 5658 5659 static void set_multisync_trigger_params( 5660 struct dc_stream_state *stream) 5661 { 5662 struct dc_stream_state *master = NULL; 5663 5664 if (stream->triggered_crtc_reset.enabled) { 5665 master = stream->triggered_crtc_reset.event_source; 5666 stream->triggered_crtc_reset.event = 5667 master->timing.flags.VSYNC_POSITIVE_POLARITY ? 5668 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING; 5669 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL; 5670 } 5671 } 5672 5673 static void set_master_stream(struct dc_stream_state *stream_set[], 5674 int stream_count) 5675 { 5676 int j, highest_rfr = 0, master_stream = 0; 5677 5678 for (j = 0; j < stream_count; j++) { 5679 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 5680 int refresh_rate = 0; 5681 5682 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ 5683 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 5684 if (refresh_rate > highest_rfr) { 5685 highest_rfr = refresh_rate; 5686 master_stream = j; 5687 } 5688 } 5689 } 5690 for (j = 0; j < stream_count; j++) { 5691 if (stream_set[j]) 5692 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 5693 } 5694 } 5695 5696 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 5697 { 5698 int i = 0; 5699 struct dc_stream_state *stream; 5700 5701 if (context->stream_count < 2) 5702 return; 5703 for (i = 0; i < context->stream_count ; i++) { 5704 if (!context->streams[i]) 5705 continue; 5706 /* 5707 * TODO: add a function to read AMD VSDB bits and set 5708 * crtc_sync_master.multi_sync_enabled flag 5709 * For now it's set to false 5710 */ 5711 } 5712 5713 set_master_stream(context->streams, context->stream_count); 5714 5715 for (i = 0; i < context->stream_count ; i++) { 5716 stream = context->streams[i]; 5717 5718 if (!stream) 5719 continue; 5720 5721 set_multisync_trigger_params(stream); 5722 } 5723 } 5724 5725 /** 5726 * DOC: FreeSync Video 5727 * 5728 * When a userspace application wants to play a video, the content follows a 5729 * standard format definition that usually specifies the FPS for that format. 5730 * The below list illustrates some video format and the expected FPS, 5731 * respectively: 5732 * 5733 * - TV/NTSC (23.976 FPS) 5734 * - Cinema (24 FPS) 5735 * - TV/PAL (25 FPS) 5736 * - TV/NTSC (29.97 FPS) 5737 * - TV/NTSC (30 FPS) 5738 * - Cinema HFR (48 FPS) 5739 * - TV/PAL (50 FPS) 5740 * - Commonly used (60 FPS) 5741 * - Multiples of 24 (48,72,96 FPS) 5742 * 5743 * The list of standards video format is not huge and can be added to the 5744 * connector modeset list beforehand. With that, userspace can leverage 5745 * FreeSync to extends the front porch in order to attain the target refresh 5746 * rate. Such a switch will happen seamlessly, without screen blanking or 5747 * reprogramming of the output in any other way. If the userspace requests a 5748 * modesetting change compatible with FreeSync modes that only differ in the 5749 * refresh rate, DC will skip the full update and avoid blink during the 5750 * transition. For example, the video player can change the modesetting from 5751 * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without 5752 * causing any display blink. This same concept can be applied to a mode 5753 * setting change. 5754 */ 5755 static struct drm_display_mode * 5756 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, 5757 bool use_probed_modes) 5758 { 5759 struct drm_display_mode *m, *m_pref = NULL; 5760 u16 current_refresh, highest_refresh; 5761 struct list_head *list_head = use_probed_modes ? 5762 &aconnector->base.probed_modes : 5763 &aconnector->base.modes; 5764 5765 if (aconnector->freesync_vid_base.clock != 0) 5766 return &aconnector->freesync_vid_base; 5767 5768 /* Find the preferred mode */ 5769 list_for_each_entry(m, list_head, head) { 5770 if (m->type & DRM_MODE_TYPE_PREFERRED) { 5771 m_pref = m; 5772 break; 5773 } 5774 } 5775 5776 if (!m_pref) { 5777 /* Probably an EDID with no preferred mode. Fallback to first entry */ 5778 m_pref = list_first_entry_or_null( 5779 &aconnector->base.modes, struct drm_display_mode, head); 5780 if (!m_pref) { 5781 DRM_DEBUG_DRIVER("No preferred mode found in EDID\n"); 5782 return NULL; 5783 } 5784 } 5785 5786 highest_refresh = drm_mode_vrefresh(m_pref); 5787 5788 /* 5789 * Find the mode with highest refresh rate with same resolution. 5790 * For some monitors, preferred mode is not the mode with highest 5791 * supported refresh rate. 5792 */ 5793 list_for_each_entry(m, list_head, head) { 5794 current_refresh = drm_mode_vrefresh(m); 5795 5796 if (m->hdisplay == m_pref->hdisplay && 5797 m->vdisplay == m_pref->vdisplay && 5798 highest_refresh < current_refresh) { 5799 highest_refresh = current_refresh; 5800 m_pref = m; 5801 } 5802 } 5803 5804 drm_mode_copy(&aconnector->freesync_vid_base, m_pref); 5805 return m_pref; 5806 } 5807 5808 static bool is_freesync_video_mode(const struct drm_display_mode *mode, 5809 struct amdgpu_dm_connector *aconnector) 5810 { 5811 struct drm_display_mode *high_mode; 5812 int timing_diff; 5813 5814 high_mode = get_highest_refresh_rate_mode(aconnector, false); 5815 if (!high_mode || !mode) 5816 return false; 5817 5818 timing_diff = high_mode->vtotal - mode->vtotal; 5819 5820 if (high_mode->clock == 0 || high_mode->clock != mode->clock || 5821 high_mode->hdisplay != mode->hdisplay || 5822 high_mode->vdisplay != mode->vdisplay || 5823 high_mode->hsync_start != mode->hsync_start || 5824 high_mode->hsync_end != mode->hsync_end || 5825 high_mode->htotal != mode->htotal || 5826 high_mode->hskew != mode->hskew || 5827 high_mode->vscan != mode->vscan || 5828 high_mode->vsync_start - mode->vsync_start != timing_diff || 5829 high_mode->vsync_end - mode->vsync_end != timing_diff) 5830 return false; 5831 else 5832 return true; 5833 } 5834 5835 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector, 5836 struct dc_sink *sink, struct dc_stream_state *stream, 5837 struct dsc_dec_dpcd_caps *dsc_caps) 5838 { 5839 stream->timing.flags.DSC = 0; 5840 dsc_caps->is_dsc_supported = false; 5841 5842 if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || 5843 sink->sink_signal == SIGNAL_TYPE_EDP)) { 5844 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE || 5845 sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) 5846 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, 5847 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, 5848 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, 5849 dsc_caps); 5850 } 5851 } 5852 5853 5854 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector, 5855 struct dc_sink *sink, struct dc_stream_state *stream, 5856 struct dsc_dec_dpcd_caps *dsc_caps, 5857 uint32_t max_dsc_target_bpp_limit_override) 5858 { 5859 const struct dc_link_settings *verified_link_cap = NULL; 5860 u32 link_bw_in_kbps; 5861 u32 edp_min_bpp_x16, edp_max_bpp_x16; 5862 struct dc *dc = sink->ctx->dc; 5863 struct dc_dsc_bw_range bw_range = {0}; 5864 struct dc_dsc_config dsc_cfg = {0}; 5865 struct dc_dsc_config_options dsc_options = {0}; 5866 5867 dc_dsc_get_default_config_option(dc, &dsc_options); 5868 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; 5869 5870 verified_link_cap = dc_link_get_link_cap(stream->link); 5871 link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap); 5872 edp_min_bpp_x16 = 8 * 16; 5873 edp_max_bpp_x16 = 8 * 16; 5874 5875 if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel) 5876 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel; 5877 5878 if (edp_max_bpp_x16 < edp_min_bpp_x16) 5879 edp_min_bpp_x16 = edp_max_bpp_x16; 5880 5881 if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0], 5882 dc->debug.dsc_min_slice_height_override, 5883 edp_min_bpp_x16, edp_max_bpp_x16, 5884 dsc_caps, 5885 &stream->timing, 5886 dc_link_get_highest_encoding_format(aconnector->dc_link), 5887 &bw_range)) { 5888 5889 if (bw_range.max_kbps < link_bw_in_kbps) { 5890 if (dc_dsc_compute_config(dc->res_pool->dscs[0], 5891 dsc_caps, 5892 &dsc_options, 5893 0, 5894 &stream->timing, 5895 dc_link_get_highest_encoding_format(aconnector->dc_link), 5896 &dsc_cfg)) { 5897 stream->timing.dsc_cfg = dsc_cfg; 5898 stream->timing.flags.DSC = 1; 5899 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16; 5900 } 5901 return; 5902 } 5903 } 5904 5905 if (dc_dsc_compute_config(dc->res_pool->dscs[0], 5906 dsc_caps, 5907 &dsc_options, 5908 link_bw_in_kbps, 5909 &stream->timing, 5910 dc_link_get_highest_encoding_format(aconnector->dc_link), 5911 &dsc_cfg)) { 5912 stream->timing.dsc_cfg = dsc_cfg; 5913 stream->timing.flags.DSC = 1; 5914 } 5915 } 5916 5917 5918 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, 5919 struct dc_sink *sink, struct dc_stream_state *stream, 5920 struct dsc_dec_dpcd_caps *dsc_caps) 5921 { 5922 struct drm_connector *drm_connector = &aconnector->base; 5923 u32 link_bandwidth_kbps; 5924 struct dc *dc = sink->ctx->dc; 5925 u32 max_supported_bw_in_kbps, timing_bw_in_kbps; 5926 u32 dsc_max_supported_bw_in_kbps; 5927 u32 max_dsc_target_bpp_limit_override = 5928 drm_connector->display_info.max_dsc_bpp; 5929 struct dc_dsc_config_options dsc_options = {0}; 5930 5931 dc_dsc_get_default_config_option(dc, &dsc_options); 5932 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; 5933 5934 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, 5935 dc_link_get_link_cap(aconnector->dc_link)); 5936 5937 /* Set DSC policy according to dsc_clock_en */ 5938 dc_dsc_policy_set_enable_dsc_when_not_needed( 5939 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE); 5940 5941 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP && 5942 !aconnector->dc_link->panel_config.dsc.disable_dsc_edp && 5943 dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) { 5944 5945 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override); 5946 5947 } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { 5948 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { 5949 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 5950 dsc_caps, 5951 &dsc_options, 5952 link_bandwidth_kbps, 5953 &stream->timing, 5954 dc_link_get_highest_encoding_format(aconnector->dc_link), 5955 &stream->timing.dsc_cfg)) { 5956 stream->timing.flags.DSC = 1; 5957 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name); 5958 } 5959 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { 5960 timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing, 5961 dc_link_get_highest_encoding_format(aconnector->dc_link)); 5962 max_supported_bw_in_kbps = link_bandwidth_kbps; 5963 dsc_max_supported_bw_in_kbps = link_bandwidth_kbps; 5964 5965 if (timing_bw_in_kbps > max_supported_bw_in_kbps && 5966 max_supported_bw_in_kbps > 0 && 5967 dsc_max_supported_bw_in_kbps > 0) 5968 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 5969 dsc_caps, 5970 &dsc_options, 5971 dsc_max_supported_bw_in_kbps, 5972 &stream->timing, 5973 dc_link_get_highest_encoding_format(aconnector->dc_link), 5974 &stream->timing.dsc_cfg)) { 5975 stream->timing.flags.DSC = 1; 5976 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n", 5977 __func__, drm_connector->name); 5978 } 5979 } 5980 } 5981 5982 /* Overwrite the stream flag if DSC is enabled through debugfs */ 5983 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE) 5984 stream->timing.flags.DSC = 1; 5985 5986 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h) 5987 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; 5988 5989 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v) 5990 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; 5991 5992 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel) 5993 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel; 5994 } 5995 5996 static struct dc_stream_state * 5997 create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 5998 const struct drm_display_mode *drm_mode, 5999 const struct dm_connector_state *dm_state, 6000 const struct dc_stream_state *old_stream, 6001 int requested_bpc) 6002 { 6003 struct drm_display_mode *preferred_mode = NULL; 6004 struct drm_connector *drm_connector; 6005 const struct drm_connector_state *con_state = &dm_state->base; 6006 struct dc_stream_state *stream = NULL; 6007 struct drm_display_mode mode; 6008 struct drm_display_mode saved_mode; 6009 struct drm_display_mode *freesync_mode = NULL; 6010 bool native_mode_found = false; 6011 bool recalculate_timing = false; 6012 bool scale = dm_state->scaling != RMX_OFF; 6013 int mode_refresh; 6014 int preferred_refresh = 0; 6015 enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN; 6016 struct dsc_dec_dpcd_caps dsc_caps; 6017 6018 struct dc_sink *sink = NULL; 6019 6020 drm_mode_init(&mode, drm_mode); 6021 memset(&saved_mode, 0, sizeof(saved_mode)); 6022 6023 if (aconnector == NULL) { 6024 DRM_ERROR("aconnector is NULL!\n"); 6025 return stream; 6026 } 6027 6028 drm_connector = &aconnector->base; 6029 6030 if (!aconnector->dc_sink) { 6031 sink = create_fake_sink(aconnector); 6032 if (!sink) 6033 return stream; 6034 } else { 6035 sink = aconnector->dc_sink; 6036 dc_sink_retain(sink); 6037 } 6038 6039 stream = dc_create_stream_for_sink(sink); 6040 6041 if (stream == NULL) { 6042 DRM_ERROR("Failed to create stream for sink!\n"); 6043 goto finish; 6044 } 6045 6046 stream->dm_stream_context = aconnector; 6047 6048 stream->timing.flags.LTE_340MCSC_SCRAMBLE = 6049 drm_connector->display_info.hdmi.scdc.scrambling.low_rates; 6050 6051 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) { 6052 /* Search for preferred mode */ 6053 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { 6054 native_mode_found = true; 6055 break; 6056 } 6057 } 6058 if (!native_mode_found) 6059 preferred_mode = list_first_entry_or_null( 6060 &aconnector->base.modes, 6061 struct drm_display_mode, 6062 head); 6063 6064 mode_refresh = drm_mode_vrefresh(&mode); 6065 6066 if (preferred_mode == NULL) { 6067 /* 6068 * This may not be an error, the use case is when we have no 6069 * usermode calls to reset and set mode upon hotplug. In this 6070 * case, we call set mode ourselves to restore the previous mode 6071 * and the modelist may not be filled in time. 6072 */ 6073 DRM_DEBUG_DRIVER("No preferred mode found\n"); 6074 } else { 6075 recalculate_timing = is_freesync_video_mode(&mode, aconnector); 6076 if (recalculate_timing) { 6077 freesync_mode = get_highest_refresh_rate_mode(aconnector, false); 6078 drm_mode_copy(&saved_mode, &mode); 6079 saved_mode.picture_aspect_ratio = mode.picture_aspect_ratio; 6080 drm_mode_copy(&mode, freesync_mode); 6081 mode.picture_aspect_ratio = saved_mode.picture_aspect_ratio; 6082 } else { 6083 decide_crtc_timing_for_drm_display_mode( 6084 &mode, preferred_mode, scale); 6085 6086 preferred_refresh = drm_mode_vrefresh(preferred_mode); 6087 } 6088 } 6089 6090 if (recalculate_timing) 6091 drm_mode_set_crtcinfo(&saved_mode, 0); 6092 6093 /* 6094 * If scaling is enabled and refresh rate didn't change 6095 * we copy the vic and polarities of the old timings 6096 */ 6097 if (!scale || mode_refresh != preferred_refresh) 6098 fill_stream_properties_from_drm_display_mode( 6099 stream, &mode, &aconnector->base, con_state, NULL, 6100 requested_bpc); 6101 else 6102 fill_stream_properties_from_drm_display_mode( 6103 stream, &mode, &aconnector->base, con_state, old_stream, 6104 requested_bpc); 6105 6106 if (aconnector->timing_changed) { 6107 DC_LOG_DEBUG("%s: overriding timing for automated test, bpc %d, changing to %d\n", 6108 __func__, 6109 stream->timing.display_color_depth, 6110 aconnector->timing_requested->display_color_depth); 6111 stream->timing = *aconnector->timing_requested; 6112 } 6113 6114 /* SST DSC determination policy */ 6115 update_dsc_caps(aconnector, sink, stream, &dsc_caps); 6116 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) 6117 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps); 6118 6119 update_stream_scaling_settings(&mode, dm_state, stream); 6120 6121 fill_audio_info( 6122 &stream->audio_info, 6123 drm_connector, 6124 sink); 6125 6126 update_stream_signal(stream, sink); 6127 6128 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 6129 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket); 6130 else if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 6131 stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST || 6132 stream->signal == SIGNAL_TYPE_EDP) { 6133 // 6134 // should decide stream support vsc sdp colorimetry capability 6135 // before building vsc info packet 6136 // 6137 stream->use_vsc_sdp_for_colorimetry = false; 6138 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 6139 stream->use_vsc_sdp_for_colorimetry = 6140 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported; 6141 } else { 6142 if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) 6143 stream->use_vsc_sdp_for_colorimetry = true; 6144 } 6145 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) 6146 tf = TRANSFER_FUNC_GAMMA_22; 6147 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf); 6148 6149 if (stream->link->psr_settings.psr_feature_enabled) 6150 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY; 6151 } 6152 finish: 6153 dc_sink_release(sink); 6154 6155 return stream; 6156 } 6157 6158 static enum drm_connector_status 6159 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) 6160 { 6161 bool connected; 6162 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6163 6164 /* 6165 * Notes: 6166 * 1. This interface is NOT called in context of HPD irq. 6167 * 2. This interface *is called* in context of user-mode ioctl. Which 6168 * makes it a bad place for *any* MST-related activity. 6169 */ 6170 6171 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && 6172 !aconnector->fake_enable) 6173 connected = (aconnector->dc_sink != NULL); 6174 else 6175 connected = (aconnector->base.force == DRM_FORCE_ON || 6176 aconnector->base.force == DRM_FORCE_ON_DIGITAL); 6177 6178 update_subconnector_property(aconnector); 6179 6180 return (connected ? connector_status_connected : 6181 connector_status_disconnected); 6182 } 6183 6184 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 6185 struct drm_connector_state *connector_state, 6186 struct drm_property *property, 6187 uint64_t val) 6188 { 6189 struct drm_device *dev = connector->dev; 6190 struct amdgpu_device *adev = drm_to_adev(dev); 6191 struct dm_connector_state *dm_old_state = 6192 to_dm_connector_state(connector->state); 6193 struct dm_connector_state *dm_new_state = 6194 to_dm_connector_state(connector_state); 6195 6196 int ret = -EINVAL; 6197 6198 if (property == dev->mode_config.scaling_mode_property) { 6199 enum amdgpu_rmx_type rmx_type; 6200 6201 switch (val) { 6202 case DRM_MODE_SCALE_CENTER: 6203 rmx_type = RMX_CENTER; 6204 break; 6205 case DRM_MODE_SCALE_ASPECT: 6206 rmx_type = RMX_ASPECT; 6207 break; 6208 case DRM_MODE_SCALE_FULLSCREEN: 6209 rmx_type = RMX_FULL; 6210 break; 6211 case DRM_MODE_SCALE_NONE: 6212 default: 6213 rmx_type = RMX_OFF; 6214 break; 6215 } 6216 6217 if (dm_old_state->scaling == rmx_type) 6218 return 0; 6219 6220 dm_new_state->scaling = rmx_type; 6221 ret = 0; 6222 } else if (property == adev->mode_info.underscan_hborder_property) { 6223 dm_new_state->underscan_hborder = val; 6224 ret = 0; 6225 } else if (property == adev->mode_info.underscan_vborder_property) { 6226 dm_new_state->underscan_vborder = val; 6227 ret = 0; 6228 } else if (property == adev->mode_info.underscan_property) { 6229 dm_new_state->underscan_enable = val; 6230 ret = 0; 6231 } else if (property == adev->mode_info.abm_level_property) { 6232 dm_new_state->abm_level = val ?: ABM_LEVEL_IMMEDIATE_DISABLE; 6233 ret = 0; 6234 } 6235 6236 return ret; 6237 } 6238 6239 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 6240 const struct drm_connector_state *state, 6241 struct drm_property *property, 6242 uint64_t *val) 6243 { 6244 struct drm_device *dev = connector->dev; 6245 struct amdgpu_device *adev = drm_to_adev(dev); 6246 struct dm_connector_state *dm_state = 6247 to_dm_connector_state(state); 6248 int ret = -EINVAL; 6249 6250 if (property == dev->mode_config.scaling_mode_property) { 6251 switch (dm_state->scaling) { 6252 case RMX_CENTER: 6253 *val = DRM_MODE_SCALE_CENTER; 6254 break; 6255 case RMX_ASPECT: 6256 *val = DRM_MODE_SCALE_ASPECT; 6257 break; 6258 case RMX_FULL: 6259 *val = DRM_MODE_SCALE_FULLSCREEN; 6260 break; 6261 case RMX_OFF: 6262 default: 6263 *val = DRM_MODE_SCALE_NONE; 6264 break; 6265 } 6266 ret = 0; 6267 } else if (property == adev->mode_info.underscan_hborder_property) { 6268 *val = dm_state->underscan_hborder; 6269 ret = 0; 6270 } else if (property == adev->mode_info.underscan_vborder_property) { 6271 *val = dm_state->underscan_vborder; 6272 ret = 0; 6273 } else if (property == adev->mode_info.underscan_property) { 6274 *val = dm_state->underscan_enable; 6275 ret = 0; 6276 } else if (property == adev->mode_info.abm_level_property) { 6277 *val = (dm_state->abm_level != ABM_LEVEL_IMMEDIATE_DISABLE) ? 6278 dm_state->abm_level : 0; 6279 ret = 0; 6280 } 6281 6282 return ret; 6283 } 6284 6285 static void amdgpu_dm_connector_unregister(struct drm_connector *connector) 6286 { 6287 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); 6288 6289 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); 6290 } 6291 6292 static void amdgpu_dm_connector_destroy(struct drm_connector *connector) 6293 { 6294 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6295 struct amdgpu_device *adev = drm_to_adev(connector->dev); 6296 struct amdgpu_display_manager *dm = &adev->dm; 6297 6298 /* 6299 * Call only if mst_mgr was initialized before since it's not done 6300 * for all connector types. 6301 */ 6302 if (aconnector->mst_mgr.dev) 6303 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr); 6304 6305 if (aconnector->bl_idx != -1) { 6306 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]); 6307 dm->backlight_dev[aconnector->bl_idx] = NULL; 6308 } 6309 6310 if (aconnector->dc_em_sink) 6311 dc_sink_release(aconnector->dc_em_sink); 6312 aconnector->dc_em_sink = NULL; 6313 if (aconnector->dc_sink) 6314 dc_sink_release(aconnector->dc_sink); 6315 aconnector->dc_sink = NULL; 6316 6317 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); 6318 drm_connector_unregister(connector); 6319 drm_connector_cleanup(connector); 6320 if (aconnector->i2c) { 6321 i2c_del_adapter(&aconnector->i2c->base); 6322 kfree(aconnector->i2c); 6323 } 6324 kfree(aconnector->dm_dp_aux.aux.name); 6325 6326 kfree(connector); 6327 } 6328 6329 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) 6330 { 6331 struct dm_connector_state *state = 6332 to_dm_connector_state(connector->state); 6333 6334 if (connector->state) 6335 __drm_atomic_helper_connector_destroy_state(connector->state); 6336 6337 kfree(state); 6338 6339 state = kzalloc(sizeof(*state), GFP_KERNEL); 6340 6341 if (state) { 6342 state->scaling = RMX_OFF; 6343 state->underscan_enable = false; 6344 state->underscan_hborder = 0; 6345 state->underscan_vborder = 0; 6346 state->base.max_requested_bpc = 8; 6347 state->vcpi_slots = 0; 6348 state->pbn = 0; 6349 6350 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 6351 state->abm_level = amdgpu_dm_abm_level ?: 6352 ABM_LEVEL_IMMEDIATE_DISABLE; 6353 6354 __drm_atomic_helper_connector_reset(connector, &state->base); 6355 } 6356 } 6357 6358 struct drm_connector_state * 6359 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) 6360 { 6361 struct dm_connector_state *state = 6362 to_dm_connector_state(connector->state); 6363 6364 struct dm_connector_state *new_state = 6365 kmemdup(state, sizeof(*state), GFP_KERNEL); 6366 6367 if (!new_state) 6368 return NULL; 6369 6370 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 6371 6372 new_state->freesync_capable = state->freesync_capable; 6373 new_state->abm_level = state->abm_level; 6374 new_state->scaling = state->scaling; 6375 new_state->underscan_enable = state->underscan_enable; 6376 new_state->underscan_hborder = state->underscan_hborder; 6377 new_state->underscan_vborder = state->underscan_vborder; 6378 new_state->vcpi_slots = state->vcpi_slots; 6379 new_state->pbn = state->pbn; 6380 return &new_state->base; 6381 } 6382 6383 static int 6384 amdgpu_dm_connector_late_register(struct drm_connector *connector) 6385 { 6386 struct amdgpu_dm_connector *amdgpu_dm_connector = 6387 to_amdgpu_dm_connector(connector); 6388 int r; 6389 6390 amdgpu_dm_register_backlight_device(amdgpu_dm_connector); 6391 6392 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 6393 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 6394 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev; 6395 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux); 6396 if (r) 6397 return r; 6398 } 6399 6400 #if defined(CONFIG_DEBUG_FS) 6401 connector_debugfs_init(amdgpu_dm_connector); 6402 #endif 6403 6404 return 0; 6405 } 6406 6407 static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) 6408 { 6409 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6410 struct dc_link *dc_link = aconnector->dc_link; 6411 struct dc_sink *dc_em_sink = aconnector->dc_em_sink; 6412 struct edid *edid; 6413 6414 if (!connector->edid_override) 6415 return; 6416 6417 drm_edid_override_connector_update(&aconnector->base); 6418 edid = aconnector->base.edid_blob_ptr->data; 6419 aconnector->edid = edid; 6420 6421 /* Update emulated (virtual) sink's EDID */ 6422 if (dc_em_sink && dc_link) { 6423 memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps)); 6424 memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH); 6425 dm_helpers_parse_edid_caps( 6426 dc_link, 6427 &dc_em_sink->dc_edid, 6428 &dc_em_sink->edid_caps); 6429 } 6430 } 6431 6432 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { 6433 .reset = amdgpu_dm_connector_funcs_reset, 6434 .detect = amdgpu_dm_connector_detect, 6435 .fill_modes = drm_helper_probe_single_connector_modes, 6436 .destroy = amdgpu_dm_connector_destroy, 6437 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 6438 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 6439 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 6440 .atomic_get_property = amdgpu_dm_connector_atomic_get_property, 6441 .late_register = amdgpu_dm_connector_late_register, 6442 .early_unregister = amdgpu_dm_connector_unregister, 6443 .force = amdgpu_dm_connector_funcs_force 6444 }; 6445 6446 static int get_modes(struct drm_connector *connector) 6447 { 6448 return amdgpu_dm_connector_get_modes(connector); 6449 } 6450 6451 static void create_eml_sink(struct amdgpu_dm_connector *aconnector) 6452 { 6453 struct dc_sink_init_data init_params = { 6454 .link = aconnector->dc_link, 6455 .sink_signal = SIGNAL_TYPE_VIRTUAL 6456 }; 6457 struct edid *edid; 6458 6459 if (!aconnector->base.edid_blob_ptr) { 6460 /* if connector->edid_override valid, pass 6461 * it to edid_override to edid_blob_ptr 6462 */ 6463 6464 drm_edid_override_connector_update(&aconnector->base); 6465 6466 if (!aconnector->base.edid_blob_ptr) { 6467 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n", 6468 aconnector->base.name); 6469 6470 aconnector->base.force = DRM_FORCE_OFF; 6471 return; 6472 } 6473 } 6474 6475 edid = (struct edid *) aconnector->base.edid_blob_ptr->data; 6476 6477 aconnector->edid = edid; 6478 6479 aconnector->dc_em_sink = dc_link_add_remote_sink( 6480 aconnector->dc_link, 6481 (uint8_t *)edid, 6482 (edid->extensions + 1) * EDID_LENGTH, 6483 &init_params); 6484 6485 if (aconnector->base.force == DRM_FORCE_ON) { 6486 aconnector->dc_sink = aconnector->dc_link->local_sink ? 6487 aconnector->dc_link->local_sink : 6488 aconnector->dc_em_sink; 6489 dc_sink_retain(aconnector->dc_sink); 6490 } 6491 } 6492 6493 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) 6494 { 6495 struct dc_link *link = (struct dc_link *)aconnector->dc_link; 6496 6497 /* 6498 * In case of headless boot with force on for DP managed connector 6499 * Those settings have to be != 0 to get initial modeset 6500 */ 6501 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { 6502 link->verified_link_cap.lane_count = LANE_COUNT_FOUR; 6503 link->verified_link_cap.link_rate = LINK_RATE_HIGH2; 6504 } 6505 6506 create_eml_sink(aconnector); 6507 } 6508 6509 static enum dc_status dm_validate_stream_and_context(struct dc *dc, 6510 struct dc_stream_state *stream) 6511 { 6512 enum dc_status dc_result = DC_ERROR_UNEXPECTED; 6513 struct dc_plane_state *dc_plane_state = NULL; 6514 struct dc_state *dc_state = NULL; 6515 6516 if (!stream) 6517 goto cleanup; 6518 6519 dc_plane_state = dc_create_plane_state(dc); 6520 if (!dc_plane_state) 6521 goto cleanup; 6522 6523 dc_state = dc_create_state(dc); 6524 if (!dc_state) 6525 goto cleanup; 6526 6527 /* populate stream to plane */ 6528 dc_plane_state->src_rect.height = stream->src.height; 6529 dc_plane_state->src_rect.width = stream->src.width; 6530 dc_plane_state->dst_rect.height = stream->src.height; 6531 dc_plane_state->dst_rect.width = stream->src.width; 6532 dc_plane_state->clip_rect.height = stream->src.height; 6533 dc_plane_state->clip_rect.width = stream->src.width; 6534 dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256; 6535 dc_plane_state->plane_size.surface_size.height = stream->src.height; 6536 dc_plane_state->plane_size.surface_size.width = stream->src.width; 6537 dc_plane_state->plane_size.chroma_size.height = stream->src.height; 6538 dc_plane_state->plane_size.chroma_size.width = stream->src.width; 6539 dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 6540 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; 6541 dc_plane_state->rotation = ROTATION_ANGLE_0; 6542 dc_plane_state->is_tiling_rotated = false; 6543 dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL; 6544 6545 dc_result = dc_validate_stream(dc, stream); 6546 if (dc_result == DC_OK) 6547 dc_result = dc_validate_plane(dc, dc_plane_state); 6548 6549 if (dc_result == DC_OK) 6550 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream); 6551 6552 if (dc_result == DC_OK && !dc_add_plane_to_context( 6553 dc, 6554 stream, 6555 dc_plane_state, 6556 dc_state)) 6557 dc_result = DC_FAIL_ATTACH_SURFACES; 6558 6559 if (dc_result == DC_OK) 6560 dc_result = dc_validate_global_state(dc, dc_state, true); 6561 6562 cleanup: 6563 if (dc_state) 6564 dc_release_state(dc_state); 6565 6566 if (dc_plane_state) 6567 dc_plane_state_release(dc_plane_state); 6568 6569 return dc_result; 6570 } 6571 6572 struct dc_stream_state * 6573 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, 6574 const struct drm_display_mode *drm_mode, 6575 const struct dm_connector_state *dm_state, 6576 const struct dc_stream_state *old_stream) 6577 { 6578 struct drm_connector *connector = &aconnector->base; 6579 struct amdgpu_device *adev = drm_to_adev(connector->dev); 6580 struct dc_stream_state *stream; 6581 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL; 6582 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8; 6583 enum dc_status dc_result = DC_OK; 6584 6585 do { 6586 stream = create_stream_for_sink(aconnector, drm_mode, 6587 dm_state, old_stream, 6588 requested_bpc); 6589 if (stream == NULL) { 6590 DRM_ERROR("Failed to create stream for sink!\n"); 6591 break; 6592 } 6593 6594 dc_result = dc_validate_stream(adev->dm.dc, stream); 6595 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 6596 dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream); 6597 6598 if (dc_result == DC_OK) 6599 dc_result = dm_validate_stream_and_context(adev->dm.dc, stream); 6600 6601 if (dc_result != DC_OK) { 6602 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n", 6603 drm_mode->hdisplay, 6604 drm_mode->vdisplay, 6605 drm_mode->clock, 6606 dc_result, 6607 dc_status_to_str(dc_result)); 6608 6609 dc_stream_release(stream); 6610 stream = NULL; 6611 requested_bpc -= 2; /* lower bpc to retry validation */ 6612 } 6613 6614 } while (stream == NULL && requested_bpc >= 6); 6615 6616 if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) { 6617 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n"); 6618 6619 aconnector->force_yuv420_output = true; 6620 stream = create_validate_stream_for_sink(aconnector, drm_mode, 6621 dm_state, old_stream); 6622 aconnector->force_yuv420_output = false; 6623 } 6624 6625 return stream; 6626 } 6627 6628 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 6629 struct drm_display_mode *mode) 6630 { 6631 int result = MODE_ERROR; 6632 struct dc_sink *dc_sink; 6633 /* TODO: Unhardcode stream count */ 6634 struct dc_stream_state *stream; 6635 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6636 6637 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || 6638 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) 6639 return result; 6640 6641 /* 6642 * Only run this the first time mode_valid is called to initilialize 6643 * EDID mgmt 6644 */ 6645 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && 6646 !aconnector->dc_em_sink) 6647 handle_edid_mgmt(aconnector); 6648 6649 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; 6650 6651 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL && 6652 aconnector->base.force != DRM_FORCE_ON) { 6653 DRM_ERROR("dc_sink is NULL!\n"); 6654 goto fail; 6655 } 6656 6657 drm_mode_set_crtcinfo(mode, 0); 6658 6659 stream = create_validate_stream_for_sink(aconnector, mode, 6660 to_dm_connector_state(connector->state), 6661 NULL); 6662 if (stream) { 6663 dc_stream_release(stream); 6664 result = MODE_OK; 6665 } 6666 6667 fail: 6668 /* TODO: error handling*/ 6669 return result; 6670 } 6671 6672 static int fill_hdr_info_packet(const struct drm_connector_state *state, 6673 struct dc_info_packet *out) 6674 { 6675 struct hdmi_drm_infoframe frame; 6676 unsigned char buf[30]; /* 26 + 4 */ 6677 ssize_t len; 6678 int ret, i; 6679 6680 memset(out, 0, sizeof(*out)); 6681 6682 if (!state->hdr_output_metadata) 6683 return 0; 6684 6685 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state); 6686 if (ret) 6687 return ret; 6688 6689 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf)); 6690 if (len < 0) 6691 return (int)len; 6692 6693 /* Static metadata is a fixed 26 bytes + 4 byte header. */ 6694 if (len != 30) 6695 return -EINVAL; 6696 6697 /* Prepare the infopacket for DC. */ 6698 switch (state->connector->connector_type) { 6699 case DRM_MODE_CONNECTOR_HDMIA: 6700 out->hb0 = 0x87; /* type */ 6701 out->hb1 = 0x01; /* version */ 6702 out->hb2 = 0x1A; /* length */ 6703 out->sb[0] = buf[3]; /* checksum */ 6704 i = 1; 6705 break; 6706 6707 case DRM_MODE_CONNECTOR_DisplayPort: 6708 case DRM_MODE_CONNECTOR_eDP: 6709 out->hb0 = 0x00; /* sdp id, zero */ 6710 out->hb1 = 0x87; /* type */ 6711 out->hb2 = 0x1D; /* payload len - 1 */ 6712 out->hb3 = (0x13 << 2); /* sdp version */ 6713 out->sb[0] = 0x01; /* version */ 6714 out->sb[1] = 0x1A; /* length */ 6715 i = 2; 6716 break; 6717 6718 default: 6719 return -EINVAL; 6720 } 6721 6722 memcpy(&out->sb[i], &buf[4], 26); 6723 out->valid = true; 6724 6725 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb, 6726 sizeof(out->sb), false); 6727 6728 return 0; 6729 } 6730 6731 static int 6732 amdgpu_dm_connector_atomic_check(struct drm_connector *conn, 6733 struct drm_atomic_state *state) 6734 { 6735 struct drm_connector_state *new_con_state = 6736 drm_atomic_get_new_connector_state(state, conn); 6737 struct drm_connector_state *old_con_state = 6738 drm_atomic_get_old_connector_state(state, conn); 6739 struct drm_crtc *crtc = new_con_state->crtc; 6740 struct drm_crtc_state *new_crtc_state; 6741 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn); 6742 int ret; 6743 6744 trace_amdgpu_dm_connector_atomic_check(new_con_state); 6745 6746 if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 6747 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr); 6748 if (ret < 0) 6749 return ret; 6750 } 6751 6752 if (!crtc) 6753 return 0; 6754 6755 if (new_con_state->colorspace != old_con_state->colorspace) { 6756 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 6757 if (IS_ERR(new_crtc_state)) 6758 return PTR_ERR(new_crtc_state); 6759 6760 new_crtc_state->mode_changed = true; 6761 } 6762 6763 if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) { 6764 struct dc_info_packet hdr_infopacket; 6765 6766 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket); 6767 if (ret) 6768 return ret; 6769 6770 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 6771 if (IS_ERR(new_crtc_state)) 6772 return PTR_ERR(new_crtc_state); 6773 6774 /* 6775 * DC considers the stream backends changed if the 6776 * static metadata changes. Forcing the modeset also 6777 * gives a simple way for userspace to switch from 6778 * 8bpc to 10bpc when setting the metadata to enter 6779 * or exit HDR. 6780 * 6781 * Changing the static metadata after it's been 6782 * set is permissible, however. So only force a 6783 * modeset if we're entering or exiting HDR. 6784 */ 6785 new_crtc_state->mode_changed = new_crtc_state->mode_changed || 6786 !old_con_state->hdr_output_metadata || 6787 !new_con_state->hdr_output_metadata; 6788 } 6789 6790 return 0; 6791 } 6792 6793 static const struct drm_connector_helper_funcs 6794 amdgpu_dm_connector_helper_funcs = { 6795 /* 6796 * If hotplugging a second bigger display in FB Con mode, bigger resolution 6797 * modes will be filtered by drm_mode_validate_size(), and those modes 6798 * are missing after user start lightdm. So we need to renew modes list. 6799 * in get_modes call back, not just return the modes count 6800 */ 6801 .get_modes = get_modes, 6802 .mode_valid = amdgpu_dm_connector_mode_valid, 6803 .atomic_check = amdgpu_dm_connector_atomic_check, 6804 }; 6805 6806 static void dm_encoder_helper_disable(struct drm_encoder *encoder) 6807 { 6808 6809 } 6810 6811 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) 6812 { 6813 switch (display_color_depth) { 6814 case COLOR_DEPTH_666: 6815 return 6; 6816 case COLOR_DEPTH_888: 6817 return 8; 6818 case COLOR_DEPTH_101010: 6819 return 10; 6820 case COLOR_DEPTH_121212: 6821 return 12; 6822 case COLOR_DEPTH_141414: 6823 return 14; 6824 case COLOR_DEPTH_161616: 6825 return 16; 6826 default: 6827 break; 6828 } 6829 return 0; 6830 } 6831 6832 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 6833 struct drm_crtc_state *crtc_state, 6834 struct drm_connector_state *conn_state) 6835 { 6836 struct drm_atomic_state *state = crtc_state->state; 6837 struct drm_connector *connector = conn_state->connector; 6838 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6839 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state); 6840 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 6841 struct drm_dp_mst_topology_mgr *mst_mgr; 6842 struct drm_dp_mst_port *mst_port; 6843 struct drm_dp_mst_topology_state *mst_state; 6844 enum dc_color_depth color_depth; 6845 int clock, bpp = 0; 6846 bool is_y420 = false; 6847 6848 if (!aconnector->mst_output_port) 6849 return 0; 6850 6851 mst_port = aconnector->mst_output_port; 6852 mst_mgr = &aconnector->mst_root->mst_mgr; 6853 6854 if (!crtc_state->connectors_changed && !crtc_state->mode_changed) 6855 return 0; 6856 6857 mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr); 6858 if (IS_ERR(mst_state)) 6859 return PTR_ERR(mst_state); 6860 6861 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link); 6862 6863 if (!state->duplicated) { 6864 int max_bpc = conn_state->max_requested_bpc; 6865 6866 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) && 6867 aconnector->force_yuv420_output; 6868 color_depth = convert_color_depth_from_display_info(connector, 6869 is_y420, 6870 max_bpc); 6871 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3; 6872 clock = adjusted_mode->clock; 6873 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4); 6874 } 6875 6876 dm_new_connector_state->vcpi_slots = 6877 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port, 6878 dm_new_connector_state->pbn); 6879 if (dm_new_connector_state->vcpi_slots < 0) { 6880 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); 6881 return dm_new_connector_state->vcpi_slots; 6882 } 6883 return 0; 6884 } 6885 6886 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { 6887 .disable = dm_encoder_helper_disable, 6888 .atomic_check = dm_encoder_helper_atomic_check 6889 }; 6890 6891 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, 6892 struct dc_state *dc_state, 6893 struct dsc_mst_fairness_vars *vars) 6894 { 6895 struct dc_stream_state *stream = NULL; 6896 struct drm_connector *connector; 6897 struct drm_connector_state *new_con_state; 6898 struct amdgpu_dm_connector *aconnector; 6899 struct dm_connector_state *dm_conn_state; 6900 int i, j, ret; 6901 int vcpi, pbn_div, pbn, slot_num = 0; 6902 6903 for_each_new_connector_in_state(state, connector, new_con_state, i) { 6904 6905 aconnector = to_amdgpu_dm_connector(connector); 6906 6907 if (!aconnector->mst_output_port) 6908 continue; 6909 6910 if (!new_con_state || !new_con_state->crtc) 6911 continue; 6912 6913 dm_conn_state = to_dm_connector_state(new_con_state); 6914 6915 for (j = 0; j < dc_state->stream_count; j++) { 6916 stream = dc_state->streams[j]; 6917 if (!stream) 6918 continue; 6919 6920 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector) 6921 break; 6922 6923 stream = NULL; 6924 } 6925 6926 if (!stream) 6927 continue; 6928 6929 pbn_div = dm_mst_get_pbn_divider(stream->link); 6930 /* pbn is calculated by compute_mst_dsc_configs_for_state*/ 6931 for (j = 0; j < dc_state->stream_count; j++) { 6932 if (vars[j].aconnector == aconnector) { 6933 pbn = vars[j].pbn; 6934 break; 6935 } 6936 } 6937 6938 if (j == dc_state->stream_count) 6939 continue; 6940 6941 slot_num = DIV_ROUND_UP(pbn, pbn_div); 6942 6943 if (stream->timing.flags.DSC != 1) { 6944 dm_conn_state->pbn = pbn; 6945 dm_conn_state->vcpi_slots = slot_num; 6946 6947 ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, 6948 dm_conn_state->pbn, false); 6949 if (ret < 0) 6950 return ret; 6951 6952 continue; 6953 } 6954 6955 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true); 6956 if (vcpi < 0) 6957 return vcpi; 6958 6959 dm_conn_state->pbn = pbn; 6960 dm_conn_state->vcpi_slots = vcpi; 6961 } 6962 return 0; 6963 } 6964 6965 static int to_drm_connector_type(enum amd_signal_type st) 6966 { 6967 switch (st) { 6968 case SIGNAL_TYPE_HDMI_TYPE_A: 6969 return DRM_MODE_CONNECTOR_HDMIA; 6970 case SIGNAL_TYPE_EDP: 6971 return DRM_MODE_CONNECTOR_eDP; 6972 case SIGNAL_TYPE_LVDS: 6973 return DRM_MODE_CONNECTOR_LVDS; 6974 case SIGNAL_TYPE_RGB: 6975 return DRM_MODE_CONNECTOR_VGA; 6976 case SIGNAL_TYPE_DISPLAY_PORT: 6977 case SIGNAL_TYPE_DISPLAY_PORT_MST: 6978 return DRM_MODE_CONNECTOR_DisplayPort; 6979 case SIGNAL_TYPE_DVI_DUAL_LINK: 6980 case SIGNAL_TYPE_DVI_SINGLE_LINK: 6981 return DRM_MODE_CONNECTOR_DVID; 6982 case SIGNAL_TYPE_VIRTUAL: 6983 return DRM_MODE_CONNECTOR_VIRTUAL; 6984 6985 default: 6986 return DRM_MODE_CONNECTOR_Unknown; 6987 } 6988 } 6989 6990 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) 6991 { 6992 struct drm_encoder *encoder; 6993 6994 /* There is only one encoder per connector */ 6995 drm_connector_for_each_possible_encoder(connector, encoder) 6996 return encoder; 6997 6998 return NULL; 6999 } 7000 7001 static void amdgpu_dm_get_native_mode(struct drm_connector *connector) 7002 { 7003 struct drm_encoder *encoder; 7004 struct amdgpu_encoder *amdgpu_encoder; 7005 7006 encoder = amdgpu_dm_connector_to_encoder(connector); 7007 7008 if (encoder == NULL) 7009 return; 7010 7011 amdgpu_encoder = to_amdgpu_encoder(encoder); 7012 7013 amdgpu_encoder->native_mode.clock = 0; 7014 7015 if (!list_empty(&connector->probed_modes)) { 7016 struct drm_display_mode *preferred_mode = NULL; 7017 7018 list_for_each_entry(preferred_mode, 7019 &connector->probed_modes, 7020 head) { 7021 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) 7022 amdgpu_encoder->native_mode = *preferred_mode; 7023 7024 break; 7025 } 7026 7027 } 7028 } 7029 7030 static struct drm_display_mode * 7031 amdgpu_dm_create_common_mode(struct drm_encoder *encoder, 7032 char *name, 7033 int hdisplay, int vdisplay) 7034 { 7035 struct drm_device *dev = encoder->dev; 7036 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 7037 struct drm_display_mode *mode = NULL; 7038 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 7039 7040 mode = drm_mode_duplicate(dev, native_mode); 7041 7042 if (mode == NULL) 7043 return NULL; 7044 7045 mode->hdisplay = hdisplay; 7046 mode->vdisplay = vdisplay; 7047 mode->type &= ~DRM_MODE_TYPE_PREFERRED; 7048 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); 7049 7050 return mode; 7051 7052 } 7053 7054 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, 7055 struct drm_connector *connector) 7056 { 7057 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 7058 struct drm_display_mode *mode = NULL; 7059 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 7060 struct amdgpu_dm_connector *amdgpu_dm_connector = 7061 to_amdgpu_dm_connector(connector); 7062 int i; 7063 int n; 7064 struct mode_size { 7065 char name[DRM_DISPLAY_MODE_LEN]; 7066 int w; 7067 int h; 7068 } common_modes[] = { 7069 { "640x480", 640, 480}, 7070 { "800x600", 800, 600}, 7071 { "1024x768", 1024, 768}, 7072 { "1280x720", 1280, 720}, 7073 { "1280x800", 1280, 800}, 7074 {"1280x1024", 1280, 1024}, 7075 { "1440x900", 1440, 900}, 7076 {"1680x1050", 1680, 1050}, 7077 {"1600x1200", 1600, 1200}, 7078 {"1920x1080", 1920, 1080}, 7079 {"1920x1200", 1920, 1200} 7080 }; 7081 7082 n = ARRAY_SIZE(common_modes); 7083 7084 for (i = 0; i < n; i++) { 7085 struct drm_display_mode *curmode = NULL; 7086 bool mode_existed = false; 7087 7088 if (common_modes[i].w > native_mode->hdisplay || 7089 common_modes[i].h > native_mode->vdisplay || 7090 (common_modes[i].w == native_mode->hdisplay && 7091 common_modes[i].h == native_mode->vdisplay)) 7092 continue; 7093 7094 list_for_each_entry(curmode, &connector->probed_modes, head) { 7095 if (common_modes[i].w == curmode->hdisplay && 7096 common_modes[i].h == curmode->vdisplay) { 7097 mode_existed = true; 7098 break; 7099 } 7100 } 7101 7102 if (mode_existed) 7103 continue; 7104 7105 mode = amdgpu_dm_create_common_mode(encoder, 7106 common_modes[i].name, common_modes[i].w, 7107 common_modes[i].h); 7108 if (!mode) 7109 continue; 7110 7111 drm_mode_probed_add(connector, mode); 7112 amdgpu_dm_connector->num_modes++; 7113 } 7114 } 7115 7116 static void amdgpu_set_panel_orientation(struct drm_connector *connector) 7117 { 7118 struct drm_encoder *encoder; 7119 struct amdgpu_encoder *amdgpu_encoder; 7120 const struct drm_display_mode *native_mode; 7121 7122 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP && 7123 connector->connector_type != DRM_MODE_CONNECTOR_LVDS) 7124 return; 7125 7126 mutex_lock(&connector->dev->mode_config.mutex); 7127 amdgpu_dm_connector_get_modes(connector); 7128 mutex_unlock(&connector->dev->mode_config.mutex); 7129 7130 encoder = amdgpu_dm_connector_to_encoder(connector); 7131 if (!encoder) 7132 return; 7133 7134 amdgpu_encoder = to_amdgpu_encoder(encoder); 7135 7136 native_mode = &amdgpu_encoder->native_mode; 7137 if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0) 7138 return; 7139 7140 drm_connector_set_panel_orientation_with_quirk(connector, 7141 DRM_MODE_PANEL_ORIENTATION_UNKNOWN, 7142 native_mode->hdisplay, 7143 native_mode->vdisplay); 7144 } 7145 7146 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, 7147 struct edid *edid) 7148 { 7149 struct amdgpu_dm_connector *amdgpu_dm_connector = 7150 to_amdgpu_dm_connector(connector); 7151 7152 if (edid) { 7153 /* empty probed_modes */ 7154 INIT_LIST_HEAD(&connector->probed_modes); 7155 amdgpu_dm_connector->num_modes = 7156 drm_add_edid_modes(connector, edid); 7157 7158 /* sorting the probed modes before calling function 7159 * amdgpu_dm_get_native_mode() since EDID can have 7160 * more than one preferred mode. The modes that are 7161 * later in the probed mode list could be of higher 7162 * and preferred resolution. For example, 3840x2160 7163 * resolution in base EDID preferred timing and 4096x2160 7164 * preferred resolution in DID extension block later. 7165 */ 7166 drm_mode_sort(&connector->probed_modes); 7167 amdgpu_dm_get_native_mode(connector); 7168 7169 /* Freesync capabilities are reset by calling 7170 * drm_add_edid_modes() and need to be 7171 * restored here. 7172 */ 7173 amdgpu_dm_update_freesync_caps(connector, edid); 7174 } else { 7175 amdgpu_dm_connector->num_modes = 0; 7176 } 7177 } 7178 7179 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector, 7180 struct drm_display_mode *mode) 7181 { 7182 struct drm_display_mode *m; 7183 7184 list_for_each_entry(m, &aconnector->base.probed_modes, head) { 7185 if (drm_mode_equal(m, mode)) 7186 return true; 7187 } 7188 7189 return false; 7190 } 7191 7192 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) 7193 { 7194 const struct drm_display_mode *m; 7195 struct drm_display_mode *new_mode; 7196 uint i; 7197 u32 new_modes_count = 0; 7198 7199 /* Standard FPS values 7200 * 7201 * 23.976 - TV/NTSC 7202 * 24 - Cinema 7203 * 25 - TV/PAL 7204 * 29.97 - TV/NTSC 7205 * 30 - TV/NTSC 7206 * 48 - Cinema HFR 7207 * 50 - TV/PAL 7208 * 60 - Commonly used 7209 * 48,72,96,120 - Multiples of 24 7210 */ 7211 static const u32 common_rates[] = { 7212 23976, 24000, 25000, 29970, 30000, 7213 48000, 50000, 60000, 72000, 96000, 120000 7214 }; 7215 7216 /* 7217 * Find mode with highest refresh rate with the same resolution 7218 * as the preferred mode. Some monitors report a preferred mode 7219 * with lower resolution than the highest refresh rate supported. 7220 */ 7221 7222 m = get_highest_refresh_rate_mode(aconnector, true); 7223 if (!m) 7224 return 0; 7225 7226 for (i = 0; i < ARRAY_SIZE(common_rates); i++) { 7227 u64 target_vtotal, target_vtotal_diff; 7228 u64 num, den; 7229 7230 if (drm_mode_vrefresh(m) * 1000 < common_rates[i]) 7231 continue; 7232 7233 if (common_rates[i] < aconnector->min_vfreq * 1000 || 7234 common_rates[i] > aconnector->max_vfreq * 1000) 7235 continue; 7236 7237 num = (unsigned long long)m->clock * 1000 * 1000; 7238 den = common_rates[i] * (unsigned long long)m->htotal; 7239 target_vtotal = div_u64(num, den); 7240 target_vtotal_diff = target_vtotal - m->vtotal; 7241 7242 /* Check for illegal modes */ 7243 if (m->vsync_start + target_vtotal_diff < m->vdisplay || 7244 m->vsync_end + target_vtotal_diff < m->vsync_start || 7245 m->vtotal + target_vtotal_diff < m->vsync_end) 7246 continue; 7247 7248 new_mode = drm_mode_duplicate(aconnector->base.dev, m); 7249 if (!new_mode) 7250 goto out; 7251 7252 new_mode->vtotal += (u16)target_vtotal_diff; 7253 new_mode->vsync_start += (u16)target_vtotal_diff; 7254 new_mode->vsync_end += (u16)target_vtotal_diff; 7255 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 7256 new_mode->type |= DRM_MODE_TYPE_DRIVER; 7257 7258 if (!is_duplicate_mode(aconnector, new_mode)) { 7259 drm_mode_probed_add(&aconnector->base, new_mode); 7260 new_modes_count += 1; 7261 } else 7262 drm_mode_destroy(aconnector->base.dev, new_mode); 7263 } 7264 out: 7265 return new_modes_count; 7266 } 7267 7268 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector, 7269 struct edid *edid) 7270 { 7271 struct amdgpu_dm_connector *amdgpu_dm_connector = 7272 to_amdgpu_dm_connector(connector); 7273 7274 if (!edid) 7275 return; 7276 7277 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 7278 amdgpu_dm_connector->num_modes += 7279 add_fs_modes(amdgpu_dm_connector); 7280 } 7281 7282 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) 7283 { 7284 struct amdgpu_dm_connector *amdgpu_dm_connector = 7285 to_amdgpu_dm_connector(connector); 7286 struct drm_encoder *encoder; 7287 struct edid *edid = amdgpu_dm_connector->edid; 7288 struct dc_link_settings *verified_link_cap = 7289 &amdgpu_dm_connector->dc_link->verified_link_cap; 7290 const struct dc *dc = amdgpu_dm_connector->dc_link->dc; 7291 7292 encoder = amdgpu_dm_connector_to_encoder(connector); 7293 7294 if (!drm_edid_is_valid(edid)) { 7295 amdgpu_dm_connector->num_modes = 7296 drm_add_modes_noedid(connector, 640, 480); 7297 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING) 7298 amdgpu_dm_connector->num_modes += 7299 drm_add_modes_noedid(connector, 1920, 1080); 7300 } else { 7301 amdgpu_dm_connector_ddc_get_modes(connector, edid); 7302 amdgpu_dm_connector_add_common_modes(encoder, connector); 7303 amdgpu_dm_connector_add_freesync_modes(connector, edid); 7304 } 7305 amdgpu_dm_fbc_init(connector); 7306 7307 return amdgpu_dm_connector->num_modes; 7308 } 7309 7310 static const u32 supported_colorspaces = 7311 BIT(DRM_MODE_COLORIMETRY_BT709_YCC) | 7312 BIT(DRM_MODE_COLORIMETRY_OPRGB) | 7313 BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) | 7314 BIT(DRM_MODE_COLORIMETRY_BT2020_YCC); 7315 7316 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 7317 struct amdgpu_dm_connector *aconnector, 7318 int connector_type, 7319 struct dc_link *link, 7320 int link_index) 7321 { 7322 struct amdgpu_device *adev = drm_to_adev(dm->ddev); 7323 7324 /* 7325 * Some of the properties below require access to state, like bpc. 7326 * Allocate some default initial connector state with our reset helper. 7327 */ 7328 if (aconnector->base.funcs->reset) 7329 aconnector->base.funcs->reset(&aconnector->base); 7330 7331 aconnector->connector_id = link_index; 7332 aconnector->bl_idx = -1; 7333 aconnector->dc_link = link; 7334 aconnector->base.interlace_allowed = false; 7335 aconnector->base.doublescan_allowed = false; 7336 aconnector->base.stereo_allowed = false; 7337 aconnector->base.dpms = DRM_MODE_DPMS_OFF; 7338 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ 7339 aconnector->audio_inst = -1; 7340 aconnector->pack_sdp_v1_3 = false; 7341 aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE; 7342 memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info)); 7343 rw_init(&aconnector->hpd_lock, "dmhpd"); 7344 rw_init(&aconnector->handle_mst_msg_ready, "dmmr"); 7345 7346 /* 7347 * configure support HPD hot plug connector_>polled default value is 0 7348 * which means HPD hot plug not supported 7349 */ 7350 switch (connector_type) { 7351 case DRM_MODE_CONNECTOR_HDMIA: 7352 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 7353 aconnector->base.ycbcr_420_allowed = 7354 link->link_enc->features.hdmi_ycbcr420_supported ? true : false; 7355 break; 7356 case DRM_MODE_CONNECTOR_DisplayPort: 7357 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 7358 link->link_enc = link_enc_cfg_get_link_enc(link); 7359 ASSERT(link->link_enc); 7360 if (link->link_enc) 7361 aconnector->base.ycbcr_420_allowed = 7362 link->link_enc->features.dp_ycbcr420_supported ? true : false; 7363 break; 7364 case DRM_MODE_CONNECTOR_DVID: 7365 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 7366 break; 7367 default: 7368 break; 7369 } 7370 7371 drm_object_attach_property(&aconnector->base.base, 7372 dm->ddev->mode_config.scaling_mode_property, 7373 DRM_MODE_SCALE_NONE); 7374 7375 drm_object_attach_property(&aconnector->base.base, 7376 adev->mode_info.underscan_property, 7377 UNDERSCAN_OFF); 7378 drm_object_attach_property(&aconnector->base.base, 7379 adev->mode_info.underscan_hborder_property, 7380 0); 7381 drm_object_attach_property(&aconnector->base.base, 7382 adev->mode_info.underscan_vborder_property, 7383 0); 7384 7385 if (!aconnector->mst_root) 7386 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16); 7387 7388 aconnector->base.state->max_bpc = 16; 7389 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc; 7390 7391 if (connector_type == DRM_MODE_CONNECTOR_eDP && 7392 (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) { 7393 drm_object_attach_property(&aconnector->base.base, 7394 adev->mode_info.abm_level_property, 0); 7395 } 7396 7397 if (connector_type == DRM_MODE_CONNECTOR_HDMIA) { 7398 if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces)) 7399 drm_connector_attach_colorspace_property(&aconnector->base); 7400 } else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root) || 7401 connector_type == DRM_MODE_CONNECTOR_eDP) { 7402 if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces)) 7403 drm_connector_attach_colorspace_property(&aconnector->base); 7404 } 7405 7406 if (connector_type == DRM_MODE_CONNECTOR_HDMIA || 7407 connector_type == DRM_MODE_CONNECTOR_DisplayPort || 7408 connector_type == DRM_MODE_CONNECTOR_eDP) { 7409 drm_connector_attach_hdr_output_metadata_property(&aconnector->base); 7410 7411 if (!aconnector->mst_root) 7412 drm_connector_attach_vrr_capable_property(&aconnector->base); 7413 7414 if (adev->dm.hdcp_workqueue) 7415 drm_connector_attach_content_protection_property(&aconnector->base, true); 7416 } 7417 } 7418 7419 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, 7420 struct i2c_msg *msgs, int num) 7421 { 7422 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); 7423 struct ddc_service *ddc_service = i2c->ddc_service; 7424 struct i2c_command cmd; 7425 int i; 7426 int result = -EIO; 7427 7428 if (!ddc_service->ddc_pin || !ddc_service->ddc_pin->hw_info.hw_supported) 7429 return result; 7430 7431 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); 7432 7433 if (!cmd.payloads) 7434 return result; 7435 7436 cmd.number_of_payloads = num; 7437 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 7438 cmd.speed = 100; 7439 7440 for (i = 0; i < num; i++) { 7441 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); 7442 cmd.payloads[i].address = msgs[i].addr; 7443 cmd.payloads[i].length = msgs[i].len; 7444 cmd.payloads[i].data = msgs[i].buf; 7445 } 7446 7447 if (dc_submit_i2c( 7448 ddc_service->ctx->dc, 7449 ddc_service->link->link_index, 7450 &cmd)) 7451 result = num; 7452 7453 kfree(cmd.payloads); 7454 return result; 7455 } 7456 7457 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) 7458 { 7459 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 7460 } 7461 7462 static const struct i2c_algorithm amdgpu_dm_i2c_algo = { 7463 .master_xfer = amdgpu_dm_i2c_xfer, 7464 .functionality = amdgpu_dm_i2c_func, 7465 }; 7466 7467 static struct amdgpu_i2c_adapter * 7468 create_i2c(struct ddc_service *ddc_service, 7469 int link_index, 7470 int *res) 7471 { 7472 struct amdgpu_device *adev = ddc_service->ctx->driver_context; 7473 struct amdgpu_i2c_adapter *i2c; 7474 7475 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); 7476 if (!i2c) 7477 return NULL; 7478 #ifdef notyet 7479 i2c->base.owner = THIS_MODULE; 7480 i2c->base.class = I2C_CLASS_DDC; 7481 i2c->base.dev.parent = &adev->pdev->dev; 7482 #endif 7483 i2c->base.algo = &amdgpu_dm_i2c_algo; 7484 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); 7485 i2c_set_adapdata(&i2c->base, i2c); 7486 i2c->ddc_service = ddc_service; 7487 7488 return i2c; 7489 } 7490 7491 7492 /* 7493 * Note: this function assumes that dc_link_detect() was called for the 7494 * dc_link which will be represented by this aconnector. 7495 */ 7496 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 7497 struct amdgpu_dm_connector *aconnector, 7498 u32 link_index, 7499 struct amdgpu_encoder *aencoder) 7500 { 7501 int res = 0; 7502 int connector_type; 7503 struct dc *dc = dm->dc; 7504 struct dc_link *link = dc_get_link_at_index(dc, link_index); 7505 struct amdgpu_i2c_adapter *i2c; 7506 7507 link->priv = aconnector; 7508 7509 7510 i2c = create_i2c(link->ddc, link->link_index, &res); 7511 if (!i2c) { 7512 DRM_ERROR("Failed to create i2c adapter data\n"); 7513 return -ENOMEM; 7514 } 7515 7516 aconnector->i2c = i2c; 7517 res = i2c_add_adapter(&i2c->base); 7518 7519 if (res) { 7520 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); 7521 goto out_free; 7522 } 7523 7524 connector_type = to_drm_connector_type(link->connector_signal); 7525 7526 res = drm_connector_init_with_ddc( 7527 dm->ddev, 7528 &aconnector->base, 7529 &amdgpu_dm_connector_funcs, 7530 connector_type, 7531 &i2c->base); 7532 7533 if (res) { 7534 DRM_ERROR("connector_init failed\n"); 7535 aconnector->connector_id = -1; 7536 goto out_free; 7537 } 7538 7539 drm_connector_helper_add( 7540 &aconnector->base, 7541 &amdgpu_dm_connector_helper_funcs); 7542 7543 amdgpu_dm_connector_init_helper( 7544 dm, 7545 aconnector, 7546 connector_type, 7547 link, 7548 link_index); 7549 7550 drm_connector_attach_encoder( 7551 &aconnector->base, &aencoder->base); 7552 7553 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort 7554 || connector_type == DRM_MODE_CONNECTOR_eDP) 7555 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index); 7556 7557 out_free: 7558 if (res) { 7559 kfree(i2c); 7560 aconnector->i2c = NULL; 7561 } 7562 return res; 7563 } 7564 7565 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) 7566 { 7567 switch (adev->mode_info.num_crtc) { 7568 case 1: 7569 return 0x1; 7570 case 2: 7571 return 0x3; 7572 case 3: 7573 return 0x7; 7574 case 4: 7575 return 0xf; 7576 case 5: 7577 return 0x1f; 7578 case 6: 7579 default: 7580 return 0x3f; 7581 } 7582 } 7583 7584 static int amdgpu_dm_encoder_init(struct drm_device *dev, 7585 struct amdgpu_encoder *aencoder, 7586 uint32_t link_index) 7587 { 7588 struct amdgpu_device *adev = drm_to_adev(dev); 7589 7590 int res = drm_encoder_init(dev, 7591 &aencoder->base, 7592 &amdgpu_dm_encoder_funcs, 7593 DRM_MODE_ENCODER_TMDS, 7594 NULL); 7595 7596 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 7597 7598 if (!res) 7599 aencoder->encoder_id = link_index; 7600 else 7601 aencoder->encoder_id = -1; 7602 7603 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); 7604 7605 return res; 7606 } 7607 7608 static void manage_dm_interrupts(struct amdgpu_device *adev, 7609 struct amdgpu_crtc *acrtc, 7610 bool enable) 7611 { 7612 /* 7613 * We have no guarantee that the frontend index maps to the same 7614 * backend index - some even map to more than one. 7615 * 7616 * TODO: Use a different interrupt or check DC itself for the mapping. 7617 */ 7618 int irq_type = 7619 amdgpu_display_crtc_idx_to_irq_type( 7620 adev, 7621 acrtc->crtc_id); 7622 7623 if (enable) { 7624 drm_crtc_vblank_on(&acrtc->base); 7625 amdgpu_irq_get( 7626 adev, 7627 &adev->pageflip_irq, 7628 irq_type); 7629 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 7630 amdgpu_irq_get( 7631 adev, 7632 &adev->vline0_irq, 7633 irq_type); 7634 #endif 7635 } else { 7636 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 7637 amdgpu_irq_put( 7638 adev, 7639 &adev->vline0_irq, 7640 irq_type); 7641 #endif 7642 amdgpu_irq_put( 7643 adev, 7644 &adev->pageflip_irq, 7645 irq_type); 7646 drm_crtc_vblank_off(&acrtc->base); 7647 } 7648 } 7649 7650 static void dm_update_pflip_irq_state(struct amdgpu_device *adev, 7651 struct amdgpu_crtc *acrtc) 7652 { 7653 int irq_type = 7654 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); 7655 7656 /** 7657 * This reads the current state for the IRQ and force reapplies 7658 * the setting to hardware. 7659 */ 7660 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type); 7661 } 7662 7663 static bool 7664 is_scaling_state_different(const struct dm_connector_state *dm_state, 7665 const struct dm_connector_state *old_dm_state) 7666 { 7667 if (dm_state->scaling != old_dm_state->scaling) 7668 return true; 7669 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 7670 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 7671 return true; 7672 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 7673 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 7674 return true; 7675 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 7676 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 7677 return true; 7678 return false; 7679 } 7680 7681 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state, 7682 struct drm_crtc_state *old_crtc_state, 7683 struct drm_connector_state *new_conn_state, 7684 struct drm_connector_state *old_conn_state, 7685 const struct drm_connector *connector, 7686 struct hdcp_workqueue *hdcp_w) 7687 { 7688 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 7689 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 7690 7691 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 7692 connector->index, connector->status, connector->dpms); 7693 pr_debug("[HDCP_DM] state protection old: %x new: %x\n", 7694 old_conn_state->content_protection, new_conn_state->content_protection); 7695 7696 if (old_crtc_state) 7697 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 7698 old_crtc_state->enable, 7699 old_crtc_state->active, 7700 old_crtc_state->mode_changed, 7701 old_crtc_state->active_changed, 7702 old_crtc_state->connectors_changed); 7703 7704 if (new_crtc_state) 7705 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 7706 new_crtc_state->enable, 7707 new_crtc_state->active, 7708 new_crtc_state->mode_changed, 7709 new_crtc_state->active_changed, 7710 new_crtc_state->connectors_changed); 7711 7712 /* hdcp content type change */ 7713 if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type && 7714 new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 7715 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 7716 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__); 7717 return true; 7718 } 7719 7720 /* CP is being re enabled, ignore this */ 7721 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && 7722 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 7723 if (new_crtc_state && new_crtc_state->mode_changed) { 7724 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 7725 pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__); 7726 return true; 7727 } 7728 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED; 7729 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__); 7730 return false; 7731 } 7732 7733 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED 7734 * 7735 * Handles: UNDESIRED -> ENABLED 7736 */ 7737 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED && 7738 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 7739 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 7740 7741 /* Stream removed and re-enabled 7742 * 7743 * Can sometimes overlap with the HPD case, 7744 * thus set update_hdcp to false to avoid 7745 * setting HDCP multiple times. 7746 * 7747 * Handles: DESIRED -> DESIRED (Special case) 7748 */ 7749 if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) && 7750 new_conn_state->crtc && new_conn_state->crtc->enabled && 7751 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 7752 dm_con_state->update_hdcp = false; 7753 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n", 7754 __func__); 7755 return true; 7756 } 7757 7758 /* Hot-plug, headless s3, dpms 7759 * 7760 * Only start HDCP if the display is connected/enabled. 7761 * update_hdcp flag will be set to false until the next 7762 * HPD comes in. 7763 * 7764 * Handles: DESIRED -> DESIRED (Special case) 7765 */ 7766 if (dm_con_state->update_hdcp && 7767 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && 7768 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) { 7769 dm_con_state->update_hdcp = false; 7770 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n", 7771 __func__); 7772 return true; 7773 } 7774 7775 if (old_conn_state->content_protection == new_conn_state->content_protection) { 7776 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) { 7777 if (new_crtc_state && new_crtc_state->mode_changed) { 7778 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n", 7779 __func__); 7780 return true; 7781 } 7782 pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n", 7783 __func__); 7784 return false; 7785 } 7786 7787 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__); 7788 return false; 7789 } 7790 7791 if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) { 7792 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n", 7793 __func__); 7794 return true; 7795 } 7796 7797 pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__); 7798 return false; 7799 } 7800 7801 static void remove_stream(struct amdgpu_device *adev, 7802 struct amdgpu_crtc *acrtc, 7803 struct dc_stream_state *stream) 7804 { 7805 /* this is the update mode case */ 7806 7807 acrtc->otg_inst = -1; 7808 acrtc->enabled = false; 7809 } 7810 7811 static void prepare_flip_isr(struct amdgpu_crtc *acrtc) 7812 { 7813 7814 assert_spin_locked(&acrtc->base.dev->event_lock); 7815 WARN_ON(acrtc->event); 7816 7817 acrtc->event = acrtc->base.state->event; 7818 7819 /* Set the flip status */ 7820 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 7821 7822 /* Mark this event as consumed */ 7823 acrtc->base.state->event = NULL; 7824 7825 DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 7826 acrtc->crtc_id); 7827 } 7828 7829 static void update_freesync_state_on_stream( 7830 struct amdgpu_display_manager *dm, 7831 struct dm_crtc_state *new_crtc_state, 7832 struct dc_stream_state *new_stream, 7833 struct dc_plane_state *surface, 7834 u32 flip_timestamp_in_us) 7835 { 7836 struct mod_vrr_params vrr_params; 7837 struct dc_info_packet vrr_infopacket = {0}; 7838 struct amdgpu_device *adev = dm->adev; 7839 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 7840 unsigned long flags; 7841 bool pack_sdp_v1_3 = false; 7842 struct amdgpu_dm_connector *aconn; 7843 enum vrr_packet_type packet_type = PACKET_TYPE_VRR; 7844 7845 if (!new_stream) 7846 return; 7847 7848 /* 7849 * TODO: Determine why min/max totals and vrefresh can be 0 here. 7850 * For now it's sufficient to just guard against these conditions. 7851 */ 7852 7853 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 7854 return; 7855 7856 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 7857 vrr_params = acrtc->dm_irq_params.vrr_params; 7858 7859 if (surface) { 7860 mod_freesync_handle_preflip( 7861 dm->freesync_module, 7862 surface, 7863 new_stream, 7864 flip_timestamp_in_us, 7865 &vrr_params); 7866 7867 if (adev->family < AMDGPU_FAMILY_AI && 7868 amdgpu_dm_crtc_vrr_active(new_crtc_state)) { 7869 mod_freesync_handle_v_update(dm->freesync_module, 7870 new_stream, &vrr_params); 7871 7872 /* Need to call this before the frame ends. */ 7873 dc_stream_adjust_vmin_vmax(dm->dc, 7874 new_crtc_state->stream, 7875 &vrr_params.adjust); 7876 } 7877 } 7878 7879 aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context; 7880 7881 if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) { 7882 pack_sdp_v1_3 = aconn->pack_sdp_v1_3; 7883 7884 if (aconn->vsdb_info.amd_vsdb_version == 1) 7885 packet_type = PACKET_TYPE_FS_V1; 7886 else if (aconn->vsdb_info.amd_vsdb_version == 2) 7887 packet_type = PACKET_TYPE_FS_V2; 7888 else if (aconn->vsdb_info.amd_vsdb_version == 3) 7889 packet_type = PACKET_TYPE_FS_V3; 7890 7891 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL, 7892 &new_stream->adaptive_sync_infopacket); 7893 } 7894 7895 mod_freesync_build_vrr_infopacket( 7896 dm->freesync_module, 7897 new_stream, 7898 &vrr_params, 7899 packet_type, 7900 TRANSFER_FUNC_UNKNOWN, 7901 &vrr_infopacket, 7902 pack_sdp_v1_3); 7903 7904 new_crtc_state->freesync_vrr_info_changed |= 7905 (memcmp(&new_crtc_state->vrr_infopacket, 7906 &vrr_infopacket, 7907 sizeof(vrr_infopacket)) != 0); 7908 7909 acrtc->dm_irq_params.vrr_params = vrr_params; 7910 new_crtc_state->vrr_infopacket = vrr_infopacket; 7911 7912 new_stream->vrr_infopacket = vrr_infopacket; 7913 new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params); 7914 7915 if (new_crtc_state->freesync_vrr_info_changed) 7916 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d", 7917 new_crtc_state->base.crtc->base.id, 7918 (int)new_crtc_state->base.vrr_enabled, 7919 (int)vrr_params.state); 7920 7921 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 7922 } 7923 7924 static void update_stream_irq_parameters( 7925 struct amdgpu_display_manager *dm, 7926 struct dm_crtc_state *new_crtc_state) 7927 { 7928 struct dc_stream_state *new_stream = new_crtc_state->stream; 7929 struct mod_vrr_params vrr_params; 7930 struct mod_freesync_config config = new_crtc_state->freesync_config; 7931 struct amdgpu_device *adev = dm->adev; 7932 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 7933 unsigned long flags; 7934 7935 if (!new_stream) 7936 return; 7937 7938 /* 7939 * TODO: Determine why min/max totals and vrefresh can be 0 here. 7940 * For now it's sufficient to just guard against these conditions. 7941 */ 7942 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 7943 return; 7944 7945 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 7946 vrr_params = acrtc->dm_irq_params.vrr_params; 7947 7948 if (new_crtc_state->vrr_supported && 7949 config.min_refresh_in_uhz && 7950 config.max_refresh_in_uhz) { 7951 /* 7952 * if freesync compatible mode was set, config.state will be set 7953 * in atomic check 7954 */ 7955 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz && 7956 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) || 7957 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) { 7958 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz; 7959 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz; 7960 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz; 7961 vrr_params.state = VRR_STATE_ACTIVE_FIXED; 7962 } else { 7963 config.state = new_crtc_state->base.vrr_enabled ? 7964 VRR_STATE_ACTIVE_VARIABLE : 7965 VRR_STATE_INACTIVE; 7966 } 7967 } else { 7968 config.state = VRR_STATE_UNSUPPORTED; 7969 } 7970 7971 mod_freesync_build_vrr_params(dm->freesync_module, 7972 new_stream, 7973 &config, &vrr_params); 7974 7975 new_crtc_state->freesync_config = config; 7976 /* Copy state for access from DM IRQ handler */ 7977 acrtc->dm_irq_params.freesync_config = config; 7978 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes; 7979 acrtc->dm_irq_params.vrr_params = vrr_params; 7980 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 7981 } 7982 7983 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, 7984 struct dm_crtc_state *new_state) 7985 { 7986 bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state); 7987 bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state); 7988 7989 if (!old_vrr_active && new_vrr_active) { 7990 /* Transition VRR inactive -> active: 7991 * While VRR is active, we must not disable vblank irq, as a 7992 * reenable after disable would compute bogus vblank/pflip 7993 * timestamps if it likely happened inside display front-porch. 7994 * 7995 * We also need vupdate irq for the actual core vblank handling 7996 * at end of vblank. 7997 */ 7998 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0); 7999 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0); 8000 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n", 8001 __func__, new_state->base.crtc->base.id); 8002 } else if (old_vrr_active && !new_vrr_active) { 8003 /* Transition VRR active -> inactive: 8004 * Allow vblank irq disable again for fixed refresh rate. 8005 */ 8006 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0); 8007 drm_crtc_vblank_put(new_state->base.crtc); 8008 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n", 8009 __func__, new_state->base.crtc->base.id); 8010 } 8011 } 8012 8013 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state) 8014 { 8015 struct drm_plane *plane; 8016 struct drm_plane_state *old_plane_state; 8017 int i; 8018 8019 /* 8020 * TODO: Make this per-stream so we don't issue redundant updates for 8021 * commits with multiple streams. 8022 */ 8023 for_each_old_plane_in_state(state, plane, old_plane_state, i) 8024 if (plane->type == DRM_PLANE_TYPE_CURSOR) 8025 amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state); 8026 } 8027 8028 static inline uint32_t get_mem_type(struct drm_framebuffer *fb) 8029 { 8030 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); 8031 8032 return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; 8033 } 8034 8035 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 8036 struct drm_device *dev, 8037 struct amdgpu_display_manager *dm, 8038 struct drm_crtc *pcrtc, 8039 bool wait_for_vblank) 8040 { 8041 u32 i; 8042 u64 timestamp_ns = ktime_get_ns(); 8043 struct drm_plane *plane; 8044 struct drm_plane_state *old_plane_state, *new_plane_state; 8045 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 8046 struct drm_crtc_state *new_pcrtc_state = 8047 drm_atomic_get_new_crtc_state(state, pcrtc); 8048 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 8049 struct dm_crtc_state *dm_old_crtc_state = 8050 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 8051 int planes_count = 0, vpos, hpos; 8052 unsigned long flags; 8053 u32 target_vblank, last_flip_vblank; 8054 bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state); 8055 bool cursor_update = false; 8056 bool pflip_present = false; 8057 bool dirty_rects_changed = false; 8058 struct { 8059 struct dc_surface_update surface_updates[MAX_SURFACES]; 8060 struct dc_plane_info plane_infos[MAX_SURFACES]; 8061 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 8062 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 8063 struct dc_stream_update stream_update; 8064 } *bundle; 8065 8066 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 8067 8068 if (!bundle) { 8069 dm_error("Failed to allocate update bundle\n"); 8070 goto cleanup; 8071 } 8072 8073 /* 8074 * Disable the cursor first if we're disabling all the planes. 8075 * It'll remain on the screen after the planes are re-enabled 8076 * if we don't. 8077 */ 8078 if (acrtc_state->active_planes == 0) 8079 amdgpu_dm_commit_cursors(state); 8080 8081 /* update planes when needed */ 8082 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 8083 struct drm_crtc *crtc = new_plane_state->crtc; 8084 struct drm_crtc_state *new_crtc_state; 8085 struct drm_framebuffer *fb = new_plane_state->fb; 8086 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb; 8087 bool plane_needs_flip; 8088 struct dc_plane_state *dc_plane; 8089 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 8090 8091 /* Cursor plane is handled after stream updates */ 8092 if (plane->type == DRM_PLANE_TYPE_CURSOR) { 8093 if ((fb && crtc == pcrtc) || 8094 (old_plane_state->fb && old_plane_state->crtc == pcrtc)) 8095 cursor_update = true; 8096 8097 continue; 8098 } 8099 8100 if (!fb || !crtc || pcrtc != crtc) 8101 continue; 8102 8103 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 8104 if (!new_crtc_state->active) 8105 continue; 8106 8107 dc_plane = dm_new_plane_state->dc_state; 8108 if (!dc_plane) 8109 continue; 8110 8111 bundle->surface_updates[planes_count].surface = dc_plane; 8112 if (new_pcrtc_state->color_mgmt_changed) { 8113 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction; 8114 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func; 8115 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix; 8116 } 8117 8118 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state, 8119 &bundle->scaling_infos[planes_count]); 8120 8121 bundle->surface_updates[planes_count].scaling_info = 8122 &bundle->scaling_infos[planes_count]; 8123 8124 plane_needs_flip = old_plane_state->fb && new_plane_state->fb; 8125 8126 pflip_present = pflip_present || plane_needs_flip; 8127 8128 if (!plane_needs_flip) { 8129 planes_count += 1; 8130 continue; 8131 } 8132 8133 fill_dc_plane_info_and_addr( 8134 dm->adev, new_plane_state, 8135 afb->tiling_flags, 8136 &bundle->plane_infos[planes_count], 8137 &bundle->flip_addrs[planes_count].address, 8138 afb->tmz_surface, false); 8139 8140 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n", 8141 new_plane_state->plane->index, 8142 bundle->plane_infos[planes_count].dcc.enable); 8143 8144 bundle->surface_updates[planes_count].plane_info = 8145 &bundle->plane_infos[planes_count]; 8146 8147 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled || 8148 acrtc_state->stream->link->replay_settings.replay_feature_enabled) { 8149 fill_dc_dirty_rects(plane, old_plane_state, 8150 new_plane_state, new_crtc_state, 8151 &bundle->flip_addrs[planes_count], 8152 &dirty_rects_changed); 8153 8154 /* 8155 * If the dirty regions changed, PSR-SU need to be disabled temporarily 8156 * and enabled it again after dirty regions are stable to avoid video glitch. 8157 * PSR-SU will be enabled in vblank_control_worker() if user pause the video 8158 * during the PSR-SU was disabled. 8159 */ 8160 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && 8161 acrtc_attach->dm_irq_params.allow_psr_entry && 8162 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 8163 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && 8164 #endif 8165 dirty_rects_changed) { 8166 mutex_lock(&dm->dc_lock); 8167 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns = 8168 timestamp_ns; 8169 if (acrtc_state->stream->link->psr_settings.psr_allow_active) 8170 amdgpu_dm_psr_disable(acrtc_state->stream); 8171 mutex_unlock(&dm->dc_lock); 8172 } 8173 } 8174 8175 /* 8176 * Only allow immediate flips for fast updates that don't 8177 * change memory domain, FB pitch, DCC state, rotation or 8178 * mirroring. 8179 * 8180 * dm_crtc_helper_atomic_check() only accepts async flips with 8181 * fast updates. 8182 */ 8183 if (crtc->state->async_flip && 8184 (acrtc_state->update_type != UPDATE_TYPE_FAST || 8185 get_mem_type(old_plane_state->fb) != get_mem_type(fb))) 8186 drm_warn_once(state->dev, 8187 "[PLANE:%d:%s] async flip with non-fast update\n", 8188 plane->base.id, plane->name); 8189 8190 bundle->flip_addrs[planes_count].flip_immediate = 8191 crtc->state->async_flip && 8192 acrtc_state->update_type == UPDATE_TYPE_FAST && 8193 get_mem_type(old_plane_state->fb) == get_mem_type(fb); 8194 8195 timestamp_ns = ktime_get_ns(); 8196 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); 8197 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; 8198 bundle->surface_updates[planes_count].surface = dc_plane; 8199 8200 if (!bundle->surface_updates[planes_count].surface) { 8201 DRM_ERROR("No surface for CRTC: id=%d\n", 8202 acrtc_attach->crtc_id); 8203 continue; 8204 } 8205 8206 if (plane == pcrtc->primary) 8207 update_freesync_state_on_stream( 8208 dm, 8209 acrtc_state, 8210 acrtc_state->stream, 8211 dc_plane, 8212 bundle->flip_addrs[planes_count].flip_timestamp_in_us); 8213 8214 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n", 8215 __func__, 8216 bundle->flip_addrs[planes_count].address.grph.addr.high_part, 8217 bundle->flip_addrs[planes_count].address.grph.addr.low_part); 8218 8219 planes_count += 1; 8220 8221 } 8222 8223 if (pflip_present) { 8224 if (!vrr_active) { 8225 /* Use old throttling in non-vrr fixed refresh rate mode 8226 * to keep flip scheduling based on target vblank counts 8227 * working in a backwards compatible way, e.g., for 8228 * clients using the GLX_OML_sync_control extension or 8229 * DRI3/Present extension with defined target_msc. 8230 */ 8231 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc); 8232 } else { 8233 /* For variable refresh rate mode only: 8234 * Get vblank of last completed flip to avoid > 1 vrr 8235 * flips per video frame by use of throttling, but allow 8236 * flip programming anywhere in the possibly large 8237 * variable vrr vblank interval for fine-grained flip 8238 * timing control and more opportunity to avoid stutter 8239 * on late submission of flips. 8240 */ 8241 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 8242 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank; 8243 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 8244 } 8245 8246 target_vblank = last_flip_vblank + wait_for_vblank; 8247 8248 /* 8249 * Wait until we're out of the vertical blank period before the one 8250 * targeted by the flip 8251 */ 8252 while ((acrtc_attach->enabled && 8253 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, 8254 0, &vpos, &hpos, NULL, 8255 NULL, &pcrtc->hwmode) 8256 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 8257 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 8258 (int)(target_vblank - 8259 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) { 8260 usleep_range(1000, 1100); 8261 } 8262 8263 /** 8264 * Prepare the flip event for the pageflip interrupt to handle. 8265 * 8266 * This only works in the case where we've already turned on the 8267 * appropriate hardware blocks (eg. HUBP) so in the transition case 8268 * from 0 -> n planes we have to skip a hardware generated event 8269 * and rely on sending it from software. 8270 */ 8271 if (acrtc_attach->base.state->event && 8272 acrtc_state->active_planes > 0) { 8273 drm_crtc_vblank_get(pcrtc); 8274 8275 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 8276 8277 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE); 8278 prepare_flip_isr(acrtc_attach); 8279 8280 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 8281 } 8282 8283 if (acrtc_state->stream) { 8284 if (acrtc_state->freesync_vrr_info_changed) 8285 bundle->stream_update.vrr_infopacket = 8286 &acrtc_state->stream->vrr_infopacket; 8287 } 8288 } else if (cursor_update && acrtc_state->active_planes > 0 && 8289 acrtc_attach->base.state->event) { 8290 drm_crtc_vblank_get(pcrtc); 8291 8292 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 8293 8294 acrtc_attach->event = acrtc_attach->base.state->event; 8295 acrtc_attach->base.state->event = NULL; 8296 8297 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 8298 } 8299 8300 /* Update the planes if changed or disable if we don't have any. */ 8301 if ((planes_count || acrtc_state->active_planes == 0) && 8302 acrtc_state->stream) { 8303 /* 8304 * If PSR or idle optimizations are enabled then flush out 8305 * any pending work before hardware programming. 8306 */ 8307 if (dm->vblank_control_workqueue) 8308 flush_workqueue(dm->vblank_control_workqueue); 8309 8310 bundle->stream_update.stream = acrtc_state->stream; 8311 if (new_pcrtc_state->mode_changed) { 8312 bundle->stream_update.src = acrtc_state->stream->src; 8313 bundle->stream_update.dst = acrtc_state->stream->dst; 8314 } 8315 8316 if (new_pcrtc_state->color_mgmt_changed) { 8317 /* 8318 * TODO: This isn't fully correct since we've actually 8319 * already modified the stream in place. 8320 */ 8321 bundle->stream_update.gamut_remap = 8322 &acrtc_state->stream->gamut_remap_matrix; 8323 bundle->stream_update.output_csc_transform = 8324 &acrtc_state->stream->csc_color_matrix; 8325 bundle->stream_update.out_transfer_func = 8326 acrtc_state->stream->out_transfer_func; 8327 } 8328 8329 acrtc_state->stream->abm_level = acrtc_state->abm_level; 8330 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) 8331 bundle->stream_update.abm_level = &acrtc_state->abm_level; 8332 8333 mutex_lock(&dm->dc_lock); 8334 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && 8335 acrtc_state->stream->link->psr_settings.psr_allow_active) 8336 amdgpu_dm_psr_disable(acrtc_state->stream); 8337 mutex_unlock(&dm->dc_lock); 8338 8339 /* 8340 * If FreeSync state on the stream has changed then we need to 8341 * re-adjust the min/max bounds now that DC doesn't handle this 8342 * as part of commit. 8343 */ 8344 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) { 8345 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 8346 dc_stream_adjust_vmin_vmax( 8347 dm->dc, acrtc_state->stream, 8348 &acrtc_attach->dm_irq_params.vrr_params.adjust); 8349 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 8350 } 8351 mutex_lock(&dm->dc_lock); 8352 update_planes_and_stream_adapter(dm->dc, 8353 acrtc_state->update_type, 8354 planes_count, 8355 acrtc_state->stream, 8356 &bundle->stream_update, 8357 bundle->surface_updates); 8358 8359 /** 8360 * Enable or disable the interrupts on the backend. 8361 * 8362 * Most pipes are put into power gating when unused. 8363 * 8364 * When power gating is enabled on a pipe we lose the 8365 * interrupt enablement state when power gating is disabled. 8366 * 8367 * So we need to update the IRQ control state in hardware 8368 * whenever the pipe turns on (since it could be previously 8369 * power gated) or off (since some pipes can't be power gated 8370 * on some ASICs). 8371 */ 8372 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes) 8373 dm_update_pflip_irq_state(drm_to_adev(dev), 8374 acrtc_attach); 8375 8376 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && 8377 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED && 8378 !acrtc_state->stream->link->psr_settings.psr_feature_enabled) 8379 amdgpu_dm_link_setup_psr(acrtc_state->stream); 8380 8381 /* Decrement skip count when PSR is enabled and we're doing fast updates. */ 8382 if (acrtc_state->update_type == UPDATE_TYPE_FAST && 8383 acrtc_state->stream->link->psr_settings.psr_feature_enabled) { 8384 struct amdgpu_dm_connector *aconn = 8385 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; 8386 8387 if (aconn->psr_skip_count > 0) 8388 aconn->psr_skip_count--; 8389 8390 /* Allow PSR when skip count is 0. */ 8391 acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count; 8392 8393 /* 8394 * If sink supports PSR SU, there is no need to rely on 8395 * a vblank event disable request to enable PSR. PSR SU 8396 * can be enabled immediately once OS demonstrates an 8397 * adequate number of fast atomic commits to notify KMD 8398 * of update events. See `vblank_control_worker()`. 8399 */ 8400 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && 8401 acrtc_attach->dm_irq_params.allow_psr_entry && 8402 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 8403 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && 8404 #endif 8405 !acrtc_state->stream->link->psr_settings.psr_allow_active && 8406 (timestamp_ns - 8407 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) > 8408 500000000) 8409 amdgpu_dm_psr_enable(acrtc_state->stream); 8410 } else { 8411 acrtc_attach->dm_irq_params.allow_psr_entry = false; 8412 } 8413 8414 mutex_unlock(&dm->dc_lock); 8415 } 8416 8417 /* 8418 * Update cursor state *after* programming all the planes. 8419 * This avoids redundant programming in the case where we're going 8420 * to be disabling a single plane - those pipes are being disabled. 8421 */ 8422 if (acrtc_state->active_planes) 8423 amdgpu_dm_commit_cursors(state); 8424 8425 cleanup: 8426 kfree(bundle); 8427 } 8428 8429 static void amdgpu_dm_commit_audio(struct drm_device *dev, 8430 struct drm_atomic_state *state) 8431 { 8432 struct amdgpu_device *adev = drm_to_adev(dev); 8433 struct amdgpu_dm_connector *aconnector; 8434 struct drm_connector *connector; 8435 struct drm_connector_state *old_con_state, *new_con_state; 8436 struct drm_crtc_state *new_crtc_state; 8437 struct dm_crtc_state *new_dm_crtc_state; 8438 const struct dc_stream_status *status; 8439 int i, inst; 8440 8441 /* Notify device removals. */ 8442 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 8443 if (old_con_state->crtc != new_con_state->crtc) { 8444 /* CRTC changes require notification. */ 8445 goto notify; 8446 } 8447 8448 if (!new_con_state->crtc) 8449 continue; 8450 8451 new_crtc_state = drm_atomic_get_new_crtc_state( 8452 state, new_con_state->crtc); 8453 8454 if (!new_crtc_state) 8455 continue; 8456 8457 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 8458 continue; 8459 8460 notify: 8461 aconnector = to_amdgpu_dm_connector(connector); 8462 8463 mutex_lock(&adev->dm.audio_lock); 8464 inst = aconnector->audio_inst; 8465 aconnector->audio_inst = -1; 8466 mutex_unlock(&adev->dm.audio_lock); 8467 8468 amdgpu_dm_audio_eld_notify(adev, inst); 8469 } 8470 8471 /* Notify audio device additions. */ 8472 for_each_new_connector_in_state(state, connector, new_con_state, i) { 8473 if (!new_con_state->crtc) 8474 continue; 8475 8476 new_crtc_state = drm_atomic_get_new_crtc_state( 8477 state, new_con_state->crtc); 8478 8479 if (!new_crtc_state) 8480 continue; 8481 8482 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 8483 continue; 8484 8485 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 8486 if (!new_dm_crtc_state->stream) 8487 continue; 8488 8489 status = dc_stream_get_status(new_dm_crtc_state->stream); 8490 if (!status) 8491 continue; 8492 8493 aconnector = to_amdgpu_dm_connector(connector); 8494 8495 mutex_lock(&adev->dm.audio_lock); 8496 inst = status->audio_inst; 8497 aconnector->audio_inst = inst; 8498 mutex_unlock(&adev->dm.audio_lock); 8499 8500 amdgpu_dm_audio_eld_notify(adev, inst); 8501 } 8502 } 8503 8504 /* 8505 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 8506 * @crtc_state: the DRM CRTC state 8507 * @stream_state: the DC stream state. 8508 * 8509 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 8510 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 8511 */ 8512 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 8513 struct dc_stream_state *stream_state) 8514 { 8515 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); 8516 } 8517 8518 static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, 8519 struct dc_state *dc_state) 8520 { 8521 struct drm_device *dev = state->dev; 8522 struct amdgpu_device *adev = drm_to_adev(dev); 8523 struct amdgpu_display_manager *dm = &adev->dm; 8524 struct drm_crtc *crtc; 8525 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 8526 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 8527 bool mode_set_reset_required = false; 8528 u32 i; 8529 8530 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 8531 new_crtc_state, i) { 8532 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 8533 8534 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8535 8536 if (old_crtc_state->active && 8537 (!new_crtc_state->active || 8538 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 8539 manage_dm_interrupts(adev, acrtc, false); 8540 dc_stream_release(dm_old_crtc_state->stream); 8541 } 8542 } 8543 8544 drm_atomic_helper_calc_timestamping_constants(state); 8545 8546 /* update changed items */ 8547 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8548 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 8549 8550 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8551 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8552 8553 drm_dbg_state(state->dev, 8554 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 8555 acrtc->crtc_id, 8556 new_crtc_state->enable, 8557 new_crtc_state->active, 8558 new_crtc_state->planes_changed, 8559 new_crtc_state->mode_changed, 8560 new_crtc_state->active_changed, 8561 new_crtc_state->connectors_changed); 8562 8563 /* Disable cursor if disabling crtc */ 8564 if (old_crtc_state->active && !new_crtc_state->active) { 8565 struct dc_cursor_position position; 8566 8567 memset(&position, 0, sizeof(position)); 8568 mutex_lock(&dm->dc_lock); 8569 dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position); 8570 mutex_unlock(&dm->dc_lock); 8571 } 8572 8573 /* Copy all transient state flags into dc state */ 8574 if (dm_new_crtc_state->stream) { 8575 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 8576 dm_new_crtc_state->stream); 8577 } 8578 8579 /* handles headless hotplug case, updating new_state and 8580 * aconnector as needed 8581 */ 8582 8583 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 8584 8585 DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); 8586 8587 if (!dm_new_crtc_state->stream) { 8588 /* 8589 * this could happen because of issues with 8590 * userspace notifications delivery. 8591 * In this case userspace tries to set mode on 8592 * display which is disconnected in fact. 8593 * dc_sink is NULL in this case on aconnector. 8594 * We expect reset mode will come soon. 8595 * 8596 * This can also happen when unplug is done 8597 * during resume sequence ended 8598 * 8599 * In this case, we want to pretend we still 8600 * have a sink to keep the pipe running so that 8601 * hw state is consistent with the sw state 8602 */ 8603 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 8604 __func__, acrtc->base.base.id); 8605 continue; 8606 } 8607 8608 if (dm_old_crtc_state->stream) 8609 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 8610 8611 pm_runtime_get_noresume(dev->dev); 8612 8613 acrtc->enabled = true; 8614 acrtc->hw_mode = new_crtc_state->mode; 8615 crtc->hwmode = new_crtc_state->mode; 8616 mode_set_reset_required = true; 8617 } else if (modereset_required(new_crtc_state)) { 8618 DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); 8619 /* i.e. reset mode */ 8620 if (dm_old_crtc_state->stream) 8621 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 8622 8623 mode_set_reset_required = true; 8624 } 8625 } /* for_each_crtc_in_state() */ 8626 8627 /* if there mode set or reset, disable eDP PSR */ 8628 if (mode_set_reset_required) { 8629 if (dm->vblank_control_workqueue) 8630 flush_workqueue(dm->vblank_control_workqueue); 8631 8632 amdgpu_dm_psr_disable_all(dm); 8633 } 8634 8635 dm_enable_per_frame_crtc_master_sync(dc_state); 8636 mutex_lock(&dm->dc_lock); 8637 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count)); 8638 8639 /* Allow idle optimization when vblank count is 0 for display off */ 8640 if (dm->active_vblank_irq_count == 0) 8641 dc_allow_idle_optimizations(dm->dc, true); 8642 mutex_unlock(&dm->dc_lock); 8643 8644 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 8645 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 8646 8647 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8648 8649 if (dm_new_crtc_state->stream != NULL) { 8650 const struct dc_stream_status *status = 8651 dc_stream_get_status(dm_new_crtc_state->stream); 8652 8653 if (!status) 8654 status = dc_stream_get_status_from_state(dc_state, 8655 dm_new_crtc_state->stream); 8656 if (!status) 8657 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc); 8658 else 8659 acrtc->otg_inst = status->primary_otg_inst; 8660 } 8661 } 8662 } 8663 8664 /** 8665 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. 8666 * @state: The atomic state to commit 8667 * 8668 * This will tell DC to commit the constructed DC state from atomic_check, 8669 * programming the hardware. Any failures here implies a hardware failure, since 8670 * atomic check should have filtered anything non-kosher. 8671 */ 8672 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) 8673 { 8674 struct drm_device *dev = state->dev; 8675 struct amdgpu_device *adev = drm_to_adev(dev); 8676 struct amdgpu_display_manager *dm = &adev->dm; 8677 struct dm_atomic_state *dm_state; 8678 struct dc_state *dc_state = NULL; 8679 u32 i, j; 8680 struct drm_crtc *crtc; 8681 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 8682 unsigned long flags; 8683 bool wait_for_vblank = true; 8684 struct drm_connector *connector; 8685 struct drm_connector_state *old_con_state, *new_con_state; 8686 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 8687 int crtc_disable_count = 0; 8688 8689 trace_amdgpu_dm_atomic_commit_tail_begin(state); 8690 8691 drm_atomic_helper_update_legacy_modeset_state(dev, state); 8692 drm_dp_mst_atomic_wait_for_dependencies(state); 8693 8694 dm_state = dm_atomic_get_new_state(state); 8695 if (dm_state && dm_state->context) { 8696 dc_state = dm_state->context; 8697 amdgpu_dm_commit_streams(state, dc_state); 8698 } 8699 8700 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 8701 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 8702 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 8703 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 8704 8705 if (!adev->dm.hdcp_workqueue) 8706 continue; 8707 8708 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i); 8709 8710 if (!connector) 8711 continue; 8712 8713 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 8714 connector->index, connector->status, connector->dpms); 8715 pr_debug("[HDCP_DM] state protection old: %x new: %x\n", 8716 old_con_state->content_protection, new_con_state->content_protection); 8717 8718 if (aconnector->dc_sink) { 8719 if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 8720 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) { 8721 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n", 8722 aconnector->dc_sink->edid_caps.display_name); 8723 } 8724 } 8725 8726 new_crtc_state = NULL; 8727 old_crtc_state = NULL; 8728 8729 if (acrtc) { 8730 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 8731 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 8732 } 8733 8734 if (old_crtc_state) 8735 pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 8736 old_crtc_state->enable, 8737 old_crtc_state->active, 8738 old_crtc_state->mode_changed, 8739 old_crtc_state->active_changed, 8740 old_crtc_state->connectors_changed); 8741 8742 if (new_crtc_state) 8743 pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 8744 new_crtc_state->enable, 8745 new_crtc_state->active, 8746 new_crtc_state->mode_changed, 8747 new_crtc_state->active_changed, 8748 new_crtc_state->connectors_changed); 8749 } 8750 8751 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 8752 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 8753 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 8754 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 8755 8756 if (!adev->dm.hdcp_workqueue) 8757 continue; 8758 8759 new_crtc_state = NULL; 8760 old_crtc_state = NULL; 8761 8762 if (acrtc) { 8763 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 8764 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 8765 } 8766 8767 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8768 8769 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL && 8770 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 8771 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 8772 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 8773 dm_new_con_state->update_hdcp = true; 8774 continue; 8775 } 8776 8777 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state, 8778 old_con_state, connector, adev->dm.hdcp_workqueue)) { 8779 /* when display is unplugged from mst hub, connctor will 8780 * be destroyed within dm_dp_mst_connector_destroy. connector 8781 * hdcp perperties, like type, undesired, desired, enabled, 8782 * will be lost. So, save hdcp properties into hdcp_work within 8783 * amdgpu_dm_atomic_commit_tail. if the same display is 8784 * plugged back with same display index, its hdcp properties 8785 * will be retrieved from hdcp_work within dm_dp_mst_get_modes 8786 */ 8787 8788 bool enable_encryption = false; 8789 8790 if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) 8791 enable_encryption = true; 8792 8793 if (aconnector->dc_link && aconnector->dc_sink && 8794 aconnector->dc_link->type == dc_connection_mst_branch) { 8795 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; 8796 struct hdcp_workqueue *hdcp_w = 8797 &hdcp_work[aconnector->dc_link->link_index]; 8798 8799 hdcp_w->hdcp_content_type[connector->index] = 8800 new_con_state->hdcp_content_type; 8801 hdcp_w->content_protection[connector->index] = 8802 new_con_state->content_protection; 8803 } 8804 8805 if (new_crtc_state && new_crtc_state->mode_changed && 8806 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) 8807 enable_encryption = true; 8808 8809 DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption); 8810 8811 hdcp_update_display( 8812 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, 8813 new_con_state->hdcp_content_type, enable_encryption); 8814 } 8815 } 8816 8817 /* Handle connector state changes */ 8818 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 8819 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 8820 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 8821 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 8822 struct dc_surface_update *dummy_updates; 8823 struct dc_stream_update stream_update; 8824 struct dc_info_packet hdr_packet; 8825 struct dc_stream_status *status = NULL; 8826 bool abm_changed, hdr_changed, scaling_changed; 8827 8828 memset(&stream_update, 0, sizeof(stream_update)); 8829 8830 if (acrtc) { 8831 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 8832 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 8833 } 8834 8835 /* Skip any modesets/resets */ 8836 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 8837 continue; 8838 8839 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8840 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8841 8842 scaling_changed = is_scaling_state_different(dm_new_con_state, 8843 dm_old_con_state); 8844 8845 abm_changed = dm_new_crtc_state->abm_level != 8846 dm_old_crtc_state->abm_level; 8847 8848 hdr_changed = 8849 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); 8850 8851 if (!scaling_changed && !abm_changed && !hdr_changed) 8852 continue; 8853 8854 stream_update.stream = dm_new_crtc_state->stream; 8855 if (scaling_changed) { 8856 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, 8857 dm_new_con_state, dm_new_crtc_state->stream); 8858 8859 stream_update.src = dm_new_crtc_state->stream->src; 8860 stream_update.dst = dm_new_crtc_state->stream->dst; 8861 } 8862 8863 if (abm_changed) { 8864 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; 8865 8866 stream_update.abm_level = &dm_new_crtc_state->abm_level; 8867 } 8868 8869 if (hdr_changed) { 8870 fill_hdr_info_packet(new_con_state, &hdr_packet); 8871 stream_update.hdr_static_metadata = &hdr_packet; 8872 } 8873 8874 status = dc_stream_get_status(dm_new_crtc_state->stream); 8875 8876 if (WARN_ON(!status)) 8877 continue; 8878 8879 WARN_ON(!status->plane_count); 8880 8881 /* 8882 * TODO: DC refuses to perform stream updates without a dc_surface_update. 8883 * Here we create an empty update on each plane. 8884 * To fix this, DC should permit updating only stream properties. 8885 */ 8886 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC); 8887 for (j = 0; j < status->plane_count; j++) 8888 dummy_updates[j].surface = status->plane_states[0]; 8889 8890 8891 mutex_lock(&dm->dc_lock); 8892 dc_update_planes_and_stream(dm->dc, 8893 dummy_updates, 8894 status->plane_count, 8895 dm_new_crtc_state->stream, 8896 &stream_update); 8897 mutex_unlock(&dm->dc_lock); 8898 kfree(dummy_updates); 8899 } 8900 8901 /** 8902 * Enable interrupts for CRTCs that are newly enabled or went through 8903 * a modeset. It was intentionally deferred until after the front end 8904 * state was modified to wait until the OTG was on and so the IRQ 8905 * handlers didn't access stale or invalid state. 8906 */ 8907 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8908 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 8909 #ifdef CONFIG_DEBUG_FS 8910 enum amdgpu_dm_pipe_crc_source cur_crc_src; 8911 #endif 8912 /* Count number of newly disabled CRTCs for dropping PM refs later. */ 8913 if (old_crtc_state->active && !new_crtc_state->active) 8914 crtc_disable_count++; 8915 8916 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8917 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8918 8919 /* For freesync config update on crtc state and params for irq */ 8920 update_stream_irq_parameters(dm, dm_new_crtc_state); 8921 8922 #ifdef CONFIG_DEBUG_FS 8923 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 8924 cur_crc_src = acrtc->dm_irq_params.crc_src; 8925 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 8926 #endif 8927 8928 if (new_crtc_state->active && 8929 (!old_crtc_state->active || 8930 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 8931 dc_stream_retain(dm_new_crtc_state->stream); 8932 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; 8933 manage_dm_interrupts(adev, acrtc, true); 8934 } 8935 /* Handle vrr on->off / off->on transitions */ 8936 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state); 8937 8938 #ifdef CONFIG_DEBUG_FS 8939 if (new_crtc_state->active && 8940 (!old_crtc_state->active || 8941 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 8942 /** 8943 * Frontend may have changed so reapply the CRC capture 8944 * settings for the stream. 8945 */ 8946 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { 8947 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 8948 if (amdgpu_dm_crc_window_is_activated(crtc)) { 8949 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 8950 acrtc->dm_irq_params.window_param.update_win = true; 8951 8952 /** 8953 * It takes 2 frames for HW to stably generate CRC when 8954 * resuming from suspend, so we set skip_frame_cnt 2. 8955 */ 8956 acrtc->dm_irq_params.window_param.skip_frame_cnt = 2; 8957 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 8958 } 8959 #endif 8960 if (amdgpu_dm_crtc_configure_crc_source( 8961 crtc, dm_new_crtc_state, cur_crc_src)) 8962 DRM_DEBUG_DRIVER("Failed to configure crc source"); 8963 } 8964 } 8965 #endif 8966 } 8967 8968 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) 8969 if (new_crtc_state->async_flip) 8970 wait_for_vblank = false; 8971 8972 /* update planes when needed per crtc*/ 8973 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 8974 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8975 8976 if (dm_new_crtc_state->stream) 8977 amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank); 8978 } 8979 8980 /* Update audio instances for each connector. */ 8981 amdgpu_dm_commit_audio(dev, state); 8982 8983 /* restore the backlight level */ 8984 for (i = 0; i < dm->num_of_edps; i++) { 8985 if (dm->backlight_dev[i] && 8986 (dm->actual_brightness[i] != dm->brightness[i])) 8987 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 8988 } 8989 8990 /* 8991 * send vblank event on all events not handled in flip and 8992 * mark consumed event for drm_atomic_helper_commit_hw_done 8993 */ 8994 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 8995 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 8996 8997 if (new_crtc_state->event) 8998 drm_send_event_locked(dev, &new_crtc_state->event->base); 8999 9000 new_crtc_state->event = NULL; 9001 } 9002 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 9003 9004 /* Signal HW programming completion */ 9005 drm_atomic_helper_commit_hw_done(state); 9006 9007 if (wait_for_vblank) 9008 drm_atomic_helper_wait_for_flip_done(dev, state); 9009 9010 drm_atomic_helper_cleanup_planes(dev, state); 9011 9012 /* Don't free the memory if we are hitting this as part of suspend. 9013 * This way we don't free any memory during suspend; see 9014 * amdgpu_bo_free_kernel(). The memory will be freed in the first 9015 * non-suspend modeset or when the driver is torn down. 9016 */ 9017 if (!adev->in_suspend) { 9018 /* return the stolen vga memory back to VRAM */ 9019 if (!adev->mman.keep_stolen_vga_memory) 9020 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 9021 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); 9022 } 9023 9024 /* 9025 * Finally, drop a runtime PM reference for each newly disabled CRTC, 9026 * so we can put the GPU into runtime suspend if we're not driving any 9027 * displays anymore 9028 */ 9029 for (i = 0; i < crtc_disable_count; i++) 9030 pm_runtime_put_autosuspend(dev->dev); 9031 pm_runtime_mark_last_busy(dev->dev); 9032 } 9033 9034 static int dm_force_atomic_commit(struct drm_connector *connector) 9035 { 9036 int ret = 0; 9037 struct drm_device *ddev = connector->dev; 9038 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); 9039 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 9040 struct drm_plane *plane = disconnected_acrtc->base.primary; 9041 struct drm_connector_state *conn_state; 9042 struct drm_crtc_state *crtc_state; 9043 struct drm_plane_state *plane_state; 9044 9045 if (!state) 9046 return -ENOMEM; 9047 9048 state->acquire_ctx = ddev->mode_config.acquire_ctx; 9049 9050 /* Construct an atomic state to restore previous display setting */ 9051 9052 /* 9053 * Attach connectors to drm_atomic_state 9054 */ 9055 conn_state = drm_atomic_get_connector_state(state, connector); 9056 9057 ret = PTR_ERR_OR_ZERO(conn_state); 9058 if (ret) 9059 goto out; 9060 9061 /* Attach crtc to drm_atomic_state*/ 9062 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); 9063 9064 ret = PTR_ERR_OR_ZERO(crtc_state); 9065 if (ret) 9066 goto out; 9067 9068 /* force a restore */ 9069 crtc_state->mode_changed = true; 9070 9071 /* Attach plane to drm_atomic_state */ 9072 plane_state = drm_atomic_get_plane_state(state, plane); 9073 9074 ret = PTR_ERR_OR_ZERO(plane_state); 9075 if (ret) 9076 goto out; 9077 9078 /* Call commit internally with the state we just constructed */ 9079 ret = drm_atomic_commit(state); 9080 9081 out: 9082 drm_atomic_state_put(state); 9083 if (ret) 9084 DRM_ERROR("Restoring old state failed with %i\n", ret); 9085 9086 return ret; 9087 } 9088 9089 /* 9090 * This function handles all cases when set mode does not come upon hotplug. 9091 * This includes when a display is unplugged then plugged back into the 9092 * same port and when running without usermode desktop manager supprot 9093 */ 9094 void dm_restore_drm_connector_state(struct drm_device *dev, 9095 struct drm_connector *connector) 9096 { 9097 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 9098 struct amdgpu_crtc *disconnected_acrtc; 9099 struct dm_crtc_state *acrtc_state; 9100 9101 if (!aconnector->dc_sink || !connector->state || !connector->encoder) 9102 return; 9103 9104 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 9105 if (!disconnected_acrtc) 9106 return; 9107 9108 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); 9109 if (!acrtc_state->stream) 9110 return; 9111 9112 /* 9113 * If the previous sink is not released and different from the current, 9114 * we deduce we are in a state where we can not rely on usermode call 9115 * to turn on the display, so we do it here 9116 */ 9117 if (acrtc_state->stream->sink != aconnector->dc_sink) 9118 dm_force_atomic_commit(&aconnector->base); 9119 } 9120 9121 /* 9122 * Grabs all modesetting locks to serialize against any blocking commits, 9123 * Waits for completion of all non blocking commits. 9124 */ 9125 static int do_aquire_global_lock(struct drm_device *dev, 9126 struct drm_atomic_state *state) 9127 { 9128 struct drm_crtc *crtc; 9129 struct drm_crtc_commit *commit; 9130 long ret; 9131 9132 /* 9133 * Adding all modeset locks to aquire_ctx will 9134 * ensure that when the framework release it the 9135 * extra locks we are locking here will get released to 9136 */ 9137 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 9138 if (ret) 9139 return ret; 9140 9141 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 9142 spin_lock(&crtc->commit_lock); 9143 commit = list_first_entry_or_null(&crtc->commit_list, 9144 struct drm_crtc_commit, commit_entry); 9145 if (commit) 9146 drm_crtc_commit_get(commit); 9147 spin_unlock(&crtc->commit_lock); 9148 9149 if (!commit) 9150 continue; 9151 9152 /* 9153 * Make sure all pending HW programming completed and 9154 * page flips done 9155 */ 9156 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 9157 9158 if (ret > 0) 9159 ret = wait_for_completion_interruptible_timeout( 9160 &commit->flip_done, 10*HZ); 9161 9162 if (ret == 0) 9163 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n", 9164 crtc->base.id, crtc->name); 9165 9166 drm_crtc_commit_put(commit); 9167 } 9168 9169 return ret < 0 ? ret : 0; 9170 } 9171 9172 static void get_freesync_config_for_crtc( 9173 struct dm_crtc_state *new_crtc_state, 9174 struct dm_connector_state *new_con_state) 9175 { 9176 struct mod_freesync_config config = {0}; 9177 struct amdgpu_dm_connector *aconnector = 9178 to_amdgpu_dm_connector(new_con_state->base.connector); 9179 struct drm_display_mode *mode = &new_crtc_state->base.mode; 9180 int vrefresh = drm_mode_vrefresh(mode); 9181 bool fs_vid_mode = false; 9182 9183 new_crtc_state->vrr_supported = new_con_state->freesync_capable && 9184 vrefresh >= aconnector->min_vfreq && 9185 vrefresh <= aconnector->max_vfreq; 9186 9187 if (new_crtc_state->vrr_supported) { 9188 new_crtc_state->stream->ignore_msa_timing_param = true; 9189 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 9190 9191 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000; 9192 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000; 9193 config.vsif_supported = true; 9194 config.btr = true; 9195 9196 if (fs_vid_mode) { 9197 config.state = VRR_STATE_ACTIVE_FIXED; 9198 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz; 9199 goto out; 9200 } else if (new_crtc_state->base.vrr_enabled) { 9201 config.state = VRR_STATE_ACTIVE_VARIABLE; 9202 } else { 9203 config.state = VRR_STATE_INACTIVE; 9204 } 9205 } 9206 out: 9207 new_crtc_state->freesync_config = config; 9208 } 9209 9210 static void reset_freesync_config_for_crtc( 9211 struct dm_crtc_state *new_crtc_state) 9212 { 9213 new_crtc_state->vrr_supported = false; 9214 9215 memset(&new_crtc_state->vrr_infopacket, 0, 9216 sizeof(new_crtc_state->vrr_infopacket)); 9217 } 9218 9219 static bool 9220 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 9221 struct drm_crtc_state *new_crtc_state) 9222 { 9223 const struct drm_display_mode *old_mode, *new_mode; 9224 9225 if (!old_crtc_state || !new_crtc_state) 9226 return false; 9227 9228 old_mode = &old_crtc_state->mode; 9229 new_mode = &new_crtc_state->mode; 9230 9231 if (old_mode->clock == new_mode->clock && 9232 old_mode->hdisplay == new_mode->hdisplay && 9233 old_mode->vdisplay == new_mode->vdisplay && 9234 old_mode->htotal == new_mode->htotal && 9235 old_mode->vtotal != new_mode->vtotal && 9236 old_mode->hsync_start == new_mode->hsync_start && 9237 old_mode->vsync_start != new_mode->vsync_start && 9238 old_mode->hsync_end == new_mode->hsync_end && 9239 old_mode->vsync_end != new_mode->vsync_end && 9240 old_mode->hskew == new_mode->hskew && 9241 old_mode->vscan == new_mode->vscan && 9242 (old_mode->vsync_end - old_mode->vsync_start) == 9243 (new_mode->vsync_end - new_mode->vsync_start)) 9244 return true; 9245 9246 return false; 9247 } 9248 9249 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) 9250 { 9251 u64 num, den, res; 9252 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base; 9253 9254 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED; 9255 9256 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000; 9257 den = (unsigned long long)new_crtc_state->mode.htotal * 9258 (unsigned long long)new_crtc_state->mode.vtotal; 9259 9260 res = div_u64(num, den); 9261 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res; 9262 } 9263 9264 static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 9265 struct drm_atomic_state *state, 9266 struct drm_crtc *crtc, 9267 struct drm_crtc_state *old_crtc_state, 9268 struct drm_crtc_state *new_crtc_state, 9269 bool enable, 9270 bool *lock_and_validation_needed) 9271 { 9272 struct dm_atomic_state *dm_state = NULL; 9273 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 9274 struct dc_stream_state *new_stream; 9275 int ret = 0; 9276 9277 /* 9278 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set 9279 * update changed items 9280 */ 9281 struct amdgpu_crtc *acrtc = NULL; 9282 struct amdgpu_dm_connector *aconnector = NULL; 9283 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 9284 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 9285 9286 new_stream = NULL; 9287 9288 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9289 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9290 acrtc = to_amdgpu_crtc(crtc); 9291 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 9292 9293 /* TODO This hack should go away */ 9294 if (aconnector && enable) { 9295 /* Make sure fake sink is created in plug-in scenario */ 9296 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 9297 &aconnector->base); 9298 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 9299 &aconnector->base); 9300 9301 if (IS_ERR(drm_new_conn_state)) { 9302 ret = PTR_ERR_OR_ZERO(drm_new_conn_state); 9303 goto fail; 9304 } 9305 9306 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 9307 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 9308 9309 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 9310 goto skip_modeset; 9311 9312 new_stream = create_validate_stream_for_sink(aconnector, 9313 &new_crtc_state->mode, 9314 dm_new_conn_state, 9315 dm_old_crtc_state->stream); 9316 9317 /* 9318 * we can have no stream on ACTION_SET if a display 9319 * was disconnected during S3, in this case it is not an 9320 * error, the OS will be updated after detection, and 9321 * will do the right thing on next atomic commit 9322 */ 9323 9324 if (!new_stream) { 9325 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 9326 __func__, acrtc->base.base.id); 9327 ret = -ENOMEM; 9328 goto fail; 9329 } 9330 9331 /* 9332 * TODO: Check VSDB bits to decide whether this should 9333 * be enabled or not. 9334 */ 9335 new_stream->triggered_crtc_reset.enabled = 9336 dm->force_timing_sync; 9337 9338 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 9339 9340 ret = fill_hdr_info_packet(drm_new_conn_state, 9341 &new_stream->hdr_static_metadata); 9342 if (ret) 9343 goto fail; 9344 9345 /* 9346 * If we already removed the old stream from the context 9347 * (and set the new stream to NULL) then we can't reuse 9348 * the old stream even if the stream and scaling are unchanged. 9349 * We'll hit the BUG_ON and black screen. 9350 * 9351 * TODO: Refactor this function to allow this check to work 9352 * in all conditions. 9353 */ 9354 if (dm_new_crtc_state->stream && 9355 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state)) 9356 goto skip_modeset; 9357 9358 if (dm_new_crtc_state->stream && 9359 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 9360 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 9361 new_crtc_state->mode_changed = false; 9362 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", 9363 new_crtc_state->mode_changed); 9364 } 9365 } 9366 9367 /* mode_changed flag may get updated above, need to check again */ 9368 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 9369 goto skip_modeset; 9370 9371 drm_dbg_state(state->dev, 9372 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 9373 acrtc->crtc_id, 9374 new_crtc_state->enable, 9375 new_crtc_state->active, 9376 new_crtc_state->planes_changed, 9377 new_crtc_state->mode_changed, 9378 new_crtc_state->active_changed, 9379 new_crtc_state->connectors_changed); 9380 9381 /* Remove stream for any changed/disabled CRTC */ 9382 if (!enable) { 9383 9384 if (!dm_old_crtc_state->stream) 9385 goto skip_modeset; 9386 9387 /* Unset freesync video if it was active before */ 9388 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) { 9389 dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE; 9390 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0; 9391 } 9392 9393 /* Now check if we should set freesync video mode */ 9394 if (dm_new_crtc_state->stream && 9395 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 9396 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) && 9397 is_timing_unchanged_for_freesync(new_crtc_state, 9398 old_crtc_state)) { 9399 new_crtc_state->mode_changed = false; 9400 DRM_DEBUG_DRIVER( 9401 "Mode change not required for front porch change, setting mode_changed to %d", 9402 new_crtc_state->mode_changed); 9403 9404 set_freesync_fixed_config(dm_new_crtc_state); 9405 9406 goto skip_modeset; 9407 } else if (aconnector && 9408 is_freesync_video_mode(&new_crtc_state->mode, 9409 aconnector)) { 9410 struct drm_display_mode *high_mode; 9411 9412 high_mode = get_highest_refresh_rate_mode(aconnector, false); 9413 if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) 9414 set_freesync_fixed_config(dm_new_crtc_state); 9415 } 9416 9417 ret = dm_atomic_get_state(state, &dm_state); 9418 if (ret) 9419 goto fail; 9420 9421 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", 9422 crtc->base.id); 9423 9424 /* i.e. reset mode */ 9425 if (dc_remove_stream_from_ctx( 9426 dm->dc, 9427 dm_state->context, 9428 dm_old_crtc_state->stream) != DC_OK) { 9429 ret = -EINVAL; 9430 goto fail; 9431 } 9432 9433 dc_stream_release(dm_old_crtc_state->stream); 9434 dm_new_crtc_state->stream = NULL; 9435 9436 reset_freesync_config_for_crtc(dm_new_crtc_state); 9437 9438 *lock_and_validation_needed = true; 9439 9440 } else {/* Add stream for any updated/enabled CRTC */ 9441 /* 9442 * Quick fix to prevent NULL pointer on new_stream when 9443 * added MST connectors not found in existing crtc_state in the chained mode 9444 * TODO: need to dig out the root cause of that 9445 */ 9446 if (!aconnector) 9447 goto skip_modeset; 9448 9449 if (modereset_required(new_crtc_state)) 9450 goto skip_modeset; 9451 9452 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream, 9453 dm_old_crtc_state->stream)) { 9454 9455 WARN_ON(dm_new_crtc_state->stream); 9456 9457 ret = dm_atomic_get_state(state, &dm_state); 9458 if (ret) 9459 goto fail; 9460 9461 dm_new_crtc_state->stream = new_stream; 9462 9463 dc_stream_retain(new_stream); 9464 9465 DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n", 9466 crtc->base.id); 9467 9468 if (dc_add_stream_to_ctx( 9469 dm->dc, 9470 dm_state->context, 9471 dm_new_crtc_state->stream) != DC_OK) { 9472 ret = -EINVAL; 9473 goto fail; 9474 } 9475 9476 *lock_and_validation_needed = true; 9477 } 9478 } 9479 9480 skip_modeset: 9481 /* Release extra reference */ 9482 if (new_stream) 9483 dc_stream_release(new_stream); 9484 9485 /* 9486 * We want to do dc stream updates that do not require a 9487 * full modeset below. 9488 */ 9489 if (!(enable && aconnector && new_crtc_state->active)) 9490 return 0; 9491 /* 9492 * Given above conditions, the dc state cannot be NULL because: 9493 * 1. We're in the process of enabling CRTCs (just been added 9494 * to the dc context, or already is on the context) 9495 * 2. Has a valid connector attached, and 9496 * 3. Is currently active and enabled. 9497 * => The dc stream state currently exists. 9498 */ 9499 BUG_ON(dm_new_crtc_state->stream == NULL); 9500 9501 /* Scaling or underscan settings */ 9502 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) || 9503 drm_atomic_crtc_needs_modeset(new_crtc_state)) 9504 update_stream_scaling_settings( 9505 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 9506 9507 /* ABM settings */ 9508 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 9509 9510 /* 9511 * Color management settings. We also update color properties 9512 * when a modeset is needed, to ensure it gets reprogrammed. 9513 */ 9514 if (dm_new_crtc_state->base.color_mgmt_changed || 9515 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 9516 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); 9517 if (ret) 9518 goto fail; 9519 } 9520 9521 /* Update Freesync settings. */ 9522 get_freesync_config_for_crtc(dm_new_crtc_state, 9523 dm_new_conn_state); 9524 9525 return ret; 9526 9527 fail: 9528 if (new_stream) 9529 dc_stream_release(new_stream); 9530 return ret; 9531 } 9532 9533 static bool should_reset_plane(struct drm_atomic_state *state, 9534 struct drm_plane *plane, 9535 struct drm_plane_state *old_plane_state, 9536 struct drm_plane_state *new_plane_state) 9537 { 9538 struct drm_plane *other; 9539 struct drm_plane_state *old_other_state, *new_other_state; 9540 struct drm_crtc_state *new_crtc_state; 9541 struct amdgpu_device *adev = drm_to_adev(plane->dev); 9542 int i; 9543 9544 /* 9545 * TODO: Remove this hack for all asics once it proves that the 9546 * fast updates works fine on DCN3.2+. 9547 */ 9548 if (adev->ip_versions[DCE_HWIP][0] < IP_VERSION(3, 2, 0) && state->allow_modeset) 9549 return true; 9550 9551 /* Exit early if we know that we're adding or removing the plane. */ 9552 if (old_plane_state->crtc != new_plane_state->crtc) 9553 return true; 9554 9555 /* old crtc == new_crtc == NULL, plane not in context. */ 9556 if (!new_plane_state->crtc) 9557 return false; 9558 9559 new_crtc_state = 9560 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 9561 9562 if (!new_crtc_state) 9563 return true; 9564 9565 /* CRTC Degamma changes currently require us to recreate planes. */ 9566 if (new_crtc_state->color_mgmt_changed) 9567 return true; 9568 9569 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) 9570 return true; 9571 9572 /* 9573 * If there are any new primary or overlay planes being added or 9574 * removed then the z-order can potentially change. To ensure 9575 * correct z-order and pipe acquisition the current DC architecture 9576 * requires us to remove and recreate all existing planes. 9577 * 9578 * TODO: Come up with a more elegant solution for this. 9579 */ 9580 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { 9581 struct amdgpu_framebuffer *old_afb, *new_afb; 9582 9583 if (other->type == DRM_PLANE_TYPE_CURSOR) 9584 continue; 9585 9586 if (old_other_state->crtc != new_plane_state->crtc && 9587 new_other_state->crtc != new_plane_state->crtc) 9588 continue; 9589 9590 if (old_other_state->crtc != new_other_state->crtc) 9591 return true; 9592 9593 /* Src/dst size and scaling updates. */ 9594 if (old_other_state->src_w != new_other_state->src_w || 9595 old_other_state->src_h != new_other_state->src_h || 9596 old_other_state->crtc_w != new_other_state->crtc_w || 9597 old_other_state->crtc_h != new_other_state->crtc_h) 9598 return true; 9599 9600 /* Rotation / mirroring updates. */ 9601 if (old_other_state->rotation != new_other_state->rotation) 9602 return true; 9603 9604 /* Blending updates. */ 9605 if (old_other_state->pixel_blend_mode != 9606 new_other_state->pixel_blend_mode) 9607 return true; 9608 9609 /* Alpha updates. */ 9610 if (old_other_state->alpha != new_other_state->alpha) 9611 return true; 9612 9613 /* Colorspace changes. */ 9614 if (old_other_state->color_range != new_other_state->color_range || 9615 old_other_state->color_encoding != new_other_state->color_encoding) 9616 return true; 9617 9618 /* Framebuffer checks fall at the end. */ 9619 if (!old_other_state->fb || !new_other_state->fb) 9620 continue; 9621 9622 /* Pixel format changes can require bandwidth updates. */ 9623 if (old_other_state->fb->format != new_other_state->fb->format) 9624 return true; 9625 9626 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb; 9627 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb; 9628 9629 /* Tiling and DCC changes also require bandwidth updates. */ 9630 if (old_afb->tiling_flags != new_afb->tiling_flags || 9631 old_afb->base.modifier != new_afb->base.modifier) 9632 return true; 9633 } 9634 9635 return false; 9636 } 9637 9638 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, 9639 struct drm_plane_state *new_plane_state, 9640 struct drm_framebuffer *fb) 9641 { 9642 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev); 9643 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); 9644 unsigned int pitch; 9645 bool linear; 9646 9647 if (fb->width > new_acrtc->max_cursor_width || 9648 fb->height > new_acrtc->max_cursor_height) { 9649 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n", 9650 new_plane_state->fb->width, 9651 new_plane_state->fb->height); 9652 return -EINVAL; 9653 } 9654 if (new_plane_state->src_w != fb->width << 16 || 9655 new_plane_state->src_h != fb->height << 16) { 9656 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); 9657 return -EINVAL; 9658 } 9659 9660 /* Pitch in pixels */ 9661 pitch = fb->pitches[0] / fb->format->cpp[0]; 9662 9663 if (fb->width != pitch) { 9664 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d", 9665 fb->width, pitch); 9666 return -EINVAL; 9667 } 9668 9669 switch (pitch) { 9670 case 64: 9671 case 128: 9672 case 256: 9673 /* FB pitch is supported by cursor plane */ 9674 break; 9675 default: 9676 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch); 9677 return -EINVAL; 9678 } 9679 9680 /* Core DRM takes care of checking FB modifiers, so we only need to 9681 * check tiling flags when the FB doesn't have a modifier. 9682 */ 9683 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) { 9684 if (adev->family < AMDGPU_FAMILY_AI) { 9685 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && 9686 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && 9687 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; 9688 } else { 9689 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; 9690 } 9691 if (!linear) { 9692 DRM_DEBUG_ATOMIC("Cursor FB not linear"); 9693 return -EINVAL; 9694 } 9695 } 9696 9697 return 0; 9698 } 9699 9700 static int dm_update_plane_state(struct dc *dc, 9701 struct drm_atomic_state *state, 9702 struct drm_plane *plane, 9703 struct drm_plane_state *old_plane_state, 9704 struct drm_plane_state *new_plane_state, 9705 bool enable, 9706 bool *lock_and_validation_needed, 9707 bool *is_top_most_overlay) 9708 { 9709 9710 struct dm_atomic_state *dm_state = NULL; 9711 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 9712 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 9713 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 9714 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 9715 struct amdgpu_crtc *new_acrtc; 9716 bool needs_reset; 9717 int ret = 0; 9718 9719 9720 new_plane_crtc = new_plane_state->crtc; 9721 old_plane_crtc = old_plane_state->crtc; 9722 dm_new_plane_state = to_dm_plane_state(new_plane_state); 9723 dm_old_plane_state = to_dm_plane_state(old_plane_state); 9724 9725 if (plane->type == DRM_PLANE_TYPE_CURSOR) { 9726 if (!enable || !new_plane_crtc || 9727 drm_atomic_plane_disabling(plane->state, new_plane_state)) 9728 return 0; 9729 9730 new_acrtc = to_amdgpu_crtc(new_plane_crtc); 9731 9732 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) { 9733 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); 9734 return -EINVAL; 9735 } 9736 9737 if (new_plane_state->fb) { 9738 ret = dm_check_cursor_fb(new_acrtc, new_plane_state, 9739 new_plane_state->fb); 9740 if (ret) 9741 return ret; 9742 } 9743 9744 return 0; 9745 } 9746 9747 needs_reset = should_reset_plane(state, plane, old_plane_state, 9748 new_plane_state); 9749 9750 /* Remove any changed/removed planes */ 9751 if (!enable) { 9752 if (!needs_reset) 9753 return 0; 9754 9755 if (!old_plane_crtc) 9756 return 0; 9757 9758 old_crtc_state = drm_atomic_get_old_crtc_state( 9759 state, old_plane_crtc); 9760 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9761 9762 if (!dm_old_crtc_state->stream) 9763 return 0; 9764 9765 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", 9766 plane->base.id, old_plane_crtc->base.id); 9767 9768 ret = dm_atomic_get_state(state, &dm_state); 9769 if (ret) 9770 return ret; 9771 9772 if (!dc_remove_plane_from_context( 9773 dc, 9774 dm_old_crtc_state->stream, 9775 dm_old_plane_state->dc_state, 9776 dm_state->context)) { 9777 9778 return -EINVAL; 9779 } 9780 9781 if (dm_old_plane_state->dc_state) 9782 dc_plane_state_release(dm_old_plane_state->dc_state); 9783 9784 dm_new_plane_state->dc_state = NULL; 9785 9786 *lock_and_validation_needed = true; 9787 9788 } else { /* Add new planes */ 9789 struct dc_plane_state *dc_new_plane_state; 9790 9791 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 9792 return 0; 9793 9794 if (!new_plane_crtc) 9795 return 0; 9796 9797 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 9798 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9799 9800 if (!dm_new_crtc_state->stream) 9801 return 0; 9802 9803 if (!needs_reset) 9804 return 0; 9805 9806 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state); 9807 if (ret) 9808 return ret; 9809 9810 WARN_ON(dm_new_plane_state->dc_state); 9811 9812 dc_new_plane_state = dc_create_plane_state(dc); 9813 if (!dc_new_plane_state) 9814 return -ENOMEM; 9815 9816 /* Block top most plane from being a video plane */ 9817 if (plane->type == DRM_PLANE_TYPE_OVERLAY) { 9818 if (is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay) 9819 return -EINVAL; 9820 9821 *is_top_most_overlay = false; 9822 } 9823 9824 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n", 9825 plane->base.id, new_plane_crtc->base.id); 9826 9827 ret = fill_dc_plane_attributes( 9828 drm_to_adev(new_plane_crtc->dev), 9829 dc_new_plane_state, 9830 new_plane_state, 9831 new_crtc_state); 9832 if (ret) { 9833 dc_plane_state_release(dc_new_plane_state); 9834 return ret; 9835 } 9836 9837 ret = dm_atomic_get_state(state, &dm_state); 9838 if (ret) { 9839 dc_plane_state_release(dc_new_plane_state); 9840 return ret; 9841 } 9842 9843 /* 9844 * Any atomic check errors that occur after this will 9845 * not need a release. The plane state will be attached 9846 * to the stream, and therefore part of the atomic 9847 * state. It'll be released when the atomic state is 9848 * cleaned. 9849 */ 9850 if (!dc_add_plane_to_context( 9851 dc, 9852 dm_new_crtc_state->stream, 9853 dc_new_plane_state, 9854 dm_state->context)) { 9855 9856 dc_plane_state_release(dc_new_plane_state); 9857 return -EINVAL; 9858 } 9859 9860 dm_new_plane_state->dc_state = dc_new_plane_state; 9861 9862 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY); 9863 9864 /* Tell DC to do a full surface update every time there 9865 * is a plane change. Inefficient, but works for now. 9866 */ 9867 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; 9868 9869 *lock_and_validation_needed = true; 9870 } 9871 9872 9873 return ret; 9874 } 9875 9876 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state, 9877 int *src_w, int *src_h) 9878 { 9879 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 9880 case DRM_MODE_ROTATE_90: 9881 case DRM_MODE_ROTATE_270: 9882 *src_w = plane_state->src_h >> 16; 9883 *src_h = plane_state->src_w >> 16; 9884 break; 9885 case DRM_MODE_ROTATE_0: 9886 case DRM_MODE_ROTATE_180: 9887 default: 9888 *src_w = plane_state->src_w >> 16; 9889 *src_h = plane_state->src_h >> 16; 9890 break; 9891 } 9892 } 9893 9894 static void 9895 dm_get_plane_scale(struct drm_plane_state *plane_state, 9896 int *out_plane_scale_w, int *out_plane_scale_h) 9897 { 9898 int plane_src_w, plane_src_h; 9899 9900 dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h); 9901 *out_plane_scale_w = plane_state->crtc_w * 1000 / plane_src_w; 9902 *out_plane_scale_h = plane_state->crtc_h * 1000 / plane_src_h; 9903 } 9904 9905 static int dm_check_crtc_cursor(struct drm_atomic_state *state, 9906 struct drm_crtc *crtc, 9907 struct drm_crtc_state *new_crtc_state) 9908 { 9909 struct drm_plane *cursor = crtc->cursor, *plane, *underlying; 9910 struct drm_plane_state *old_plane_state, *new_plane_state; 9911 struct drm_plane_state *new_cursor_state, *new_underlying_state; 9912 int i; 9913 int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h; 9914 bool any_relevant_change = false; 9915 9916 /* On DCE and DCN there is no dedicated hardware cursor plane. We get a 9917 * cursor per pipe but it's going to inherit the scaling and 9918 * positioning from the underlying pipe. Check the cursor plane's 9919 * blending properties match the underlying planes'. 9920 */ 9921 9922 /* If no plane was enabled or changed scaling, no need to check again */ 9923 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 9924 int new_scale_w, new_scale_h, old_scale_w, old_scale_h; 9925 9926 if (!new_plane_state || !new_plane_state->fb || new_plane_state->crtc != crtc) 9927 continue; 9928 9929 if (!old_plane_state || !old_plane_state->fb || old_plane_state->crtc != crtc) { 9930 any_relevant_change = true; 9931 break; 9932 } 9933 9934 if (new_plane_state->fb == old_plane_state->fb && 9935 new_plane_state->crtc_w == old_plane_state->crtc_w && 9936 new_plane_state->crtc_h == old_plane_state->crtc_h) 9937 continue; 9938 9939 dm_get_plane_scale(new_plane_state, &new_scale_w, &new_scale_h); 9940 dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h); 9941 9942 if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) { 9943 any_relevant_change = true; 9944 break; 9945 } 9946 } 9947 9948 if (!any_relevant_change) 9949 return 0; 9950 9951 new_cursor_state = drm_atomic_get_plane_state(state, cursor); 9952 if (IS_ERR(new_cursor_state)) 9953 return PTR_ERR(new_cursor_state); 9954 9955 if (!new_cursor_state->fb) 9956 return 0; 9957 9958 dm_get_plane_scale(new_cursor_state, &cursor_scale_w, &cursor_scale_h); 9959 9960 /* Need to check all enabled planes, even if this commit doesn't change 9961 * their state 9962 */ 9963 i = drm_atomic_add_affected_planes(state, crtc); 9964 if (i) 9965 return i; 9966 9967 for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) { 9968 /* Narrow down to non-cursor planes on the same CRTC as the cursor */ 9969 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor) 9970 continue; 9971 9972 /* Ignore disabled planes */ 9973 if (!new_underlying_state->fb) 9974 continue; 9975 9976 dm_get_plane_scale(new_underlying_state, 9977 &underlying_scale_w, &underlying_scale_h); 9978 9979 if (cursor_scale_w != underlying_scale_w || 9980 cursor_scale_h != underlying_scale_h) { 9981 drm_dbg_atomic(crtc->dev, 9982 "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n", 9983 cursor->base.id, cursor->name, underlying->base.id, underlying->name); 9984 return -EINVAL; 9985 } 9986 9987 /* If this plane covers the whole CRTC, no need to check planes underneath */ 9988 if (new_underlying_state->crtc_x <= 0 && 9989 new_underlying_state->crtc_y <= 0 && 9990 new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay && 9991 new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay) 9992 break; 9993 } 9994 9995 return 0; 9996 } 9997 9998 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc) 9999 { 10000 struct drm_connector *connector; 10001 struct drm_connector_state *conn_state, *old_conn_state; 10002 struct amdgpu_dm_connector *aconnector = NULL; 10003 int i; 10004 10005 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) { 10006 if (!conn_state->crtc) 10007 conn_state = old_conn_state; 10008 10009 if (conn_state->crtc != crtc) 10010 continue; 10011 10012 aconnector = to_amdgpu_dm_connector(connector); 10013 if (!aconnector->mst_output_port || !aconnector->mst_root) 10014 aconnector = NULL; 10015 else 10016 break; 10017 } 10018 10019 if (!aconnector) 10020 return 0; 10021 10022 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr); 10023 } 10024 10025 /** 10026 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. 10027 * 10028 * @dev: The DRM device 10029 * @state: The atomic state to commit 10030 * 10031 * Validate that the given atomic state is programmable by DC into hardware. 10032 * This involves constructing a &struct dc_state reflecting the new hardware 10033 * state we wish to commit, then querying DC to see if it is programmable. It's 10034 * important not to modify the existing DC state. Otherwise, atomic_check 10035 * may unexpectedly commit hardware changes. 10036 * 10037 * When validating the DC state, it's important that the right locks are 10038 * acquired. For full updates case which removes/adds/updates streams on one 10039 * CRTC while flipping on another CRTC, acquiring global lock will guarantee 10040 * that any such full update commit will wait for completion of any outstanding 10041 * flip using DRMs synchronization events. 10042 * 10043 * Note that DM adds the affected connectors for all CRTCs in state, when that 10044 * might not seem necessary. This is because DC stream creation requires the 10045 * DC sink, which is tied to the DRM connector state. Cleaning this up should 10046 * be possible but non-trivial - a possible TODO item. 10047 * 10048 * Return: -Error code if validation failed. 10049 */ 10050 static int amdgpu_dm_atomic_check(struct drm_device *dev, 10051 struct drm_atomic_state *state) 10052 { 10053 struct amdgpu_device *adev = drm_to_adev(dev); 10054 struct dm_atomic_state *dm_state = NULL; 10055 struct dc *dc = adev->dm.dc; 10056 struct drm_connector *connector; 10057 struct drm_connector_state *old_con_state, *new_con_state; 10058 struct drm_crtc *crtc; 10059 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 10060 struct drm_plane *plane; 10061 struct drm_plane_state *old_plane_state, *new_plane_state; 10062 enum dc_status status; 10063 int ret, i; 10064 bool lock_and_validation_needed = false; 10065 bool is_top_most_overlay = true; 10066 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 10067 struct drm_dp_mst_topology_mgr *mgr; 10068 struct drm_dp_mst_topology_state *mst_state; 10069 struct dsc_mst_fairness_vars vars[MAX_PIPES]; 10070 10071 trace_amdgpu_dm_atomic_check_begin(state); 10072 10073 ret = drm_atomic_helper_check_modeset(dev, state); 10074 if (ret) { 10075 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n"); 10076 goto fail; 10077 } 10078 10079 /* Check connector changes */ 10080 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 10081 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 10082 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 10083 10084 /* Skip connectors that are disabled or part of modeset already. */ 10085 if (!new_con_state->crtc) 10086 continue; 10087 10088 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc); 10089 if (IS_ERR(new_crtc_state)) { 10090 DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n"); 10091 ret = PTR_ERR(new_crtc_state); 10092 goto fail; 10093 } 10094 10095 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level || 10096 dm_old_con_state->scaling != dm_new_con_state->scaling) 10097 new_crtc_state->connectors_changed = true; 10098 } 10099 10100 if (dc_resource_is_dsc_encoding_supported(dc)) { 10101 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 10102 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { 10103 ret = add_affected_mst_dsc_crtcs(state, crtc); 10104 if (ret) { 10105 DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n"); 10106 goto fail; 10107 } 10108 } 10109 } 10110 } 10111 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 10112 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 10113 10114 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 10115 !new_crtc_state->color_mgmt_changed && 10116 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled && 10117 dm_old_crtc_state->dsc_force_changed == false) 10118 continue; 10119 10120 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state); 10121 if (ret) { 10122 DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n"); 10123 goto fail; 10124 } 10125 10126 if (!new_crtc_state->enable) 10127 continue; 10128 10129 ret = drm_atomic_add_affected_connectors(state, crtc); 10130 if (ret) { 10131 DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n"); 10132 goto fail; 10133 } 10134 10135 ret = drm_atomic_add_affected_planes(state, crtc); 10136 if (ret) { 10137 DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n"); 10138 goto fail; 10139 } 10140 10141 if (dm_old_crtc_state->dsc_force_changed) 10142 new_crtc_state->mode_changed = true; 10143 } 10144 10145 /* 10146 * Add all primary and overlay planes on the CRTC to the state 10147 * whenever a plane is enabled to maintain correct z-ordering 10148 * and to enable fast surface updates. 10149 */ 10150 drm_for_each_crtc(crtc, dev) { 10151 bool modified = false; 10152 10153 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 10154 if (plane->type == DRM_PLANE_TYPE_CURSOR) 10155 continue; 10156 10157 if (new_plane_state->crtc == crtc || 10158 old_plane_state->crtc == crtc) { 10159 modified = true; 10160 break; 10161 } 10162 } 10163 10164 if (!modified) 10165 continue; 10166 10167 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { 10168 if (plane->type == DRM_PLANE_TYPE_CURSOR) 10169 continue; 10170 10171 new_plane_state = 10172 drm_atomic_get_plane_state(state, plane); 10173 10174 if (IS_ERR(new_plane_state)) { 10175 ret = PTR_ERR(new_plane_state); 10176 DRM_DEBUG_DRIVER("new_plane_state is BAD\n"); 10177 goto fail; 10178 } 10179 } 10180 } 10181 10182 /* 10183 * DC consults the zpos (layer_index in DC terminology) to determine the 10184 * hw plane on which to enable the hw cursor (see 10185 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in 10186 * atomic state, so call drm helper to normalize zpos. 10187 */ 10188 ret = drm_atomic_normalize_zpos(dev, state); 10189 if (ret) { 10190 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n"); 10191 goto fail; 10192 } 10193 10194 /* Remove exiting planes if they are modified */ 10195 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 10196 if (old_plane_state->fb && new_plane_state->fb && 10197 get_mem_type(old_plane_state->fb) != 10198 get_mem_type(new_plane_state->fb)) 10199 lock_and_validation_needed = true; 10200 10201 ret = dm_update_plane_state(dc, state, plane, 10202 old_plane_state, 10203 new_plane_state, 10204 false, 10205 &lock_and_validation_needed, 10206 &is_top_most_overlay); 10207 if (ret) { 10208 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n"); 10209 goto fail; 10210 } 10211 } 10212 10213 /* Disable all crtcs which require disable */ 10214 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 10215 ret = dm_update_crtc_state(&adev->dm, state, crtc, 10216 old_crtc_state, 10217 new_crtc_state, 10218 false, 10219 &lock_and_validation_needed); 10220 if (ret) { 10221 DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n"); 10222 goto fail; 10223 } 10224 } 10225 10226 /* Enable all crtcs which require enable */ 10227 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 10228 ret = dm_update_crtc_state(&adev->dm, state, crtc, 10229 old_crtc_state, 10230 new_crtc_state, 10231 true, 10232 &lock_and_validation_needed); 10233 if (ret) { 10234 DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n"); 10235 goto fail; 10236 } 10237 } 10238 10239 /* Add new/modified planes */ 10240 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 10241 ret = dm_update_plane_state(dc, state, plane, 10242 old_plane_state, 10243 new_plane_state, 10244 true, 10245 &lock_and_validation_needed, 10246 &is_top_most_overlay); 10247 if (ret) { 10248 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n"); 10249 goto fail; 10250 } 10251 } 10252 10253 if (dc_resource_is_dsc_encoding_supported(dc)) { 10254 ret = pre_validate_dsc(state, &dm_state, vars); 10255 if (ret != 0) 10256 goto fail; 10257 } 10258 10259 /* Run this here since we want to validate the streams we created */ 10260 ret = drm_atomic_helper_check_planes(dev, state); 10261 if (ret) { 10262 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n"); 10263 goto fail; 10264 } 10265 10266 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 10267 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 10268 if (dm_new_crtc_state->mpo_requested) 10269 DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc); 10270 } 10271 10272 /* Check cursor planes scaling */ 10273 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 10274 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state); 10275 if (ret) { 10276 DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n"); 10277 goto fail; 10278 } 10279 } 10280 10281 if (state->legacy_cursor_update) { 10282 /* 10283 * This is a fast cursor update coming from the plane update 10284 * helper, check if it can be done asynchronously for better 10285 * performance. 10286 */ 10287 state->async_update = 10288 !drm_atomic_helper_async_check(dev, state); 10289 10290 /* 10291 * Skip the remaining global validation if this is an async 10292 * update. Cursor updates can be done without affecting 10293 * state or bandwidth calcs and this avoids the performance 10294 * penalty of locking the private state object and 10295 * allocating a new dc_state. 10296 */ 10297 if (state->async_update) 10298 return 0; 10299 } 10300 10301 /* Check scaling and underscan changes*/ 10302 /* TODO Removed scaling changes validation due to inability to commit 10303 * new stream into context w\o causing full reset. Need to 10304 * decide how to handle. 10305 */ 10306 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 10307 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 10308 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 10309 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 10310 10311 /* Skip any modesets/resets */ 10312 if (!acrtc || drm_atomic_crtc_needs_modeset( 10313 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 10314 continue; 10315 10316 /* Skip any thing not scale or underscan changes */ 10317 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 10318 continue; 10319 10320 lock_and_validation_needed = true; 10321 } 10322 10323 /* set the slot info for each mst_state based on the link encoding format */ 10324 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { 10325 struct amdgpu_dm_connector *aconnector; 10326 struct drm_connector *connector; 10327 struct drm_connector_list_iter iter; 10328 u8 link_coding_cap; 10329 10330 drm_connector_list_iter_begin(dev, &iter); 10331 drm_for_each_connector_iter(connector, &iter) { 10332 if (connector->index == mst_state->mgr->conn_base_id) { 10333 aconnector = to_amdgpu_dm_connector(connector); 10334 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); 10335 drm_dp_mst_update_slots(mst_state, link_coding_cap); 10336 10337 break; 10338 } 10339 } 10340 drm_connector_list_iter_end(&iter); 10341 } 10342 10343 /** 10344 * Streams and planes are reset when there are changes that affect 10345 * bandwidth. Anything that affects bandwidth needs to go through 10346 * DC global validation to ensure that the configuration can be applied 10347 * to hardware. 10348 * 10349 * We have to currently stall out here in atomic_check for outstanding 10350 * commits to finish in this case because our IRQ handlers reference 10351 * DRM state directly - we can end up disabling interrupts too early 10352 * if we don't. 10353 * 10354 * TODO: Remove this stall and drop DM state private objects. 10355 */ 10356 if (lock_and_validation_needed) { 10357 ret = dm_atomic_get_state(state, &dm_state); 10358 if (ret) { 10359 DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n"); 10360 goto fail; 10361 } 10362 10363 ret = do_aquire_global_lock(dev, state); 10364 if (ret) { 10365 DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n"); 10366 goto fail; 10367 } 10368 10369 if (dc_resource_is_dsc_encoding_supported(dc)) { 10370 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); 10371 if (ret) { 10372 DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n"); 10373 ret = -EINVAL; 10374 goto fail; 10375 } 10376 } 10377 10378 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); 10379 if (ret) { 10380 DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n"); 10381 goto fail; 10382 } 10383 10384 /* 10385 * Perform validation of MST topology in the state: 10386 * We need to perform MST atomic check before calling 10387 * dc_validate_global_state(), or there is a chance 10388 * to get stuck in an infinite loop and hang eventually. 10389 */ 10390 ret = drm_dp_mst_atomic_check(state); 10391 if (ret) { 10392 DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n"); 10393 goto fail; 10394 } 10395 status = dc_validate_global_state(dc, dm_state->context, true); 10396 if (status != DC_OK) { 10397 DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)", 10398 dc_status_to_str(status), status); 10399 ret = -EINVAL; 10400 goto fail; 10401 } 10402 } else { 10403 /* 10404 * The commit is a fast update. Fast updates shouldn't change 10405 * the DC context, affect global validation, and can have their 10406 * commit work done in parallel with other commits not touching 10407 * the same resource. If we have a new DC context as part of 10408 * the DM atomic state from validation we need to free it and 10409 * retain the existing one instead. 10410 * 10411 * Furthermore, since the DM atomic state only contains the DC 10412 * context and can safely be annulled, we can free the state 10413 * and clear the associated private object now to free 10414 * some memory and avoid a possible use-after-free later. 10415 */ 10416 10417 for (i = 0; i < state->num_private_objs; i++) { 10418 struct drm_private_obj *obj = state->private_objs[i].ptr; 10419 10420 if (obj->funcs == adev->dm.atomic_obj.funcs) { 10421 int j = state->num_private_objs-1; 10422 10423 dm_atomic_destroy_state(obj, 10424 state->private_objs[i].state); 10425 10426 /* If i is not at the end of the array then the 10427 * last element needs to be moved to where i was 10428 * before the array can safely be truncated. 10429 */ 10430 if (i != j) 10431 state->private_objs[i] = 10432 state->private_objs[j]; 10433 10434 state->private_objs[j].ptr = NULL; 10435 state->private_objs[j].state = NULL; 10436 state->private_objs[j].old_state = NULL; 10437 state->private_objs[j].new_state = NULL; 10438 10439 state->num_private_objs = j; 10440 break; 10441 } 10442 } 10443 } 10444 10445 /* Store the overall update type for use later in atomic check. */ 10446 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 10447 struct dm_crtc_state *dm_new_crtc_state = 10448 to_dm_crtc_state(new_crtc_state); 10449 10450 /* 10451 * Only allow async flips for fast updates that don't change 10452 * the FB pitch, the DCC state, rotation, etc. 10453 */ 10454 if (new_crtc_state->async_flip && lock_and_validation_needed) { 10455 drm_dbg_atomic(crtc->dev, 10456 "[CRTC:%d:%s] async flips are only supported for fast updates\n", 10457 crtc->base.id, crtc->name); 10458 ret = -EINVAL; 10459 goto fail; 10460 } 10461 10462 dm_new_crtc_state->update_type = lock_and_validation_needed ? 10463 UPDATE_TYPE_FULL : UPDATE_TYPE_FAST; 10464 } 10465 10466 /* Must be success */ 10467 WARN_ON(ret); 10468 10469 trace_amdgpu_dm_atomic_check_finish(state, ret); 10470 10471 return ret; 10472 10473 fail: 10474 if (ret == -EDEADLK) 10475 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n"); 10476 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 10477 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); 10478 else 10479 DRM_DEBUG_DRIVER("Atomic check failed with err: %d\n", ret); 10480 10481 trace_amdgpu_dm_atomic_check_finish(state, ret); 10482 10483 return ret; 10484 } 10485 10486 static bool is_dp_capable_without_timing_msa(struct dc *dc, 10487 struct amdgpu_dm_connector *amdgpu_dm_connector) 10488 { 10489 u8 dpcd_data; 10490 bool capable = false; 10491 10492 if (amdgpu_dm_connector->dc_link && 10493 dm_helpers_dp_read_dpcd( 10494 NULL, 10495 amdgpu_dm_connector->dc_link, 10496 DP_DOWN_STREAM_PORT_COUNT, 10497 &dpcd_data, 10498 sizeof(dpcd_data))) { 10499 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; 10500 } 10501 10502 return capable; 10503 } 10504 10505 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm, 10506 unsigned int offset, 10507 unsigned int total_length, 10508 u8 *data, 10509 unsigned int length, 10510 struct amdgpu_hdmi_vsdb_info *vsdb) 10511 { 10512 bool res; 10513 union dmub_rb_cmd cmd; 10514 struct dmub_cmd_send_edid_cea *input; 10515 struct dmub_cmd_edid_cea_output *output; 10516 10517 if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES) 10518 return false; 10519 10520 memset(&cmd, 0, sizeof(cmd)); 10521 10522 input = &cmd.edid_cea.data.input; 10523 10524 cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA; 10525 cmd.edid_cea.header.sub_type = 0; 10526 cmd.edid_cea.header.payload_bytes = 10527 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header); 10528 input->offset = offset; 10529 input->length = length; 10530 input->cea_total_length = total_length; 10531 memcpy(input->payload, data, length); 10532 10533 res = dm_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY); 10534 if (!res) { 10535 DRM_ERROR("EDID CEA parser failed\n"); 10536 return false; 10537 } 10538 10539 output = &cmd.edid_cea.data.output; 10540 10541 if (output->type == DMUB_CMD__EDID_CEA_ACK) { 10542 if (!output->ack.success) { 10543 DRM_ERROR("EDID CEA ack failed at offset %d\n", 10544 output->ack.offset); 10545 } 10546 } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) { 10547 if (!output->amd_vsdb.vsdb_found) 10548 return false; 10549 10550 vsdb->freesync_supported = output->amd_vsdb.freesync_supported; 10551 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version; 10552 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate; 10553 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate; 10554 } else { 10555 if (output->type != 0) 10556 DRM_WARN("Unknown EDID CEA parser results\n"); 10557 return false; 10558 } 10559 10560 return true; 10561 } 10562 10563 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm, 10564 u8 *edid_ext, int len, 10565 struct amdgpu_hdmi_vsdb_info *vsdb_info) 10566 { 10567 int i; 10568 10569 /* send extension block to DMCU for parsing */ 10570 for (i = 0; i < len; i += 8) { 10571 bool res; 10572 int offset; 10573 10574 /* send 8 bytes a time */ 10575 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8)) 10576 return false; 10577 10578 if (i+8 == len) { 10579 /* EDID block sent completed, expect result */ 10580 int version, min_rate, max_rate; 10581 10582 res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate); 10583 if (res) { 10584 /* amd vsdb found */ 10585 vsdb_info->freesync_supported = 1; 10586 vsdb_info->amd_vsdb_version = version; 10587 vsdb_info->min_refresh_rate_hz = min_rate; 10588 vsdb_info->max_refresh_rate_hz = max_rate; 10589 return true; 10590 } 10591 /* not amd vsdb */ 10592 return false; 10593 } 10594 10595 /* check for ack*/ 10596 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset); 10597 if (!res) 10598 return false; 10599 } 10600 10601 return false; 10602 } 10603 10604 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm, 10605 u8 *edid_ext, int len, 10606 struct amdgpu_hdmi_vsdb_info *vsdb_info) 10607 { 10608 int i; 10609 10610 /* send extension block to DMCU for parsing */ 10611 for (i = 0; i < len; i += 8) { 10612 /* send 8 bytes a time */ 10613 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info)) 10614 return false; 10615 } 10616 10617 return vsdb_info->freesync_supported; 10618 } 10619 10620 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector, 10621 u8 *edid_ext, int len, 10622 struct amdgpu_hdmi_vsdb_info *vsdb_info) 10623 { 10624 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); 10625 bool ret; 10626 10627 mutex_lock(&adev->dm.dc_lock); 10628 if (adev->dm.dmub_srv) 10629 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info); 10630 else 10631 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info); 10632 mutex_unlock(&adev->dm.dc_lock); 10633 return ret; 10634 } 10635 10636 static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector, 10637 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) 10638 { 10639 u8 *edid_ext = NULL; 10640 int i; 10641 int j = 0; 10642 10643 if (edid == NULL || edid->extensions == 0) 10644 return -ENODEV; 10645 10646 /* Find DisplayID extension */ 10647 for (i = 0; i < edid->extensions; i++) { 10648 edid_ext = (void *)(edid + (i + 1)); 10649 if (edid_ext[0] == DISPLAYID_EXT) 10650 break; 10651 } 10652 10653 while (j < EDID_LENGTH) { 10654 struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j]; 10655 unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]); 10656 10657 if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID && 10658 amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) { 10659 vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false; 10660 vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3; 10661 DRM_DEBUG_KMS("Panel supports Replay Mode: %d\n", vsdb_info->replay_mode); 10662 10663 return true; 10664 } 10665 j++; 10666 } 10667 10668 return false; 10669 } 10670 10671 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, 10672 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) 10673 { 10674 u8 *edid_ext = NULL; 10675 int i; 10676 bool valid_vsdb_found = false; 10677 10678 /*----- drm_find_cea_extension() -----*/ 10679 /* No EDID or EDID extensions */ 10680 if (edid == NULL || edid->extensions == 0) 10681 return -ENODEV; 10682 10683 /* Find CEA extension */ 10684 for (i = 0; i < edid->extensions; i++) { 10685 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1); 10686 if (edid_ext[0] == CEA_EXT) 10687 break; 10688 } 10689 10690 if (i == edid->extensions) 10691 return -ENODEV; 10692 10693 /*----- cea_db_offsets() -----*/ 10694 if (edid_ext[0] != CEA_EXT) 10695 return -ENODEV; 10696 10697 valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info); 10698 10699 return valid_vsdb_found ? i : -ENODEV; 10700 } 10701 10702 /** 10703 * amdgpu_dm_update_freesync_caps - Update Freesync capabilities 10704 * 10705 * @connector: Connector to query. 10706 * @edid: EDID from monitor 10707 * 10708 * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep 10709 * track of some of the display information in the internal data struct used by 10710 * amdgpu_dm. This function checks which type of connector we need to set the 10711 * FreeSync parameters. 10712 */ 10713 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 10714 struct edid *edid) 10715 { 10716 int i = 0; 10717 struct detailed_timing *timing; 10718 struct detailed_non_pixel *data; 10719 struct detailed_data_monitor_range *range; 10720 struct amdgpu_dm_connector *amdgpu_dm_connector = 10721 to_amdgpu_dm_connector(connector); 10722 struct dm_connector_state *dm_con_state = NULL; 10723 struct dc_sink *sink; 10724 10725 struct drm_device *dev = connector->dev; 10726 struct amdgpu_device *adev = drm_to_adev(dev); 10727 struct amdgpu_hdmi_vsdb_info vsdb_info = {0}; 10728 bool freesync_capable = false; 10729 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; 10730 10731 if (!connector->state) { 10732 DRM_ERROR("%s - Connector has no state", __func__); 10733 goto update; 10734 } 10735 10736 sink = amdgpu_dm_connector->dc_sink ? 10737 amdgpu_dm_connector->dc_sink : 10738 amdgpu_dm_connector->dc_em_sink; 10739 10740 if (!edid || !sink) { 10741 dm_con_state = to_dm_connector_state(connector->state); 10742 10743 amdgpu_dm_connector->min_vfreq = 0; 10744 amdgpu_dm_connector->max_vfreq = 0; 10745 amdgpu_dm_connector->pixel_clock_mhz = 0; 10746 connector->display_info.monitor_range.min_vfreq = 0; 10747 connector->display_info.monitor_range.max_vfreq = 0; 10748 freesync_capable = false; 10749 10750 goto update; 10751 } 10752 10753 dm_con_state = to_dm_connector_state(connector->state); 10754 10755 if (!adev->dm.freesync_module) 10756 goto update; 10757 10758 if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT 10759 || sink->sink_signal == SIGNAL_TYPE_EDP) { 10760 bool edid_check_required = false; 10761 10762 if (edid) { 10763 edid_check_required = is_dp_capable_without_timing_msa( 10764 adev->dm.dc, 10765 amdgpu_dm_connector); 10766 } 10767 10768 if (edid_check_required == true && (edid->version > 1 || 10769 (edid->version == 1 && edid->revision > 1))) { 10770 for (i = 0; i < 4; i++) { 10771 10772 timing = &edid->detailed_timings[i]; 10773 data = &timing->data.other_data; 10774 range = &data->data.range; 10775 /* 10776 * Check if monitor has continuous frequency mode 10777 */ 10778 if (data->type != EDID_DETAIL_MONITOR_RANGE) 10779 continue; 10780 /* 10781 * Check for flag range limits only. If flag == 1 then 10782 * no additional timing information provided. 10783 * Default GTF, GTF Secondary curve and CVT are not 10784 * supported 10785 */ 10786 if (range->flags != 1) 10787 continue; 10788 10789 amdgpu_dm_connector->min_vfreq = range->min_vfreq; 10790 amdgpu_dm_connector->max_vfreq = range->max_vfreq; 10791 amdgpu_dm_connector->pixel_clock_mhz = 10792 range->pixel_clock_mhz * 10; 10793 10794 connector->display_info.monitor_range.min_vfreq = range->min_vfreq; 10795 connector->display_info.monitor_range.max_vfreq = range->max_vfreq; 10796 10797 break; 10798 } 10799 10800 if (amdgpu_dm_connector->max_vfreq - 10801 amdgpu_dm_connector->min_vfreq > 10) { 10802 10803 freesync_capable = true; 10804 } 10805 } 10806 parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 10807 10808 if (vsdb_info.replay_mode) { 10809 amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode; 10810 amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version; 10811 amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP; 10812 } 10813 10814 } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { 10815 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 10816 if (i >= 0 && vsdb_info.freesync_supported) { 10817 timing = &edid->detailed_timings[i]; 10818 data = &timing->data.other_data; 10819 10820 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; 10821 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; 10822 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 10823 freesync_capable = true; 10824 10825 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; 10826 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; 10827 } 10828 } 10829 10830 as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link); 10831 10832 if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) { 10833 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 10834 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) { 10835 10836 amdgpu_dm_connector->pack_sdp_v1_3 = true; 10837 amdgpu_dm_connector->as_type = as_type; 10838 amdgpu_dm_connector->vsdb_info = vsdb_info; 10839 10840 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; 10841 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; 10842 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 10843 freesync_capable = true; 10844 10845 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; 10846 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; 10847 } 10848 } 10849 10850 update: 10851 if (dm_con_state) 10852 dm_con_state->freesync_capable = freesync_capable; 10853 10854 if (connector->vrr_capable_property) 10855 drm_connector_set_vrr_capable_property(connector, 10856 freesync_capable); 10857 } 10858 10859 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev) 10860 { 10861 struct amdgpu_device *adev = drm_to_adev(dev); 10862 struct dc *dc = adev->dm.dc; 10863 int i; 10864 10865 mutex_lock(&adev->dm.dc_lock); 10866 if (dc->current_state) { 10867 for (i = 0; i < dc->current_state->stream_count; ++i) 10868 dc->current_state->streams[i] 10869 ->triggered_crtc_reset.enabled = 10870 adev->dm.force_timing_sync; 10871 10872 dm_enable_per_frame_crtc_master_sync(dc->current_state); 10873 dc_trigger_sync(dc, dc->current_state); 10874 } 10875 mutex_unlock(&adev->dm.dc_lock); 10876 } 10877 10878 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address, 10879 u32 value, const char *func_name) 10880 { 10881 #ifdef DM_CHECK_ADDR_0 10882 if (address == 0) { 10883 DC_ERR("invalid register write. address = 0"); 10884 return; 10885 } 10886 #endif 10887 cgs_write_register(ctx->cgs_device, address, value); 10888 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value); 10889 } 10890 10891 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address, 10892 const char *func_name) 10893 { 10894 u32 value; 10895 #ifdef DM_CHECK_ADDR_0 10896 if (address == 0) { 10897 DC_ERR("invalid register read; address = 0\n"); 10898 return 0; 10899 } 10900 #endif 10901 10902 if (ctx->dmub_srv && 10903 ctx->dmub_srv->reg_helper_offload.gather_in_progress && 10904 !ctx->dmub_srv->reg_helper_offload.should_burst_write) { 10905 ASSERT(false); 10906 return 0; 10907 } 10908 10909 value = cgs_read_register(ctx->cgs_device, address); 10910 10911 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value); 10912 10913 return value; 10914 } 10915 10916 int amdgpu_dm_process_dmub_aux_transfer_sync( 10917 struct dc_context *ctx, 10918 unsigned int link_index, 10919 struct aux_payload *payload, 10920 enum aux_return_code_type *operation_result) 10921 { 10922 struct amdgpu_device *adev = ctx->driver_context; 10923 struct dmub_notification *p_notify = adev->dm.dmub_notify; 10924 int ret = -1; 10925 10926 mutex_lock(&adev->dm.dpia_aux_lock); 10927 if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) { 10928 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE; 10929 goto out; 10930 } 10931 10932 if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { 10933 DRM_ERROR("wait_for_completion_timeout timeout!"); 10934 *operation_result = AUX_RET_ERROR_TIMEOUT; 10935 goto out; 10936 } 10937 10938 if (p_notify->result != AUX_RET_SUCCESS) { 10939 /* 10940 * Transient states before tunneling is enabled could 10941 * lead to this error. We can ignore this for now. 10942 */ 10943 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) { 10944 DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n", 10945 payload->address, payload->length, 10946 p_notify->result); 10947 } 10948 *operation_result = AUX_RET_ERROR_INVALID_REPLY; 10949 goto out; 10950 } 10951 10952 10953 payload->reply[0] = adev->dm.dmub_notify->aux_reply.command; 10954 if (!payload->write && p_notify->aux_reply.length && 10955 (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) { 10956 10957 if (payload->length != p_notify->aux_reply.length) { 10958 DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n", 10959 p_notify->aux_reply.length, 10960 payload->address, payload->length); 10961 *operation_result = AUX_RET_ERROR_INVALID_REPLY; 10962 goto out; 10963 } 10964 10965 memcpy(payload->data, p_notify->aux_reply.data, 10966 p_notify->aux_reply.length); 10967 } 10968 10969 /* success */ 10970 ret = p_notify->aux_reply.length; 10971 *operation_result = p_notify->result; 10972 out: 10973 reinit_completion(&adev->dm.dmub_aux_transfer_done); 10974 mutex_unlock(&adev->dm.dpia_aux_lock); 10975 return ret; 10976 } 10977 10978 int amdgpu_dm_process_dmub_set_config_sync( 10979 struct dc_context *ctx, 10980 unsigned int link_index, 10981 struct set_config_cmd_payload *payload, 10982 enum set_config_status *operation_result) 10983 { 10984 struct amdgpu_device *adev = ctx->driver_context; 10985 bool is_cmd_complete; 10986 int ret; 10987 10988 mutex_lock(&adev->dm.dpia_aux_lock); 10989 is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc, 10990 link_index, payload, adev->dm.dmub_notify); 10991 10992 if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { 10993 ret = 0; 10994 *operation_result = adev->dm.dmub_notify->sc_status; 10995 } else { 10996 DRM_ERROR("wait_for_completion_timeout timeout!"); 10997 ret = -1; 10998 *operation_result = SET_CONFIG_UNKNOWN_ERROR; 10999 } 11000 11001 if (!is_cmd_complete) 11002 reinit_completion(&adev->dm.dmub_aux_transfer_done); 11003 mutex_unlock(&adev->dm.dpia_aux_lock); 11004 return ret; 11005 } 11006 11007 /* 11008 * Check whether seamless boot is supported. 11009 * 11010 * So far we only support seamless boot on CHIP_VANGOGH. 11011 * If everything goes well, we may consider expanding 11012 * seamless boot to other ASICs. 11013 */ 11014 bool check_seamless_boot_capability(struct amdgpu_device *adev) 11015 { 11016 switch (adev->ip_versions[DCE_HWIP][0]) { 11017 case IP_VERSION(3, 0, 1): 11018 if (!adev->mman.keep_stolen_vga_memory) 11019 return true; 11020 break; 11021 default: 11022 break; 11023 } 11024 11025 return false; 11026 } 11027 11028 bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) 11029 { 11030 return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type); 11031 } 11032 11033 bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) 11034 { 11035 return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type); 11036 } 11037