1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 #include <linux/slab.h> 26 27 #include <drm/amdgpu_drm.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_atombios.h" 31 #include "amdgpu_ih.h" 32 #include "amdgpu_uvd.h" 33 #include "amdgpu_vce.h" 34 #include "amdgpu_ucode.h" 35 #include "atom.h" 36 #include "amd_pcie.h" 37 38 #include "gmc/gmc_8_1_d.h" 39 #include "gmc/gmc_8_1_sh_mask.h" 40 41 #include "oss/oss_3_0_d.h" 42 #include "oss/oss_3_0_sh_mask.h" 43 44 #include "bif/bif_5_0_d.h" 45 #include "bif/bif_5_0_sh_mask.h" 46 47 #include "gca/gfx_8_0_d.h" 48 #include "gca/gfx_8_0_sh_mask.h" 49 50 #include "smu/smu_7_1_1_d.h" 51 #include "smu/smu_7_1_1_sh_mask.h" 52 53 #include "uvd/uvd_5_0_d.h" 54 #include "uvd/uvd_5_0_sh_mask.h" 55 56 #include "vce/vce_3_0_d.h" 57 #include "vce/vce_3_0_sh_mask.h" 58 59 #include "dce/dce_10_0_d.h" 60 #include "dce/dce_10_0_sh_mask.h" 61 62 #include "vid.h" 63 #include "vi.h" 64 #include "gmc_v8_0.h" 65 #include "gmc_v7_0.h" 66 #include "gfx_v8_0.h" 67 #include "sdma_v2_4.h" 68 #include "sdma_v3_0.h" 69 #include "dce_v10_0.h" 70 #include "dce_v11_0.h" 71 #include "iceland_ih.h" 72 #include "tonga_ih.h" 73 #include "cz_ih.h" 74 #include "uvd_v5_0.h" 75 #include "uvd_v6_0.h" 76 #include "vce_v3_0.h" 77 #if defined(CONFIG_DRM_AMD_ACP) 78 #include "amdgpu_acp.h" 79 #endif 80 #include "amdgpu_vkms.h" 81 #include "mxgpu_vi.h" 82 #include "amdgpu_dm.h" 83 84 #define ixPCIE_LC_L1_PM_SUBSTATE 0x100100C6 85 #define PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L 86 #define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L 87 #define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L 88 #define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L 89 #define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L 90 #define ixPCIE_L1_PM_SUB_CNTL 0x378 91 #define PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L 92 #define PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L 93 #define PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L 94 #define PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L 95 #define PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L 96 #define LINK_CAP 0x64 97 #define PCIE_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L 98 #define ixCPM_CONTROL 0x1400118 99 #define ixPCIE_LC_CNTL7 0x100100BC 100 #define PCIE_LC_CNTL7__LC_L1_SIDEBAND_CLKREQ_PDWN_EN_MASK 0x00000400L 101 #define PCIE_LC_CNTL__LC_L0S_INACTIVITY_DEFAULT 0x00000007 102 #define PCIE_LC_CNTL__LC_L1_INACTIVITY_DEFAULT 0x00000009 103 #define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK 0x01000000L 104 #define PCIE_L1_PM_SUB_CNTL 0x378 105 #define ASIC_IS_P22(asic_type, rid) ((asic_type >= CHIP_POLARIS10) && \ 106 (asic_type <= CHIP_POLARIS12) && \ 107 (rid >= 0x6E)) 108 /* Topaz */ 109 static const struct amdgpu_video_codecs topaz_video_codecs_encode = 110 { 111 .codec_count = 0, 112 .codec_array = NULL, 113 }; 114 115 /* Tonga, CZ, ST, Fiji */ 116 static const struct amdgpu_video_codec_info tonga_video_codecs_encode_array[] = 117 { 118 { 119 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 120 .max_width = 4096, 121 .max_height = 2304, 122 .max_pixels_per_frame = 4096 * 2304, 123 .max_level = 0, 124 }, 125 }; 126 127 static const struct amdgpu_video_codecs tonga_video_codecs_encode = 128 { 129 .codec_count = ARRAY_SIZE(tonga_video_codecs_encode_array), 130 .codec_array = tonga_video_codecs_encode_array, 131 }; 132 133 /* Polaris */ 134 static const struct amdgpu_video_codec_info polaris_video_codecs_encode_array[] = 135 { 136 { 137 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 138 .max_width = 4096, 139 .max_height = 2304, 140 .max_pixels_per_frame = 4096 * 2304, 141 .max_level = 0, 142 }, 143 { 144 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 145 .max_width = 4096, 146 .max_height = 2304, 147 .max_pixels_per_frame = 4096 * 2304, 148 .max_level = 0, 149 }, 150 }; 151 152 static const struct amdgpu_video_codecs polaris_video_codecs_encode = 153 { 154 .codec_count = ARRAY_SIZE(polaris_video_codecs_encode_array), 155 .codec_array = polaris_video_codecs_encode_array, 156 }; 157 158 /* Topaz */ 159 static const struct amdgpu_video_codecs topaz_video_codecs_decode = 160 { 161 .codec_count = 0, 162 .codec_array = NULL, 163 }; 164 165 /* Tonga */ 166 static const struct amdgpu_video_codec_info tonga_video_codecs_decode_array[] = 167 { 168 { 169 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 170 .max_width = 4096, 171 .max_height = 4096, 172 .max_pixels_per_frame = 4096 * 4096, 173 .max_level = 3, 174 }, 175 { 176 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 177 .max_width = 4096, 178 .max_height = 4096, 179 .max_pixels_per_frame = 4096 * 4096, 180 .max_level = 5, 181 }, 182 { 183 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 184 .max_width = 4096, 185 .max_height = 4096, 186 .max_pixels_per_frame = 4096 * 4096, 187 .max_level = 52, 188 }, 189 { 190 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 191 .max_width = 4096, 192 .max_height = 4096, 193 .max_pixels_per_frame = 4096 * 4096, 194 .max_level = 4, 195 }, 196 }; 197 198 static const struct amdgpu_video_codecs tonga_video_codecs_decode = 199 { 200 .codec_count = ARRAY_SIZE(tonga_video_codecs_decode_array), 201 .codec_array = tonga_video_codecs_decode_array, 202 }; 203 204 /* CZ, ST, Fiji, Polaris */ 205 static const struct amdgpu_video_codec_info cz_video_codecs_decode_array[] = 206 { 207 { 208 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 209 .max_width = 4096, 210 .max_height = 4096, 211 .max_pixels_per_frame = 4096 * 4096, 212 .max_level = 3, 213 }, 214 { 215 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 216 .max_width = 4096, 217 .max_height = 4096, 218 .max_pixels_per_frame = 4096 * 4096, 219 .max_level = 5, 220 }, 221 { 222 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 223 .max_width = 4096, 224 .max_height = 4096, 225 .max_pixels_per_frame = 4096 * 4096, 226 .max_level = 52, 227 }, 228 { 229 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 230 .max_width = 4096, 231 .max_height = 4096, 232 .max_pixels_per_frame = 4096 * 4096, 233 .max_level = 4, 234 }, 235 { 236 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 237 .max_width = 4096, 238 .max_height = 4096, 239 .max_pixels_per_frame = 4096 * 4096, 240 .max_level = 186, 241 }, 242 { 243 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 244 .max_width = 4096, 245 .max_height = 4096, 246 .max_pixels_per_frame = 4096 * 4096, 247 .max_level = 0, 248 }, 249 }; 250 251 static const struct amdgpu_video_codecs cz_video_codecs_decode = 252 { 253 .codec_count = ARRAY_SIZE(cz_video_codecs_decode_array), 254 .codec_array = cz_video_codecs_decode_array, 255 }; 256 257 static int vi_query_video_codecs(struct amdgpu_device *adev, bool encode, 258 const struct amdgpu_video_codecs **codecs) 259 { 260 switch (adev->asic_type) { 261 case CHIP_TOPAZ: 262 if (encode) 263 *codecs = &topaz_video_codecs_encode; 264 else 265 *codecs = &topaz_video_codecs_decode; 266 return 0; 267 case CHIP_TONGA: 268 if (encode) 269 *codecs = &tonga_video_codecs_encode; 270 else 271 *codecs = &tonga_video_codecs_decode; 272 return 0; 273 case CHIP_POLARIS10: 274 case CHIP_POLARIS11: 275 case CHIP_POLARIS12: 276 case CHIP_VEGAM: 277 if (encode) 278 *codecs = &polaris_video_codecs_encode; 279 else 280 *codecs = &cz_video_codecs_decode; 281 return 0; 282 case CHIP_FIJI: 283 case CHIP_CARRIZO: 284 case CHIP_STONEY: 285 if (encode) 286 *codecs = &tonga_video_codecs_encode; 287 else 288 *codecs = &cz_video_codecs_decode; 289 return 0; 290 default: 291 return -EINVAL; 292 } 293 } 294 295 /* 296 * Indirect registers accessor 297 */ 298 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg) 299 { 300 unsigned long flags; 301 u32 r; 302 303 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 304 WREG32_NO_KIQ(mmPCIE_INDEX, reg); 305 (void)RREG32_NO_KIQ(mmPCIE_INDEX); 306 r = RREG32_NO_KIQ(mmPCIE_DATA); 307 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 308 return r; 309 } 310 311 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 312 { 313 unsigned long flags; 314 315 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 316 WREG32_NO_KIQ(mmPCIE_INDEX, reg); 317 (void)RREG32_NO_KIQ(mmPCIE_INDEX); 318 WREG32_NO_KIQ(mmPCIE_DATA, v); 319 (void)RREG32_NO_KIQ(mmPCIE_DATA); 320 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 321 } 322 323 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg) 324 { 325 unsigned long flags; 326 u32 r; 327 328 spin_lock_irqsave(&adev->smc_idx_lock, flags); 329 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg)); 330 r = RREG32_NO_KIQ(mmSMC_IND_DATA_11); 331 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 332 return r; 333 } 334 335 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 336 { 337 unsigned long flags; 338 339 spin_lock_irqsave(&adev->smc_idx_lock, flags); 340 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg)); 341 WREG32_NO_KIQ(mmSMC_IND_DATA_11, (v)); 342 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 343 } 344 345 /* smu_8_0_d.h */ 346 #define mmMP0PUB_IND_INDEX 0x180 347 #define mmMP0PUB_IND_DATA 0x181 348 349 static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg) 350 { 351 unsigned long flags; 352 u32 r; 353 354 spin_lock_irqsave(&adev->smc_idx_lock, flags); 355 WREG32(mmMP0PUB_IND_INDEX, (reg)); 356 r = RREG32(mmMP0PUB_IND_DATA); 357 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 358 return r; 359 } 360 361 static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 362 { 363 unsigned long flags; 364 365 spin_lock_irqsave(&adev->smc_idx_lock, flags); 366 WREG32(mmMP0PUB_IND_INDEX, (reg)); 367 WREG32(mmMP0PUB_IND_DATA, (v)); 368 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 369 } 370 371 static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 372 { 373 unsigned long flags; 374 u32 r; 375 376 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 377 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 378 r = RREG32(mmUVD_CTX_DATA); 379 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 380 return r; 381 } 382 383 static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 384 { 385 unsigned long flags; 386 387 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 388 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 389 WREG32(mmUVD_CTX_DATA, (v)); 390 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 391 } 392 393 static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg) 394 { 395 unsigned long flags; 396 u32 r; 397 398 spin_lock_irqsave(&adev->didt_idx_lock, flags); 399 WREG32(mmDIDT_IND_INDEX, (reg)); 400 r = RREG32(mmDIDT_IND_DATA); 401 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 402 return r; 403 } 404 405 static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 406 { 407 unsigned long flags; 408 409 spin_lock_irqsave(&adev->didt_idx_lock, flags); 410 WREG32(mmDIDT_IND_INDEX, (reg)); 411 WREG32(mmDIDT_IND_DATA, (v)); 412 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 413 } 414 415 static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) 416 { 417 unsigned long flags; 418 u32 r; 419 420 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 421 WREG32(mmGC_CAC_IND_INDEX, (reg)); 422 r = RREG32(mmGC_CAC_IND_DATA); 423 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 424 return r; 425 } 426 427 static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 428 { 429 unsigned long flags; 430 431 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 432 WREG32(mmGC_CAC_IND_INDEX, (reg)); 433 WREG32(mmGC_CAC_IND_DATA, (v)); 434 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 435 } 436 437 438 static const u32 tonga_mgcg_cgcg_init[] = 439 { 440 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100, 441 mmPCIE_INDEX, 0xffffffff, 0x0140001c, 442 mmPCIE_DATA, 0x000f0000, 0x00000000, 443 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C, 444 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100, 445 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 446 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 447 }; 448 449 static const u32 fiji_mgcg_cgcg_init[] = 450 { 451 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100, 452 mmPCIE_INDEX, 0xffffffff, 0x0140001c, 453 mmPCIE_DATA, 0x000f0000, 0x00000000, 454 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C, 455 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100, 456 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 457 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 458 }; 459 460 static const u32 iceland_mgcg_cgcg_init[] = 461 { 462 mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2, 463 mmPCIE_DATA, 0x000f0000, 0x00000000, 464 mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0, 465 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100, 466 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 467 }; 468 469 static const u32 cz_mgcg_cgcg_init[] = 470 { 471 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100, 472 mmPCIE_INDEX, 0xffffffff, 0x0140001c, 473 mmPCIE_DATA, 0x000f0000, 0x00000000, 474 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 475 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 476 }; 477 478 static const u32 stoney_mgcg_cgcg_init[] = 479 { 480 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100, 481 mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104, 482 mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027, 483 }; 484 485 static void vi_init_golden_registers(struct amdgpu_device *adev) 486 { 487 /* Some of the registers might be dependent on GRBM_GFX_INDEX */ 488 mutex_lock(&adev->grbm_idx_mutex); 489 490 if (amdgpu_sriov_vf(adev)) { 491 xgpu_vi_init_golden_registers(adev); 492 mutex_unlock(&adev->grbm_idx_mutex); 493 return; 494 } 495 496 switch (adev->asic_type) { 497 case CHIP_TOPAZ: 498 amdgpu_device_program_register_sequence(adev, 499 iceland_mgcg_cgcg_init, 500 ARRAY_SIZE(iceland_mgcg_cgcg_init)); 501 break; 502 case CHIP_FIJI: 503 amdgpu_device_program_register_sequence(adev, 504 fiji_mgcg_cgcg_init, 505 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 506 break; 507 case CHIP_TONGA: 508 amdgpu_device_program_register_sequence(adev, 509 tonga_mgcg_cgcg_init, 510 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 511 break; 512 case CHIP_CARRIZO: 513 amdgpu_device_program_register_sequence(adev, 514 cz_mgcg_cgcg_init, 515 ARRAY_SIZE(cz_mgcg_cgcg_init)); 516 break; 517 case CHIP_STONEY: 518 amdgpu_device_program_register_sequence(adev, 519 stoney_mgcg_cgcg_init, 520 ARRAY_SIZE(stoney_mgcg_cgcg_init)); 521 break; 522 case CHIP_POLARIS10: 523 case CHIP_POLARIS11: 524 case CHIP_POLARIS12: 525 case CHIP_VEGAM: 526 default: 527 break; 528 } 529 mutex_unlock(&adev->grbm_idx_mutex); 530 } 531 532 /** 533 * vi_get_xclk - get the xclk 534 * 535 * @adev: amdgpu_device pointer 536 * 537 * Returns the reference clock used by the gfx engine 538 * (VI). 539 */ 540 static u32 vi_get_xclk(struct amdgpu_device *adev) 541 { 542 u32 reference_clock = adev->clock.spll.reference_freq; 543 u32 tmp; 544 545 if (adev->flags & AMD_IS_APU) { 546 switch (adev->asic_type) { 547 case CHIP_STONEY: 548 /* vbios says 48Mhz, but the actual freq is 100Mhz */ 549 return 10000; 550 default: 551 return reference_clock; 552 } 553 } 554 555 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2); 556 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK)) 557 return 1000; 558 559 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL); 560 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE)) 561 return reference_clock / 4; 562 563 return reference_clock; 564 } 565 566 /** 567 * vi_srbm_select - select specific register instances 568 * 569 * @adev: amdgpu_device pointer 570 * @me: selected ME (micro engine) 571 * @pipe: pipe 572 * @queue: queue 573 * @vmid: VMID 574 * 575 * Switches the currently active registers instances. Some 576 * registers are instanced per VMID, others are instanced per 577 * me/pipe/queue combination. 578 */ 579 void vi_srbm_select(struct amdgpu_device *adev, 580 u32 me, u32 pipe, u32 queue, u32 vmid) 581 { 582 u32 srbm_gfx_cntl = 0; 583 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe); 584 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me); 585 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid); 586 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue); 587 WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl); 588 } 589 590 static void vi_vga_set_state(struct amdgpu_device *adev, bool state) 591 { 592 /* todo */ 593 } 594 595 static bool vi_read_disabled_bios(struct amdgpu_device *adev) 596 { 597 u32 bus_cntl; 598 u32 d1vga_control = 0; 599 u32 d2vga_control = 0; 600 u32 vga_render_control = 0; 601 u32 rom_cntl; 602 bool r; 603 604 bus_cntl = RREG32(mmBUS_CNTL); 605 if (adev->mode_info.num_crtc) { 606 d1vga_control = RREG32(mmD1VGA_CONTROL); 607 d2vga_control = RREG32(mmD2VGA_CONTROL); 608 vga_render_control = RREG32(mmVGA_RENDER_CONTROL); 609 } 610 rom_cntl = RREG32_SMC(ixROM_CNTL); 611 612 /* enable the rom */ 613 WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK)); 614 if (adev->mode_info.num_crtc) { 615 /* Disable VGA mode */ 616 WREG32(mmD1VGA_CONTROL, 617 (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK | 618 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK))); 619 WREG32(mmD2VGA_CONTROL, 620 (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK | 621 D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK))); 622 WREG32(mmVGA_RENDER_CONTROL, 623 (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK)); 624 } 625 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); 626 627 r = amdgpu_read_bios(adev); 628 629 /* restore regs */ 630 WREG32(mmBUS_CNTL, bus_cntl); 631 if (adev->mode_info.num_crtc) { 632 WREG32(mmD1VGA_CONTROL, d1vga_control); 633 WREG32(mmD2VGA_CONTROL, d2vga_control); 634 WREG32(mmVGA_RENDER_CONTROL, vga_render_control); 635 } 636 WREG32_SMC(ixROM_CNTL, rom_cntl); 637 return r; 638 } 639 640 static bool vi_read_bios_from_rom(struct amdgpu_device *adev, 641 u8 *bios, u32 length_bytes) 642 { 643 u32 *dw_ptr; 644 unsigned long flags; 645 u32 i, length_dw; 646 647 if (bios == NULL) 648 return false; 649 if (length_bytes == 0) 650 return false; 651 /* APU vbios image is part of sbios image */ 652 if (adev->flags & AMD_IS_APU) 653 return false; 654 655 dw_ptr = (u32 *)bios; 656 length_dw = roundup2(length_bytes, 4) / 4; 657 /* take the smc lock since we are using the smc index */ 658 spin_lock_irqsave(&adev->smc_idx_lock, flags); 659 /* set rom index to 0 */ 660 WREG32(mmSMC_IND_INDEX_11, ixROM_INDEX); 661 WREG32(mmSMC_IND_DATA_11, 0); 662 /* set index to data for continous read */ 663 WREG32(mmSMC_IND_INDEX_11, ixROM_DATA); 664 for (i = 0; i < length_dw; i++) 665 dw_ptr[i] = RREG32(mmSMC_IND_DATA_11); 666 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 667 668 return true; 669 } 670 671 static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = { 672 {mmGRBM_STATUS}, 673 {mmGRBM_STATUS2}, 674 {mmGRBM_STATUS_SE0}, 675 {mmGRBM_STATUS_SE1}, 676 {mmGRBM_STATUS_SE2}, 677 {mmGRBM_STATUS_SE3}, 678 {mmSRBM_STATUS}, 679 {mmSRBM_STATUS2}, 680 {mmSRBM_STATUS3}, 681 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET}, 682 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET}, 683 {mmCP_STAT}, 684 {mmCP_STALLED_STAT1}, 685 {mmCP_STALLED_STAT2}, 686 {mmCP_STALLED_STAT3}, 687 {mmCP_CPF_BUSY_STAT}, 688 {mmCP_CPF_STALLED_STAT1}, 689 {mmCP_CPF_STATUS}, 690 {mmCP_CPC_BUSY_STAT}, 691 {mmCP_CPC_STALLED_STAT1}, 692 {mmCP_CPC_STATUS}, 693 {mmGB_ADDR_CONFIG}, 694 {mmMC_ARB_RAMCFG}, 695 {mmGB_TILE_MODE0}, 696 {mmGB_TILE_MODE1}, 697 {mmGB_TILE_MODE2}, 698 {mmGB_TILE_MODE3}, 699 {mmGB_TILE_MODE4}, 700 {mmGB_TILE_MODE5}, 701 {mmGB_TILE_MODE6}, 702 {mmGB_TILE_MODE7}, 703 {mmGB_TILE_MODE8}, 704 {mmGB_TILE_MODE9}, 705 {mmGB_TILE_MODE10}, 706 {mmGB_TILE_MODE11}, 707 {mmGB_TILE_MODE12}, 708 {mmGB_TILE_MODE13}, 709 {mmGB_TILE_MODE14}, 710 {mmGB_TILE_MODE15}, 711 {mmGB_TILE_MODE16}, 712 {mmGB_TILE_MODE17}, 713 {mmGB_TILE_MODE18}, 714 {mmGB_TILE_MODE19}, 715 {mmGB_TILE_MODE20}, 716 {mmGB_TILE_MODE21}, 717 {mmGB_TILE_MODE22}, 718 {mmGB_TILE_MODE23}, 719 {mmGB_TILE_MODE24}, 720 {mmGB_TILE_MODE25}, 721 {mmGB_TILE_MODE26}, 722 {mmGB_TILE_MODE27}, 723 {mmGB_TILE_MODE28}, 724 {mmGB_TILE_MODE29}, 725 {mmGB_TILE_MODE30}, 726 {mmGB_TILE_MODE31}, 727 {mmGB_MACROTILE_MODE0}, 728 {mmGB_MACROTILE_MODE1}, 729 {mmGB_MACROTILE_MODE2}, 730 {mmGB_MACROTILE_MODE3}, 731 {mmGB_MACROTILE_MODE4}, 732 {mmGB_MACROTILE_MODE5}, 733 {mmGB_MACROTILE_MODE6}, 734 {mmGB_MACROTILE_MODE7}, 735 {mmGB_MACROTILE_MODE8}, 736 {mmGB_MACROTILE_MODE9}, 737 {mmGB_MACROTILE_MODE10}, 738 {mmGB_MACROTILE_MODE11}, 739 {mmGB_MACROTILE_MODE12}, 740 {mmGB_MACROTILE_MODE13}, 741 {mmGB_MACROTILE_MODE14}, 742 {mmGB_MACROTILE_MODE15}, 743 {mmCC_RB_BACKEND_DISABLE, true}, 744 {mmGC_USER_RB_BACKEND_DISABLE, true}, 745 {mmGB_BACKEND_MAP, false}, 746 {mmPA_SC_RASTER_CONFIG, true}, 747 {mmPA_SC_RASTER_CONFIG_1, true}, 748 }; 749 750 static uint32_t vi_get_register_value(struct amdgpu_device *adev, 751 bool indexed, u32 se_num, 752 u32 sh_num, u32 reg_offset) 753 { 754 if (indexed) { 755 uint32_t val; 756 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num; 757 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; 758 759 switch (reg_offset) { 760 case mmCC_RB_BACKEND_DISABLE: 761 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable; 762 case mmGC_USER_RB_BACKEND_DISABLE: 763 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable; 764 case mmPA_SC_RASTER_CONFIG: 765 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config; 766 case mmPA_SC_RASTER_CONFIG_1: 767 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1; 768 } 769 770 mutex_lock(&adev->grbm_idx_mutex); 771 if (se_num != 0xffffffff || sh_num != 0xffffffff) 772 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 773 774 val = RREG32(reg_offset); 775 776 if (se_num != 0xffffffff || sh_num != 0xffffffff) 777 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 778 mutex_unlock(&adev->grbm_idx_mutex); 779 return val; 780 } else { 781 unsigned idx; 782 783 switch (reg_offset) { 784 case mmGB_ADDR_CONFIG: 785 return adev->gfx.config.gb_addr_config; 786 case mmMC_ARB_RAMCFG: 787 return adev->gfx.config.mc_arb_ramcfg; 788 case mmGB_TILE_MODE0: 789 case mmGB_TILE_MODE1: 790 case mmGB_TILE_MODE2: 791 case mmGB_TILE_MODE3: 792 case mmGB_TILE_MODE4: 793 case mmGB_TILE_MODE5: 794 case mmGB_TILE_MODE6: 795 case mmGB_TILE_MODE7: 796 case mmGB_TILE_MODE8: 797 case mmGB_TILE_MODE9: 798 case mmGB_TILE_MODE10: 799 case mmGB_TILE_MODE11: 800 case mmGB_TILE_MODE12: 801 case mmGB_TILE_MODE13: 802 case mmGB_TILE_MODE14: 803 case mmGB_TILE_MODE15: 804 case mmGB_TILE_MODE16: 805 case mmGB_TILE_MODE17: 806 case mmGB_TILE_MODE18: 807 case mmGB_TILE_MODE19: 808 case mmGB_TILE_MODE20: 809 case mmGB_TILE_MODE21: 810 case mmGB_TILE_MODE22: 811 case mmGB_TILE_MODE23: 812 case mmGB_TILE_MODE24: 813 case mmGB_TILE_MODE25: 814 case mmGB_TILE_MODE26: 815 case mmGB_TILE_MODE27: 816 case mmGB_TILE_MODE28: 817 case mmGB_TILE_MODE29: 818 case mmGB_TILE_MODE30: 819 case mmGB_TILE_MODE31: 820 idx = (reg_offset - mmGB_TILE_MODE0); 821 return adev->gfx.config.tile_mode_array[idx]; 822 case mmGB_MACROTILE_MODE0: 823 case mmGB_MACROTILE_MODE1: 824 case mmGB_MACROTILE_MODE2: 825 case mmGB_MACROTILE_MODE3: 826 case mmGB_MACROTILE_MODE4: 827 case mmGB_MACROTILE_MODE5: 828 case mmGB_MACROTILE_MODE6: 829 case mmGB_MACROTILE_MODE7: 830 case mmGB_MACROTILE_MODE8: 831 case mmGB_MACROTILE_MODE9: 832 case mmGB_MACROTILE_MODE10: 833 case mmGB_MACROTILE_MODE11: 834 case mmGB_MACROTILE_MODE12: 835 case mmGB_MACROTILE_MODE13: 836 case mmGB_MACROTILE_MODE14: 837 case mmGB_MACROTILE_MODE15: 838 idx = (reg_offset - mmGB_MACROTILE_MODE0); 839 return adev->gfx.config.macrotile_mode_array[idx]; 840 default: 841 return RREG32(reg_offset); 842 } 843 } 844 } 845 846 static int vi_read_register(struct amdgpu_device *adev, u32 se_num, 847 u32 sh_num, u32 reg_offset, u32 *value) 848 { 849 uint32_t i; 850 851 *value = 0; 852 for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) { 853 bool indexed = vi_allowed_read_registers[i].grbm_indexed; 854 855 if (reg_offset != vi_allowed_read_registers[i].reg_offset) 856 continue; 857 858 *value = vi_get_register_value(adev, indexed, se_num, sh_num, 859 reg_offset); 860 return 0; 861 } 862 return -EINVAL; 863 } 864 865 /** 866 * vi_asic_pci_config_reset - soft reset GPU 867 * 868 * @adev: amdgpu_device pointer 869 * 870 * Use PCI Config method to reset the GPU. 871 * 872 * Returns 0 for success. 873 */ 874 static int vi_asic_pci_config_reset(struct amdgpu_device *adev) 875 { 876 u32 i; 877 int r = -EINVAL; 878 879 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 880 881 /* disable BM */ 882 pci_clear_master(adev->pdev); 883 /* reset */ 884 amdgpu_device_pci_config_reset(adev); 885 886 udelay(100); 887 888 /* wait for asic to come out of reset */ 889 for (i = 0; i < adev->usec_timeout; i++) { 890 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) { 891 /* enable BM */ 892 pci_set_master(adev->pdev); 893 adev->has_hw_reset = true; 894 r = 0; 895 break; 896 } 897 udelay(1); 898 } 899 900 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 901 902 return r; 903 } 904 905 static bool vi_asic_supports_baco(struct amdgpu_device *adev) 906 { 907 switch (adev->asic_type) { 908 case CHIP_FIJI: 909 case CHIP_TONGA: 910 case CHIP_POLARIS10: 911 case CHIP_POLARIS11: 912 case CHIP_POLARIS12: 913 case CHIP_TOPAZ: 914 return amdgpu_dpm_is_baco_supported(adev); 915 default: 916 return false; 917 } 918 } 919 920 static enum amd_reset_method 921 vi_asic_reset_method(struct amdgpu_device *adev) 922 { 923 bool baco_reset; 924 925 if (amdgpu_reset_method == AMD_RESET_METHOD_LEGACY || 926 amdgpu_reset_method == AMD_RESET_METHOD_BACO) 927 return amdgpu_reset_method; 928 929 if (amdgpu_reset_method != -1) 930 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 931 amdgpu_reset_method); 932 933 switch (adev->asic_type) { 934 case CHIP_FIJI: 935 case CHIP_TONGA: 936 case CHIP_POLARIS10: 937 case CHIP_POLARIS11: 938 case CHIP_POLARIS12: 939 case CHIP_TOPAZ: 940 baco_reset = amdgpu_dpm_is_baco_supported(adev); 941 break; 942 default: 943 baco_reset = false; 944 break; 945 } 946 947 if (baco_reset) 948 return AMD_RESET_METHOD_BACO; 949 else 950 return AMD_RESET_METHOD_LEGACY; 951 } 952 953 /** 954 * vi_asic_reset - soft reset GPU 955 * 956 * @adev: amdgpu_device pointer 957 * 958 * Look up which blocks are hung and attempt 959 * to reset them. 960 * Returns 0 for success. 961 */ 962 static int vi_asic_reset(struct amdgpu_device *adev) 963 { 964 int r; 965 966 /* APUs don't have full asic reset */ 967 if (adev->flags & AMD_IS_APU) 968 return 0; 969 970 if (vi_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { 971 dev_info(adev->dev, "BACO reset\n"); 972 r = amdgpu_dpm_baco_reset(adev); 973 } else { 974 dev_info(adev->dev, "PCI CONFIG reset\n"); 975 r = vi_asic_pci_config_reset(adev); 976 } 977 978 return r; 979 } 980 981 static u32 vi_get_config_memsize(struct amdgpu_device *adev) 982 { 983 return RREG32(mmCONFIG_MEMSIZE); 984 } 985 986 static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 987 u32 cntl_reg, u32 status_reg) 988 { 989 int r, i; 990 struct atom_clock_dividers dividers; 991 uint32_t tmp; 992 993 r = amdgpu_atombios_get_clock_dividers(adev, 994 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 995 clock, false, ÷rs); 996 if (r) 997 return r; 998 999 tmp = RREG32_SMC(cntl_reg); 1000 1001 if (adev->flags & AMD_IS_APU) 1002 tmp &= ~CG_DCLK_CNTL__DCLK_DIVIDER_MASK; 1003 else 1004 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK | 1005 CG_DCLK_CNTL__DCLK_DIVIDER_MASK); 1006 tmp |= dividers.post_divider; 1007 WREG32_SMC(cntl_reg, tmp); 1008 1009 for (i = 0; i < 100; i++) { 1010 tmp = RREG32_SMC(status_reg); 1011 if (adev->flags & AMD_IS_APU) { 1012 if (tmp & 0x10000) 1013 break; 1014 } else { 1015 if (tmp & CG_DCLK_STATUS__DCLK_STATUS_MASK) 1016 break; 1017 } 1018 mdelay(10); 1019 } 1020 if (i == 100) 1021 return -ETIMEDOUT; 1022 return 0; 1023 } 1024 1025 #define ixGNB_CLK1_DFS_CNTL 0xD82200F0 1026 #define ixGNB_CLK1_STATUS 0xD822010C 1027 #define ixGNB_CLK2_DFS_CNTL 0xD8220110 1028 #define ixGNB_CLK2_STATUS 0xD822012C 1029 #define ixGNB_CLK3_DFS_CNTL 0xD8220130 1030 #define ixGNB_CLK3_STATUS 0xD822014C 1031 1032 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 1033 { 1034 int r; 1035 1036 if (adev->flags & AMD_IS_APU) { 1037 r = vi_set_uvd_clock(adev, vclk, ixGNB_CLK2_DFS_CNTL, ixGNB_CLK2_STATUS); 1038 if (r) 1039 return r; 1040 1041 r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS); 1042 if (r) 1043 return r; 1044 } else { 1045 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 1046 if (r) 1047 return r; 1048 1049 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 1050 if (r) 1051 return r; 1052 } 1053 1054 return 0; 1055 } 1056 1057 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 1058 { 1059 int r, i; 1060 struct atom_clock_dividers dividers; 1061 u32 tmp; 1062 u32 reg_ctrl; 1063 u32 reg_status; 1064 u32 status_mask; 1065 u32 reg_mask; 1066 1067 if (adev->flags & AMD_IS_APU) { 1068 reg_ctrl = ixGNB_CLK3_DFS_CNTL; 1069 reg_status = ixGNB_CLK3_STATUS; 1070 status_mask = 0x00010000; 1071 reg_mask = CG_ECLK_CNTL__ECLK_DIVIDER_MASK; 1072 } else { 1073 reg_ctrl = ixCG_ECLK_CNTL; 1074 reg_status = ixCG_ECLK_STATUS; 1075 status_mask = CG_ECLK_STATUS__ECLK_STATUS_MASK; 1076 reg_mask = CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK | CG_ECLK_CNTL__ECLK_DIVIDER_MASK; 1077 } 1078 1079 r = amdgpu_atombios_get_clock_dividers(adev, 1080 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 1081 ecclk, false, ÷rs); 1082 if (r) 1083 return r; 1084 1085 for (i = 0; i < 100; i++) { 1086 if (RREG32_SMC(reg_status) & status_mask) 1087 break; 1088 mdelay(10); 1089 } 1090 1091 if (i == 100) 1092 return -ETIMEDOUT; 1093 1094 tmp = RREG32_SMC(reg_ctrl); 1095 tmp &= ~reg_mask; 1096 tmp |= dividers.post_divider; 1097 WREG32_SMC(reg_ctrl, tmp); 1098 1099 for (i = 0; i < 100; i++) { 1100 if (RREG32_SMC(reg_status) & status_mask) 1101 break; 1102 mdelay(10); 1103 } 1104 1105 if (i == 100) 1106 return -ETIMEDOUT; 1107 1108 return 0; 1109 } 1110 1111 static void vi_pcie_gen3_enable(struct amdgpu_device *adev) 1112 { 1113 if (pci_is_root_bus(adev->pdev->bus)) 1114 return; 1115 1116 if (amdgpu_pcie_gen2 == 0) 1117 return; 1118 1119 if (adev->flags & AMD_IS_APU) 1120 return; 1121 1122 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 1123 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 1124 return; 1125 1126 /* todo */ 1127 } 1128 1129 static void vi_enable_aspm(struct amdgpu_device *adev) 1130 { 1131 u32 data, orig; 1132 1133 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); 1134 data |= PCIE_LC_CNTL__LC_L0S_INACTIVITY_DEFAULT << 1135 PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT; 1136 data |= PCIE_LC_CNTL__LC_L1_INACTIVITY_DEFAULT << 1137 PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; 1138 data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 1139 data |= PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK; 1140 if (orig != data) 1141 WREG32_PCIE(ixPCIE_LC_CNTL, data); 1142 } 1143 1144 static void vi_program_aspm(struct amdgpu_device *adev) 1145 { 1146 u32 data, data1, orig; 1147 bool bL1SS = false; 1148 bool bClkReqSupport = true; 1149 1150 if (!amdgpu_device_should_use_aspm(adev) || !amdgpu_device_pcie_dynamic_switching_supported()) 1151 return; 1152 1153 if (adev->flags & AMD_IS_APU || 1154 adev->asic_type < CHIP_POLARIS10) 1155 return; 1156 1157 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); 1158 data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK; 1159 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; 1160 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 1161 if (orig != data) 1162 WREG32_PCIE(ixPCIE_LC_CNTL, data); 1163 1164 orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); 1165 data &= ~PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK; 1166 data |= 0x0024 << PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT; 1167 data |= PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK; 1168 if (orig != data) 1169 WREG32_PCIE(ixPCIE_LC_N_FTS_CNTL, data); 1170 1171 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3); 1172 data |= PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK; 1173 if (orig != data) 1174 WREG32_PCIE(ixPCIE_LC_CNTL3, data); 1175 1176 orig = data = RREG32_PCIE(ixPCIE_P_CNTL); 1177 data |= PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK; 1178 if (orig != data) 1179 WREG32_PCIE(ixPCIE_P_CNTL, data); 1180 1181 data = RREG32_PCIE(ixPCIE_LC_L1_PM_SUBSTATE); 1182 pci_read_config_dword(adev->pdev, PCIE_L1_PM_SUB_CNTL, &data1); 1183 if (data & PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK && 1184 (data & (PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK | 1185 PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK | 1186 PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK | 1187 PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK))) { 1188 bL1SS = true; 1189 } else if (data1 & (PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK | 1190 PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK | 1191 PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK | 1192 PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK)) { 1193 bL1SS = true; 1194 } 1195 1196 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL6); 1197 data |= PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK; 1198 if (orig != data) 1199 WREG32_PCIE(ixPCIE_LC_CNTL6, data); 1200 1201 orig = data = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL); 1202 data |= PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK; 1203 if (orig != data) 1204 WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, data); 1205 1206 pci_read_config_dword(adev->pdev, LINK_CAP, &data); 1207 if (!(data & PCIE_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK)) 1208 bClkReqSupport = false; 1209 1210 if (bClkReqSupport) { 1211 orig = data = RREG32_SMC(ixTHM_CLK_CNTL); 1212 data &= ~(THM_CLK_CNTL__CMON_CLK_SEL_MASK | THM_CLK_CNTL__TMON_CLK_SEL_MASK); 1213 data |= (1 << THM_CLK_CNTL__CMON_CLK_SEL__SHIFT) | 1214 (1 << THM_CLK_CNTL__TMON_CLK_SEL__SHIFT); 1215 if (orig != data) 1216 WREG32_SMC(ixTHM_CLK_CNTL, data); 1217 1218 orig = data = RREG32_SMC(ixMISC_CLK_CTRL); 1219 data &= ~(MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK | 1220 MISC_CLK_CTRL__ZCLK_SEL_MASK | MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK); 1221 data |= (1 << MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT) | 1222 (1 << MISC_CLK_CTRL__ZCLK_SEL__SHIFT); 1223 data |= (0x20 << MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT); 1224 if (orig != data) 1225 WREG32_SMC(ixMISC_CLK_CTRL, data); 1226 1227 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL); 1228 data |= CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK; 1229 if (orig != data) 1230 WREG32_SMC(ixCG_CLKPIN_CNTL, data); 1231 1232 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL_2); 1233 data |= CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK; 1234 if (orig != data) 1235 WREG32_SMC(ixCG_CLKPIN_CNTL, data); 1236 1237 orig = data = RREG32_SMC(ixMPLL_BYPASSCLK_SEL); 1238 data &= ~MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK; 1239 data |= (4 << MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT); 1240 if (orig != data) 1241 WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data); 1242 1243 orig = data = RREG32_PCIE(ixCPM_CONTROL); 1244 data |= (CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK | 1245 CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK); 1246 if (orig != data) 1247 WREG32_PCIE(ixCPM_CONTROL, data); 1248 1249 orig = data = RREG32_PCIE(ixPCIE_CONFIG_CNTL); 1250 data &= ~PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK; 1251 data |= (0xE << PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT); 1252 if (orig != data) 1253 WREG32_PCIE(ixPCIE_CONFIG_CNTL, data); 1254 1255 orig = data = RREG32(mmBIF_CLK_CTRL); 1256 data |= BIF_CLK_CTRL__BIF_XSTCLK_READY_MASK; 1257 if (orig != data) 1258 WREG32(mmBIF_CLK_CTRL, data); 1259 1260 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL7); 1261 data |= PCIE_LC_CNTL7__LC_L1_SIDEBAND_CLKREQ_PDWN_EN_MASK; 1262 if (orig != data) 1263 WREG32_PCIE(ixPCIE_LC_CNTL7, data); 1264 1265 orig = data = RREG32_PCIE(ixPCIE_HW_DEBUG); 1266 data |= PCIE_HW_DEBUG__HW_01_DEBUG_MASK; 1267 if (orig != data) 1268 WREG32_PCIE(ixPCIE_HW_DEBUG, data); 1269 1270 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL2); 1271 data |= PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK; 1272 data |= PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK; 1273 if (bL1SS) 1274 data &= ~PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK; 1275 if (orig != data) 1276 WREG32_PCIE(ixPCIE_LC_CNTL2, data); 1277 1278 } 1279 1280 vi_enable_aspm(adev); 1281 1282 data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); 1283 data1 = RREG32_PCIE(ixPCIE_LC_STATUS1); 1284 if (((data & PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) == PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) && 1285 data1 & PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK && 1286 data1 & PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK) { 1287 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); 1288 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; 1289 if (orig != data) 1290 WREG32_PCIE(ixPCIE_LC_CNTL, data); 1291 } 1292 1293 if ((adev->asic_type == CHIP_POLARIS12 && 1294 !(ASICID_IS_P23(adev->pdev->device, adev->pdev->revision))) || 1295 ASIC_IS_P22(adev->asic_type, adev->external_rev_id)) { 1296 orig = data = RREG32_PCIE(ixPCIE_LC_TRAINING_CNTL); 1297 data &= ~PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK; 1298 if (orig != data) 1299 WREG32_PCIE(ixPCIE_LC_TRAINING_CNTL, data); 1300 } 1301 } 1302 1303 static void vi_enable_doorbell_aperture(struct amdgpu_device *adev, 1304 bool enable) 1305 { 1306 u32 tmp; 1307 1308 /* not necessary on CZ */ 1309 if (adev->flags & AMD_IS_APU) 1310 return; 1311 1312 tmp = RREG32(mmBIF_DOORBELL_APER_EN); 1313 if (enable) 1314 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1); 1315 else 1316 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0); 1317 1318 WREG32(mmBIF_DOORBELL_APER_EN, tmp); 1319 } 1320 1321 #define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044 1322 #define ATI_REV_ID_FUSE_MACRO__SHIFT 9 1323 #define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00 1324 1325 static uint32_t vi_get_rev_id(struct amdgpu_device *adev) 1326 { 1327 if (adev->flags & AMD_IS_APU) 1328 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK) 1329 >> ATI_REV_ID_FUSE_MACRO__SHIFT; 1330 else 1331 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK) 1332 >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT; 1333 } 1334 1335 static void vi_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 1336 { 1337 if (!ring || !ring->funcs->emit_wreg) { 1338 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); 1339 RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL); 1340 } else { 1341 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); 1342 } 1343 } 1344 1345 static void vi_invalidate_hdp(struct amdgpu_device *adev, 1346 struct amdgpu_ring *ring) 1347 { 1348 if (!ring || !ring->funcs->emit_wreg) { 1349 WREG32(mmHDP_DEBUG0, 1); 1350 RREG32(mmHDP_DEBUG0); 1351 } else { 1352 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1); 1353 } 1354 } 1355 1356 static bool vi_need_full_reset(struct amdgpu_device *adev) 1357 { 1358 switch (adev->asic_type) { 1359 case CHIP_CARRIZO: 1360 case CHIP_STONEY: 1361 /* CZ has hang issues with full reset at the moment */ 1362 return false; 1363 case CHIP_FIJI: 1364 case CHIP_TONGA: 1365 /* XXX: soft reset should work on fiji and tonga */ 1366 return true; 1367 case CHIP_POLARIS10: 1368 case CHIP_POLARIS11: 1369 case CHIP_POLARIS12: 1370 case CHIP_TOPAZ: 1371 default: 1372 /* change this when we support soft reset */ 1373 return true; 1374 } 1375 } 1376 1377 static void vi_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 1378 uint64_t *count1) 1379 { 1380 uint32_t perfctr = 0; 1381 uint64_t cnt0_of, cnt1_of; 1382 int tmp; 1383 1384 /* This reports 0 on APUs, so return to avoid writing/reading registers 1385 * that may or may not be different from their GPU counterparts 1386 */ 1387 if (adev->flags & AMD_IS_APU) 1388 return; 1389 1390 /* Set the 2 events that we wish to watch, defined above */ 1391 /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */ 1392 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); 1393 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); 1394 1395 /* Write to enable desired perf counters */ 1396 WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr); 1397 /* Zero out and enable the perf counters 1398 * Write 0x5: 1399 * Bit 0 = Start all counters(1) 1400 * Bit 2 = Global counter reset enable(1) 1401 */ 1402 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005); 1403 1404 drm_msleep(1000); 1405 1406 /* Load the shadow and disable the perf counters 1407 * Write 0x2: 1408 * Bit 0 = Stop counters(0) 1409 * Bit 1 = Load the shadow counters(1) 1410 */ 1411 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002); 1412 1413 /* Read register values to get any >32bit overflow */ 1414 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK); 1415 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); 1416 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); 1417 1418 /* Get the values and add the overflow */ 1419 *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); 1420 *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); 1421 } 1422 1423 static uint64_t vi_get_pcie_replay_count(struct amdgpu_device *adev) 1424 { 1425 uint64_t nak_r, nak_g; 1426 1427 /* Get the number of NAKs received and generated */ 1428 nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK); 1429 nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED); 1430 1431 /* Add the total number of NAKs, i.e the number of replays */ 1432 return (nak_r + nak_g); 1433 } 1434 1435 static bool vi_need_reset_on_init(struct amdgpu_device *adev) 1436 { 1437 u32 clock_cntl, pc; 1438 1439 if (adev->flags & AMD_IS_APU) 1440 return false; 1441 1442 /* check if the SMC is already running */ 1443 clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); 1444 pc = RREG32_SMC(ixSMC_PC_C); 1445 if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) && 1446 (0x20100 <= pc)) 1447 return true; 1448 1449 return false; 1450 } 1451 1452 static void vi_pre_asic_init(struct amdgpu_device *adev) 1453 { 1454 } 1455 1456 static const struct amdgpu_asic_funcs vi_asic_funcs = 1457 { 1458 .read_disabled_bios = &vi_read_disabled_bios, 1459 .read_bios_from_rom = &vi_read_bios_from_rom, 1460 .read_register = &vi_read_register, 1461 .reset = &vi_asic_reset, 1462 .reset_method = &vi_asic_reset_method, 1463 .set_vga_state = &vi_vga_set_state, 1464 .get_xclk = &vi_get_xclk, 1465 .set_uvd_clocks = &vi_set_uvd_clocks, 1466 .set_vce_clocks = &vi_set_vce_clocks, 1467 .get_config_memsize = &vi_get_config_memsize, 1468 .flush_hdp = &vi_flush_hdp, 1469 .invalidate_hdp = &vi_invalidate_hdp, 1470 .need_full_reset = &vi_need_full_reset, 1471 .init_doorbell_index = &legacy_doorbell_index_init, 1472 .get_pcie_usage = &vi_get_pcie_usage, 1473 .need_reset_on_init = &vi_need_reset_on_init, 1474 .get_pcie_replay_count = &vi_get_pcie_replay_count, 1475 .supports_baco = &vi_asic_supports_baco, 1476 .pre_asic_init = &vi_pre_asic_init, 1477 .query_video_codecs = &vi_query_video_codecs, 1478 }; 1479 1480 #define CZ_REV_BRISTOL(rev) \ 1481 ((rev >= 0xC8 && rev <= 0xCE) || (rev >= 0xE1 && rev <= 0xE6)) 1482 1483 static int vi_common_early_init(void *handle) 1484 { 1485 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1486 1487 if (adev->flags & AMD_IS_APU) { 1488 adev->smc_rreg = &cz_smc_rreg; 1489 adev->smc_wreg = &cz_smc_wreg; 1490 } else { 1491 adev->smc_rreg = &vi_smc_rreg; 1492 adev->smc_wreg = &vi_smc_wreg; 1493 } 1494 adev->pcie_rreg = &vi_pcie_rreg; 1495 adev->pcie_wreg = &vi_pcie_wreg; 1496 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg; 1497 adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg; 1498 adev->didt_rreg = &vi_didt_rreg; 1499 adev->didt_wreg = &vi_didt_wreg; 1500 adev->gc_cac_rreg = &vi_gc_cac_rreg; 1501 adev->gc_cac_wreg = &vi_gc_cac_wreg; 1502 1503 adev->asic_funcs = &vi_asic_funcs; 1504 1505 adev->rev_id = vi_get_rev_id(adev); 1506 adev->external_rev_id = 0xFF; 1507 switch (adev->asic_type) { 1508 case CHIP_TOPAZ: 1509 adev->cg_flags = 0; 1510 adev->pg_flags = 0; 1511 adev->external_rev_id = 0x1; 1512 break; 1513 case CHIP_FIJI: 1514 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1515 AMD_CG_SUPPORT_GFX_MGLS | 1516 AMD_CG_SUPPORT_GFX_RLC_LS | 1517 AMD_CG_SUPPORT_GFX_CP_LS | 1518 AMD_CG_SUPPORT_GFX_CGTS | 1519 AMD_CG_SUPPORT_GFX_CGTS_LS | 1520 AMD_CG_SUPPORT_GFX_CGCG | 1521 AMD_CG_SUPPORT_GFX_CGLS | 1522 AMD_CG_SUPPORT_SDMA_MGCG | 1523 AMD_CG_SUPPORT_SDMA_LS | 1524 AMD_CG_SUPPORT_BIF_LS | 1525 AMD_CG_SUPPORT_HDP_MGCG | 1526 AMD_CG_SUPPORT_HDP_LS | 1527 AMD_CG_SUPPORT_ROM_MGCG | 1528 AMD_CG_SUPPORT_MC_MGCG | 1529 AMD_CG_SUPPORT_MC_LS | 1530 AMD_CG_SUPPORT_UVD_MGCG; 1531 adev->pg_flags = 0; 1532 adev->external_rev_id = adev->rev_id + 0x3c; 1533 break; 1534 case CHIP_TONGA: 1535 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1536 AMD_CG_SUPPORT_GFX_CGCG | 1537 AMD_CG_SUPPORT_GFX_CGLS | 1538 AMD_CG_SUPPORT_SDMA_MGCG | 1539 AMD_CG_SUPPORT_SDMA_LS | 1540 AMD_CG_SUPPORT_BIF_LS | 1541 AMD_CG_SUPPORT_HDP_MGCG | 1542 AMD_CG_SUPPORT_HDP_LS | 1543 AMD_CG_SUPPORT_ROM_MGCG | 1544 AMD_CG_SUPPORT_MC_MGCG | 1545 AMD_CG_SUPPORT_MC_LS | 1546 AMD_CG_SUPPORT_DRM_LS | 1547 AMD_CG_SUPPORT_UVD_MGCG; 1548 adev->pg_flags = 0; 1549 adev->external_rev_id = adev->rev_id + 0x14; 1550 break; 1551 case CHIP_POLARIS11: 1552 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1553 AMD_CG_SUPPORT_GFX_RLC_LS | 1554 AMD_CG_SUPPORT_GFX_CP_LS | 1555 AMD_CG_SUPPORT_GFX_CGCG | 1556 AMD_CG_SUPPORT_GFX_CGLS | 1557 AMD_CG_SUPPORT_GFX_3D_CGCG | 1558 AMD_CG_SUPPORT_GFX_3D_CGLS | 1559 AMD_CG_SUPPORT_SDMA_MGCG | 1560 AMD_CG_SUPPORT_SDMA_LS | 1561 AMD_CG_SUPPORT_BIF_MGCG | 1562 AMD_CG_SUPPORT_BIF_LS | 1563 AMD_CG_SUPPORT_HDP_MGCG | 1564 AMD_CG_SUPPORT_HDP_LS | 1565 AMD_CG_SUPPORT_ROM_MGCG | 1566 AMD_CG_SUPPORT_MC_MGCG | 1567 AMD_CG_SUPPORT_MC_LS | 1568 AMD_CG_SUPPORT_DRM_LS | 1569 AMD_CG_SUPPORT_UVD_MGCG | 1570 AMD_CG_SUPPORT_VCE_MGCG; 1571 adev->pg_flags = 0; 1572 adev->external_rev_id = adev->rev_id + 0x5A; 1573 break; 1574 case CHIP_POLARIS10: 1575 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1576 AMD_CG_SUPPORT_GFX_RLC_LS | 1577 AMD_CG_SUPPORT_GFX_CP_LS | 1578 AMD_CG_SUPPORT_GFX_CGCG | 1579 AMD_CG_SUPPORT_GFX_CGLS | 1580 AMD_CG_SUPPORT_GFX_3D_CGCG | 1581 AMD_CG_SUPPORT_GFX_3D_CGLS | 1582 AMD_CG_SUPPORT_SDMA_MGCG | 1583 AMD_CG_SUPPORT_SDMA_LS | 1584 AMD_CG_SUPPORT_BIF_MGCG | 1585 AMD_CG_SUPPORT_BIF_LS | 1586 AMD_CG_SUPPORT_HDP_MGCG | 1587 AMD_CG_SUPPORT_HDP_LS | 1588 AMD_CG_SUPPORT_ROM_MGCG | 1589 AMD_CG_SUPPORT_MC_MGCG | 1590 AMD_CG_SUPPORT_MC_LS | 1591 AMD_CG_SUPPORT_DRM_LS | 1592 AMD_CG_SUPPORT_UVD_MGCG | 1593 AMD_CG_SUPPORT_VCE_MGCG; 1594 adev->pg_flags = 0; 1595 adev->external_rev_id = adev->rev_id + 0x50; 1596 break; 1597 case CHIP_POLARIS12: 1598 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1599 AMD_CG_SUPPORT_GFX_RLC_LS | 1600 AMD_CG_SUPPORT_GFX_CP_LS | 1601 AMD_CG_SUPPORT_GFX_CGCG | 1602 AMD_CG_SUPPORT_GFX_CGLS | 1603 AMD_CG_SUPPORT_GFX_3D_CGCG | 1604 AMD_CG_SUPPORT_GFX_3D_CGLS | 1605 AMD_CG_SUPPORT_SDMA_MGCG | 1606 AMD_CG_SUPPORT_SDMA_LS | 1607 AMD_CG_SUPPORT_BIF_MGCG | 1608 AMD_CG_SUPPORT_BIF_LS | 1609 AMD_CG_SUPPORT_HDP_MGCG | 1610 AMD_CG_SUPPORT_HDP_LS | 1611 AMD_CG_SUPPORT_ROM_MGCG | 1612 AMD_CG_SUPPORT_MC_MGCG | 1613 AMD_CG_SUPPORT_MC_LS | 1614 AMD_CG_SUPPORT_DRM_LS | 1615 AMD_CG_SUPPORT_UVD_MGCG | 1616 AMD_CG_SUPPORT_VCE_MGCG; 1617 adev->pg_flags = 0; 1618 adev->external_rev_id = adev->rev_id + 0x64; 1619 break; 1620 case CHIP_VEGAM: 1621 adev->cg_flags = 0; 1622 /*AMD_CG_SUPPORT_GFX_MGCG | 1623 AMD_CG_SUPPORT_GFX_RLC_LS | 1624 AMD_CG_SUPPORT_GFX_CP_LS | 1625 AMD_CG_SUPPORT_GFX_CGCG | 1626 AMD_CG_SUPPORT_GFX_CGLS | 1627 AMD_CG_SUPPORT_GFX_3D_CGCG | 1628 AMD_CG_SUPPORT_GFX_3D_CGLS | 1629 AMD_CG_SUPPORT_SDMA_MGCG | 1630 AMD_CG_SUPPORT_SDMA_LS | 1631 AMD_CG_SUPPORT_BIF_MGCG | 1632 AMD_CG_SUPPORT_BIF_LS | 1633 AMD_CG_SUPPORT_HDP_MGCG | 1634 AMD_CG_SUPPORT_HDP_LS | 1635 AMD_CG_SUPPORT_ROM_MGCG | 1636 AMD_CG_SUPPORT_MC_MGCG | 1637 AMD_CG_SUPPORT_MC_LS | 1638 AMD_CG_SUPPORT_DRM_LS | 1639 AMD_CG_SUPPORT_UVD_MGCG | 1640 AMD_CG_SUPPORT_VCE_MGCG;*/ 1641 adev->pg_flags = 0; 1642 adev->external_rev_id = adev->rev_id + 0x6E; 1643 break; 1644 case CHIP_CARRIZO: 1645 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | 1646 AMD_CG_SUPPORT_GFX_MGCG | 1647 AMD_CG_SUPPORT_GFX_MGLS | 1648 AMD_CG_SUPPORT_GFX_RLC_LS | 1649 AMD_CG_SUPPORT_GFX_CP_LS | 1650 AMD_CG_SUPPORT_GFX_CGTS | 1651 AMD_CG_SUPPORT_GFX_CGTS_LS | 1652 AMD_CG_SUPPORT_GFX_CGCG | 1653 AMD_CG_SUPPORT_GFX_CGLS | 1654 AMD_CG_SUPPORT_BIF_LS | 1655 AMD_CG_SUPPORT_HDP_MGCG | 1656 AMD_CG_SUPPORT_HDP_LS | 1657 AMD_CG_SUPPORT_SDMA_MGCG | 1658 AMD_CG_SUPPORT_SDMA_LS | 1659 AMD_CG_SUPPORT_VCE_MGCG; 1660 /* rev0 hardware requires workarounds to support PG */ 1661 adev->pg_flags = 0; 1662 if (adev->rev_id != 0x00 || CZ_REV_BRISTOL(adev->pdev->revision)) { 1663 adev->pg_flags |= AMD_PG_SUPPORT_GFX_SMG | 1664 AMD_PG_SUPPORT_GFX_PIPELINE | 1665 AMD_PG_SUPPORT_CP | 1666 AMD_PG_SUPPORT_UVD | 1667 AMD_PG_SUPPORT_VCE; 1668 } 1669 adev->external_rev_id = adev->rev_id + 0x1; 1670 break; 1671 case CHIP_STONEY: 1672 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | 1673 AMD_CG_SUPPORT_GFX_MGCG | 1674 AMD_CG_SUPPORT_GFX_MGLS | 1675 AMD_CG_SUPPORT_GFX_RLC_LS | 1676 AMD_CG_SUPPORT_GFX_CP_LS | 1677 AMD_CG_SUPPORT_GFX_CGTS | 1678 AMD_CG_SUPPORT_GFX_CGTS_LS | 1679 AMD_CG_SUPPORT_GFX_CGLS | 1680 AMD_CG_SUPPORT_BIF_LS | 1681 AMD_CG_SUPPORT_HDP_MGCG | 1682 AMD_CG_SUPPORT_HDP_LS | 1683 AMD_CG_SUPPORT_SDMA_MGCG | 1684 AMD_CG_SUPPORT_SDMA_LS | 1685 AMD_CG_SUPPORT_VCE_MGCG; 1686 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 1687 AMD_PG_SUPPORT_GFX_SMG | 1688 AMD_PG_SUPPORT_GFX_PIPELINE | 1689 AMD_PG_SUPPORT_CP | 1690 AMD_PG_SUPPORT_UVD | 1691 AMD_PG_SUPPORT_VCE; 1692 adev->external_rev_id = adev->rev_id + 0x61; 1693 break; 1694 default: 1695 /* FIXME: not supported yet */ 1696 return -EINVAL; 1697 } 1698 1699 if (amdgpu_sriov_vf(adev)) { 1700 amdgpu_virt_init_setting(adev); 1701 xgpu_vi_mailbox_set_irq_funcs(adev); 1702 } 1703 1704 return 0; 1705 } 1706 1707 static int vi_common_late_init(void *handle) 1708 { 1709 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1710 1711 if (amdgpu_sriov_vf(adev)) 1712 xgpu_vi_mailbox_get_irq(adev); 1713 1714 return 0; 1715 } 1716 1717 static int vi_common_sw_init(void *handle) 1718 { 1719 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1720 1721 if (amdgpu_sriov_vf(adev)) 1722 xgpu_vi_mailbox_add_irq_id(adev); 1723 1724 return 0; 1725 } 1726 1727 static int vi_common_sw_fini(void *handle) 1728 { 1729 return 0; 1730 } 1731 1732 static int vi_common_hw_init(void *handle) 1733 { 1734 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1735 1736 /* move the golden regs per IP block */ 1737 vi_init_golden_registers(adev); 1738 /* enable pcie gen2/3 link */ 1739 vi_pcie_gen3_enable(adev); 1740 /* enable aspm */ 1741 vi_program_aspm(adev); 1742 /* enable the doorbell aperture */ 1743 vi_enable_doorbell_aperture(adev, true); 1744 1745 return 0; 1746 } 1747 1748 static int vi_common_hw_fini(void *handle) 1749 { 1750 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1751 1752 /* enable the doorbell aperture */ 1753 vi_enable_doorbell_aperture(adev, false); 1754 1755 if (amdgpu_sriov_vf(adev)) 1756 xgpu_vi_mailbox_put_irq(adev); 1757 1758 return 0; 1759 } 1760 1761 static int vi_common_suspend(void *handle) 1762 { 1763 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1764 1765 return vi_common_hw_fini(adev); 1766 } 1767 1768 static int vi_common_resume(void *handle) 1769 { 1770 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1771 1772 return vi_common_hw_init(adev); 1773 } 1774 1775 static bool vi_common_is_idle(void *handle) 1776 { 1777 return true; 1778 } 1779 1780 static int vi_common_wait_for_idle(void *handle) 1781 { 1782 return 0; 1783 } 1784 1785 static int vi_common_soft_reset(void *handle) 1786 { 1787 return 0; 1788 } 1789 1790 static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev, 1791 bool enable) 1792 { 1793 uint32_t temp, data; 1794 1795 temp = data = RREG32_PCIE(ixPCIE_CNTL2); 1796 1797 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) 1798 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 1799 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 1800 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK; 1801 else 1802 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 1803 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 1804 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 1805 1806 if (temp != data) 1807 WREG32_PCIE(ixPCIE_CNTL2, data); 1808 } 1809 1810 static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev, 1811 bool enable) 1812 { 1813 uint32_t temp, data; 1814 1815 temp = data = RREG32(mmHDP_HOST_PATH_CNTL); 1816 1817 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 1818 data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK; 1819 else 1820 data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK; 1821 1822 if (temp != data) 1823 WREG32(mmHDP_HOST_PATH_CNTL, data); 1824 } 1825 1826 static void vi_update_hdp_light_sleep(struct amdgpu_device *adev, 1827 bool enable) 1828 { 1829 uint32_t temp, data; 1830 1831 temp = data = RREG32(mmHDP_MEM_POWER_LS); 1832 1833 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 1834 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK; 1835 else 1836 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK; 1837 1838 if (temp != data) 1839 WREG32(mmHDP_MEM_POWER_LS, data); 1840 } 1841 1842 static void vi_update_drm_light_sleep(struct amdgpu_device *adev, 1843 bool enable) 1844 { 1845 uint32_t temp, data; 1846 1847 temp = data = RREG32(0x157a); 1848 1849 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) 1850 data |= 1; 1851 else 1852 data &= ~1; 1853 1854 if (temp != data) 1855 WREG32(0x157a, data); 1856 } 1857 1858 1859 static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, 1860 bool enable) 1861 { 1862 uint32_t temp, data; 1863 1864 temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0); 1865 1866 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) 1867 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 1868 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK); 1869 else 1870 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 1871 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK; 1872 1873 if (temp != data) 1874 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data); 1875 } 1876 1877 static int vi_common_set_clockgating_state_by_smu(void *handle, 1878 enum amd_clockgating_state state) 1879 { 1880 uint32_t msg_id, pp_state = 0; 1881 uint32_t pp_support_state = 0; 1882 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1883 1884 if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) { 1885 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) { 1886 pp_support_state = PP_STATE_SUPPORT_LS; 1887 pp_state = PP_STATE_LS; 1888 } 1889 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) { 1890 pp_support_state |= PP_STATE_SUPPORT_CG; 1891 pp_state |= PP_STATE_CG; 1892 } 1893 if (state == AMD_CG_STATE_UNGATE) 1894 pp_state = 0; 1895 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1896 PP_BLOCK_SYS_MC, 1897 pp_support_state, 1898 pp_state); 1899 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 1900 } 1901 1902 if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) { 1903 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) { 1904 pp_support_state = PP_STATE_SUPPORT_LS; 1905 pp_state = PP_STATE_LS; 1906 } 1907 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) { 1908 pp_support_state |= PP_STATE_SUPPORT_CG; 1909 pp_state |= PP_STATE_CG; 1910 } 1911 if (state == AMD_CG_STATE_UNGATE) 1912 pp_state = 0; 1913 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1914 PP_BLOCK_SYS_SDMA, 1915 pp_support_state, 1916 pp_state); 1917 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 1918 } 1919 1920 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) { 1921 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 1922 pp_support_state = PP_STATE_SUPPORT_LS; 1923 pp_state = PP_STATE_LS; 1924 } 1925 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) { 1926 pp_support_state |= PP_STATE_SUPPORT_CG; 1927 pp_state |= PP_STATE_CG; 1928 } 1929 if (state == AMD_CG_STATE_UNGATE) 1930 pp_state = 0; 1931 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1932 PP_BLOCK_SYS_HDP, 1933 pp_support_state, 1934 pp_state); 1935 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 1936 } 1937 1938 1939 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) { 1940 if (state == AMD_CG_STATE_UNGATE) 1941 pp_state = 0; 1942 else 1943 pp_state = PP_STATE_LS; 1944 1945 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1946 PP_BLOCK_SYS_BIF, 1947 PP_STATE_SUPPORT_LS, 1948 pp_state); 1949 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 1950 } 1951 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) { 1952 if (state == AMD_CG_STATE_UNGATE) 1953 pp_state = 0; 1954 else 1955 pp_state = PP_STATE_CG; 1956 1957 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1958 PP_BLOCK_SYS_BIF, 1959 PP_STATE_SUPPORT_CG, 1960 pp_state); 1961 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 1962 } 1963 1964 if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) { 1965 1966 if (state == AMD_CG_STATE_UNGATE) 1967 pp_state = 0; 1968 else 1969 pp_state = PP_STATE_LS; 1970 1971 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1972 PP_BLOCK_SYS_DRM, 1973 PP_STATE_SUPPORT_LS, 1974 pp_state); 1975 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 1976 } 1977 1978 if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) { 1979 1980 if (state == AMD_CG_STATE_UNGATE) 1981 pp_state = 0; 1982 else 1983 pp_state = PP_STATE_CG; 1984 1985 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1986 PP_BLOCK_SYS_ROM, 1987 PP_STATE_SUPPORT_CG, 1988 pp_state); 1989 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 1990 } 1991 return 0; 1992 } 1993 1994 static int vi_common_set_clockgating_state(void *handle, 1995 enum amd_clockgating_state state) 1996 { 1997 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1998 1999 if (amdgpu_sriov_vf(adev)) 2000 return 0; 2001 2002 switch (adev->asic_type) { 2003 case CHIP_FIJI: 2004 vi_update_bif_medium_grain_light_sleep(adev, 2005 state == AMD_CG_STATE_GATE); 2006 vi_update_hdp_medium_grain_clock_gating(adev, 2007 state == AMD_CG_STATE_GATE); 2008 vi_update_hdp_light_sleep(adev, 2009 state == AMD_CG_STATE_GATE); 2010 vi_update_rom_medium_grain_clock_gating(adev, 2011 state == AMD_CG_STATE_GATE); 2012 break; 2013 case CHIP_CARRIZO: 2014 case CHIP_STONEY: 2015 vi_update_bif_medium_grain_light_sleep(adev, 2016 state == AMD_CG_STATE_GATE); 2017 vi_update_hdp_medium_grain_clock_gating(adev, 2018 state == AMD_CG_STATE_GATE); 2019 vi_update_hdp_light_sleep(adev, 2020 state == AMD_CG_STATE_GATE); 2021 vi_update_drm_light_sleep(adev, 2022 state == AMD_CG_STATE_GATE); 2023 break; 2024 case CHIP_TONGA: 2025 case CHIP_POLARIS10: 2026 case CHIP_POLARIS11: 2027 case CHIP_POLARIS12: 2028 case CHIP_VEGAM: 2029 vi_common_set_clockgating_state_by_smu(adev, state); 2030 break; 2031 default: 2032 break; 2033 } 2034 return 0; 2035 } 2036 2037 static int vi_common_set_powergating_state(void *handle, 2038 enum amd_powergating_state state) 2039 { 2040 return 0; 2041 } 2042 2043 static void vi_common_get_clockgating_state(void *handle, u64 *flags) 2044 { 2045 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2046 int data; 2047 2048 if (amdgpu_sriov_vf(adev)) 2049 *flags = 0; 2050 2051 /* AMD_CG_SUPPORT_BIF_LS */ 2052 data = RREG32_PCIE(ixPCIE_CNTL2); 2053 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 2054 *flags |= AMD_CG_SUPPORT_BIF_LS; 2055 2056 /* AMD_CG_SUPPORT_HDP_LS */ 2057 data = RREG32(mmHDP_MEM_POWER_LS); 2058 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK) 2059 *flags |= AMD_CG_SUPPORT_HDP_LS; 2060 2061 /* AMD_CG_SUPPORT_HDP_MGCG */ 2062 data = RREG32(mmHDP_HOST_PATH_CNTL); 2063 if (!(data & HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK)) 2064 *flags |= AMD_CG_SUPPORT_HDP_MGCG; 2065 2066 /* AMD_CG_SUPPORT_ROM_MGCG */ 2067 data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0); 2068 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK)) 2069 *flags |= AMD_CG_SUPPORT_ROM_MGCG; 2070 } 2071 2072 static const struct amd_ip_funcs vi_common_ip_funcs = { 2073 .name = "vi_common", 2074 .early_init = vi_common_early_init, 2075 .late_init = vi_common_late_init, 2076 .sw_init = vi_common_sw_init, 2077 .sw_fini = vi_common_sw_fini, 2078 .hw_init = vi_common_hw_init, 2079 .hw_fini = vi_common_hw_fini, 2080 .suspend = vi_common_suspend, 2081 .resume = vi_common_resume, 2082 .is_idle = vi_common_is_idle, 2083 .wait_for_idle = vi_common_wait_for_idle, 2084 .soft_reset = vi_common_soft_reset, 2085 .set_clockgating_state = vi_common_set_clockgating_state, 2086 .set_powergating_state = vi_common_set_powergating_state, 2087 .get_clockgating_state = vi_common_get_clockgating_state, 2088 }; 2089 2090 static const struct amdgpu_ip_block_version vi_common_ip_block = 2091 { 2092 .type = AMD_IP_BLOCK_TYPE_COMMON, 2093 .major = 1, 2094 .minor = 0, 2095 .rev = 0, 2096 .funcs = &vi_common_ip_funcs, 2097 }; 2098 2099 void vi_set_virt_ops(struct amdgpu_device *adev) 2100 { 2101 adev->virt.ops = &xgpu_vi_virt_ops; 2102 } 2103 2104 int vi_set_ip_blocks(struct amdgpu_device *adev) 2105 { 2106 switch (adev->asic_type) { 2107 case CHIP_TOPAZ: 2108 /* topaz has no DCE, UVD, VCE */ 2109 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); 2110 amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block); 2111 amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block); 2112 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); 2113 amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block); 2114 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2115 if (adev->enable_virtual_display) 2116 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2117 break; 2118 case CHIP_FIJI: 2119 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); 2120 amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block); 2121 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block); 2122 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); 2123 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); 2124 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2125 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 2126 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2127 #if defined(CONFIG_DRM_AMD_DC) 2128 else if (amdgpu_device_has_dc_support(adev)) 2129 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2130 #endif 2131 else 2132 amdgpu_device_ip_block_add(adev, &dce_v10_1_ip_block); 2133 if (!amdgpu_sriov_vf(adev)) { 2134 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block); 2135 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block); 2136 } 2137 break; 2138 case CHIP_TONGA: 2139 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); 2140 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block); 2141 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block); 2142 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); 2143 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); 2144 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2145 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 2146 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2147 #if defined(CONFIG_DRM_AMD_DC) 2148 else if (amdgpu_device_has_dc_support(adev)) 2149 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2150 #endif 2151 else 2152 amdgpu_device_ip_block_add(adev, &dce_v10_0_ip_block); 2153 if (!amdgpu_sriov_vf(adev)) { 2154 amdgpu_device_ip_block_add(adev, &uvd_v5_0_ip_block); 2155 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block); 2156 } 2157 break; 2158 case CHIP_POLARIS10: 2159 case CHIP_POLARIS11: 2160 case CHIP_POLARIS12: 2161 case CHIP_VEGAM: 2162 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); 2163 amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block); 2164 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block); 2165 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); 2166 amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block); 2167 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2168 if (adev->enable_virtual_display) 2169 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2170 #if defined(CONFIG_DRM_AMD_DC) 2171 else if (amdgpu_device_has_dc_support(adev)) 2172 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2173 #endif 2174 else 2175 amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block); 2176 amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block); 2177 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block); 2178 break; 2179 case CHIP_CARRIZO: 2180 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); 2181 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block); 2182 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block); 2183 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); 2184 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); 2185 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2186 if (adev->enable_virtual_display) 2187 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2188 #if defined(CONFIG_DRM_AMD_DC) 2189 else if (amdgpu_device_has_dc_support(adev)) 2190 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2191 #endif 2192 else 2193 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block); 2194 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block); 2195 amdgpu_device_ip_block_add(adev, &vce_v3_1_ip_block); 2196 #if defined(CONFIG_DRM_AMD_ACP) 2197 amdgpu_device_ip_block_add(adev, &acp_ip_block); 2198 #endif 2199 break; 2200 case CHIP_STONEY: 2201 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); 2202 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block); 2203 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block); 2204 amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block); 2205 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); 2206 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2207 if (adev->enable_virtual_display) 2208 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2209 #if defined(CONFIG_DRM_AMD_DC) 2210 else if (amdgpu_device_has_dc_support(adev)) 2211 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2212 #endif 2213 else 2214 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block); 2215 amdgpu_device_ip_block_add(adev, &uvd_v6_2_ip_block); 2216 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block); 2217 #if defined(CONFIG_DRM_AMD_ACP) 2218 amdgpu_device_ip_block_add(adev, &acp_ip_block); 2219 #endif 2220 break; 2221 default: 2222 /* FIXME: not supported yet */ 2223 return -EINVAL; 2224 } 2225 2226 return 0; 2227 } 2228 2229 void legacy_doorbell_index_init(struct amdgpu_device *adev) 2230 { 2231 adev->doorbell_index.kiq = AMDGPU_DOORBELL_KIQ; 2232 adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL_MEC_RING0; 2233 adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL_MEC_RING1; 2234 adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL_MEC_RING2; 2235 adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL_MEC_RING3; 2236 adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL_MEC_RING4; 2237 adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL_MEC_RING5; 2238 adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL_MEC_RING6; 2239 adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL_MEC_RING7; 2240 adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL_GFX_RING0; 2241 adev->doorbell_index.sdma_engine[0] = AMDGPU_DOORBELL_sDMA_ENGINE0; 2242 adev->doorbell_index.sdma_engine[1] = AMDGPU_DOORBELL_sDMA_ENGINE1; 2243 adev->doorbell_index.ih = AMDGPU_DOORBELL_IH; 2244 adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_MAX_ASSIGNMENT; 2245 } 2246